hotspot/src/cpu/aarch64/vm/c1_MacroAssembler_aarch64.cpp
author aph
Tue, 20 Jan 2015 12:47:43 -0800
changeset 29184 e234025cafb6
child 29195 7d6208ea1775
permissions -rw-r--r--
8068053: AARCH64: C1 and C2 compilers Summary: add src/cpu/aarch64/vm/* C1 and C2 files Reviewed-by: kvn, roland
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/*
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 * Copyright (c) 1999, 2011, Oracle and/or its affiliates. All rights reserved.
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 * Copyright (c) 2014, Red Hat Inc. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#include "precompiled.hpp"
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#include "c1/c1_MacroAssembler.hpp"
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#include "c1/c1_Runtime1.hpp"
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#include "classfile/systemDictionary.hpp"
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#include "gc_interface/collectedHeap.hpp"
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#include "interpreter/interpreter.hpp"
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#include "oops/arrayOop.hpp"
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#include "oops/markOop.hpp"
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#include "runtime/basicLock.hpp"
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#include "runtime/biasedLocking.hpp"
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#include "runtime/os.hpp"
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#include "runtime/stubRoutines.hpp"
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void C1_MacroAssembler::float_cmp(bool is_float, int unordered_result,
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                                  FloatRegister f0, FloatRegister f1,
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                                  Register result)
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{
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  Label done;
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  if (is_float) {
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    fcmps(f0, f1);
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  } else {
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    fcmpd(f0, f1);
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  }
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  if (unordered_result < 0) {
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    // we want -1 for unordered or less than, 0 for equal and 1 for
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    // greater than.
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    cset(result, NE);  // Not equal or unordered
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    cneg(result, result, LT);  // Less than or unordered
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  } else {
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    // we want -1 for less than, 0 for equal and 1 for unordered or
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    // greater than.
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    cset(result, NE);  // Not equal or unordered
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    cneg(result, result, LO);  // Less than
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  }
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}
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int C1_MacroAssembler::lock_object(Register hdr, Register obj, Register disp_hdr, Register scratch, Label& slow_case) {
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  const int aligned_mask = BytesPerWord -1;
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  const int hdr_offset = oopDesc::mark_offset_in_bytes();
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  assert(hdr != obj && hdr != disp_hdr && obj != disp_hdr, "registers must be different");
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  Label done, fail;
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  int null_check_offset = -1;
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  verify_oop(obj);
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  // save object being locked into the BasicObjectLock
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  str(obj, Address(disp_hdr, BasicObjectLock::obj_offset_in_bytes()));
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  if (UseBiasedLocking) {
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    assert(scratch != noreg, "should have scratch register at this point");
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    null_check_offset = biased_locking_enter(disp_hdr, obj, hdr, scratch, false, done, &slow_case);
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  } else {
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    null_check_offset = offset();
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  }
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  // Load object header
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  ldr(hdr, Address(obj, hdr_offset));
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  // and mark it as unlocked
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  orr(hdr, hdr, markOopDesc::unlocked_value);
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  // save unlocked object header into the displaced header location on the stack
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  str(hdr, Address(disp_hdr, 0));
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  // test if object header is still the same (i.e. unlocked), and if so, store the
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  // displaced header address in the object header - if it is not the same, get the
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  // object header instead
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  lea(rscratch2, Address(obj, hdr_offset));
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  cmpxchgptr(hdr, disp_hdr, rscratch2, rscratch1, done, /*fallthough*/NULL);
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  // if the object header was the same, we're done
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  // if the object header was not the same, it is now in the hdr register
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  // => test if it is a stack pointer into the same stack (recursive locking), i.e.:
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  //
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  // 1) (hdr & aligned_mask) == 0
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  // 2) sp <= hdr
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  // 3) hdr <= sp + page_size
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  //
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  // these 3 tests can be done by evaluating the following expression:
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  //
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  // (hdr - sp) & (aligned_mask - page_size)
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  //
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  // assuming both the stack pointer and page_size have their least
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  // significant 2 bits cleared and page_size is a power of 2
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  mov(rscratch1, sp);
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  sub(hdr, hdr, rscratch1);
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  ands(hdr, hdr, aligned_mask - os::vm_page_size());
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  // for recursive locking, the result is zero => save it in the displaced header
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  // location (NULL in the displaced hdr location indicates recursive locking)
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  str(hdr, Address(disp_hdr, 0));
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  // otherwise we don't care about the result and handle locking via runtime call
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  cbnz(hdr, slow_case);
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  // done
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  bind(done);
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  if (PrintBiasedLockingStatistics) {
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    lea(rscratch2, ExternalAddress((address)BiasedLocking::fast_path_entry_count_addr()));
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    addmw(Address(rscratch2, 0), 1, rscratch1);
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  }
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  return null_check_offset;
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}
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void C1_MacroAssembler::unlock_object(Register hdr, Register obj, Register disp_hdr, Label& slow_case) {
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  const int aligned_mask = BytesPerWord -1;
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  const int hdr_offset = oopDesc::mark_offset_in_bytes();
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  assert(hdr != obj && hdr != disp_hdr && obj != disp_hdr, "registers must be different");
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  Label done;
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  if (UseBiasedLocking) {
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    // load object
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    ldr(obj, Address(disp_hdr, BasicObjectLock::obj_offset_in_bytes()));
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    biased_locking_exit(obj, hdr, done);
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  }
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  // load displaced header
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  ldr(hdr, Address(disp_hdr, 0));
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  // if the loaded hdr is NULL we had recursive locking
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  // if we had recursive locking, we are done
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  cbz(hdr, done);
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  if (!UseBiasedLocking) {
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    // load object
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    ldr(obj, Address(disp_hdr, BasicObjectLock::obj_offset_in_bytes()));
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  }
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  verify_oop(obj);
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  // test if object header is pointing to the displaced header, and if so, restore
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  // the displaced header in the object - if the object header is not pointing to
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  // the displaced header, get the object header instead
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  // if the object header was not pointing to the displaced header,
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  // we do unlocking via runtime call
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  if (hdr_offset) {
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    lea(rscratch1, Address(obj, hdr_offset));
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    cmpxchgptr(disp_hdr, hdr, rscratch1, rscratch2, done, &slow_case);
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  } else {
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    cmpxchgptr(disp_hdr, hdr, obj, rscratch2, done, &slow_case);
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  }
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  // done
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  bind(done);
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   159
}
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   160
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   161
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// Defines obj, preserves var_size_in_bytes
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void C1_MacroAssembler::try_allocate(Register obj, Register var_size_in_bytes, int con_size_in_bytes, Register t1, Register t2, Label& slow_case) {
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  if (UseTLAB) {
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    tlab_allocate(obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
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  } else {
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    eden_allocate(obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case);
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    incr_allocated_bytes(noreg, var_size_in_bytes, con_size_in_bytes, t1);
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  }
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}
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   171
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void C1_MacroAssembler::initialize_header(Register obj, Register klass, Register len, Register t1, Register t2) {
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  assert_different_registers(obj, klass, len);
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   174
  if (UseBiasedLocking && !len->is_valid()) {
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    assert_different_registers(obj, klass, len, t1, t2);
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    ldr(t1, Address(klass, Klass::prototype_header_offset()));
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  } else {
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    // This assumes that all prototype bits fit in an int32_t
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    mov(t1, (int32_t)(intptr_t)markOopDesc::prototype());
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  }
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  str(t1, Address(obj, oopDesc::mark_offset_in_bytes()));
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  if (UseCompressedClassPointers) { // Take care not to kill klass
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    encode_klass_not_null(t1, klass);
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    strw(t1, Address(obj, oopDesc::klass_offset_in_bytes()));
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   186
  } else {
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    str(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
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  }
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   189
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  if (len->is_valid()) {
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    strw(len, Address(obj, arrayOopDesc::length_offset_in_bytes()));
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   192
  } else if (UseCompressedClassPointers) {
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    store_klass_gap(obj, zr);
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   194
  }
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   195
}
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   196
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// Zero words; len is in bytes
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// Destroys all registers except addr
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   199
// len must be a nonzero multiple of wordSize
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void C1_MacroAssembler::zero_memory(Register addr, Register len, Register t1) {
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  assert_different_registers(addr, len, t1, rscratch1, rscratch2);
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   202
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#ifdef ASSERT
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  { Label L;
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    tst(len, BytesPerWord - 1);
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    br(Assembler::EQ, L);
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    stop("len is not a multiple of BytesPerWord");
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    bind(L);
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  }
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#endif
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   211
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#ifndef PRODUCT
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  block_comment("zero memory");
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#endif
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   215
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  Label loop;
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  Label entry;
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   218
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//  Algorithm:
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//
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//    scratch1 = cnt & 7;
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//    cnt -= scratch1;
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   223
//    p += scratch1;
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   224
//    switch (scratch1) {
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//      do {
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//        cnt -= 8;
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//          p[-8] = 0;
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   228
//        case 7:
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   229
//          p[-7] = 0;
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   230
//        case 6:
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   231
//          p[-6] = 0;
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   232
//          // ...
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   233
//        case 1:
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   234
//          p[-1] = 0;
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   235
//        case 0:
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   236
//          p += 8;
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   237
//      } while (cnt);
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//    }
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   239
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  const int unroll = 8; // Number of str(zr) instructions we'll unroll
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   241
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  lsr(len, len, LogBytesPerWord);
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  andr(rscratch1, len, unroll - 1);  // tmp1 = cnt % unroll
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  sub(len, len, rscratch1);      // cnt -= unroll
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   245
  // t1 always points to the end of the region we're about to zero
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  add(t1, addr, rscratch1, Assembler::LSL, LogBytesPerWord);
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   247
  adr(rscratch2, entry);
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  sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 2);
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   249
  br(rscratch2);
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   250
  bind(loop);
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   251
  sub(len, len, unroll);
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   252
  for (int i = -unroll; i < 0; i++)
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   253
    str(zr, Address(t1, i * wordSize));
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   254
  bind(entry);
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   255
  add(t1, t1, unroll * wordSize);
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   256
  cbnz(len, loop);
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   257
}
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   258
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   259
// preserves obj, destroys len_in_bytes
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   260
void C1_MacroAssembler::initialize_body(Register obj, Register len_in_bytes, int hdr_size_in_bytes, Register t1) {
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  Label done;
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   262
  assert(obj != len_in_bytes && obj != t1 && t1 != len_in_bytes, "registers must be different");
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   263
  assert((hdr_size_in_bytes & (BytesPerWord - 1)) == 0, "header size is not a multiple of BytesPerWord");
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   264
  Register index = len_in_bytes;
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   265
  // index is positive and ptr sized
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   266
  subs(index, index, hdr_size_in_bytes);
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   267
  br(Assembler::EQ, done);
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  // note: for the remaining code to work, index must be a multiple of BytesPerWord
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#ifdef ASSERT
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   270
  { Label L;
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   271
    tst(index, BytesPerWord - 1);
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    br(Assembler::EQ, L);
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   273
    stop("index is not a multiple of BytesPerWord");
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   274
    bind(L);
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   275
  }
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   276
#endif
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   277
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  // Preserve obj
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   279
  if (hdr_size_in_bytes)
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   280
    add(obj, obj, hdr_size_in_bytes);
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   281
  zero_memory(obj, index, t1);
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   282
  if (hdr_size_in_bytes)
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   283
    sub(obj, obj, hdr_size_in_bytes);
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   284
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   285
  // done
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   286
  bind(done);
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   287
}
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   288
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   289
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   290
void C1_MacroAssembler::allocate_object(Register obj, Register t1, Register t2, int header_size, int object_size, Register klass, Label& slow_case) {
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   291
  assert_different_registers(obj, t1, t2); // XXX really?
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   292
  assert(header_size >= 0 && object_size >= header_size, "illegal sizes");
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   293
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   294
  try_allocate(obj, noreg, object_size * BytesPerWord, t1, t2, slow_case);
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   295
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diff changeset
   296
  initialize_object(obj, klass, noreg, object_size * HeapWordSize, t1, t2);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   297
}
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   298
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   299
void C1_MacroAssembler::initialize_object(Register obj, Register klass, Register var_size_in_bytes, int con_size_in_bytes, Register t1, Register t2) {
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   300
  assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0,
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   301
         "con_size_in_bytes is not multiple of alignment");
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   302
  const int hdr_size_in_bytes = instanceOopDesc::header_size() * HeapWordSize;
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   303
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   304
  initialize_header(obj, klass, noreg, t1, t2);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   305
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   306
  // clear rest of allocated space
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   307
  const Register index = t2;
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   308
  const int threshold = 16 * BytesPerWord;   // approximate break even point for code size (see comments below)
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   309
  if (var_size_in_bytes != noreg) {
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   310
    mov(index, var_size_in_bytes);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   311
    initialize_body(obj, index, hdr_size_in_bytes, t1);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   312
  } else if (con_size_in_bytes <= threshold) {
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   313
    // use explicit null stores
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   314
    int i = hdr_size_in_bytes;
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   315
    if (i < con_size_in_bytes && (con_size_in_bytes % (2 * BytesPerWord))) {
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   316
      str(zr, Address(obj, i));
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   317
      i += BytesPerWord;
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   318
    }
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   319
    for (; i < con_size_in_bytes; i += 2 * BytesPerWord)
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   320
      stp(zr, zr, Address(obj, i));
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   321
  } else if (con_size_in_bytes > hdr_size_in_bytes) {
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   322
    block_comment("zero memory");
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   323
    // use loop to null out the fields
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   324
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   325
    int words = (con_size_in_bytes - hdr_size_in_bytes) / BytesPerWord;
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   326
    mov(index,  words / 8);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   327
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   328
    const int unroll = 8; // Number of str(zr) instructions we'll unroll
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   329
    int remainder = words % unroll;
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   330
    lea(rscratch1, Address(obj, hdr_size_in_bytes + remainder * BytesPerWord));
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   331
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   332
    Label entry_point, loop;
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   333
    b(entry_point);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   334
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   335
    bind(loop);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   336
    sub(index, index, 1);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   337
    for (int i = -unroll; i < 0; i++) {
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   338
      if (-i == remainder)
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   339
        bind(entry_point);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   340
      str(zr, Address(rscratch1, i * wordSize));
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   341
    }
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   342
    if (remainder == 0)
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   343
      bind(entry_point);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   344
    add(rscratch1, rscratch1, unroll * wordSize);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   345
    cbnz(index, loop);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   346
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   347
  }
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   348
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   349
  membar(StoreStore);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   350
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   351
  if (CURRENT_ENV->dtrace_alloc_probes()) {
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   352
    assert(obj == r0, "must be");
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   353
    far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::dtrace_object_alloc_id)));
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   354
  }
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   355
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   356
  verify_oop(obj);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   357
}
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   358
void C1_MacroAssembler::allocate_array(Register obj, Register len, Register t1, Register t2, int header_size, int f, Register klass, Label& slow_case) {
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   359
  assert_different_registers(obj, len, t1, t2, klass);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   360
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   361
  // determine alignment mask
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   362
  assert(!(BytesPerWord & 1), "must be a multiple of 2 for masking code to work");
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   363
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   364
  // check for negative or excessive length
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   365
  mov(rscratch1, (int32_t)max_array_allocation_length);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   366
  cmp(len, rscratch1);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   367
  br(Assembler::HS, slow_case);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   368
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   369
  const Register arr_size = t2; // okay to be the same
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   370
  // align object end
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   371
  mov(arr_size, (int32_t)header_size * BytesPerWord + MinObjAlignmentInBytesMask);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   372
  add(arr_size, arr_size, len, ext::uxtw, f);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   373
  andr(arr_size, arr_size, ~MinObjAlignmentInBytesMask);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   374
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   375
  try_allocate(obj, arr_size, 0, t1, t2, slow_case);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   376
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   377
  initialize_header(obj, klass, len, t1, t2);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   378
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   379
  // clear rest of allocated space
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   380
  const Register len_zero = len;
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   381
  initialize_body(obj, arr_size, header_size * BytesPerWord, len_zero);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   382
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   383
  membar(StoreStore);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   384
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   385
  if (CURRENT_ENV->dtrace_alloc_probes()) {
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   386
    assert(obj == r0, "must be");
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   387
    far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::dtrace_object_alloc_id)));
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   388
  }
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   389
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   390
  verify_oop(obj);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   391
}
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   392
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   393
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   394
void C1_MacroAssembler::inline_cache_check(Register receiver, Register iCache) {
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   395
  verify_oop(receiver);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   396
  // explicit NULL check not needed since load from [klass_offset] causes a trap
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   397
  // check against inline cache
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   398
  assert(!MacroAssembler::needs_explicit_null_check(oopDesc::klass_offset_in_bytes()), "must add explicit null check");
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   399
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   400
  cmp_klass(receiver, iCache, rscratch1);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   401
}
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   402
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   403
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   404
void C1_MacroAssembler::build_frame(int framesize, int bang_size_in_bytes) {
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   405
  // If we have to make this method not-entrant we'll overwrite its
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   406
  // first instruction with a jump.  For this action to be legal we
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   407
  // must ensure that this first instruction is a B, BL, NOP, BKPT,
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   408
  // SVC, HVC, or SMC.  Make it a NOP.
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   409
  nop();
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   410
  assert(bang_size_in_bytes >= framesize, "stack bang size incorrect");
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   411
  // Make sure there is enough stack space for this method's activation.
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   412
  // Note that we do this before doing an enter().
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   413
  generate_stack_overflow_check(bang_size_in_bytes);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   414
  MacroAssembler::build_frame(framesize + 2 * wordSize);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   415
  if (NotifySimulator) {
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   416
    notify(Assembler::method_entry);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   417
  }
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   418
}
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   419
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   420
void C1_MacroAssembler::remove_frame(int framesize) {
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   421
  MacroAssembler::remove_frame(framesize + 2 * wordSize);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   422
  if (NotifySimulator) {
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   423
    notify(Assembler::method_reentry);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   424
  }
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   425
}
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   426
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   427
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   428
void C1_MacroAssembler::verified_entry() {
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   429
}
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   430
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   431
#ifndef PRODUCT
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   432
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   433
void C1_MacroAssembler::verify_stack_oop(int stack_offset) {
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   434
  if (!VerifyOops) return;
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   435
  verify_oop_addr(Address(sp, stack_offset), "oop");
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   436
}
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   437
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   438
void C1_MacroAssembler::verify_not_null_oop(Register r) {
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   439
  if (!VerifyOops) return;
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   440
  Label not_null;
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   441
  cbnz(r, not_null);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   442
  stop("non-null oop required");
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   443
  bind(not_null);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   444
  verify_oop(r);
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   445
}
e234025cafb6 8068053: AARCH64: C1 and C2 compilers
aph
parents:
diff changeset
   446
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void C1_MacroAssembler::invalidate_registers(bool inv_r0, bool inv_r19, bool inv_r2, bool inv_r3, bool inv_r4, bool inv_r5) {
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#ifdef ASSERT
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  static int nn;
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  if (inv_r0) mov(r0, 0xDEAD);
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  if (inv_r19) mov(r19, 0xDEAD);
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  if (inv_r2) mov(r2, nn++);
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  if (inv_r3) mov(r3, 0xDEAD);
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  if (inv_r4) mov(r4, 0xDEAD);
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  if (inv_r5) mov(r5, 0xDEAD);
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#endif
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}
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#endif // ifndef PRODUCT