hotspot/src/cpu/x86/vm/stubGenerator_x86_32.cpp
author twisti
Fri, 18 Dec 2015 12:39:02 -0800
changeset 35135 dd2ce9021031
parent 35113 b11bd150ed8a
parent 35071 a0910b1d3e0d
child 35146 9ebfec283f56
permissions -rw-r--r--
Merge
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/*
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 * Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#include "precompiled.hpp"
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#include "asm/macroAssembler.hpp"
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#include "asm/macroAssembler.inline.hpp"
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#include "interpreter/interpreter.hpp"
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#include "nativeInst_x86.hpp"
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#include "oops/instanceOop.hpp"
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#include "oops/method.hpp"
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#include "oops/objArrayKlass.hpp"
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#include "oops/oop.inline.hpp"
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#include "prims/methodHandles.hpp"
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#include "runtime/frame.inline.hpp"
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#include "runtime/handles.inline.hpp"
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#include "runtime/sharedRuntime.hpp"
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#include "runtime/stubCodeGenerator.hpp"
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#include "runtime/stubRoutines.hpp"
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#include "runtime/thread.inline.hpp"
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#include "utilities/top.hpp"
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#ifdef COMPILER2
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#include "opto/runtime.hpp"
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#endif
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// Declaration and definition of StubGenerator (no .hpp file).
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// For a more detailed description of the stub routine structure
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// see the comment in stubRoutines.hpp
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#define __ _masm->
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#define a__ ((Assembler*)_masm)->
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#ifdef PRODUCT
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#define BLOCK_COMMENT(str) /* nothing */
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#else
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#define BLOCK_COMMENT(str) __ block_comment(str)
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#endif
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#define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
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const int MXCSR_MASK  = 0xFFC0;  // Mask out any pending exceptions
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const int FPU_CNTRL_WRD_MASK = 0xFFFF;
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// -------------------------------------------------------------------------------------------------------------------------
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// Stub Code definitions
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static address handle_unsafe_access() {
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  JavaThread* thread = JavaThread::current();
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  address pc  = thread->saved_exception_pc();
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  // pc is the instruction which we must emulate
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  // doing a no-op is fine:  return garbage from the load
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  // therefore, compute npc
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  address npc = Assembler::locate_next_instruction(pc);
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  // request an async exception
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  thread->set_pending_unsafe_access_error();
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  // return address of next instruction to execute
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  return npc;
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}
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class StubGenerator: public StubCodeGenerator {
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 private:
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#ifdef PRODUCT
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#define inc_counter_np(counter) ((void)0)
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#else
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  void inc_counter_np_(int& counter) {
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    __ incrementl(ExternalAddress((address)&counter));
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  }
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#define inc_counter_np(counter) \
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  BLOCK_COMMENT("inc_counter " #counter); \
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  inc_counter_np_(counter);
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#endif //PRODUCT
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  void inc_copy_counter_np(BasicType t) {
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#ifndef PRODUCT
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    switch (t) {
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    case T_BYTE:    inc_counter_np(SharedRuntime::_jbyte_array_copy_ctr); return;
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    case T_SHORT:   inc_counter_np(SharedRuntime::_jshort_array_copy_ctr); return;
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    case T_INT:     inc_counter_np(SharedRuntime::_jint_array_copy_ctr); return;
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    case T_LONG:    inc_counter_np(SharedRuntime::_jlong_array_copy_ctr); return;
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    case T_OBJECT:  inc_counter_np(SharedRuntime::_oop_array_copy_ctr); return;
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    }
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    ShouldNotReachHere();
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#endif //PRODUCT
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  }
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  //------------------------------------------------------------------------------------------------------------------------
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  // Call stubs are used to call Java from C
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  //
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  //    [ return_from_Java     ] <--- rsp
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  //    [ argument word n      ]
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  //      ...
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  // -N [ argument word 1      ]
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  // -7 [ Possible padding for stack alignment ]
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  // -6 [ Possible padding for stack alignment ]
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  // -5 [ Possible padding for stack alignment ]
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  // -4 [ mxcsr save           ] <--- rsp_after_call
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  // -3 [ saved rbx,            ]
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  // -2 [ saved rsi            ]
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  // -1 [ saved rdi            ]
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  //  0 [ saved rbp,            ] <--- rbp,
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  //  1 [ return address       ]
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  //  2 [ ptr. to call wrapper ]
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  //  3 [ result               ]
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  //  4 [ result_type          ]
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  //  5 [ method               ]
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  //  6 [ entry_point          ]
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  //  7 [ parameters           ]
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  //  8 [ parameter_size       ]
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  //  9 [ thread               ]
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  address generate_call_stub(address& return_address) {
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    StubCodeMark mark(this, "StubRoutines", "call_stub");
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    address start = __ pc();
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    // stub code parameters / addresses
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    assert(frame::entry_frame_call_wrapper_offset == 2, "adjust this code");
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    bool  sse_save = false;
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    const Address rsp_after_call(rbp, -4 * wordSize); // same as in generate_catch_exception()!
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    const int     locals_count_in_bytes  (4*wordSize);
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    const Address mxcsr_save    (rbp, -4 * wordSize);
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    const Address saved_rbx     (rbp, -3 * wordSize);
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    const Address saved_rsi     (rbp, -2 * wordSize);
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    const Address saved_rdi     (rbp, -1 * wordSize);
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    const Address result        (rbp,  3 * wordSize);
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    const Address result_type   (rbp,  4 * wordSize);
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    const Address method        (rbp,  5 * wordSize);
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    const Address entry_point   (rbp,  6 * wordSize);
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    const Address parameters    (rbp,  7 * wordSize);
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    const Address parameter_size(rbp,  8 * wordSize);
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    const Address thread        (rbp,  9 * wordSize); // same as in generate_catch_exception()!
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    sse_save =  UseSSE > 0;
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    // stub code
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    __ enter();
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    __ movptr(rcx, parameter_size);              // parameter counter
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    __ shlptr(rcx, Interpreter::logStackElementSize); // convert parameter count to bytes
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    __ addptr(rcx, locals_count_in_bytes);       // reserve space for register saves
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    __ subptr(rsp, rcx);
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    __ andptr(rsp, -(StackAlignmentInBytes));    // Align stack
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    // save rdi, rsi, & rbx, according to C calling conventions
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    __ movptr(saved_rdi, rdi);
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    __ movptr(saved_rsi, rsi);
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    __ movptr(saved_rbx, rbx);
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    // provide initial value for required masks
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    if (UseAVX > 2) {
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      __ movl(rbx, 0xffff);
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      __ kmovwl(k1, rbx);
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    }
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    // save and initialize %mxcsr
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    if (sse_save) {
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      Label skip_ldmx;
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      __ stmxcsr(mxcsr_save);
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      __ movl(rax, mxcsr_save);
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      __ andl(rax, MXCSR_MASK);    // Only check control and mask bits
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      ExternalAddress mxcsr_std(StubRoutines::addr_mxcsr_std());
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      __ cmp32(rax, mxcsr_std);
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      __ jcc(Assembler::equal, skip_ldmx);
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      __ ldmxcsr(mxcsr_std);
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      __ bind(skip_ldmx);
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    }
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    // make sure the control word is correct.
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    __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
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#ifdef ASSERT
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    // make sure we have no pending exceptions
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    { Label L;
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      __ movptr(rcx, thread);
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      __ cmpptr(Address(rcx, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
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      __ jcc(Assembler::equal, L);
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      __ stop("StubRoutines::call_stub: entered with pending exception");
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      __ bind(L);
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    }
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#endif
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    // pass parameters if any
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    BLOCK_COMMENT("pass parameters if any");
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    Label parameters_done;
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    __ movl(rcx, parameter_size);  // parameter counter
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    __ testl(rcx, rcx);
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    __ jcc(Assembler::zero, parameters_done);
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    // parameter passing loop
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    Label loop;
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    // Copy Java parameters in reverse order (receiver last)
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    // Note that the argument order is inverted in the process
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    // source is rdx[rcx: N-1..0]
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    // dest   is rsp[rbx: 0..N-1]
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    __ movptr(rdx, parameters);          // parameter pointer
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    __ xorptr(rbx, rbx);
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    __ BIND(loop);
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    // get parameter
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    __ movptr(rax, Address(rdx, rcx, Interpreter::stackElementScale(), -wordSize));
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    __ movptr(Address(rsp, rbx, Interpreter::stackElementScale(),
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                    Interpreter::expr_offset_in_bytes(0)), rax);          // store parameter
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    __ increment(rbx);
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    __ decrement(rcx);
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    __ jcc(Assembler::notZero, loop);
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    // call Java function
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    __ BIND(parameters_done);
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    __ movptr(rbx, method);           // get Method*
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    __ movptr(rax, entry_point);      // get entry_point
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    __ mov(rsi, rsp);                 // set sender sp
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    BLOCK_COMMENT("call Java function");
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    __ call(rax);
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    BLOCK_COMMENT("call_stub_return_address:");
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    return_address = __ pc();
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#ifdef COMPILER2
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    {
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      Label L_skip;
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      if (UseSSE >= 2) {
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        __ verify_FPU(0, "call_stub_return");
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      } else {
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        for (int i = 1; i < 8; i++) {
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          __ ffree(i);
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        }
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        // UseSSE <= 1 so double result should be left on TOS
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        __ movl(rsi, result_type);
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        __ cmpl(rsi, T_DOUBLE);
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        __ jcc(Assembler::equal, L_skip);
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        if (UseSSE == 0) {
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          // UseSSE == 0 so float result should be left on TOS
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          __ cmpl(rsi, T_FLOAT);
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          __ jcc(Assembler::equal, L_skip);
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        }
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        __ ffree(0);
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      }
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      __ BIND(L_skip);
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    }
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#endif // COMPILER2
1
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    // store result depending on type
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    // (everything that is not T_LONG, T_FLOAT or T_DOUBLE is treated as T_INT)
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    __ movptr(rdi, result);
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    Label is_long, is_float, is_double, exit;
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    __ movl(rsi, result_type);
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    __ cmpl(rsi, T_LONG);
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    __ jcc(Assembler::equal, is_long);
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    __ cmpl(rsi, T_FLOAT);
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    __ jcc(Assembler::equal, is_float);
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    __ cmpl(rsi, T_DOUBLE);
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    __ jcc(Assembler::equal, is_double);
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    // handle T_INT case
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    __ movl(Address(rdi, 0), rax);
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    __ BIND(exit);
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    // check that FPU stack is empty
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    __ verify_FPU(0, "generate_call_stub");
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    // pop parameters
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    __ lea(rsp, rsp_after_call);
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    // restore %mxcsr
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    if (sse_save) {
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      __ ldmxcsr(mxcsr_save);
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    }
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    // restore rdi, rsi and rbx,
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    __ movptr(rbx, saved_rbx);
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    __ movptr(rsi, saved_rsi);
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    __ movptr(rdi, saved_rdi);
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    __ addptr(rsp, 4*wordSize);
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    // return
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    __ pop(rbp);
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    __ ret(0);
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    // handle return types different from T_INT
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    __ BIND(is_long);
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    __ movl(Address(rdi, 0 * wordSize), rax);
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    __ movl(Address(rdi, 1 * wordSize), rdx);
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    __ jmp(exit);
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    __ BIND(is_float);
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    // interpreter uses xmm0 for return values
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    if (UseSSE >= 1) {
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      __ movflt(Address(rdi, 0), xmm0);
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    } else {
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      __ fstp_s(Address(rdi, 0));
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    }
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    __ jmp(exit);
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    __ BIND(is_double);
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    // interpreter uses xmm0 for return values
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    if (UseSSE >= 2) {
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      __ movdbl(Address(rdi, 0), xmm0);
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    } else {
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      __ fstp_d(Address(rdi, 0));
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    }
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    __ jmp(exit);
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    return start;
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  }
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  //------------------------------------------------------------------------------------------------------------------------
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  // Return point for a Java call if there's an exception thrown in Java code.
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  // The exception is caught and transformed into a pending exception stored in
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  // JavaThread that can be tested from within the VM.
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  //
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  // Note: Usually the parameters are removed by the callee. In case of an exception
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  //       crossing an activation frame boundary, that is not the case if the callee
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  //       is compiled code => need to setup the rsp.
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  //
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  // rax,: exception oop
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  address generate_catch_exception() {
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    StubCodeMark mark(this, "StubRoutines", "catch_exception");
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    const Address rsp_after_call(rbp, -4 * wordSize); // same as in generate_call_stub()!
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    const Address thread        (rbp,  9 * wordSize); // same as in generate_call_stub()!
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    address start = __ pc();
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    // get thread directly
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    __ movptr(rcx, thread);
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#ifdef ASSERT
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    // verify that threads correspond
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    { Label L;
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      __ get_thread(rbx);
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      __ cmpptr(rbx, rcx);
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      __ jcc(Assembler::equal, L);
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   357
      __ stop("StubRoutines::catch_exception: threads must correspond");
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      __ bind(L);
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    }
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#endif
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   361
    // set pending exception
489c9b5090e2 Initial load
duke
parents:
diff changeset
   362
    __ verify_oop(rax);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
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parents: 957
diff changeset
   363
    __ movptr(Address(rcx, Thread::pending_exception_offset()), rax          );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   364
    __ lea(Address(rcx, Thread::exception_file_offset   ()),
489c9b5090e2 Initial load
duke
parents:
diff changeset
   365
           ExternalAddress((address)__FILE__));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   366
    __ movl(Address(rcx, Thread::exception_line_offset   ()), __LINE__ );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   367
    // complete return to VM
489c9b5090e2 Initial load
duke
parents:
diff changeset
   368
    assert(StubRoutines::_call_stub_return_address != NULL, "_call_stub_return_address must have been generated before");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   369
    __ jump(RuntimeAddress(StubRoutines::_call_stub_return_address));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   370
489c9b5090e2 Initial load
duke
parents:
diff changeset
   371
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   372
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   373
489c9b5090e2 Initial load
duke
parents:
diff changeset
   374
489c9b5090e2 Initial load
duke
parents:
diff changeset
   375
  //------------------------------------------------------------------------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   376
  // Continuation point for runtime calls returning with a pending exception.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   377
  // The pending exception check happened in the runtime or native call stub.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   378
  // The pending exception in Thread is converted into a Java-level exception.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   379
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   380
  // Contract with Java-level exception handlers:
5046
27e801a857cb 6919934: JSR 292 needs to support x86 C1
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parents: 4740
diff changeset
   381
  // rax: exception
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   382
  // rdx: throwing pc
489c9b5090e2 Initial load
duke
parents:
diff changeset
   383
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   384
  // NOTE: At entry of this stub, exception-pc must be on stack !!
489c9b5090e2 Initial load
duke
parents:
diff changeset
   385
489c9b5090e2 Initial load
duke
parents:
diff changeset
   386
  address generate_forward_exception() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   387
    StubCodeMark mark(this, "StubRoutines", "forward exception");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   388
    address start = __ pc();
5046
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4740
diff changeset
   389
    const Register thread = rcx;
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4740
diff changeset
   390
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4740
diff changeset
   391
    // other registers used in this stub
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4740
diff changeset
   392
    const Register exception_oop = rax;
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4740
diff changeset
   393
    const Register handler_addr  = rbx;
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4740
diff changeset
   394
    const Register exception_pc  = rdx;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   395
489c9b5090e2 Initial load
duke
parents:
diff changeset
   396
    // Upon entry, the sp points to the return address returning into Java
489c9b5090e2 Initial load
duke
parents:
diff changeset
   397
    // (interpreted or compiled) code; i.e., the return address becomes the
489c9b5090e2 Initial load
duke
parents:
diff changeset
   398
    // throwing pc.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   399
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   400
    // Arguments pushed before the runtime call are still on the stack but
489c9b5090e2 Initial load
duke
parents:
diff changeset
   401
    // the exception handler will reset the stack pointer -> ignore them.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   402
    // A potential result in registers can be ignored as well.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   403
489c9b5090e2 Initial load
duke
parents:
diff changeset
   404
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   405
    // make sure this code is only executed if there is a pending exception
489c9b5090e2 Initial load
duke
parents:
diff changeset
   406
    { Label L;
5046
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4740
diff changeset
   407
      __ get_thread(thread);
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4740
diff changeset
   408
      __ cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   409
      __ jcc(Assembler::notEqual, L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   410
      __ stop("StubRoutines::forward exception: no pending exception (1)");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   411
      __ bind(L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   412
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   413
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   414
489c9b5090e2 Initial load
duke
parents:
diff changeset
   415
    // compute exception handler into rbx,
5046
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4740
diff changeset
   416
    __ get_thread(thread);
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4740
diff changeset
   417
    __ movptr(exception_pc, Address(rsp, 0));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   418
    BLOCK_COMMENT("call exception_handler_for_return_address");
5046
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4740
diff changeset
   419
    __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), thread, exception_pc);
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4740
diff changeset
   420
    __ mov(handler_addr, rax);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   421
5046
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4740
diff changeset
   422
    // setup rax & rdx, remove return address & clear pending exception
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4740
diff changeset
   423
    __ get_thread(thread);
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4740
diff changeset
   424
    __ pop(exception_pc);
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4740
diff changeset
   425
    __ movptr(exception_oop, Address(thread, Thread::pending_exception_offset()));
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4740
diff changeset
   426
    __ movptr(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   427
489c9b5090e2 Initial load
duke
parents:
diff changeset
   428
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   429
    // make sure exception is set
489c9b5090e2 Initial load
duke
parents:
diff changeset
   430
    { Label L;
5046
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4740
diff changeset
   431
      __ testptr(exception_oop, exception_oop);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   432
      __ jcc(Assembler::notEqual, L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   433
      __ stop("StubRoutines::forward exception: no pending exception (2)");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   434
      __ bind(L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   435
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   436
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   437
5046
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4740
diff changeset
   438
    // Verify that there is really a valid exception in RAX.
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4740
diff changeset
   439
    __ verify_oop(exception_oop);
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4740
diff changeset
   440
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   441
    // continue at exception handler (return address removed)
5046
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4740
diff changeset
   442
    // rax: exception
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4740
diff changeset
   443
    // rbx: exception handler
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   444
    // rdx: throwing pc
5046
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4740
diff changeset
   445
    __ jmp(handler_addr);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   446
489c9b5090e2 Initial load
duke
parents:
diff changeset
   447
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   448
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   449
489c9b5090e2 Initial load
duke
parents:
diff changeset
   450
489c9b5090e2 Initial load
duke
parents:
diff changeset
   451
  //----------------------------------------------------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   452
  // Support for jint Atomic::xchg(jint exchange_value, volatile jint* dest)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   453
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   454
  // xchg exists as far back as 8086, lock needed for MP only
489c9b5090e2 Initial load
duke
parents:
diff changeset
   455
  // Stack layout immediately after call:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   456
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   457
  // 0 [ret addr ] <--- rsp
489c9b5090e2 Initial load
duke
parents:
diff changeset
   458
  // 1 [  ex     ]
489c9b5090e2 Initial load
duke
parents:
diff changeset
   459
  // 2 [  dest   ]
489c9b5090e2 Initial load
duke
parents:
diff changeset
   460
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   461
  // Result:   *dest <- ex, return (old *dest)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   462
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   463
  // Note: win32 does not currently use this code
489c9b5090e2 Initial load
duke
parents:
diff changeset
   464
489c9b5090e2 Initial load
duke
parents:
diff changeset
   465
  address generate_atomic_xchg() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   466
    StubCodeMark mark(this, "StubRoutines", "atomic_xchg");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   467
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   468
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   469
    __ push(rdx);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   470
    Address exchange(rsp, 2 * wordSize);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   471
    Address dest_addr(rsp, 3 * wordSize);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   472
    __ movl(rax, exchange);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   473
    __ movptr(rdx, dest_addr);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   474
    __ xchgl(rax, Address(rdx, 0));
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   475
    __ pop(rdx);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   476
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   477
489c9b5090e2 Initial load
duke
parents:
diff changeset
   478
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   479
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   480
489c9b5090e2 Initial load
duke
parents:
diff changeset
   481
  //----------------------------------------------------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   482
  // Support for void verify_mxcsr()
489c9b5090e2 Initial load
duke
parents:
diff changeset
   483
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   484
  // This routine is used with -Xcheck:jni to verify that native
489c9b5090e2 Initial load
duke
parents:
diff changeset
   485
  // JNI code does not return to Java code without restoring the
489c9b5090e2 Initial load
duke
parents:
diff changeset
   486
  // MXCSR register to our expected state.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   487
489c9b5090e2 Initial load
duke
parents:
diff changeset
   488
489c9b5090e2 Initial load
duke
parents:
diff changeset
   489
  address generate_verify_mxcsr() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   490
    StubCodeMark mark(this, "StubRoutines", "verify_mxcsr");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   491
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   492
489c9b5090e2 Initial load
duke
parents:
diff changeset
   493
    const Address mxcsr_save(rsp, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   494
489c9b5090e2 Initial load
duke
parents:
diff changeset
   495
    if (CheckJNICalls && UseSSE > 0 ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   496
      Label ok_ret;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   497
      ExternalAddress mxcsr_std(StubRoutines::addr_mxcsr_std());
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   498
      __ push(rax);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   499
      __ subptr(rsp, wordSize);      // allocate a temp location
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   500
      __ stmxcsr(mxcsr_save);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   501
      __ movl(rax, mxcsr_save);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   502
      __ andl(rax, MXCSR_MASK);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   503
      __ cmp32(rax, mxcsr_std);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   504
      __ jcc(Assembler::equal, ok_ret);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   505
489c9b5090e2 Initial load
duke
parents:
diff changeset
   506
      __ warn("MXCSR changed by native JNI code.");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   507
489c9b5090e2 Initial load
duke
parents:
diff changeset
   508
      __ ldmxcsr(mxcsr_std);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   509
489c9b5090e2 Initial load
duke
parents:
diff changeset
   510
      __ bind(ok_ret);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   511
      __ addptr(rsp, wordSize);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   512
      __ pop(rax);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   513
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   514
489c9b5090e2 Initial load
duke
parents:
diff changeset
   515
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   516
489c9b5090e2 Initial load
duke
parents:
diff changeset
   517
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   518
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   519
489c9b5090e2 Initial load
duke
parents:
diff changeset
   520
489c9b5090e2 Initial load
duke
parents:
diff changeset
   521
  //---------------------------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   522
  // Support for void verify_fpu_cntrl_wrd()
489c9b5090e2 Initial load
duke
parents:
diff changeset
   523
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   524
  // This routine is used with -Xcheck:jni to verify that native
489c9b5090e2 Initial load
duke
parents:
diff changeset
   525
  // JNI code does not return to Java code without restoring the
489c9b5090e2 Initial load
duke
parents:
diff changeset
   526
  // FP control word to our expected state.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   527
489c9b5090e2 Initial load
duke
parents:
diff changeset
   528
  address generate_verify_fpu_cntrl_wrd() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   529
    StubCodeMark mark(this, "StubRoutines", "verify_spcw");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   530
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   531
489c9b5090e2 Initial load
duke
parents:
diff changeset
   532
    const Address fpu_cntrl_wrd_save(rsp, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   533
489c9b5090e2 Initial load
duke
parents:
diff changeset
   534
    if (CheckJNICalls) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   535
      Label ok_ret;
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   536
      __ push(rax);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   537
      __ subptr(rsp, wordSize);      // allocate a temp location
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   538
      __ fnstcw(fpu_cntrl_wrd_save);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   539
      __ movl(rax, fpu_cntrl_wrd_save);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   540
      __ andl(rax, FPU_CNTRL_WRD_MASK);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   541
      ExternalAddress fpu_std(StubRoutines::addr_fpu_cntrl_wrd_std());
489c9b5090e2 Initial load
duke
parents:
diff changeset
   542
      __ cmp32(rax, fpu_std);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   543
      __ jcc(Assembler::equal, ok_ret);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   544
489c9b5090e2 Initial load
duke
parents:
diff changeset
   545
      __ warn("Floating point control word changed by native JNI code.");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   546
489c9b5090e2 Initial load
duke
parents:
diff changeset
   547
      __ fldcw(fpu_std);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   548
489c9b5090e2 Initial load
duke
parents:
diff changeset
   549
      __ bind(ok_ret);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   550
      __ addptr(rsp, wordSize);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   551
      __ pop(rax);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   552
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   553
489c9b5090e2 Initial load
duke
parents:
diff changeset
   554
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   555
489c9b5090e2 Initial load
duke
parents:
diff changeset
   556
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   557
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   558
489c9b5090e2 Initial load
duke
parents:
diff changeset
   559
  //---------------------------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   560
  // Wrapper for slow-case handling of double-to-integer conversion
489c9b5090e2 Initial load
duke
parents:
diff changeset
   561
  // d2i or f2i fast case failed either because it is nan or because
489c9b5090e2 Initial load
duke
parents:
diff changeset
   562
  // of under/overflow.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   563
  // Input:  FPU TOS: float value
489c9b5090e2 Initial load
duke
parents:
diff changeset
   564
  // Output: rax, (rdx): integer (long) result
489c9b5090e2 Initial load
duke
parents:
diff changeset
   565
489c9b5090e2 Initial load
duke
parents:
diff changeset
   566
  address generate_d2i_wrapper(BasicType t, address fcn) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   567
    StubCodeMark mark(this, "StubRoutines", "d2i_wrapper");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   568
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   569
489c9b5090e2 Initial load
duke
parents:
diff changeset
   570
  // Capture info about frame layout
489c9b5090e2 Initial load
duke
parents:
diff changeset
   571
  enum layout { FPUState_off         = 0,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   572
                rbp_off              = FPUStateSizeInWords,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   573
                rdi_off,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   574
                rsi_off,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   575
                rcx_off,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   576
                rbx_off,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   577
                saved_argument_off,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   578
                saved_argument_off2, // 2nd half of double
489c9b5090e2 Initial load
duke
parents:
diff changeset
   579
                framesize
489c9b5090e2 Initial load
duke
parents:
diff changeset
   580
  };
489c9b5090e2 Initial load
duke
parents:
diff changeset
   581
489c9b5090e2 Initial load
duke
parents:
diff changeset
   582
  assert(FPUStateSizeInWords == 27, "update stack layout");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   583
489c9b5090e2 Initial load
duke
parents:
diff changeset
   584
    // Save outgoing argument to stack across push_FPU_state()
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   585
    __ subptr(rsp, wordSize * 2);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   586
    __ fstp_d(Address(rsp, 0));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   587
489c9b5090e2 Initial load
duke
parents:
diff changeset
   588
    // Save CPU & FPU state
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   589
    __ push(rbx);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   590
    __ push(rcx);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   591
    __ push(rsi);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   592
    __ push(rdi);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   593
    __ push(rbp);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   594
    __ push_FPU_state();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   595
489c9b5090e2 Initial load
duke
parents:
diff changeset
   596
    // push_FPU_state() resets the FP top of stack
489c9b5090e2 Initial load
duke
parents:
diff changeset
   597
    // Load original double into FP top of stack
489c9b5090e2 Initial load
duke
parents:
diff changeset
   598
    __ fld_d(Address(rsp, saved_argument_off * wordSize));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   599
    // Store double into stack as outgoing argument
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   600
    __ subptr(rsp, wordSize*2);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   601
    __ fst_d(Address(rsp, 0));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   602
489c9b5090e2 Initial load
duke
parents:
diff changeset
   603
    // Prepare FPU for doing math in C-land
489c9b5090e2 Initial load
duke
parents:
diff changeset
   604
    __ empty_FPU_stack();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   605
    // Call the C code to massage the double.  Result in EAX
489c9b5090e2 Initial load
duke
parents:
diff changeset
   606
    if (t == T_INT)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   607
      { BLOCK_COMMENT("SharedRuntime::d2i"); }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   608
    else if (t == T_LONG)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   609
      { BLOCK_COMMENT("SharedRuntime::d2l"); }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   610
    __ call_VM_leaf( fcn, 2 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   611
489c9b5090e2 Initial load
duke
parents:
diff changeset
   612
    // Restore CPU & FPU state
489c9b5090e2 Initial load
duke
parents:
diff changeset
   613
    __ pop_FPU_state();
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   614
    __ pop(rbp);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   615
    __ pop(rdi);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   616
    __ pop(rsi);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   617
    __ pop(rcx);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   618
    __ pop(rbx);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   619
    __ addptr(rsp, wordSize * 2);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   620
489c9b5090e2 Initial load
duke
parents:
diff changeset
   621
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   622
489c9b5090e2 Initial load
duke
parents:
diff changeset
   623
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   624
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   625
489c9b5090e2 Initial load
duke
parents:
diff changeset
   626
489c9b5090e2 Initial load
duke
parents:
diff changeset
   627
  //---------------------------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   628
  // The following routine generates a subroutine to throw an asynchronous
489c9b5090e2 Initial load
duke
parents:
diff changeset
   629
  // UnknownError when an unsafe access gets a fault that could not be
489c9b5090e2 Initial load
duke
parents:
diff changeset
   630
  // reasonably prevented by the programmer.  (Example: SIGBUS/OBJERR.)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   631
  address generate_handler_for_unsafe_access() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   632
    StubCodeMark mark(this, "StubRoutines", "handler_for_unsafe_access");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   633
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   634
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   635
    __ push(0);                       // hole for return address-to-be
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   636
    __ pusha();                       // push registers
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   637
    Address next_pc(rsp, RegisterImpl::number_of_registers * BytesPerWord);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   638
    BLOCK_COMMENT("call handle_unsafe_access");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   639
    __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, handle_unsafe_access)));
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   640
    __ movptr(next_pc, rax);          // stuff next address
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   641
    __ popa();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   642
    __ ret(0);                        // jump to next address
489c9b5090e2 Initial load
duke
parents:
diff changeset
   643
489c9b5090e2 Initial load
duke
parents:
diff changeset
   644
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   645
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   646
489c9b5090e2 Initial load
duke
parents:
diff changeset
   647
489c9b5090e2 Initial load
duke
parents:
diff changeset
   648
  //----------------------------------------------------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   649
  // Non-destructive plausibility checks for oops
489c9b5090e2 Initial load
duke
parents:
diff changeset
   650
489c9b5090e2 Initial load
duke
parents:
diff changeset
   651
  address generate_verify_oop() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   652
    StubCodeMark mark(this, "StubRoutines", "verify_oop");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   653
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   654
489c9b5090e2 Initial load
duke
parents:
diff changeset
   655
    // Incoming arguments on stack after saving rax,:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   656
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   657
    // [tos    ]: saved rdx
489c9b5090e2 Initial load
duke
parents:
diff changeset
   658
    // [tos + 1]: saved EFLAGS
489c9b5090e2 Initial load
duke
parents:
diff changeset
   659
    // [tos + 2]: return address
489c9b5090e2 Initial load
duke
parents:
diff changeset
   660
    // [tos + 3]: char* error message
489c9b5090e2 Initial load
duke
parents:
diff changeset
   661
    // [tos + 4]: oop   object to verify
489c9b5090e2 Initial load
duke
parents:
diff changeset
   662
    // [tos + 5]: saved rax, - saved by caller and bashed
489c9b5090e2 Initial load
duke
parents:
diff changeset
   663
489c9b5090e2 Initial load
duke
parents:
diff changeset
   664
    Label exit, error;
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   665
    __ pushf();
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   666
    __ incrementl(ExternalAddress((address) StubRoutines::verify_oop_count_addr()));
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   667
    __ push(rdx);                                // save rdx
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   668
    // make sure object is 'reasonable'
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   669
    __ movptr(rax, Address(rsp, 4 * wordSize));    // get object
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   670
    __ testptr(rax, rax);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   671
    __ jcc(Assembler::zero, exit);               // if obj is NULL it is ok
489c9b5090e2 Initial load
duke
parents:
diff changeset
   672
489c9b5090e2 Initial load
duke
parents:
diff changeset
   673
    // Check if the oop is in the right area of memory
489c9b5090e2 Initial load
duke
parents:
diff changeset
   674
    const int oop_mask = Universe::verify_oop_mask();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   675
    const int oop_bits = Universe::verify_oop_bits();
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   676
    __ mov(rdx, rax);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   677
    __ andptr(rdx, oop_mask);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   678
    __ cmpptr(rdx, oop_bits);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   679
    __ jcc(Assembler::notZero, error);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   680
13728
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 13391
diff changeset
   681
    // make sure klass is 'reasonable', which is not zero.
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   682
    __ movptr(rax, Address(rax, oopDesc::klass_offset_in_bytes())); // get klass
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   683
    __ testptr(rax, rax);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   684
    __ jcc(Assembler::zero, error);              // if klass is NULL it is broken
489c9b5090e2 Initial load
duke
parents:
diff changeset
   685
489c9b5090e2 Initial load
duke
parents:
diff changeset
   686
    // return if everything seems ok
489c9b5090e2 Initial load
duke
parents:
diff changeset
   687
    __ bind(exit);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   688
    __ movptr(rax, Address(rsp, 5 * wordSize));  // get saved rax, back
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   689
    __ pop(rdx);                                 // restore rdx
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   690
    __ popf();                                   // restore EFLAGS
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   691
    __ ret(3 * wordSize);                        // pop arguments
489c9b5090e2 Initial load
duke
parents:
diff changeset
   692
489c9b5090e2 Initial load
duke
parents:
diff changeset
   693
    // handle errors
489c9b5090e2 Initial load
duke
parents:
diff changeset
   694
    __ bind(error);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   695
    __ movptr(rax, Address(rsp, 5 * wordSize));  // get saved rax, back
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   696
    __ pop(rdx);                                 // get saved rdx back
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   697
    __ popf();                                   // get saved EFLAGS off stack -- will be ignored
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   698
    __ pusha();                                  // push registers (eip = return address & msg are already pushed)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   699
    BLOCK_COMMENT("call MacroAssembler::debug");
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   700
    __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   701
    __ popa();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   702
    __ ret(3 * wordSize);                        // pop arguments
489c9b5090e2 Initial load
duke
parents:
diff changeset
   703
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   704
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   705
489c9b5090e2 Initial load
duke
parents:
diff changeset
   706
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   707
  //  Generate pre-barrier for array stores
489c9b5090e2 Initial load
duke
parents:
diff changeset
   708
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   709
  //  Input:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   710
  //     start   -  starting address
3262
30d1c247fc25 6700789: G1: Enable use of compressed oops with G1 heaps
ysr
parents: 2534
diff changeset
   711
  //     count   -  element count
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
   712
  void  gen_write_ref_array_pre_barrier(Register start, Register count, bool uninitialized_target) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   713
    assert_different_registers(start, count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   714
    BarrierSet* bs = Universe::heap()->barrier_set();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   715
    switch (bs->kind()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   716
      case BarrierSet::G1SATBCTLogging:
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
   717
        // With G1, don't generate the call if we statically know that the target in uninitialized
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
   718
        if (!uninitialized_target) {
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
   719
           __ pusha();                      // push registers
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
   720
           __ call_VM_leaf(CAST_FROM_FN_PTR(address, BarrierSet::static_write_ref_array_pre),
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
   721
                           start, count);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
   722
           __ popa();
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
   723
         }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   724
        break;
32596
8feecdee3156 8072817: CardTableExtension kind() should be BarrierSet::CardTableExtension
kbarrett
parents: 31771
diff changeset
   725
      case BarrierSet::CardTableForRS:
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   726
      case BarrierSet::CardTableExtension:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   727
      case BarrierSet::ModRef:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   728
        break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   729
      default      :
489c9b5090e2 Initial load
duke
parents:
diff changeset
   730
        ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   731
489c9b5090e2 Initial load
duke
parents:
diff changeset
   732
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   733
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   734
489c9b5090e2 Initial load
duke
parents:
diff changeset
   735
489c9b5090e2 Initial load
duke
parents:
diff changeset
   736
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   737
  // Generate a post-barrier for an array store
489c9b5090e2 Initial load
duke
parents:
diff changeset
   738
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   739
  //     start    -  starting address
489c9b5090e2 Initial load
duke
parents:
diff changeset
   740
  //     count    -  element count
489c9b5090e2 Initial load
duke
parents:
diff changeset
   741
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   742
  //  The two input registers are overwritten.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   743
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   744
  void  gen_write_ref_array_post_barrier(Register start, Register count) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   745
    BarrierSet* bs = Universe::heap()->barrier_set();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   746
    assert_different_registers(start, count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   747
    switch (bs->kind()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   748
      case BarrierSet::G1SATBCTLogging:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   749
        {
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   750
          __ pusha();                      // push registers
4740
d708800308b7 6918006: G1: spill space must be reserved on the stack for barrier calls on Windows x64
apetrusenko
parents: 4645
diff changeset
   751
          __ call_VM_leaf(CAST_FROM_FN_PTR(address, BarrierSet::static_write_ref_array_post),
d708800308b7 6918006: G1: spill space must be reserved on the stack for barrier calls on Windows x64
apetrusenko
parents: 4645
diff changeset
   752
                          start, count);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   753
          __ popa();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   754
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   755
        break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   756
32596
8feecdee3156 8072817: CardTableExtension kind() should be BarrierSet::CardTableExtension
kbarrett
parents: 31771
diff changeset
   757
      case BarrierSet::CardTableForRS:
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   758
      case BarrierSet::CardTableExtension:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   759
        {
29325
0e86e64c66e5 8069016: Add BarrierSet downcast support
kbarrett
parents: 22505
diff changeset
   760
          CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   761
          assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   762
489c9b5090e2 Initial load
duke
parents:
diff changeset
   763
          Label L_loop;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   764
          const Register end = count;  // elements count; end == start+count-1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   765
          assert_different_registers(start, end);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   766
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   767
          __ lea(end,  Address(start, count, Address::times_ptr, -wordSize));
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   768
          __ shrptr(start, CardTableModRefBS::card_shift);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   769
          __ shrptr(end,   CardTableModRefBS::card_shift);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   770
          __ subptr(end, start); // end --> count
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   771
        __ BIND(L_loop);
957
386f9fbd4cb3 6717457: Internal Error (src/share/vm/code/relocInfo.hpp:1089)
never
parents: 192
diff changeset
   772
          intptr_t disp = (intptr_t) ct->byte_map_base;
386f9fbd4cb3 6717457: Internal Error (src/share/vm/code/relocInfo.hpp:1089)
never
parents: 192
diff changeset
   773
          Address cardtable(start, count, Address::times_1, disp);
386f9fbd4cb3 6717457: Internal Error (src/share/vm/code/relocInfo.hpp:1089)
never
parents: 192
diff changeset
   774
          __ movb(cardtable, 0);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   775
          __ decrement(count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   776
          __ jcc(Assembler::greaterEqual, L_loop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   777
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   778
        break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   779
      case BarrierSet::ModRef:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   780
        break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   781
      default      :
489c9b5090e2 Initial load
duke
parents:
diff changeset
   782
        ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   783
489c9b5090e2 Initial load
duke
parents:
diff changeset
   784
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   785
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   786
1437
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   787
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   788
  // Copy 64 bytes chunks
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   789
  //
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   790
  // Inputs:
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   791
  //   from        - source array address
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   792
  //   to_from     - destination array address - from
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   793
  //   qword_count - 8-bytes element count, negative
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   794
  //
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   795
  void xmm_copy_forward(Register from, Register to_from, Register qword_count) {
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   796
    assert( UseSSE >= 2, "supported cpu only" );
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   797
    Label L_copy_64_bytes_loop, L_copy_64_bytes, L_copy_8_bytes, L_exit;
32727
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
   798
    if (UseAVX > 2) {
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
   799
      __ push(rbx);
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
   800
      __ movl(rbx, 0xffff);
35113
b11bd150ed8a 8144771: Use AVX3 instructions for string compare
kvn
parents: 33465
diff changeset
   801
      __ kmovwl(k1, rbx);
32727
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
   802
      __ pop(rbx);
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
   803
    }
1437
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   804
    // Copy 64-byte chunks
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   805
    __ jmpb(L_copy_64_bytes);
5249
5cac34e6fe54 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 5050
diff changeset
   806
    __ align(OptoLoopAlignment);
1437
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   807
  __ BIND(L_copy_64_bytes_loop);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   808
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
   809
    if (UseUnalignedLoadStores) {
30624
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30299
diff changeset
   810
      if (UseAVX > 2) {
32727
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
   811
        __ evmovdqul(xmm0, Address(from, 0), Assembler::AVX_512bit);
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
   812
        __ evmovdqul(Address(from, to_from, Address::times_1, 0), xmm0, Assembler::AVX_512bit);
30624
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30299
diff changeset
   813
      } else if (UseAVX == 2) {
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
   814
        __ vmovdqu(xmm0, Address(from,  0));
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
   815
        __ vmovdqu(Address(from, to_from, Address::times_1,  0), xmm0);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
   816
        __ vmovdqu(xmm1, Address(from, 32));
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
   817
        __ vmovdqu(Address(from, to_from, Address::times_1, 32), xmm1);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
   818
      } else {
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
   819
        __ movdqu(xmm0, Address(from, 0));
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
   820
        __ movdqu(Address(from, to_from, Address::times_1, 0), xmm0);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
   821
        __ movdqu(xmm1, Address(from, 16));
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
   822
        __ movdqu(Address(from, to_from, Address::times_1, 16), xmm1);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
   823
        __ movdqu(xmm2, Address(from, 32));
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
   824
        __ movdqu(Address(from, to_from, Address::times_1, 32), xmm2);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
   825
        __ movdqu(xmm3, Address(from, 48));
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
   826
        __ movdqu(Address(from, to_from, Address::times_1, 48), xmm3);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
   827
      }
1437
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   828
    } else {
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   829
      __ movq(xmm0, Address(from, 0));
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   830
      __ movq(Address(from, to_from, Address::times_1, 0), xmm0);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   831
      __ movq(xmm1, Address(from, 8));
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   832
      __ movq(Address(from, to_from, Address::times_1, 8), xmm1);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   833
      __ movq(xmm2, Address(from, 16));
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   834
      __ movq(Address(from, to_from, Address::times_1, 16), xmm2);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   835
      __ movq(xmm3, Address(from, 24));
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   836
      __ movq(Address(from, to_from, Address::times_1, 24), xmm3);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   837
      __ movq(xmm4, Address(from, 32));
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   838
      __ movq(Address(from, to_from, Address::times_1, 32), xmm4);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   839
      __ movq(xmm5, Address(from, 40));
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   840
      __ movq(Address(from, to_from, Address::times_1, 40), xmm5);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   841
      __ movq(xmm6, Address(from, 48));
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   842
      __ movq(Address(from, to_from, Address::times_1, 48), xmm6);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   843
      __ movq(xmm7, Address(from, 56));
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   844
      __ movq(Address(from, to_from, Address::times_1, 56), xmm7);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   845
    }
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   846
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   847
    __ addl(from, 64);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   848
  __ BIND(L_copy_64_bytes);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   849
    __ subl(qword_count, 8);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   850
    __ jcc(Assembler::greaterEqual, L_copy_64_bytes_loop);
16624
9dbd4b210bf9 8011102: Clear AVX registers after return from JNI call
kvn
parents: 15115
diff changeset
   851
30624
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30299
diff changeset
   852
    if (UseUnalignedLoadStores && (UseAVX == 2)) {
16624
9dbd4b210bf9 8011102: Clear AVX registers after return from JNI call
kvn
parents: 15115
diff changeset
   853
      // clean upper bits of YMM registers
30299
1f6f7d1e0c1e 8078113: 8011102 changes may cause incorrect results
kvn
parents: 29695
diff changeset
   854
      __ vpxor(xmm0, xmm0);
1f6f7d1e0c1e 8078113: 8011102 changes may cause incorrect results
kvn
parents: 29695
diff changeset
   855
      __ vpxor(xmm1, xmm1);
16624
9dbd4b210bf9 8011102: Clear AVX registers after return from JNI call
kvn
parents: 15115
diff changeset
   856
    }
1437
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   857
    __ addl(qword_count, 8);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   858
    __ jccb(Assembler::zero, L_exit);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   859
    //
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   860
    // length is too short, just copy qwords
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   861
    //
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   862
  __ BIND(L_copy_8_bytes);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   863
    __ movq(xmm0, Address(from, 0));
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   864
    __ movq(Address(from, to_from, Address::times_1), xmm0);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   865
    __ addl(from, 8);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   866
    __ decrement(qword_count);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   867
    __ jcc(Assembler::greater, L_copy_8_bytes);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   868
  __ BIND(L_exit);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   869
  }
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   870
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   871
  // Copy 64 bytes chunks
489c9b5090e2 Initial load
duke
parents:
diff changeset
   872
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   873
  // Inputs:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   874
  //   from        - source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
   875
  //   to_from     - destination array address - from
489c9b5090e2 Initial load
duke
parents:
diff changeset
   876
  //   qword_count - 8-bytes element count, negative
489c9b5090e2 Initial load
duke
parents:
diff changeset
   877
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   878
  void mmx_copy_forward(Register from, Register to_from, Register qword_count) {
1437
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   879
    assert( VM_Version::supports_mmx(), "supported cpu only" );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   880
    Label L_copy_64_bytes_loop, L_copy_64_bytes, L_copy_8_bytes, L_exit;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   881
    // Copy 64-byte chunks
489c9b5090e2 Initial load
duke
parents:
diff changeset
   882
    __ jmpb(L_copy_64_bytes);
5249
5cac34e6fe54 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 5050
diff changeset
   883
    __ align(OptoLoopAlignment);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   884
  __ BIND(L_copy_64_bytes_loop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   885
    __ movq(mmx0, Address(from, 0));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   886
    __ movq(mmx1, Address(from, 8));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   887
    __ movq(mmx2, Address(from, 16));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   888
    __ movq(Address(from, to_from, Address::times_1, 0), mmx0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   889
    __ movq(mmx3, Address(from, 24));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   890
    __ movq(Address(from, to_from, Address::times_1, 8), mmx1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   891
    __ movq(mmx4, Address(from, 32));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   892
    __ movq(Address(from, to_from, Address::times_1, 16), mmx2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   893
    __ movq(mmx5, Address(from, 40));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   894
    __ movq(Address(from, to_from, Address::times_1, 24), mmx3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   895
    __ movq(mmx6, Address(from, 48));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   896
    __ movq(Address(from, to_from, Address::times_1, 32), mmx4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   897
    __ movq(mmx7, Address(from, 56));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   898
    __ movq(Address(from, to_from, Address::times_1, 40), mmx5);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   899
    __ movq(Address(from, to_from, Address::times_1, 48), mmx6);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   900
    __ movq(Address(from, to_from, Address::times_1, 56), mmx7);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   901
    __ addptr(from, 64);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   902
  __ BIND(L_copy_64_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   903
    __ subl(qword_count, 8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   904
    __ jcc(Assembler::greaterEqual, L_copy_64_bytes_loop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   905
    __ addl(qword_count, 8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   906
    __ jccb(Assembler::zero, L_exit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   907
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   908
    // length is too short, just copy qwords
489c9b5090e2 Initial load
duke
parents:
diff changeset
   909
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   910
  __ BIND(L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   911
    __ movq(mmx0, Address(from, 0));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   912
    __ movq(Address(from, to_from, Address::times_1), mmx0);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   913
    __ addptr(from, 8);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   914
    __ decrement(qword_count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   915
    __ jcc(Assembler::greater, L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   916
  __ BIND(L_exit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   917
    __ emms();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   918
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   919
489c9b5090e2 Initial load
duke
parents:
diff changeset
   920
  address generate_disjoint_copy(BasicType t, bool aligned,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   921
                                 Address::ScaleFactor sf,
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
   922
                                 address* entry, const char *name,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
   923
                                 bool dest_uninitialized = false) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   924
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   925
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   926
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   927
489c9b5090e2 Initial load
duke
parents:
diff changeset
   928
    Label L_0_count, L_exit, L_skip_align1, L_skip_align2, L_copy_byte;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   929
    Label L_copy_2_bytes, L_copy_4_bytes, L_copy_64_bytes;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   930
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   931
    int shift = Address::times_ptr - sf;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   932
489c9b5090e2 Initial load
duke
parents:
diff changeset
   933
    const Register from     = rsi;  // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
   934
    const Register to       = rdi;  // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
   935
    const Register count    = rcx;  // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
   936
    const Register to_from  = to;   // (to - from)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   937
    const Register saved_to = rdx;  // saved destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
   938
489c9b5090e2 Initial load
duke
parents:
diff changeset
   939
    __ enter(); // required for proper stackwalking of RuntimeStub frame
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   940
    __ push(rsi);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   941
    __ push(rdi);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   942
    __ movptr(from , Address(rsp, 12+ 4));
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   943
    __ movptr(to   , Address(rsp, 12+ 8));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   944
    __ movl(count, Address(rsp, 12+ 12));
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 8315
diff changeset
   945
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 8315
diff changeset
   946
    if (entry != NULL) {
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 8315
diff changeset
   947
      *entry = __ pc(); // Entry point from conjoint arraycopy stub.
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 8315
diff changeset
   948
      BLOCK_COMMENT("Entry:");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 8315
diff changeset
   949
    }
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 8315
diff changeset
   950
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   951
    if (t == T_OBJECT) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   952
      __ testl(count, count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   953
      __ jcc(Assembler::zero, L_0_count);
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
   954
      gen_write_ref_array_pre_barrier(to, count, dest_uninitialized);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   955
      __ mov(saved_to, to);          // save 'to'
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   956
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   957
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   958
    __ subptr(to, from); // to --> to_from
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   959
    __ cmpl(count, 2<<shift); // Short arrays (< 8 bytes) copy by element
489c9b5090e2 Initial load
duke
parents:
diff changeset
   960
    __ jcc(Assembler::below, L_copy_4_bytes); // use unsigned cmp
1437
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   961
    if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   962
      // align source address at 4 bytes address boundary
489c9b5090e2 Initial load
duke
parents:
diff changeset
   963
      if (t == T_BYTE) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   964
        // One byte misalignment happens only for byte arrays
489c9b5090e2 Initial load
duke
parents:
diff changeset
   965
        __ testl(from, 1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   966
        __ jccb(Assembler::zero, L_skip_align1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   967
        __ movb(rax, Address(from, 0));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   968
        __ movb(Address(from, to_from, Address::times_1, 0), rax);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   969
        __ increment(from);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   970
        __ decrement(count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   971
      __ BIND(L_skip_align1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   972
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   973
      // Two bytes misalignment happens only for byte and short (char) arrays
489c9b5090e2 Initial load
duke
parents:
diff changeset
   974
      __ testl(from, 2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   975
      __ jccb(Assembler::zero, L_skip_align2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   976
      __ movw(rax, Address(from, 0));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   977
      __ movw(Address(from, to_from, Address::times_1, 0), rax);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   978
      __ addptr(from, 2);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   979
      __ subl(count, 1<<(shift-1));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   980
    __ BIND(L_skip_align2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   981
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   982
    if (!VM_Version::supports_mmx()) {
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   983
      __ mov(rax, count);      // save 'count'
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   984
      __ shrl(count, shift); // bytes count
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   985
      __ addptr(to_from, from);// restore 'to'
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   986
      __ rep_mov();
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   987
      __ subptr(to_from, from);// restore 'to_from'
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   988
      __ mov(count, rax);      // restore 'count'
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   989
      __ jmpb(L_copy_2_bytes); // all dwords were copied
489c9b5090e2 Initial load
duke
parents:
diff changeset
   990
    } else {
1437
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   991
      if (!UseUnalignedLoadStores) {
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   992
        // align to 8 bytes, we know we are 4 byte aligned to start
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   993
        __ testptr(from, 4);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   994
        __ jccb(Assembler::zero, L_copy_64_bytes);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   995
        __ movl(rax, Address(from, 0));
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   996
        __ movl(Address(from, to_from, Address::times_1, 0), rax);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   997
        __ addptr(from, 4);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   998
        __ subl(count, 1<<shift);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
   999
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1000
    __ BIND(L_copy_64_bytes);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1001
      __ mov(rax, count);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1002
      __ shrl(rax, shift+1);  // 8 bytes chunk count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1003
      //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1004
      // Copy 8-byte chunks through MMX registers, 8 per iteration of the loop
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1005
      //
1437
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1006
      if (UseXMMForArrayCopy) {
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1007
        xmm_copy_forward(from, to_from, rax);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1008
      } else {
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1009
        mmx_copy_forward(from, to_from, rax);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1010
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1011
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1012
    // copy tailing dword
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1013
  __ BIND(L_copy_4_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1014
    __ testl(count, 1<<shift);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1015
    __ jccb(Assembler::zero, L_copy_2_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1016
    __ movl(rax, Address(from, 0));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1017
    __ movl(Address(from, to_from, Address::times_1, 0), rax);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1018
    if (t == T_BYTE || t == T_SHORT) {
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1019
      __ addptr(from, 4);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1020
    __ BIND(L_copy_2_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1021
      // copy tailing word
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1022
      __ testl(count, 1<<(shift-1));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1023
      __ jccb(Assembler::zero, L_copy_byte);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1024
      __ movw(rax, Address(from, 0));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1025
      __ movw(Address(from, to_from, Address::times_1, 0), rax);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1026
      if (t == T_BYTE) {
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1027
        __ addptr(from, 2);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1028
      __ BIND(L_copy_byte);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1029
        // copy tailing byte
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1030
        __ testl(count, 1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1031
        __ jccb(Assembler::zero, L_exit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1032
        __ movb(rax, Address(from, 0));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1033
        __ movb(Address(from, to_from, Address::times_1, 0), rax);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1034
      __ BIND(L_exit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1035
      } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1036
      __ BIND(L_copy_byte);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1037
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1038
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1039
    __ BIND(L_copy_2_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1040
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1041
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1042
    if (t == T_OBJECT) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1043
      __ movl(count, Address(rsp, 12+12)); // reread 'count'
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1044
      __ mov(to, saved_to); // restore 'to'
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1045
      gen_write_ref_array_post_barrier(to, count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1046
    __ BIND(L_0_count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1047
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1048
    inc_copy_counter_np(t);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1049
    __ pop(rdi);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1050
    __ pop(rsi);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1051
    __ leave(); // required for proper stackwalking of RuntimeStub frame
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1052
    __ xorptr(rax, rax); // return 0
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1053
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1054
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1055
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1056
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1057
6433
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1058
  address generate_fill(BasicType t, bool aligned, const char *name) {
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1059
    __ align(CodeEntryAlignment);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1060
    StubCodeMark mark(this, "StubRoutines", name);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1061
    address start = __ pc();
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1062
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1063
    BLOCK_COMMENT("Entry:");
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1064
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1065
    const Register to       = rdi;  // source array address
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1066
    const Register value    = rdx;  // value
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1067
    const Register count    = rsi;  // elements count
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1068
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1069
    __ enter(); // required for proper stackwalking of RuntimeStub frame
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1070
    __ push(rsi);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1071
    __ push(rdi);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1072
    __ movptr(to   , Address(rsp, 12+ 4));
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1073
    __ movl(value, Address(rsp, 12+ 8));
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1074
    __ movl(count, Address(rsp, 12+ 12));
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1075
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1076
    __ generate_fill(t, aligned, to, value, count, rax, xmm0);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1077
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1078
    __ pop(rdi);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1079
    __ pop(rsi);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1080
    __ leave(); // required for proper stackwalking of RuntimeStub frame
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1081
    __ ret(0);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1082
    return start;
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1083
  }
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  1084
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1085
  address generate_conjoint_copy(BasicType t, bool aligned,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1086
                                 Address::ScaleFactor sf,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1087
                                 address nooverlap_target,
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
  1088
                                 address* entry, const char *name,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
  1089
                                 bool dest_uninitialized = false) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1090
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1091
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1092
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1093
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1094
    Label L_0_count, L_exit, L_skip_align1, L_skip_align2, L_copy_byte;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1095
    Label L_copy_2_bytes, L_copy_4_bytes, L_copy_8_bytes, L_copy_8_bytes_loop;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1096
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1097
    int shift = Address::times_ptr - sf;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1098
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1099
    const Register src   = rax;  // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1100
    const Register dst   = rdx;  // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1101
    const Register from  = rsi;  // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1102
    const Register to    = rdi;  // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1103
    const Register count = rcx;  // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1104
    const Register end   = rax;  // array end address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1105
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1106
    __ enter(); // required for proper stackwalking of RuntimeStub frame
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1107
    __ push(rsi);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1108
    __ push(rdi);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1109
    __ movptr(src  , Address(rsp, 12+ 4));   // from
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1110
    __ movptr(dst  , Address(rsp, 12+ 8));   // to
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1111
    __ movl2ptr(count, Address(rsp, 12+12)); // count
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1112
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1113
    if (entry != NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1114
      *entry = __ pc(); // Entry point from generic arraycopy stub.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1115
      BLOCK_COMMENT("Entry:");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1116
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1117
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 8315
diff changeset
  1118
    // nooverlap_target expects arguments in rsi and rdi.
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1119
    __ mov(from, src);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1120
    __ mov(to  , dst);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1121
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 8315
diff changeset
  1122
    // arrays overlap test: dispatch to disjoint stub if necessary.
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1123
    RuntimeAddress nooverlap(nooverlap_target);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1124
    __ cmpptr(dst, src);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1125
    __ lea(end, Address(src, count, sf, 0)); // src + count * elem_size
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1126
    __ jump_cc(Assembler::belowEqual, nooverlap);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1127
    __ cmpptr(dst, end);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1128
    __ jump_cc(Assembler::aboveEqual, nooverlap);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1129
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 8315
diff changeset
  1130
    if (t == T_OBJECT) {
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 8315
diff changeset
  1131
      __ testl(count, count);
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 8315
diff changeset
  1132
      __ jcc(Assembler::zero, L_0_count);
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
  1133
      gen_write_ref_array_pre_barrier(dst, count, dest_uninitialized);
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 8315
diff changeset
  1134
    }
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 8315
diff changeset
  1135
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1136
    // copy from high to low
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1137
    __ cmpl(count, 2<<shift); // Short arrays (< 8 bytes) copy by element
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1138
    __ jcc(Assembler::below, L_copy_4_bytes); // use unsigned cmp
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1139
    if (t == T_BYTE || t == T_SHORT) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1140
      // Align the end of destination array at 4 bytes address boundary
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1141
      __ lea(end, Address(dst, count, sf, 0));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1142
      if (t == T_BYTE) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1143
        // One byte misalignment happens only for byte arrays
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1144
        __ testl(end, 1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1145
        __ jccb(Assembler::zero, L_skip_align1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1146
        __ decrement(count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1147
        __ movb(rdx, Address(from, count, sf, 0));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1148
        __ movb(Address(to, count, sf, 0), rdx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1149
      __ BIND(L_skip_align1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1150
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1151
      // Two bytes misalignment happens only for byte and short (char) arrays
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1152
      __ testl(end, 2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1153
      __ jccb(Assembler::zero, L_skip_align2);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1154
      __ subptr(count, 1<<(shift-1));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1155
      __ movw(rdx, Address(from, count, sf, 0));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1156
      __ movw(Address(to, count, sf, 0), rdx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1157
    __ BIND(L_skip_align2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1158
      __ cmpl(count, 2<<shift); // Short arrays (< 8 bytes) copy by element
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1159
      __ jcc(Assembler::below, L_copy_4_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1160
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1161
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1162
    if (!VM_Version::supports_mmx()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1163
      __ std();
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1164
      __ mov(rax, count); // Save 'count'
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1165
      __ mov(rdx, to);    // Save 'to'
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1166
      __ lea(rsi, Address(from, count, sf, -4));
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1167
      __ lea(rdi, Address(to  , count, sf, -4));
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1168
      __ shrptr(count, shift); // bytes count
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1169
      __ rep_mov();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1170
      __ cld();
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1171
      __ mov(count, rax); // restore 'count'
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1172
      __ andl(count, (1<<shift)-1);      // mask the number of rest elements
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1173
      __ movptr(from, Address(rsp, 12+4)); // reread 'from'
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1174
      __ mov(to, rdx);   // restore 'to'
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1175
      __ jmpb(L_copy_2_bytes); // all dword were copied
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1176
   } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1177
      // Align to 8 bytes the end of array. It is aligned to 4 bytes already.
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1178
      __ testptr(end, 4);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1179
      __ jccb(Assembler::zero, L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1180
      __ subl(count, 1<<shift);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1181
      __ movl(rdx, Address(from, count, sf, 0));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1182
      __ movl(Address(to, count, sf, 0), rdx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1183
      __ jmpb(L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1184
5249
5cac34e6fe54 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 5050
diff changeset
  1185
      __ align(OptoLoopAlignment);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1186
      // Move 8 bytes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1187
    __ BIND(L_copy_8_bytes_loop);
1437
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1188
      if (UseXMMForArrayCopy) {
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1189
        __ movq(xmm0, Address(from, count, sf, 0));
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1190
        __ movq(Address(to, count, sf, 0), xmm0);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1191
      } else {
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1192
        __ movq(mmx0, Address(from, count, sf, 0));
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1193
        __ movq(Address(to, count, sf, 0), mmx0);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1194
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1195
    __ BIND(L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1196
      __ subl(count, 2<<shift);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1197
      __ jcc(Assembler::greaterEqual, L_copy_8_bytes_loop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1198
      __ addl(count, 2<<shift);
1437
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1199
      if (!UseXMMForArrayCopy) {
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1200
        __ emms();
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1201
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1202
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1203
  __ BIND(L_copy_4_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1204
    // copy prefix qword
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1205
    __ testl(count, 1<<shift);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1206
    __ jccb(Assembler::zero, L_copy_2_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1207
    __ movl(rdx, Address(from, count, sf, -4));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1208
    __ movl(Address(to, count, sf, -4), rdx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1209
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1210
    if (t == T_BYTE || t == T_SHORT) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1211
        __ subl(count, (1<<shift));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1212
      __ BIND(L_copy_2_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1213
        // copy prefix dword
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1214
        __ testl(count, 1<<(shift-1));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1215
        __ jccb(Assembler::zero, L_copy_byte);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1216
        __ movw(rdx, Address(from, count, sf, -2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1217
        __ movw(Address(to, count, sf, -2), rdx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1218
        if (t == T_BYTE) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1219
          __ subl(count, 1<<(shift-1));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1220
        __ BIND(L_copy_byte);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1221
          // copy prefix byte
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1222
          __ testl(count, 1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1223
          __ jccb(Assembler::zero, L_exit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1224
          __ movb(rdx, Address(from, 0));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1225
          __ movb(Address(to, 0), rdx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1226
        __ BIND(L_exit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1227
        } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1228
        __ BIND(L_copy_byte);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1229
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1230
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1231
    __ BIND(L_copy_2_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1232
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1233
    if (t == T_OBJECT) {
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1234
      __ movl2ptr(count, Address(rsp, 12+12)); // reread count
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1235
      gen_write_ref_array_post_barrier(to, count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1236
    __ BIND(L_0_count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1237
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1238
    inc_copy_counter_np(t);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1239
    __ pop(rdi);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1240
    __ pop(rsi);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1241
    __ leave(); // required for proper stackwalking of RuntimeStub frame
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1242
    __ xorptr(rax, rax); // return 0
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1243
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1244
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1245
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1246
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1247
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1248
  address generate_disjoint_long_copy(address* entry, const char *name) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1249
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1250
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1251
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1252
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1253
    Label L_copy_8_bytes, L_copy_8_bytes_loop;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1254
    const Register from       = rax;  // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1255
    const Register to         = rdx;  // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1256
    const Register count      = rcx;  // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1257
    const Register to_from    = rdx;  // (to - from)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1258
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1259
    __ enter(); // required for proper stackwalking of RuntimeStub frame
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1260
    __ movptr(from , Address(rsp, 8+0));       // from
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1261
    __ movptr(to   , Address(rsp, 8+4));       // to
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1262
    __ movl2ptr(count, Address(rsp, 8+8));     // count
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1263
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1264
    *entry = __ pc(); // Entry point from conjoint arraycopy stub.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1265
    BLOCK_COMMENT("Entry:");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1266
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1267
    __ subptr(to, from); // to --> to_from
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1268
    if (VM_Version::supports_mmx()) {
1437
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1269
      if (UseXMMForArrayCopy) {
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1270
        xmm_copy_forward(from, to_from, count);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1271
      } else {
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1272
        mmx_copy_forward(from, to_from, count);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1273
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1274
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1275
      __ jmpb(L_copy_8_bytes);
5249
5cac34e6fe54 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 5050
diff changeset
  1276
      __ align(OptoLoopAlignment);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1277
    __ BIND(L_copy_8_bytes_loop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1278
      __ fild_d(Address(from, 0));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1279
      __ fistp_d(Address(from, to_from, Address::times_1));
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1280
      __ addptr(from, 8);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1281
    __ BIND(L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1282
      __ decrement(count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1283
      __ jcc(Assembler::greaterEqual, L_copy_8_bytes_loop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1284
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1285
    inc_copy_counter_np(T_LONG);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1286
    __ leave(); // required for proper stackwalking of RuntimeStub frame
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1287
    __ xorptr(rax, rax); // return 0
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1288
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1289
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1290
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1291
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1292
  address generate_conjoint_long_copy(address nooverlap_target,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1293
                                      address* entry, const char *name) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1294
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1295
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1296
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1297
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1298
    Label L_copy_8_bytes, L_copy_8_bytes_loop;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1299
    const Register from       = rax;  // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1300
    const Register to         = rdx;  // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1301
    const Register count      = rcx;  // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1302
    const Register end_from   = rax;  // source array end address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1303
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1304
    __ enter(); // required for proper stackwalking of RuntimeStub frame
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1305
    __ movptr(from , Address(rsp, 8+0));       // from
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1306
    __ movptr(to   , Address(rsp, 8+4));       // to
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1307
    __ movl2ptr(count, Address(rsp, 8+8));     // count
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1308
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1309
    *entry = __ pc(); // Entry point from generic arraycopy stub.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1310
    BLOCK_COMMENT("Entry:");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1311
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1312
    // arrays overlap test
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1313
    __ cmpptr(to, from);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1314
    RuntimeAddress nooverlap(nooverlap_target);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1315
    __ jump_cc(Assembler::belowEqual, nooverlap);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1316
    __ lea(end_from, Address(from, count, Address::times_8, 0));
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1317
    __ cmpptr(to, end_from);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1318
    __ movptr(from, Address(rsp, 8));  // from
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1319
    __ jump_cc(Assembler::aboveEqual, nooverlap);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1320
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1321
    __ jmpb(L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1322
5249
5cac34e6fe54 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 5050
diff changeset
  1323
    __ align(OptoLoopAlignment);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1324
  __ BIND(L_copy_8_bytes_loop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1325
    if (VM_Version::supports_mmx()) {
1437
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1326
      if (UseXMMForArrayCopy) {
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1327
        __ movq(xmm0, Address(from, count, Address::times_8));
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1328
        __ movq(Address(to, count, Address::times_8), xmm0);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1329
      } else {
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1330
        __ movq(mmx0, Address(from, count, Address::times_8));
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1331
        __ movq(Address(to, count, Address::times_8), mmx0);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1332
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1333
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1334
      __ fild_d(Address(from, count, Address::times_8));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1335
      __ fistp_d(Address(to, count, Address::times_8));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1336
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1337
  __ BIND(L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1338
    __ decrement(count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1339
    __ jcc(Assembler::greaterEqual, L_copy_8_bytes_loop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1340
1437
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1341
    if (VM_Version::supports_mmx() && !UseXMMForArrayCopy) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1342
      __ emms();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1343
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1344
    inc_copy_counter_np(T_LONG);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1345
    __ leave(); // required for proper stackwalking of RuntimeStub frame
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1346
    __ xorptr(rax, rax); // return 0
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1347
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1348
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1349
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1350
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1351
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1352
  // Helper for generating a dynamic type check.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1353
  // The sub_klass must be one of {rbx, rdx, rsi}.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1354
  // The temp is killed.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1355
  void generate_type_check(Register sub_klass,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1356
                           Address& super_check_offset_addr,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1357
                           Address& super_klass_addr,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1358
                           Register temp,
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1909
diff changeset
  1359
                           Label* L_success, Label* L_failure) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1360
    BLOCK_COMMENT("type_check:");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1361
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1362
    Label L_fallthrough;
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1909
diff changeset
  1363
#define LOCAL_JCC(assembler_con, label_ptr)                             \
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1909
diff changeset
  1364
    if (label_ptr != NULL)  __ jcc(assembler_con, *(label_ptr));        \
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1909
diff changeset
  1365
    else                    __ jcc(assembler_con, L_fallthrough) /*omit semi*/
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1366
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1909
diff changeset
  1367
    // The following is a strange variation of the fast path which requires
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1909
diff changeset
  1368
    // one less register, because needed values are on the argument stack.
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1909
diff changeset
  1369
    // __ check_klass_subtype_fast_path(sub_klass, *super_klass*, temp,
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1909
diff changeset
  1370
    //                                  L_success, L_failure, NULL);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1371
    assert_different_registers(sub_klass, temp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1372
11430
718fc06da49a 7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents: 10565
diff changeset
  1373
    int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1374
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1375
    // if the pointers are equal, we are done (e.g., String[] elements)
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1376
    __ cmpptr(sub_klass, super_klass_addr);
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1909
diff changeset
  1377
    LOCAL_JCC(Assembler::equal, L_success);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1378
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1379
    // check the supertype display:
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1380
    __ movl2ptr(temp, super_check_offset_addr);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1381
    Address super_check_addr(sub_klass, temp, Address::times_1, 0);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1382
    __ movptr(temp, super_check_addr); // load displayed supertype
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1383
    __ cmpptr(temp, super_klass_addr); // test the super type
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1909
diff changeset
  1384
    LOCAL_JCC(Assembler::equal, L_success);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1385
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1386
    // if it was a primary super, we can just fail immediately
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1387
    __ cmpl(super_check_offset_addr, sc_offset);
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1909
diff changeset
  1388
    LOCAL_JCC(Assembler::notEqual, L_failure);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1389
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1909
diff changeset
  1390
    // The repne_scan instruction uses fixed registers, which will get spilled.
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1909
diff changeset
  1391
    // We happen to know this works best when super_klass is in rax.
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1909
diff changeset
  1392
    Register super_klass = temp;
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1909
diff changeset
  1393
    __ movptr(super_klass, super_klass_addr);
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1909
diff changeset
  1394
    __ check_klass_subtype_slow_path(sub_klass, super_klass, noreg, noreg,
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1909
diff changeset
  1395
                                     L_success, L_failure);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1396
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1909
diff changeset
  1397
    __ bind(L_fallthrough);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1398
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1909
diff changeset
  1399
    if (L_success == NULL) { BLOCK_COMMENT("L_success:"); }
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1909
diff changeset
  1400
    if (L_failure == NULL) { BLOCK_COMMENT("L_failure:"); }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1401
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1909
diff changeset
  1402
#undef LOCAL_JCC
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1403
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1404
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1405
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1406
  //  Generate checkcasting array copy stub
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1407
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1408
  //  Input:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1409
  //    4(rsp)   - source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1410
  //    8(rsp)   - destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1411
  //   12(rsp)   - element count, can be zero
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1412
  //   16(rsp)   - size_t ckoff (super_check_offset)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1413
  //   20(rsp)   - oop ckval (super_klass)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1414
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1415
  //  Output:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1416
  //    rax, ==  0  -  success
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1417
  //    rax, == -1^K - failure, where K is partial transfer count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1418
  //
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
  1419
  address generate_checkcast_copy(const char *name, address* entry, bool dest_uninitialized = false) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1420
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1421
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1422
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1423
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1424
    Label L_load_element, L_store_element, L_do_card_marks, L_done;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1425
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1426
    // register use:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1427
    //  rax, rdx, rcx -- loop control (end_from, end_to, count)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1428
    //  rdi, rsi      -- element access (oop, klass)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1429
    //  rbx,           -- temp
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1430
    const Register from       = rax;    // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1431
    const Register to         = rdx;    // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1432
    const Register length     = rcx;    // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1433
    const Register elem       = rdi;    // each oop copied
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1434
    const Register elem_klass = rsi;    // each elem._klass (sub_klass)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1435
    const Register temp       = rbx;    // lone remaining temp
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1436
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1437
    __ enter(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1438
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1439
    __ push(rsi);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1440
    __ push(rdi);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1441
    __ push(rbx);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1442
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1443
    Address   from_arg(rsp, 16+ 4);     // from
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1444
    Address     to_arg(rsp, 16+ 8);     // to
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1445
    Address length_arg(rsp, 16+12);     // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1446
    Address  ckoff_arg(rsp, 16+16);     // super_check_offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1447
    Address  ckval_arg(rsp, 16+20);     // super_klass
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1448
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1449
    // Load up:
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1450
    __ movptr(from,     from_arg);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1451
    __ movptr(to,         to_arg);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1452
    __ movl2ptr(length, length_arg);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1453
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 8315
diff changeset
  1454
    if (entry != NULL) {
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 8315
diff changeset
  1455
      *entry = __ pc(); // Entry point from generic arraycopy stub.
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 8315
diff changeset
  1456
      BLOCK_COMMENT("Entry:");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 8315
diff changeset
  1457
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1458
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1459
    //---------------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1460
    // Assembler stub will be used for this call to arraycopy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1461
    // if the two arrays are subtypes of Object[] but the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1462
    // destination array type is not equal to or a supertype
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1463
    // of the source type.  Each element must be separately
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1464
    // checked.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1465
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1466
    // Loop-invariant addresses.  They are exclusive end pointers.
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1467
    Address end_from_addr(from, length, Address::times_ptr, 0);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1468
    Address   end_to_addr(to,   length, Address::times_ptr, 0);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1469
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1470
    Register end_from = from;           // re-use
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1471
    Register end_to   = to;             // re-use
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1472
    Register count    = length;         // re-use
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1473
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1474
    // Loop-variant addresses.  They assume post-incremented count < 0.
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1475
    Address from_element_addr(end_from, count, Address::times_ptr, 0);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1476
    Address   to_element_addr(end_to,   count, Address::times_ptr, 0);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1477
    Address elem_klass_addr(elem, oopDesc::klass_offset_in_bytes());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1478
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1479
    // Copy from low to high addresses, indexed from the end of each array.
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
  1480
    gen_write_ref_array_pre_barrier(to, count, dest_uninitialized);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1481
    __ lea(end_from, end_from_addr);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1482
    __ lea(end_to,   end_to_addr);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1483
    assert(length == count, "");        // else fix next line:
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1484
    __ negptr(count);                   // negate and test the length
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1485
    __ jccb(Assembler::notZero, L_load_element);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1486
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1487
    // Empty array:  Nothing to do.
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1488
    __ xorptr(rax, rax);                  // return 0 on (trivial) success
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1489
    __ jmp(L_done);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1490
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1491
    // ======== begin loop ========
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1492
    // (Loop is rotated; its entry is L_load_element.)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1493
    // Loop control:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1494
    //   for (count = -count; count != 0; count++)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1495
    // Base pointers src, dst are biased by 8*count,to last element.
5249
5cac34e6fe54 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 5050
diff changeset
  1496
    __ align(OptoLoopAlignment);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1497
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1498
    __ BIND(L_store_element);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1499
    __ movptr(to_element_addr, elem);     // store the oop
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1500
    __ increment(count);                // increment the count toward zero
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1501
    __ jccb(Assembler::zero, L_do_card_marks);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1502
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1503
    // ======== loop entry is here ========
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1504
    __ BIND(L_load_element);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1505
    __ movptr(elem, from_element_addr);   // load the oop
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1506
    __ testptr(elem, elem);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1507
    __ jccb(Assembler::zero, L_store_element);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1508
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1509
    // (Could do a trick here:  Remember last successful non-null
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1510
    // element stored and make a quick oop equality check on it.)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1511
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1512
    __ movptr(elem_klass, elem_klass_addr); // query the object klass
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1513
    generate_type_check(elem_klass, ckoff_arg, ckval_arg, temp,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1514
                        &L_store_element, NULL);
17622
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1515
    // (On fall-through, we have failed the element type check.)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1516
    // ======== end loop ========
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1517
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1518
    // It was a real error; we must depend on the caller to finish the job.
192
d66300cdf939 6614036: REGRESSION: Java server x86 VM intermittently crash with SIGSEGV (0xb)
rasbold
parents: 189
diff changeset
  1519
    // Register "count" = -1 * number of *remaining* oops, length_arg = *total* oops.
d66300cdf939 6614036: REGRESSION: Java server x86 VM intermittently crash with SIGSEGV (0xb)
rasbold
parents: 189
diff changeset
  1520
    // Emit GC store barriers for the oops we have copied (length_arg + count),
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1521
    // and report their number to the caller.
17622
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1522
    assert_different_registers(to, count, rax);
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1523
    Label L_post_barrier;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1524
    __ addl(count, length_arg);         // transfers = (length - remaining)
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1525
    __ movl2ptr(rax, count);            // save the value
17622
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1526
    __ notptr(rax);                     // report (-1^K) to caller (does not affect flags)
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1527
    __ jccb(Assembler::notZero, L_post_barrier);
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1528
    __ jmp(L_done); // K == 0, nothing was copied, skip post barrier
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1529
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1530
    // Come here on success only.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1531
    __ BIND(L_do_card_marks);
17622
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1532
    __ xorptr(rax, rax);                // return 0 on success
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1533
    __ movl2ptr(count, length_arg);
17622
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1534
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1535
    __ BIND(L_post_barrier);
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1536
    __ movptr(to, to_arg);              // reload
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1537
    gen_write_ref_array_post_barrier(to, count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1538
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1539
    // Common exit point (success or failure).
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1540
    __ BIND(L_done);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1541
    __ pop(rbx);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1542
    __ pop(rdi);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1543
    __ pop(rsi);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1544
    inc_counter_np(SharedRuntime::_checkcast_array_copy_ctr);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1545
    __ leave(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1546
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1547
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1548
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1549
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1550
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1551
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1552
  //  Generate 'unsafe' array copy stub
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1553
  //  Though just as safe as the other stubs, it takes an unscaled
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1554
  //  size_t argument instead of an element count.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1555
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1556
  //  Input:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1557
  //    4(rsp)   - source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1558
  //    8(rsp)   - destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1559
  //   12(rsp)   - byte count, can be zero
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1560
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1561
  //  Output:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1562
  //    rax, ==  0  -  success
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1563
  //    rax, == -1  -  need to call System.arraycopy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1564
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1565
  // Examines the alignment of the operands and dispatches
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1566
  // to a long, int, short, or byte copy loop.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1567
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1568
  address generate_unsafe_copy(const char *name,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1569
                               address byte_copy_entry,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1570
                               address short_copy_entry,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1571
                               address int_copy_entry,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1572
                               address long_copy_entry) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1573
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1574
    Label L_long_aligned, L_int_aligned, L_short_aligned;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1575
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1576
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1577
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1578
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1579
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1580
    const Register from       = rax;  // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1581
    const Register to         = rdx;  // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1582
    const Register count      = rcx;  // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1583
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1584
    __ enter(); // required for proper stackwalking of RuntimeStub frame
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1585
    __ push(rsi);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1586
    __ push(rdi);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1587
    Address  from_arg(rsp, 12+ 4);      // from
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1588
    Address    to_arg(rsp, 12+ 8);      // to
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1589
    Address count_arg(rsp, 12+12);      // byte count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1590
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1591
    // Load up:
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1592
    __ movptr(from ,  from_arg);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1593
    __ movptr(to   ,    to_arg);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1594
    __ movl2ptr(count, count_arg);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1595
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1596
    // bump this on entry, not on exit:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1597
    inc_counter_np(SharedRuntime::_unsafe_array_copy_ctr);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1598
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1599
    const Register bits = rsi;
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1600
    __ mov(bits, from);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1601
    __ orptr(bits, to);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1602
    __ orptr(bits, count);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1603
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1604
    __ testl(bits, BytesPerLong-1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1605
    __ jccb(Assembler::zero, L_long_aligned);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1606
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1607
    __ testl(bits, BytesPerInt-1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1608
    __ jccb(Assembler::zero, L_int_aligned);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1609
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1610
    __ testl(bits, BytesPerShort-1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1611
    __ jump_cc(Assembler::notZero, RuntimeAddress(byte_copy_entry));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1612
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1613
    __ BIND(L_short_aligned);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1614
    __ shrptr(count, LogBytesPerShort); // size => short_count
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1615
    __ movl(count_arg, count);          // update 'count'
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1616
    __ jump(RuntimeAddress(short_copy_entry));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1617
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1618
    __ BIND(L_int_aligned);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1619
    __ shrptr(count, LogBytesPerInt); // size => int_count
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1620
    __ movl(count_arg, count);          // update 'count'
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1621
    __ jump(RuntimeAddress(int_copy_entry));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1622
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1623
    __ BIND(L_long_aligned);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1624
    __ shrptr(count, LogBytesPerLong); // size => qword_count
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1625
    __ movl(count_arg, count);          // update 'count'
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1626
    __ pop(rdi); // Do pops here since jlong_arraycopy stub does not do it.
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1627
    __ pop(rsi);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1628
    __ jump(RuntimeAddress(long_copy_entry));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1629
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1630
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1631
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1632
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1633
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1634
  // Perform range checks on the proposed arraycopy.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1635
  // Smashes src_pos and dst_pos.  (Uses them up for temps.)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1636
  void arraycopy_range_checks(Register src,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1637
                              Register src_pos,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1638
                              Register dst,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1639
                              Register dst_pos,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1640
                              Address& length,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1641
                              Label& L_failed) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1642
    BLOCK_COMMENT("arraycopy_range_checks:");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1643
    const Register src_end = src_pos;   // source array end position
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1644
    const Register dst_end = dst_pos;   // destination array end position
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1645
    __ addl(src_end, length); // src_pos + length
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1646
    __ addl(dst_end, length); // dst_pos + length
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1647
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1648
    //  if (src_pos + length > arrayOop(src)->length() ) FAIL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1649
    __ cmpl(src_end, Address(src, arrayOopDesc::length_offset_in_bytes()));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1650
    __ jcc(Assembler::above, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1651
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1652
    //  if (dst_pos + length > arrayOop(dst)->length() ) FAIL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1653
    __ cmpl(dst_end, Address(dst, arrayOopDesc::length_offset_in_bytes()));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1654
    __ jcc(Assembler::above, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1655
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1656
    BLOCK_COMMENT("arraycopy_range_checks done");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1657
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1658
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1659
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1660
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1661
  //  Generate generic array copy stubs
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1662
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1663
  //  Input:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1664
  //     4(rsp)    -  src oop
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1665
  //     8(rsp)    -  src_pos
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1666
  //    12(rsp)    -  dst oop
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1667
  //    16(rsp)    -  dst_pos
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1668
  //    20(rsp)    -  element count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1669
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1670
  //  Output:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1671
  //    rax, ==  0  -  success
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1672
  //    rax, == -1^K - failure, where K is partial transfer count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1673
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1674
  address generate_generic_copy(const char *name,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1675
                                address entry_jbyte_arraycopy,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1676
                                address entry_jshort_arraycopy,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1677
                                address entry_jint_arraycopy,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1678
                                address entry_oop_arraycopy,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1679
                                address entry_jlong_arraycopy,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1680
                                address entry_checkcast_arraycopy) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1681
    Label L_failed, L_failed_0, L_objArray;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1682
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1683
    { int modulus = CodeEntryAlignment;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1684
      int target  = modulus - 5; // 5 = sizeof jmp(L_failed)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1685
      int advance = target - (__ offset() % modulus);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1686
      if (advance < 0)  advance += modulus;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1687
      if (advance > 0)  __ nop(advance);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1688
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1689
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1690
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1691
    // Short-hop target to L_failed.  Makes for denser prologue code.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1692
    __ BIND(L_failed_0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1693
    __ jmp(L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1694
    assert(__ offset() % CodeEntryAlignment == 0, "no further alignment needed");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1695
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1696
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1697
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1698
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1699
    __ enter(); // required for proper stackwalking of RuntimeStub frame
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1700
    __ push(rsi);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1701
    __ push(rdi);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1702
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1703
    // bump this on entry, not on exit:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1704
    inc_counter_np(SharedRuntime::_generic_array_copy_ctr);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1705
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1706
    // Input values
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1707
    Address SRC     (rsp, 12+ 4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1708
    Address SRC_POS (rsp, 12+ 8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1709
    Address DST     (rsp, 12+12);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1710
    Address DST_POS (rsp, 12+16);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1711
    Address LENGTH  (rsp, 12+20);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1712
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1713
    //-----------------------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1714
    // Assembler stub will be used for this call to arraycopy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1715
    // if the following conditions are met:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1716
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1717
    // (1) src and dst must not be null.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1718
    // (2) src_pos must not be negative.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1719
    // (3) dst_pos must not be negative.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1720
    // (4) length  must not be negative.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1721
    // (5) src klass and dst klass should be the same and not NULL.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1722
    // (6) src and dst should be arrays.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1723
    // (7) src_pos + length must not exceed length of src.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1724
    // (8) dst_pos + length must not exceed length of dst.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1725
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1726
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1727
    const Register src     = rax;       // source array oop
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1728
    const Register src_pos = rsi;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1729
    const Register dst     = rdx;       // destination array oop
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1730
    const Register dst_pos = rdi;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1731
    const Register length  = rcx;       // transfer count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1732
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1733
    //  if (src == NULL) return -1;
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1734
    __ movptr(src, SRC);      // src oop
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1735
    __ testptr(src, src);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1736
    __ jccb(Assembler::zero, L_failed_0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1737
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1738
    //  if (src_pos < 0) return -1;
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1739
    __ movl2ptr(src_pos, SRC_POS);  // src_pos
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1740
    __ testl(src_pos, src_pos);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1741
    __ jccb(Assembler::negative, L_failed_0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1742
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1743
    //  if (dst == NULL) return -1;
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1744
    __ movptr(dst, DST);      // dst oop
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1745
    __ testptr(dst, dst);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1746
    __ jccb(Assembler::zero, L_failed_0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1747
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1748
    //  if (dst_pos < 0) return -1;
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1749
    __ movl2ptr(dst_pos, DST_POS);  // dst_pos
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1750
    __ testl(dst_pos, dst_pos);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1751
    __ jccb(Assembler::negative, L_failed_0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1752
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1753
    //  if (length < 0) return -1;
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1754
    __ movl2ptr(length, LENGTH);   // length
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1755
    __ testl(length, length);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1756
    __ jccb(Assembler::negative, L_failed_0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1757
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1758
    //  if (src->klass() == NULL) return -1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1759
    Address src_klass_addr(src, oopDesc::klass_offset_in_bytes());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1760
    Address dst_klass_addr(dst, oopDesc::klass_offset_in_bytes());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1761
    const Register rcx_src_klass = rcx;    // array klass
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1762
    __ movptr(rcx_src_klass, Address(src, oopDesc::klass_offset_in_bytes()));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1763
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1764
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1765
    //  assert(src->klass() != NULL);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1766
    BLOCK_COMMENT("assert klasses not null");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1767
    { Label L1, L2;
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1768
      __ testptr(rcx_src_klass, rcx_src_klass);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1769
      __ jccb(Assembler::notZero, L2);   // it is broken if klass is NULL
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1770
      __ bind(L1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1771
      __ stop("broken null klass");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1772
      __ bind(L2);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1773
      __ cmpptr(dst_klass_addr, (int32_t)NULL_WORD);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1774
      __ jccb(Assembler::equal, L1);      // this would be broken also
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1775
      BLOCK_COMMENT("assert done");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1776
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1777
#endif //ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1778
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1779
    // Load layout helper (32-bits)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1780
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1781
    //  |array_tag|     | header_size | element_type |     |log2_element_size|
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1782
    // 32        30    24            16              8     2                 0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1783
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1784
    //   array_tag: typeArray = 0x3, objArray = 0x2, non-array = 0x0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1785
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1786
11430
718fc06da49a 7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents: 10565
diff changeset
  1787
    int lh_offset = in_bytes(Klass::layout_helper_offset());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1788
    Address src_klass_lh_addr(rcx_src_klass, lh_offset);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1789
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1790
    // Handle objArrays completely differently...
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1791
    jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1792
    __ cmpl(src_klass_lh_addr, objArray_lh);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1793
    __ jcc(Assembler::equal, L_objArray);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1794
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1795
    //  if (src->klass() != dst->klass()) return -1;
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1796
    __ cmpptr(rcx_src_klass, dst_klass_addr);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1797
    __ jccb(Assembler::notEqual, L_failed_0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1798
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1799
    const Register rcx_lh = rcx;  // layout helper
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1800
    assert(rcx_lh == rcx_src_klass, "known alias");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1801
    __ movl(rcx_lh, src_klass_lh_addr);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1802
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1803
    //  if (!src->is_Array()) return -1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1804
    __ cmpl(rcx_lh, Klass::_lh_neutral_value);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1805
    __ jcc(Assembler::greaterEqual, L_failed_0); // signed cmp
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1806
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1807
    // At this point, it is known to be a typeArray (array_tag 0x3).
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1808
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1809
    { Label L;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1810
      __ cmpl(rcx_lh, (Klass::_lh_array_tag_type_value << Klass::_lh_array_tag_shift));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1811
      __ jcc(Assembler::greaterEqual, L); // signed cmp
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1812
      __ stop("must be a primitive array");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1813
      __ bind(L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1814
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1815
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1816
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1817
    assert_different_registers(src, src_pos, dst, dst_pos, rcx_lh);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1818
    arraycopy_range_checks(src, src_pos, dst, dst_pos, LENGTH, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1819
13952
e3cf184080bc 8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents: 13728
diff changeset
  1820
    // TypeArrayKlass
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1821
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1822
    // src_addr = (src + array_header_in_bytes()) + (src_pos << log2elemsize);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1823
    // dst_addr = (dst + array_header_in_bytes()) + (dst_pos << log2elemsize);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1824
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1825
    const Register rsi_offset = rsi; // array offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1826
    const Register src_array  = src; // src array offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1827
    const Register dst_array  = dst; // dst array offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1828
    const Register rdi_elsize = rdi; // log2 element size
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1829
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1830
    __ mov(rsi_offset, rcx_lh);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1831
    __ shrptr(rsi_offset, Klass::_lh_header_size_shift);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1832
    __ andptr(rsi_offset, Klass::_lh_header_size_mask);   // array_offset
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1833
    __ addptr(src_array, rsi_offset);  // src array offset
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1834
    __ addptr(dst_array, rsi_offset);  // dst array offset
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1835
    __ andptr(rcx_lh, Klass::_lh_log2_element_size_mask); // log2 elsize
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1836
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1837
    // next registers should be set before the jump to corresponding stub
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1838
    const Register from       = src; // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1839
    const Register to         = dst; // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1840
    const Register count      = rcx; // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1841
    // some of them should be duplicated on stack
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1842
#define FROM   Address(rsp, 12+ 4)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1843
#define TO     Address(rsp, 12+ 8)   // Not used now
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1844
#define COUNT  Address(rsp, 12+12)   // Only for oop arraycopy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1845
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1846
    BLOCK_COMMENT("scale indexes to element size");
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1847
    __ movl2ptr(rsi, SRC_POS);  // src_pos
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1848
    __ shlptr(rsi);             // src_pos << rcx (log2 elsize)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1849
    assert(src_array == from, "");
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1850
    __ addptr(from, rsi);       // from = src_array + SRC_POS << log2 elsize
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1851
    __ movl2ptr(rdi, DST_POS);  // dst_pos
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1852
    __ shlptr(rdi);             // dst_pos << rcx (log2 elsize)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1853
    assert(dst_array == to, "");
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1854
    __ addptr(to,  rdi);        // to   = dst_array + DST_POS << log2 elsize
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1855
    __ movptr(FROM, from);      // src_addr
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1856
    __ mov(rdi_elsize, rcx_lh); // log2 elsize
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1857
    __ movl2ptr(count, LENGTH); // elements count
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1858
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1859
    BLOCK_COMMENT("choose copy loop based on element size");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1860
    __ cmpl(rdi_elsize, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1861
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1862
    __ jump_cc(Assembler::equal, RuntimeAddress(entry_jbyte_arraycopy));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1863
    __ cmpl(rdi_elsize, LogBytesPerShort);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1864
    __ jump_cc(Assembler::equal, RuntimeAddress(entry_jshort_arraycopy));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1865
    __ cmpl(rdi_elsize, LogBytesPerInt);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1866
    __ jump_cc(Assembler::equal, RuntimeAddress(entry_jint_arraycopy));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1867
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1868
    __ cmpl(rdi_elsize, LogBytesPerLong);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1869
    __ jccb(Assembler::notEqual, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1870
#endif
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1871
    __ pop(rdi); // Do pops here since jlong_arraycopy stub does not do it.
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1872
    __ pop(rsi);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1873
    __ jump(RuntimeAddress(entry_jlong_arraycopy));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1874
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1875
  __ BIND(L_failed);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1876
    __ xorptr(rax, rax);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1877
    __ notptr(rax); // return -1
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1878
    __ pop(rdi);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1879
    __ pop(rsi);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1880
    __ leave(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1881
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1882
13952
e3cf184080bc 8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents: 13728
diff changeset
  1883
    // ObjArrayKlass
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1884
  __ BIND(L_objArray);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1885
    // live at this point:  rcx_src_klass, src[_pos], dst[_pos]
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1886
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1887
    Label L_plain_copy, L_checkcast_copy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1888
    //  test array classes for subtyping
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1889
    __ cmpptr(rcx_src_klass, dst_klass_addr); // usual case is exact equality
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1890
    __ jccb(Assembler::notEqual, L_checkcast_copy);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1891
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1892
    // Identically typed arrays can be copied without element-wise checks.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1893
    assert_different_registers(src, src_pos, dst, dst_pos, rcx_src_klass);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1894
    arraycopy_range_checks(src, src_pos, dst, dst_pos, LENGTH, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1895
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1896
  __ BIND(L_plain_copy);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1897
    __ movl2ptr(count, LENGTH); // elements count
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1898
    __ movl2ptr(src_pos, SRC_POS);  // reload src_pos
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1899
    __ lea(from, Address(src, src_pos, Address::times_ptr,
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1900
                 arrayOopDesc::base_offset_in_bytes(T_OBJECT))); // src_addr
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1901
    __ movl2ptr(dst_pos, DST_POS);  // reload dst_pos
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1902
    __ lea(to,   Address(dst, dst_pos, Address::times_ptr,
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1903
                 arrayOopDesc::base_offset_in_bytes(T_OBJECT))); // dst_addr
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1904
    __ movptr(FROM,  from);   // src_addr
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1905
    __ movptr(TO,    to);     // dst_addr
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1906
    __ movl(COUNT, count);  // count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1907
    __ jump(RuntimeAddress(entry_oop_arraycopy));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1908
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1909
  __ BIND(L_checkcast_copy);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1910
    // live at this point:  rcx_src_klass, dst[_pos], src[_pos]
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1911
    {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1912
      // Handy offsets:
13952
e3cf184080bc 8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents: 13728
diff changeset
  1913
      int  ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
11430
718fc06da49a 7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents: 10565
diff changeset
  1914
      int sco_offset = in_bytes(Klass::super_check_offset_offset());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1915
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1916
      Register rsi_dst_klass = rsi;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1917
      Register rdi_temp      = rdi;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1918
      assert(rsi_dst_klass == src_pos, "expected alias w/ src_pos");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1919
      assert(rdi_temp      == dst_pos, "expected alias w/ dst_pos");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1920
      Address dst_klass_lh_addr(rsi_dst_klass, lh_offset);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1921
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1922
      // Before looking at dst.length, make sure dst is also an objArray.
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1923
      __ movptr(rsi_dst_klass, dst_klass_addr);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1924
      __ cmpl(dst_klass_lh_addr, objArray_lh);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1925
      __ jccb(Assembler::notEqual, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1926
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1927
      // It is safe to examine both src.length and dst.length.
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1928
      __ movl2ptr(src_pos, SRC_POS);        // reload rsi
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1929
      arraycopy_range_checks(src, src_pos, dst, dst_pos, LENGTH, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1930
      // (Now src_pos and dst_pos are killed, but not src and dst.)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1931
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1932
      // We'll need this temp (don't forget to pop it after the type check).
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1933
      __ push(rbx);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1934
      Register rbx_src_klass = rbx;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1935
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1936
      __ mov(rbx_src_klass, rcx_src_klass); // spill away from rcx
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1937
      __ movptr(rsi_dst_klass, dst_klass_addr);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1938
      Address super_check_offset_addr(rsi_dst_klass, sco_offset);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1939
      Label L_fail_array_check;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1940
      generate_type_check(rbx_src_klass,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1941
                          super_check_offset_addr, dst_klass_addr,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1942
                          rdi_temp, NULL, &L_fail_array_check);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1943
      // (On fall-through, we have passed the array type check.)
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1944
      __ pop(rbx);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1945
      __ jmp(L_plain_copy);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1946
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1947
      __ BIND(L_fail_array_check);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1948
      // Reshuffle arguments so we can call checkcast_arraycopy:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1949
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1950
      // match initial saves for checkcast_arraycopy
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1951
      // push(rsi);    // already done; see above
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1952
      // push(rdi);    // already done; see above
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1953
      // push(rbx);    // already done; see above
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1954
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1955
      // Marshal outgoing arguments now, freeing registers.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1956
      Address   from_arg(rsp, 16+ 4);   // from
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1957
      Address     to_arg(rsp, 16+ 8);   // to
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1958
      Address length_arg(rsp, 16+12);   // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1959
      Address  ckoff_arg(rsp, 16+16);   // super_check_offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1960
      Address  ckval_arg(rsp, 16+20);   // super_klass
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1961
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1962
      Address SRC_POS_arg(rsp, 16+ 8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1963
      Address DST_POS_arg(rsp, 16+16);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1964
      Address  LENGTH_arg(rsp, 16+20);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1965
      // push rbx, changed the incoming offsets (why not just use rbp,??)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1966
      // assert(SRC_POS_arg.disp() == SRC_POS.disp() + 4, "");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1967
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1968
      __ movptr(rbx, Address(rsi_dst_klass, ek_offset));
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1969
      __ movl2ptr(length, LENGTH_arg);    // reload elements count
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1970
      __ movl2ptr(src_pos, SRC_POS_arg);  // reload src_pos
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1971
      __ movl2ptr(dst_pos, DST_POS_arg);  // reload dst_pos
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1972
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1973
      __ movptr(ckval_arg, rbx);          // destination element type
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1974
      __ movl(rbx, Address(rbx, sco_offset));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1975
      __ movl(ckoff_arg, rbx);          // corresponding class check offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1976
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1977
      __ movl(length_arg, length);      // outgoing length argument
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1978
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1979
      __ lea(from, Address(src, src_pos, Address::times_ptr,
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1980
                            arrayOopDesc::base_offset_in_bytes(T_OBJECT)));
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1981
      __ movptr(from_arg, from);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1982
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1983
      __ lea(to, Address(dst, dst_pos, Address::times_ptr,
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1984
                          arrayOopDesc::base_offset_in_bytes(T_OBJECT)));
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1985
      __ movptr(to_arg, to);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1986
      __ jump(RuntimeAddress(entry_checkcast_arraycopy));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1987
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1988
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1989
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1990
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1991
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1992
  void generate_arraycopy_stubs() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1993
    address entry;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1994
    address entry_jbyte_arraycopy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1995
    address entry_jshort_arraycopy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1996
    address entry_jint_arraycopy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1997
    address entry_oop_arraycopy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1998
    address entry_jlong_arraycopy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1999
    address entry_checkcast_arraycopy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2000
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2001
    StubRoutines::_arrayof_jbyte_disjoint_arraycopy =
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2002
        generate_disjoint_copy(T_BYTE,  true, Address::times_1, &entry,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2003
                               "arrayof_jbyte_disjoint_arraycopy");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2004
    StubRoutines::_arrayof_jbyte_arraycopy =
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2005
        generate_conjoint_copy(T_BYTE,  true, Address::times_1,  entry,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2006
                               NULL, "arrayof_jbyte_arraycopy");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2007
    StubRoutines::_jbyte_disjoint_arraycopy =
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2008
        generate_disjoint_copy(T_BYTE, false, Address::times_1, &entry,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2009
                               "jbyte_disjoint_arraycopy");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2010
    StubRoutines::_jbyte_arraycopy =
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2011
        generate_conjoint_copy(T_BYTE, false, Address::times_1,  entry,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2012
                               &entry_jbyte_arraycopy, "jbyte_arraycopy");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2013
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2014
    StubRoutines::_arrayof_jshort_disjoint_arraycopy =
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2015
        generate_disjoint_copy(T_SHORT,  true, Address::times_2, &entry,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2016
                               "arrayof_jshort_disjoint_arraycopy");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2017
    StubRoutines::_arrayof_jshort_arraycopy =
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2018
        generate_conjoint_copy(T_SHORT,  true, Address::times_2,  entry,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2019
                               NULL, "arrayof_jshort_arraycopy");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2020
    StubRoutines::_jshort_disjoint_arraycopy =
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2021
        generate_disjoint_copy(T_SHORT, false, Address::times_2, &entry,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2022
                               "jshort_disjoint_arraycopy");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2023
    StubRoutines::_jshort_arraycopy =
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2024
        generate_conjoint_copy(T_SHORT, false, Address::times_2,  entry,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2025
                               &entry_jshort_arraycopy, "jshort_arraycopy");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2026
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2027
    // Next arrays are always aligned on 4 bytes at least.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2028
    StubRoutines::_jint_disjoint_arraycopy =
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2029
        generate_disjoint_copy(T_INT, true, Address::times_4, &entry,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2030
                               "jint_disjoint_arraycopy");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2031
    StubRoutines::_jint_arraycopy =
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2032
        generate_conjoint_copy(T_INT, true, Address::times_4,  entry,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2033
                               &entry_jint_arraycopy, "jint_arraycopy");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2034
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2035
    StubRoutines::_oop_disjoint_arraycopy =
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2036
        generate_disjoint_copy(T_OBJECT, true, Address::times_ptr, &entry,
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2037
                               "oop_disjoint_arraycopy");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2038
    StubRoutines::_oop_arraycopy =
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2039
        generate_conjoint_copy(T_OBJECT, true, Address::times_ptr,  entry,
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2040
                               &entry_oop_arraycopy, "oop_arraycopy");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2041
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
  2042
    StubRoutines::_oop_disjoint_arraycopy_uninit =
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
  2043
        generate_disjoint_copy(T_OBJECT, true, Address::times_ptr, &entry,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
  2044
                               "oop_disjoint_arraycopy_uninit",
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
  2045
                               /*dest_uninitialized*/true);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
  2046
    StubRoutines::_oop_arraycopy_uninit =
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
  2047
        generate_conjoint_copy(T_OBJECT, true, Address::times_ptr,  entry,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
  2048
                               NULL, "oop_arraycopy_uninit",
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
  2049
                               /*dest_uninitialized*/true);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
  2050
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2051
    StubRoutines::_jlong_disjoint_arraycopy =
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2052
        generate_disjoint_long_copy(&entry, "jlong_disjoint_arraycopy");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2053
    StubRoutines::_jlong_arraycopy =
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2054
        generate_conjoint_long_copy(entry, &entry_jlong_arraycopy,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2055
                                    "jlong_arraycopy");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2056
6433
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  2057
    StubRoutines::_jbyte_fill = generate_fill(T_BYTE, false, "jbyte_fill");
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  2058
    StubRoutines::_jshort_fill = generate_fill(T_SHORT, false, "jshort_fill");
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  2059
    StubRoutines::_jint_fill = generate_fill(T_INT, false, "jint_fill");
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  2060
    StubRoutines::_arrayof_jbyte_fill = generate_fill(T_BYTE, true, "arrayof_jbyte_fill");
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  2061
    StubRoutines::_arrayof_jshort_fill = generate_fill(T_SHORT, true, "arrayof_jshort_fill");
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  2062
    StubRoutines::_arrayof_jint_fill = generate_fill(T_INT, true, "arrayof_jint_fill");
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5547
diff changeset
  2063
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
  2064
    StubRoutines::_arrayof_jint_disjoint_arraycopy       = StubRoutines::_jint_disjoint_arraycopy;
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
  2065
    StubRoutines::_arrayof_oop_disjoint_arraycopy        = StubRoutines::_oop_disjoint_arraycopy;
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
  2066
    StubRoutines::_arrayof_oop_disjoint_arraycopy_uninit = StubRoutines::_oop_disjoint_arraycopy_uninit;
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
  2067
    StubRoutines::_arrayof_jlong_disjoint_arraycopy      = StubRoutines::_jlong_disjoint_arraycopy;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2068
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
  2069
    StubRoutines::_arrayof_jint_arraycopy       = StubRoutines::_jint_arraycopy;
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
  2070
    StubRoutines::_arrayof_oop_arraycopy        = StubRoutines::_oop_arraycopy;
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
  2071
    StubRoutines::_arrayof_oop_arraycopy_uninit = StubRoutines::_oop_arraycopy_uninit;
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
  2072
    StubRoutines::_arrayof_jlong_arraycopy      = StubRoutines::_jlong_arraycopy;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2073
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2074
    StubRoutines::_checkcast_arraycopy =
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
  2075
        generate_checkcast_copy("checkcast_arraycopy", &entry_checkcast_arraycopy);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
  2076
    StubRoutines::_checkcast_arraycopy_uninit =
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8495
diff changeset
  2077
        generate_checkcast_copy("checkcast_arraycopy_uninit", NULL, /*dest_uninitialized*/true);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2078
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2079
    StubRoutines::_unsafe_arraycopy =
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2080
        generate_unsafe_copy("unsafe_arraycopy",
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2081
                               entry_jbyte_arraycopy,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2082
                               entry_jshort_arraycopy,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2083
                               entry_jint_arraycopy,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2084
                               entry_jlong_arraycopy);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2085
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2086
    StubRoutines::_generic_arraycopy =
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2087
        generate_generic_copy("generic_arraycopy",
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2088
                               entry_jbyte_arraycopy,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2089
                               entry_jshort_arraycopy,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2090
                               entry_jint_arraycopy,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2091
                               entry_oop_arraycopy,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2092
                               entry_jlong_arraycopy,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2093
                               entry_checkcast_arraycopy);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2094
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2095
4645
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2096
  void generate_math_stubs() {
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2097
    {
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2098
      StubCodeMark mark(this, "StubRoutines", "log10");
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2099
      StubRoutines::_intrinsic_log10 = (double (*)(double)) __ pc();
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2100
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2101
      __ fld_d(Address(rsp, 4));
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2102
      __ flog10();
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2103
      __ ret(0);
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2104
    }
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2105
    {
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2106
      StubCodeMark mark(this, "StubRoutines", "sin");
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2107
      StubRoutines::_intrinsic_sin = (double (*)(double))  __ pc();
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2108
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2109
      __ fld_d(Address(rsp, 4));
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2110
      __ trigfunc('s');
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2111
      __ ret(0);
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2112
    }
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2113
    {
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2114
      StubCodeMark mark(this, "StubRoutines", "cos");
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2115
      StubRoutines::_intrinsic_cos = (double (*)(double)) __ pc();
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2116
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2117
      __ fld_d(Address(rsp, 4));
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2118
      __ trigfunc('c');
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2119
      __ ret(0);
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2120
    }
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2121
    {
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2122
      StubCodeMark mark(this, "StubRoutines", "tan");
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2123
      StubRoutines::_intrinsic_tan = (double (*)(double)) __ pc();
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2124
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2125
      __ fld_d(Address(rsp, 4));
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2126
      __ trigfunc('t');
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2127
      __ ret(0);
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2128
    }
12739
09f26b73ae66 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 11439
diff changeset
  2129
    {
09f26b73ae66 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 11439
diff changeset
  2130
      StubCodeMark mark(this, "StubRoutines", "pow");
09f26b73ae66 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 11439
diff changeset
  2131
      StubRoutines::_intrinsic_pow = (double (*)(double,double)) __ pc();
09f26b73ae66 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 11439
diff changeset
  2132
09f26b73ae66 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 11439
diff changeset
  2133
      __ fld_d(Address(rsp, 12));
09f26b73ae66 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 11439
diff changeset
  2134
      __ fld_d(Address(rsp, 4));
09f26b73ae66 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 11439
diff changeset
  2135
      __ pow_with_fallback(0);
09f26b73ae66 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 11439
diff changeset
  2136
      __ ret(0);
09f26b73ae66 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 11439
diff changeset
  2137
    }
4645
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2138
  }
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  2139
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2140
  // AES intrinsic stubs
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2141
  enum {AESBlockSize = 16};
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2142
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2143
  address generate_key_shuffle_mask() {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2144
    __ align(16);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2145
    StubCodeMark mark(this, "StubRoutines", "key_shuffle_mask");
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2146
    address start = __ pc();
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2147
    __ emit_data(0x00010203, relocInfo::none, 0 );
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2148
    __ emit_data(0x04050607, relocInfo::none, 0 );
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2149
    __ emit_data(0x08090a0b, relocInfo::none, 0 );
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2150
    __ emit_data(0x0c0d0e0f, relocInfo::none, 0 );
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2151
    return start;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2152
  }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2153
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2154
  // Utility routine for loading a 128-bit key word in little endian format
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2155
  // can optionally specify that the shuffle mask is already in an xmmregister
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2156
  void load_key(XMMRegister xmmdst, Register key, int offset, XMMRegister xmm_shuf_mask=NULL) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2157
    __ movdqu(xmmdst, Address(key, offset));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2158
    if (xmm_shuf_mask != NULL) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2159
      __ pshufb(xmmdst, xmm_shuf_mask);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2160
    } else {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2161
      __ pshufb(xmmdst, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2162
    }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2163
  }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2164
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2165
  // aesenc using specified key+offset
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2166
  // can optionally specify that the shuffle mask is already in an xmmregister
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2167
  void aes_enc_key(XMMRegister xmmdst, XMMRegister xmmtmp, Register key, int offset, XMMRegister xmm_shuf_mask=NULL) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2168
    load_key(xmmtmp, key, offset, xmm_shuf_mask);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2169
    __ aesenc(xmmdst, xmmtmp);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2170
  }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2171
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2172
  // aesdec using specified key+offset
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2173
  // can optionally specify that the shuffle mask is already in an xmmregister
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2174
  void aes_dec_key(XMMRegister xmmdst, XMMRegister xmmtmp, Register key, int offset, XMMRegister xmm_shuf_mask=NULL) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2175
    load_key(xmmtmp, key, offset, xmm_shuf_mask);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2176
    __ aesdec(xmmdst, xmmtmp);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2177
  }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2178
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2179
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2180
  // Arguments:
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2181
  //
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2182
  // Inputs:
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2183
  //   c_rarg0   - source byte array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2184
  //   c_rarg1   - destination byte array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2185
  //   c_rarg2   - K (key) in little endian int array
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2186
  //
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2187
  address generate_aescrypt_encryptBlock() {
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2188
    assert(UseAES, "need AES instructions and misaligned SSE support");
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2189
    __ align(CodeEntryAlignment);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2190
    StubCodeMark mark(this, "StubRoutines", "aescrypt_encryptBlock");
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2191
    Label L_doLast;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2192
    address start = __ pc();
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2193
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2194
    const Register from        = rdx;      // source array address
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2195
    const Register to          = rdx;      // destination array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2196
    const Register key         = rcx;      // key array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2197
    const Register keylen      = rax;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2198
    const Address  from_param(rbp, 8+0);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2199
    const Address  to_param  (rbp, 8+4);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2200
    const Address  key_param (rbp, 8+8);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2201
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2202
    const XMMRegister xmm_result = xmm0;
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2203
    const XMMRegister xmm_key_shuf_mask = xmm1;
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2204
    const XMMRegister xmm_temp1  = xmm2;
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2205
    const XMMRegister xmm_temp2  = xmm3;
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2206
    const XMMRegister xmm_temp3  = xmm4;
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2207
    const XMMRegister xmm_temp4  = xmm5;
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2208
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2209
    __ enter();   // required for proper stackwalking of RuntimeStub frame
32727
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2210
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2211
    // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2212
    // context for the registers used, where all instructions below are using 128-bit mode
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2213
    // On EVEX without VL and BW, these instructions will all be AVX.
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2214
    if (VM_Version::supports_avx512vlbw()) {
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2215
      __ movl(rdx, 0xffff);
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2216
      __ kmovdl(k1, rdx);
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2217
    }
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2218
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2219
    __ movptr(from, from_param);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2220
    __ movptr(key, key_param);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2221
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2222
    // keylen could be only {11, 13, 15} * 4 = {44, 52, 60}
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2223
    __ movl(keylen, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2224
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2225
    __ movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2226
    __ movdqu(xmm_result, Address(from, 0));  // get 16 bytes of input
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2227
    __ movptr(to, to_param);
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2228
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2229
    // For encryption, the java expanded key ordering is just what we need
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2230
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2231
    load_key(xmm_temp1, key, 0x00, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2232
    __ pxor(xmm_result, xmm_temp1);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2233
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2234
    load_key(xmm_temp1, key, 0x10, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2235
    load_key(xmm_temp2, key, 0x20, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2236
    load_key(xmm_temp3, key, 0x30, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2237
    load_key(xmm_temp4, key, 0x40, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2238
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2239
    __ aesenc(xmm_result, xmm_temp1);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2240
    __ aesenc(xmm_result, xmm_temp2);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2241
    __ aesenc(xmm_result, xmm_temp3);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2242
    __ aesenc(xmm_result, xmm_temp4);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2243
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2244
    load_key(xmm_temp1, key, 0x50, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2245
    load_key(xmm_temp2, key, 0x60, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2246
    load_key(xmm_temp3, key, 0x70, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2247
    load_key(xmm_temp4, key, 0x80, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2248
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2249
    __ aesenc(xmm_result, xmm_temp1);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2250
    __ aesenc(xmm_result, xmm_temp2);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2251
    __ aesenc(xmm_result, xmm_temp3);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2252
    __ aesenc(xmm_result, xmm_temp4);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2253
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2254
    load_key(xmm_temp1, key, 0x90, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2255
    load_key(xmm_temp2, key, 0xa0, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2256
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2257
    __ cmpl(keylen, 44);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2258
    __ jccb(Assembler::equal, L_doLast);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2259
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2260
    __ aesenc(xmm_result, xmm_temp1);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2261
    __ aesenc(xmm_result, xmm_temp2);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2262
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2263
    load_key(xmm_temp1, key, 0xb0, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2264
    load_key(xmm_temp2, key, 0xc0, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2265
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2266
    __ cmpl(keylen, 52);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2267
    __ jccb(Assembler::equal, L_doLast);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2268
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2269
    __ aesenc(xmm_result, xmm_temp1);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2270
    __ aesenc(xmm_result, xmm_temp2);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2271
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2272
    load_key(xmm_temp1, key, 0xd0, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2273
    load_key(xmm_temp2, key, 0xe0, xmm_key_shuf_mask);
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2274
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2275
    __ BIND(L_doLast);
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2276
    __ aesenc(xmm_result, xmm_temp1);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2277
    __ aesenclast(xmm_result, xmm_temp2);
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2278
    __ movdqu(Address(to, 0), xmm_result);        // store the result
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2279
    __ xorptr(rax, rax); // return 0
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2280
    __ leave(); // required for proper stackwalking of RuntimeStub frame
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2281
    __ ret(0);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2282
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2283
    return start;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2284
  }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2285
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2286
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2287
  // Arguments:
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2288
  //
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2289
  // Inputs:
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2290
  //   c_rarg0   - source byte array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2291
  //   c_rarg1   - destination byte array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2292
  //   c_rarg2   - K (key) in little endian int array
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2293
  //
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2294
  address generate_aescrypt_decryptBlock() {
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2295
    assert(UseAES, "need AES instructions and misaligned SSE support");
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2296
    __ align(CodeEntryAlignment);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2297
    StubCodeMark mark(this, "StubRoutines", "aescrypt_decryptBlock");
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2298
    Label L_doLast;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2299
    address start = __ pc();
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2300
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2301
    const Register from        = rdx;      // source array address
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2302
    const Register to          = rdx;      // destination array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2303
    const Register key         = rcx;      // key array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2304
    const Register keylen      = rax;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2305
    const Address  from_param(rbp, 8+0);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2306
    const Address  to_param  (rbp, 8+4);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2307
    const Address  key_param (rbp, 8+8);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2308
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2309
    const XMMRegister xmm_result = xmm0;
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2310
    const XMMRegister xmm_key_shuf_mask = xmm1;
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2311
    const XMMRegister xmm_temp1  = xmm2;
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2312
    const XMMRegister xmm_temp2  = xmm3;
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2313
    const XMMRegister xmm_temp3  = xmm4;
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2314
    const XMMRegister xmm_temp4  = xmm5;
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2315
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2316
    __ enter(); // required for proper stackwalking of RuntimeStub frame
32727
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2317
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2318
    // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2319
    // context for the registers used, where all instructions below are using 128-bit mode
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2320
    // On EVEX without VL and BW, these instructions will all be AVX.
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2321
    if (VM_Version::supports_avx512vlbw()) {
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2322
      __ movl(rdx, 0xffff);
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2323
      __ kmovdl(k1, rdx);
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2324
    }
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2325
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2326
    __ movptr(from, from_param);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2327
    __ movptr(key, key_param);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2328
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2329
    // keylen could be only {11, 13, 15} * 4 = {44, 52, 60}
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2330
    __ movl(keylen, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2331
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2332
    __ movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2333
    __ movdqu(xmm_result, Address(from, 0));
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2334
    __ movptr(to, to_param);
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2335
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2336
    // for decryption java expanded key ordering is rotated one position from what we want
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2337
    // so we start from 0x10 here and hit 0x00 last
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2338
    // we don't know if the key is aligned, hence not using load-execute form
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2339
    load_key(xmm_temp1, key, 0x10, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2340
    load_key(xmm_temp2, key, 0x20, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2341
    load_key(xmm_temp3, key, 0x30, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2342
    load_key(xmm_temp4, key, 0x40, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2343
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2344
    __ pxor  (xmm_result, xmm_temp1);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2345
    __ aesdec(xmm_result, xmm_temp2);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2346
    __ aesdec(xmm_result, xmm_temp3);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2347
    __ aesdec(xmm_result, xmm_temp4);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2348
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2349
    load_key(xmm_temp1, key, 0x50, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2350
    load_key(xmm_temp2, key, 0x60, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2351
    load_key(xmm_temp3, key, 0x70, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2352
    load_key(xmm_temp4, key, 0x80, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2353
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2354
    __ aesdec(xmm_result, xmm_temp1);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2355
    __ aesdec(xmm_result, xmm_temp2);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2356
    __ aesdec(xmm_result, xmm_temp3);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2357
    __ aesdec(xmm_result, xmm_temp4);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2358
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2359
    load_key(xmm_temp1, key, 0x90, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2360
    load_key(xmm_temp2, key, 0xa0, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2361
    load_key(xmm_temp3, key, 0x00, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2362
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2363
    __ cmpl(keylen, 44);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2364
    __ jccb(Assembler::equal, L_doLast);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2365
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2366
    __ aesdec(xmm_result, xmm_temp1);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2367
    __ aesdec(xmm_result, xmm_temp2);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2368
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2369
    load_key(xmm_temp1, key, 0xb0, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2370
    load_key(xmm_temp2, key, 0xc0, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2371
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2372
    __ cmpl(keylen, 52);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2373
    __ jccb(Assembler::equal, L_doLast);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2374
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2375
    __ aesdec(xmm_result, xmm_temp1);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2376
    __ aesdec(xmm_result, xmm_temp2);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2377
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2378
    load_key(xmm_temp1, key, 0xd0, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2379
    load_key(xmm_temp2, key, 0xe0, xmm_key_shuf_mask);
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2380
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2381
    __ BIND(L_doLast);
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2382
    __ aesdec(xmm_result, xmm_temp1);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2383
    __ aesdec(xmm_result, xmm_temp2);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2384
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2385
    // for decryption the aesdeclast operation is always on key+0x00
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2386
    __ aesdeclast(xmm_result, xmm_temp3);
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2387
    __ movdqu(Address(to, 0), xmm_result);  // store the result
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2388
    __ xorptr(rax, rax); // return 0
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2389
    __ leave(); // required for proper stackwalking of RuntimeStub frame
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2390
    __ ret(0);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2391
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2392
    return start;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2393
  }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2394
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2395
  void handleSOERegisters(bool saving) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2396
    const int saveFrameSizeInBytes = 4 * wordSize;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2397
    const Address saved_rbx     (rbp, -3 * wordSize);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2398
    const Address saved_rsi     (rbp, -2 * wordSize);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2399
    const Address saved_rdi     (rbp, -1 * wordSize);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2400
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2401
    if (saving) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2402
      __ subptr(rsp, saveFrameSizeInBytes);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2403
      __ movptr(saved_rsi, rsi);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2404
      __ movptr(saved_rdi, rdi);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2405
      __ movptr(saved_rbx, rbx);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2406
    } else {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2407
      // restoring
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2408
      __ movptr(rsi, saved_rsi);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2409
      __ movptr(rdi, saved_rdi);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2410
      __ movptr(rbx, saved_rbx);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2411
    }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2412
  }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2413
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2414
  // Arguments:
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2415
  //
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2416
  // Inputs:
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2417
  //   c_rarg0   - source byte array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2418
  //   c_rarg1   - destination byte array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2419
  //   c_rarg2   - K (key) in little endian int array
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2420
  //   c_rarg3   - r vector byte array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2421
  //   c_rarg4   - input length
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2422
  //
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  2423
  // Output:
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  2424
  //   rax       - input length
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  2425
  //
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2426
  address generate_cipherBlockChaining_encryptAESCrypt() {
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2427
    assert(UseAES, "need AES instructions and misaligned SSE support");
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2428
    __ align(CodeEntryAlignment);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2429
    StubCodeMark mark(this, "StubRoutines", "cipherBlockChaining_encryptAESCrypt");
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2430
    address start = __ pc();
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2431
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2432
    Label L_exit, L_key_192_256, L_key_256, L_loopTop_128, L_loopTop_192, L_loopTop_256;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2433
    const Register from        = rsi;      // source array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2434
    const Register to          = rdx;      // destination array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2435
    const Register key         = rcx;      // key array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2436
    const Register rvec        = rdi;      // r byte array initialized from initvector array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2437
                                           // and left with the results of the last encryption block
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2438
    const Register len_reg     = rbx;      // src len (must be multiple of blocksize 16)
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2439
    const Register pos         = rax;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2440
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2441
    // xmm register assignments for the loops below
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2442
    const XMMRegister xmm_result = xmm0;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2443
    const XMMRegister xmm_temp   = xmm1;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2444
    // first 6 keys preloaded into xmm2-xmm7
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2445
    const int XMM_REG_NUM_KEY_FIRST = 2;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2446
    const int XMM_REG_NUM_KEY_LAST  = 7;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2447
    const XMMRegister xmm_key0   = as_XMMRegister(XMM_REG_NUM_KEY_FIRST);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2448
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2449
    __ enter(); // required for proper stackwalking of RuntimeStub frame
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2450
    handleSOERegisters(true /*saving*/);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2451
32727
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2452
    // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2453
    // context for the registers used, where all instructions below are using 128-bit mode
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2454
    // On EVEX without VL and BW, these instructions will all be AVX.
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2455
    if (VM_Version::supports_avx512vlbw()) {
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2456
      __ movl(rdx, 0xffff);
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2457
      __ kmovdl(k1, rdx);
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2458
    }
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2459
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2460
    // load registers from incoming parameters
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2461
    const Address  from_param(rbp, 8+0);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2462
    const Address  to_param  (rbp, 8+4);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2463
    const Address  key_param (rbp, 8+8);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2464
    const Address  rvec_param (rbp, 8+12);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2465
    const Address  len_param  (rbp, 8+16);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2466
    __ movptr(from , from_param);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2467
    __ movptr(to   , to_param);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2468
    __ movptr(key  , key_param);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2469
    __ movptr(rvec , rvec_param);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2470
    __ movptr(len_reg , len_param);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2471
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2472
    const XMMRegister xmm_key_shuf_mask = xmm_temp;  // used temporarily to swap key bytes up front
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2473
    __ movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2474
    // load up xmm regs 2 thru 7 with keys 0-5
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2475
    for (int rnum = XMM_REG_NUM_KEY_FIRST, offset = 0x00; rnum  <= XMM_REG_NUM_KEY_LAST; rnum++) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2476
      load_key(as_XMMRegister(rnum), key, offset, xmm_key_shuf_mask);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2477
      offset += 0x10;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2478
    }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2479
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2480
    __ movdqu(xmm_result, Address(rvec, 0x00));   // initialize xmm_result with r vec
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2481
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2482
    // now split to different paths depending on the keylen (len in ints of AESCrypt.KLE array (52=192, or 60=256))
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2483
    __ movl(rax, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2484
    __ cmpl(rax, 44);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2485
    __ jcc(Assembler::notEqual, L_key_192_256);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2486
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2487
    // 128 bit code follows here
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2488
    __ movl(pos, 0);
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2489
    __ align(OptoLoopAlignment);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2490
    __ BIND(L_loopTop_128);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2491
    __ movdqu(xmm_temp, Address(from, pos, Address::times_1, 0));   // get next 16 bytes of input
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2492
    __ pxor  (xmm_result, xmm_temp);                                // xor with the current r vector
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2493
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2494
    __ pxor  (xmm_result, xmm_key0);                                // do the aes rounds
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2495
    for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum  <= XMM_REG_NUM_KEY_LAST; rnum++) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2496
      __ aesenc(xmm_result, as_XMMRegister(rnum));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2497
    }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2498
    for (int key_offset = 0x60; key_offset <= 0x90; key_offset += 0x10) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2499
      aes_enc_key(xmm_result, xmm_temp, key, key_offset);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2500
    }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2501
    load_key(xmm_temp, key, 0xa0);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2502
    __ aesenclast(xmm_result, xmm_temp);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2503
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2504
    __ movdqu(Address(to, pos, Address::times_1, 0), xmm_result);     // store into the next 16 bytes of output
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2505
    // no need to store r to memory until we exit
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2506
    __ addptr(pos, AESBlockSize);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2507
    __ subptr(len_reg, AESBlockSize);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2508
    __ jcc(Assembler::notEqual, L_loopTop_128);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2509
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2510
    __ BIND(L_exit);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2511
    __ movdqu(Address(rvec, 0), xmm_result);     // final value of r stored in rvec of CipherBlockChaining object
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2512
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2513
    handleSOERegisters(false /*restoring*/);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  2514
    __ movptr(rax, len_param); // return length
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2515
    __ leave();                                  // required for proper stackwalking of RuntimeStub frame
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2516
    __ ret(0);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2517
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2518
    __ BIND(L_key_192_256);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2519
    // here rax = len in ints of AESCrypt.KLE array (52=192, or 60=256)
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2520
    __ cmpl(rax, 52);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2521
    __ jcc(Assembler::notEqual, L_key_256);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2522
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2523
    // 192-bit code follows here (could be changed to use more xmm registers)
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2524
    __ movl(pos, 0);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2525
    __ align(OptoLoopAlignment);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2526
    __ BIND(L_loopTop_192);
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2527
    __ movdqu(xmm_temp, Address(from, pos, Address::times_1, 0));   // get next 16 bytes of input
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2528
    __ pxor  (xmm_result, xmm_temp);                                // xor with the current r vector
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2529
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2530
    __ pxor  (xmm_result, xmm_key0);                                // do the aes rounds
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2531
    for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum  <= XMM_REG_NUM_KEY_LAST; rnum++) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2532
      __ aesenc(xmm_result, as_XMMRegister(rnum));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2533
    }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2534
    for (int key_offset = 0x60; key_offset <= 0xb0; key_offset += 0x10) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2535
      aes_enc_key(xmm_result, xmm_temp, key, key_offset);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2536
    }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2537
    load_key(xmm_temp, key, 0xc0);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2538
    __ aesenclast(xmm_result, xmm_temp);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2539
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2540
    __ movdqu(Address(to, pos, Address::times_1, 0), xmm_result);   // store into the next 16 bytes of output
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2541
    // no need to store r to memory until we exit
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2542
    __ addptr(pos, AESBlockSize);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2543
    __ subptr(len_reg, AESBlockSize);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2544
    __ jcc(Assembler::notEqual, L_loopTop_192);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2545
    __ jmp(L_exit);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2546
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2547
    __ BIND(L_key_256);
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2548
    // 256-bit code follows here (could be changed to use more xmm registers)
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2549
    __ movl(pos, 0);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2550
    __ align(OptoLoopAlignment);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2551
    __ BIND(L_loopTop_256);
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2552
    __ movdqu(xmm_temp, Address(from, pos, Address::times_1, 0));   // get next 16 bytes of input
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2553
    __ pxor  (xmm_result, xmm_temp);                                // xor with the current r vector
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2554
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2555
    __ pxor  (xmm_result, xmm_key0);                                // do the aes rounds
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2556
    for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum  <= XMM_REG_NUM_KEY_LAST; rnum++) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2557
      __ aesenc(xmm_result, as_XMMRegister(rnum));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2558
    }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2559
    for (int key_offset = 0x60; key_offset <= 0xd0; key_offset += 0x10) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2560
      aes_enc_key(xmm_result, xmm_temp, key, key_offset);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2561
    }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2562
    load_key(xmm_temp, key, 0xe0);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2563
    __ aesenclast(xmm_result, xmm_temp);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2564
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2565
    __ movdqu(Address(to, pos, Address::times_1, 0), xmm_result);   // store into the next 16 bytes of output
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2566
    // no need to store r to memory until we exit
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2567
    __ addptr(pos, AESBlockSize);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2568
    __ subptr(len_reg, AESBlockSize);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2569
    __ jcc(Assembler::notEqual, L_loopTop_256);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2570
    __ jmp(L_exit);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2571
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2572
    return start;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2573
  }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2574
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2575
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2576
  // CBC AES Decryption.
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2577
  // In 32-bit stub, because of lack of registers we do not try to parallelize 4 blocks at a time.
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2578
  //
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2579
  // Arguments:
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2580
  //
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2581
  // Inputs:
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2582
  //   c_rarg0   - source byte array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2583
  //   c_rarg1   - destination byte array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2584
  //   c_rarg2   - K (key) in little endian int array
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2585
  //   c_rarg3   - r vector byte array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2586
  //   c_rarg4   - input length
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2587
  //
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  2588
  // Output:
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  2589
  //   rax       - input length
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  2590
  //
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2591
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2592
  address generate_cipherBlockChaining_decryptAESCrypt() {
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2593
    assert(UseAES, "need AES instructions and misaligned SSE support");
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2594
    __ align(CodeEntryAlignment);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2595
    StubCodeMark mark(this, "StubRoutines", "cipherBlockChaining_decryptAESCrypt");
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2596
    address start = __ pc();
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2597
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2598
    Label L_exit, L_key_192_256, L_key_256;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2599
    Label L_singleBlock_loopTop_128;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2600
    Label L_singleBlock_loopTop_192, L_singleBlock_loopTop_256;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2601
    const Register from        = rsi;      // source array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2602
    const Register to          = rdx;      // destination array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2603
    const Register key         = rcx;      // key array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2604
    const Register rvec        = rdi;      // r byte array initialized from initvector array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2605
                                           // and left with the results of the last encryption block
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2606
    const Register len_reg     = rbx;      // src len (must be multiple of blocksize 16)
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2607
    const Register pos         = rax;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2608
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2609
    // xmm register assignments for the loops below
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2610
    const XMMRegister xmm_result = xmm0;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2611
    const XMMRegister xmm_temp   = xmm1;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2612
    // first 6 keys preloaded into xmm2-xmm7
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2613
    const int XMM_REG_NUM_KEY_FIRST = 2;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2614
    const int XMM_REG_NUM_KEY_LAST  = 7;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2615
    const int FIRST_NON_REG_KEY_offset = 0x70;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2616
    const XMMRegister xmm_key_first   = as_XMMRegister(XMM_REG_NUM_KEY_FIRST);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2617
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2618
    __ enter(); // required for proper stackwalking of RuntimeStub frame
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2619
    handleSOERegisters(true /*saving*/);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2620
32727
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2621
    // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2622
    // context for the registers used, where all instructions below are using 128-bit mode
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2623
    // On EVEX without VL and BW, these instructions will all be AVX.
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2624
    if (VM_Version::supports_avx512vlbw()) {
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2625
      __ movl(rdx, 0xffff);
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2626
      __ kmovdl(k1, rdx);
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2627
    }
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2628
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2629
    // load registers from incoming parameters
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2630
    const Address  from_param(rbp, 8+0);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2631
    const Address  to_param  (rbp, 8+4);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2632
    const Address  key_param (rbp, 8+8);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2633
    const Address  rvec_param (rbp, 8+12);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2634
    const Address  len_param  (rbp, 8+16);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2635
    __ movptr(from , from_param);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2636
    __ movptr(to   , to_param);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2637
    __ movptr(key  , key_param);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2638
    __ movptr(rvec , rvec_param);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2639
    __ movptr(len_reg , len_param);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2640
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2641
    // the java expanded key ordering is rotated one position from what we want
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2642
    // so we start from 0x10 here and hit 0x00 last
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2643
    const XMMRegister xmm_key_shuf_mask = xmm1;  // used temporarily to swap key bytes up front
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2644
    __ movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2645
    // load up xmm regs 2 thru 6 with first 5 keys
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2646
    for (int rnum = XMM_REG_NUM_KEY_FIRST, offset = 0x10; rnum  <= XMM_REG_NUM_KEY_LAST; rnum++) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2647
      load_key(as_XMMRegister(rnum), key, offset, xmm_key_shuf_mask);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2648
      offset += 0x10;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2649
    }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2650
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2651
    // inside here, use the rvec register to point to previous block cipher
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2652
    // with which we xor at the end of each newly decrypted block
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2653
    const Register  prev_block_cipher_ptr = rvec;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2654
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2655
    // now split to different paths depending on the keylen (len in ints of AESCrypt.KLE array (52=192, or 60=256))
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2656
    __ movl(rax, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2657
    __ cmpl(rax, 44);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2658
    __ jcc(Assembler::notEqual, L_key_192_256);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2659
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2660
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2661
    // 128-bit code follows here, parallelized
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2662
    __ movl(pos, 0);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2663
    __ align(OptoLoopAlignment);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2664
    __ BIND(L_singleBlock_loopTop_128);
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2665
    __ cmpptr(len_reg, 0);           // any blocks left??
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2666
    __ jcc(Assembler::equal, L_exit);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2667
    __ movdqu(xmm_result, Address(from, pos, Address::times_1, 0));   // get next 16 bytes of cipher input
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2668
    __ pxor  (xmm_result, xmm_key_first);                             // do the aes dec rounds
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2669
    for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum  <= XMM_REG_NUM_KEY_LAST; rnum++) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2670
      __ aesdec(xmm_result, as_XMMRegister(rnum));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2671
    }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2672
    for (int key_offset = FIRST_NON_REG_KEY_offset; key_offset <= 0xa0; key_offset += 0x10) {   // 128-bit runs up to key offset a0
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2673
      aes_dec_key(xmm_result, xmm_temp, key, key_offset);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2674
    }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2675
    load_key(xmm_temp, key, 0x00);                                     // final key is stored in java expanded array at offset 0
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2676
    __ aesdeclast(xmm_result, xmm_temp);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2677
    __ movdqu(xmm_temp, Address(prev_block_cipher_ptr, 0x00));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2678
    __ pxor  (xmm_result, xmm_temp);                                  // xor with the current r vector
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2679
    __ movdqu(Address(to, pos, Address::times_1, 0), xmm_result);     // store into the next 16 bytes of output
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2680
    // no need to store r to memory until we exit
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2681
    __ lea(prev_block_cipher_ptr, Address(from, pos, Address::times_1, 0));     // set up new ptr
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2682
    __ addptr(pos, AESBlockSize);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2683
    __ subptr(len_reg, AESBlockSize);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2684
    __ jmp(L_singleBlock_loopTop_128);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2685
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2686
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2687
    __ BIND(L_exit);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2688
    __ movdqu(xmm_temp, Address(prev_block_cipher_ptr, 0x00));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2689
    __ movptr(rvec , rvec_param);                                     // restore this since used in loop
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2690
    __ movdqu(Address(rvec, 0), xmm_temp);                            // final value of r stored in rvec of CipherBlockChaining object
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2691
    handleSOERegisters(false /*restoring*/);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  2692
    __ movptr(rax, len_param); // return length
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2693
    __ leave();                                                       // required for proper stackwalking of RuntimeStub frame
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2694
    __ ret(0);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2695
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2696
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2697
    __ BIND(L_key_192_256);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2698
    // here rax = len in ints of AESCrypt.KLE array (52=192, or 60=256)
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2699
    __ cmpl(rax, 52);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2700
    __ jcc(Assembler::notEqual, L_key_256);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2701
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2702
    // 192-bit code follows here (could be optimized to use parallelism)
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2703
    __ movl(pos, 0);
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2704
    __ align(OptoLoopAlignment);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2705
    __ BIND(L_singleBlock_loopTop_192);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2706
    __ movdqu(xmm_result, Address(from, pos, Address::times_1, 0));   // get next 16 bytes of cipher input
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2707
    __ pxor  (xmm_result, xmm_key_first);                             // do the aes dec rounds
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2708
    for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum <= XMM_REG_NUM_KEY_LAST; rnum++) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2709
      __ aesdec(xmm_result, as_XMMRegister(rnum));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2710
    }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2711
    for (int key_offset = FIRST_NON_REG_KEY_offset; key_offset <= 0xc0; key_offset += 0x10) {   // 192-bit runs up to key offset c0
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2712
      aes_dec_key(xmm_result, xmm_temp, key, key_offset);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2713
    }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2714
    load_key(xmm_temp, key, 0x00);                                     // final key is stored in java expanded array at offset 0
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2715
    __ aesdeclast(xmm_result, xmm_temp);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2716
    __ movdqu(xmm_temp, Address(prev_block_cipher_ptr, 0x00));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2717
    __ pxor  (xmm_result, xmm_temp);                                  // xor with the current r vector
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2718
    __ movdqu(Address(to, pos, Address::times_1, 0), xmm_result);     // store into the next 16 bytes of output
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2719
    // no need to store r to memory until we exit
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2720
    __ lea(prev_block_cipher_ptr, Address(from, pos, Address::times_1, 0));     // set up new ptr
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2721
    __ addptr(pos, AESBlockSize);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2722
    __ subptr(len_reg, AESBlockSize);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2723
    __ jcc(Assembler::notEqual,L_singleBlock_loopTop_192);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2724
    __ jmp(L_exit);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2725
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2726
    __ BIND(L_key_256);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2727
    // 256-bit code follows here (could be optimized to use parallelism)
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  2728
    __ movl(pos, 0);
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2729
    __ align(OptoLoopAlignment);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2730
    __ BIND(L_singleBlock_loopTop_256);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2731
    __ movdqu(xmm_result, Address(from, pos, Address::times_1, 0));   // get next 16 bytes of cipher input
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2732
    __ pxor  (xmm_result, xmm_key_first);                             // do the aes dec rounds
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2733
    for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum <= XMM_REG_NUM_KEY_LAST; rnum++) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2734
      __ aesdec(xmm_result, as_XMMRegister(rnum));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2735
    }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2736
    for (int key_offset = FIRST_NON_REG_KEY_offset; key_offset <= 0xe0; key_offset += 0x10) {   // 256-bit runs up to key offset e0
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2737
      aes_dec_key(xmm_result, xmm_temp, key, key_offset);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2738
    }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2739
    load_key(xmm_temp, key, 0x00);                                     // final key is stored in java expanded array at offset 0
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2740
    __ aesdeclast(xmm_result, xmm_temp);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2741
    __ movdqu(xmm_temp, Address(prev_block_cipher_ptr, 0x00));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2742
    __ pxor  (xmm_result, xmm_temp);                                  // xor with the current r vector
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2743
    __ movdqu(Address(to, pos, Address::times_1, 0), xmm_result);     // store into the next 16 bytes of output
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2744
    // no need to store r to memory until we exit
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2745
    __ lea(prev_block_cipher_ptr, Address(from, pos, Address::times_1, 0));     // set up new ptr
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2746
    __ addptr(pos, AESBlockSize);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2747
    __ subptr(len_reg, AESBlockSize);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2748
    __ jcc(Assembler::notEqual,L_singleBlock_loopTop_256);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2749
    __ jmp(L_exit);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2750
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2751
    return start;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2752
  }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2753
31404
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2754
  // byte swap x86 long
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2755
  address generate_ghash_long_swap_mask() {
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2756
    __ align(CodeEntryAlignment);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2757
    StubCodeMark mark(this, "StubRoutines", "ghash_long_swap_mask");
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2758
    address start = __ pc();
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2759
    __ emit_data(0x0b0a0908, relocInfo::none, 0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2760
    __ emit_data(0x0f0e0d0c, relocInfo::none, 0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2761
    __ emit_data(0x03020100, relocInfo::none, 0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2762
    __ emit_data(0x07060504, relocInfo::none, 0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2763
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2764
  return start;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2765
  }
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2766
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2767
  // byte swap x86 byte array
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2768
  address generate_ghash_byte_swap_mask() {
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2769
    __ align(CodeEntryAlignment);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2770
    StubCodeMark mark(this, "StubRoutines", "ghash_byte_swap_mask");
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2771
    address start = __ pc();
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2772
    __ emit_data(0x0c0d0e0f, relocInfo::none, 0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2773
    __ emit_data(0x08090a0b, relocInfo::none, 0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2774
    __ emit_data(0x04050607, relocInfo::none, 0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2775
    __ emit_data(0x00010203, relocInfo::none, 0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2776
  return start;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2777
  }
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2778
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2779
  /* Single and multi-block ghash operations */
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2780
  address generate_ghash_processBlocks() {
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2781
    assert(UseGHASHIntrinsics, "need GHASH intrinsics and CLMUL support");
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2782
    __ align(CodeEntryAlignment);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2783
    Label L_ghash_loop, L_exit;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2784
    StubCodeMark mark(this, "StubRoutines", "ghash_processBlocks");
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2785
    address start = __ pc();
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2786
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2787
    const Register state        = rdi;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2788
    const Register subkeyH      = rsi;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2789
    const Register data         = rdx;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2790
    const Register blocks       = rcx;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2791
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2792
    const Address  state_param(rbp, 8+0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2793
    const Address  subkeyH_param(rbp, 8+4);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2794
    const Address  data_param(rbp, 8+8);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2795
    const Address  blocks_param(rbp, 8+12);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2796
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2797
    const XMMRegister xmm_temp0 = xmm0;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2798
    const XMMRegister xmm_temp1 = xmm1;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2799
    const XMMRegister xmm_temp2 = xmm2;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2800
    const XMMRegister xmm_temp3 = xmm3;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2801
    const XMMRegister xmm_temp4 = xmm4;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2802
    const XMMRegister xmm_temp5 = xmm5;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2803
    const XMMRegister xmm_temp6 = xmm6;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2804
    const XMMRegister xmm_temp7 = xmm7;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2805
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2806
    __ enter();
31771
c9f593020799 8130341: GHASH 32bit intrinsics has AEADBadTagException
ascarpino
parents: 31404
diff changeset
  2807
    handleSOERegisters(true);  // Save registers
31404
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2808
32727
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2809
    // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2810
    // context for the registers used, where all instructions below are using 128-bit mode
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2811
    // On EVEX without VL and BW, these instructions will all be AVX.
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2812
    if (VM_Version::supports_avx512vlbw()) {
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2813
      __ movl(rdx, 0xffff);
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2814
      __ kmovdl(k1, rdx);
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2815
    }
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  2816
31404
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2817
    __ movptr(state, state_param);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2818
    __ movptr(subkeyH, subkeyH_param);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2819
    __ movptr(data, data_param);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2820
    __ movptr(blocks, blocks_param);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2821
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2822
    __ movdqu(xmm_temp0, Address(state, 0));
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2823
    __ pshufb(xmm_temp0, ExternalAddress(StubRoutines::x86::ghash_long_swap_mask_addr()));
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2824
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2825
    __ movdqu(xmm_temp1, Address(subkeyH, 0));
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2826
    __ pshufb(xmm_temp1, ExternalAddress(StubRoutines::x86::ghash_long_swap_mask_addr()));
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2827
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2828
    __ BIND(L_ghash_loop);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2829
    __ movdqu(xmm_temp2, Address(data, 0));
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2830
    __ pshufb(xmm_temp2, ExternalAddress(StubRoutines::x86::ghash_byte_swap_mask_addr()));
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2831
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2832
    __ pxor(xmm_temp0, xmm_temp2);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2833
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2834
    //
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2835
    // Multiply with the hash key
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2836
    //
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2837
    __ movdqu(xmm_temp3, xmm_temp0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2838
    __ pclmulqdq(xmm_temp3, xmm_temp1, 0);      // xmm3 holds a0*b0
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2839
    __ movdqu(xmm_temp4, xmm_temp0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2840
    __ pclmulqdq(xmm_temp4, xmm_temp1, 16);     // xmm4 holds a0*b1
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2841
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2842
    __ movdqu(xmm_temp5, xmm_temp0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2843
    __ pclmulqdq(xmm_temp5, xmm_temp1, 1);      // xmm5 holds a1*b0
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2844
    __ movdqu(xmm_temp6, xmm_temp0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2845
    __ pclmulqdq(xmm_temp6, xmm_temp1, 17);     // xmm6 holds a1*b1
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2846
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2847
    __ pxor(xmm_temp4, xmm_temp5);      // xmm4 holds a0*b1 + a1*b0
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2848
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2849
    __ movdqu(xmm_temp5, xmm_temp4);    // move the contents of xmm4 to xmm5
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2850
    __ psrldq(xmm_temp4, 8);    // shift by xmm4 64 bits to the right
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2851
    __ pslldq(xmm_temp5, 8);    // shift by xmm5 64 bits to the left
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2852
    __ pxor(xmm_temp3, xmm_temp5);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2853
    __ pxor(xmm_temp6, xmm_temp4);      // Register pair <xmm6:xmm3> holds the result
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2854
                                        // of the carry-less multiplication of
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2855
                                        // xmm0 by xmm1.
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2856
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2857
    // We shift the result of the multiplication by one bit position
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2858
    // to the left to cope for the fact that the bits are reversed.
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2859
    __ movdqu(xmm_temp7, xmm_temp3);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2860
    __ movdqu(xmm_temp4, xmm_temp6);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2861
    __ pslld (xmm_temp3, 1);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2862
    __ pslld(xmm_temp6, 1);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2863
    __ psrld(xmm_temp7, 31);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2864
    __ psrld(xmm_temp4, 31);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2865
    __ movdqu(xmm_temp5, xmm_temp7);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2866
    __ pslldq(xmm_temp4, 4);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2867
    __ pslldq(xmm_temp7, 4);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2868
    __ psrldq(xmm_temp5, 12);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2869
    __ por(xmm_temp3, xmm_temp7);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2870
    __ por(xmm_temp6, xmm_temp4);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2871
    __ por(xmm_temp6, xmm_temp5);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2872
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2873
    //
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2874
    // First phase of the reduction
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2875
    //
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2876
    // Move xmm3 into xmm4, xmm5, xmm7 in order to perform the shifts
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2877
    // independently.
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2878
    __ movdqu(xmm_temp7, xmm_temp3);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2879
    __ movdqu(xmm_temp4, xmm_temp3);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2880
    __ movdqu(xmm_temp5, xmm_temp3);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2881
    __ pslld(xmm_temp7, 31);    // packed right shift shifting << 31
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2882
    __ pslld(xmm_temp4, 30);    // packed right shift shifting << 30
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2883
    __ pslld(xmm_temp5, 25);    // packed right shift shifting << 25
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2884
    __ pxor(xmm_temp7, xmm_temp4);      // xor the shifted versions
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2885
    __ pxor(xmm_temp7, xmm_temp5);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2886
    __ movdqu(xmm_temp4, xmm_temp7);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2887
    __ pslldq(xmm_temp7, 12);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2888
    __ psrldq(xmm_temp4, 4);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2889
    __ pxor(xmm_temp3, xmm_temp7);      // first phase of the reduction complete
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2890
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2891
    //
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2892
    // Second phase of the reduction
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2893
    //
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2894
    // Make 3 copies of xmm3 in xmm2, xmm5, xmm7 for doing these
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2895
    // shift operations.
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2896
    __ movdqu(xmm_temp2, xmm_temp3);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2897
    __ movdqu(xmm_temp7, xmm_temp3);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2898
    __ movdqu(xmm_temp5, xmm_temp3);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2899
    __ psrld(xmm_temp2, 1);     // packed left shifting >> 1
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2900
    __ psrld(xmm_temp7, 2);     // packed left shifting >> 2
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2901
    __ psrld(xmm_temp5, 7);     // packed left shifting >> 7
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2902
    __ pxor(xmm_temp2, xmm_temp7);      // xor the shifted versions
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2903
    __ pxor(xmm_temp2, xmm_temp5);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2904
    __ pxor(xmm_temp2, xmm_temp4);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2905
    __ pxor(xmm_temp3, xmm_temp2);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2906
    __ pxor(xmm_temp6, xmm_temp3);      // the result is in xmm6
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2907
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2908
    __ decrement(blocks);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2909
    __ jcc(Assembler::zero, L_exit);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2910
    __ movdqu(xmm_temp0, xmm_temp6);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2911
    __ addptr(data, 16);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2912
    __ jmp(L_ghash_loop);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2913
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2914
    __ BIND(L_exit);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2915
       // Byte swap 16-byte result
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2916
    __ pshufb(xmm_temp6, ExternalAddress(StubRoutines::x86::ghash_long_swap_mask_addr()));
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2917
    __ movdqu(Address(state, 0), xmm_temp6);   // store the result
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2918
31771
c9f593020799 8130341: GHASH 32bit intrinsics has AEADBadTagException
ascarpino
parents: 31404
diff changeset
  2919
    handleSOERegisters(false);  // restore registers
31404
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2920
    __ leave();
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2921
    __ ret(0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2922
    return start;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2923
  }
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  2924
18507
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2925
  /**
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2926
   *  Arguments:
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2927
   *
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2928
   * Inputs:
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2929
   *   rsp(4)   - int crc
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2930
   *   rsp(8)   - byte* buf
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2931
   *   rsp(12)  - int length
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2932
   *
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2933
   * Ouput:
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2934
   *       rax   - int crc result
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2935
   */
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2936
  address generate_updateBytesCRC32() {
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2937
    assert(UseCRC32Intrinsics, "need AVX and CLMUL instructions");
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2938
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2939
    __ align(CodeEntryAlignment);
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2940
    StubCodeMark mark(this, "StubRoutines", "updateBytesCRC32");
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2941
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2942
    address start = __ pc();
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2943
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2944
    const Register crc   = rdx;  // crc
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2945
    const Register buf   = rsi;  // source java byte array address
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2946
    const Register len   = rcx;  // length
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2947
    const Register table = rdi;  // crc_table address (reuse register)
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2948
    const Register tmp   = rbx;
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2949
    assert_different_registers(crc, buf, len, table, tmp, rax);
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2950
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2951
    BLOCK_COMMENT("Entry:");
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2952
    __ enter(); // required for proper stackwalking of RuntimeStub frame
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2953
    __ push(rsi);
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2954
    __ push(rdi);
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2955
    __ push(rbx);
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2956
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2957
    Address crc_arg(rbp, 8 + 0);
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2958
    Address buf_arg(rbp, 8 + 4);
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2959
    Address len_arg(rbp, 8 + 8);
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2960
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2961
    // Load up:
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2962
    __ movl(crc,   crc_arg);
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2963
    __ movptr(buf, buf_arg);
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2964
    __ movl(len,   len_arg);
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2965
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2966
    __ kernel_crc32(crc, buf, len, table, tmp);
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2967
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2968
    __ movl(rax, crc);
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2969
    __ pop(rbx);
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2970
    __ pop(rdi);
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2971
    __ pop(rsi);
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2972
    __ leave(); // required for proper stackwalking of RuntimeStub frame
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2973
    __ ret(0);
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2974
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2975
    return start;
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2976
  }
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  2977
33066
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  2978
  /**
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  2979
  *  Arguments:
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  2980
  *
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  2981
  * Inputs:
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  2982
  *   rsp(4)   - int crc
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  2983
  *   rsp(8)   - byte* buf
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  2984
  *   rsp(12)  - int length
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  2985
  *   rsp(16)  - table_start - optional (present only when doing a library_calll,
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  2986
  *              not used by x86 algorithm)
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  2987
  *
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  2988
  * Ouput:
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  2989
  *       rax  - int crc result
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  2990
  */
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  2991
  address generate_updateBytesCRC32C(bool is_pclmulqdq_supported) {
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  2992
    assert(UseCRC32CIntrinsics, "need SSE4_2");
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  2993
    __ align(CodeEntryAlignment);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  2994
    StubCodeMark mark(this, "StubRoutines", "updateBytesCRC32C");
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  2995
    address start = __ pc();
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  2996
    const Register crc = rax;  // crc
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  2997
    const Register buf = rcx;  // source java byte array address
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  2998
    const Register len = rdx;  // length
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  2999
    const Register d = rbx;
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3000
    const Register g = rsi;
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3001
    const Register h = rdi;
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3002
    const Register empty = 0; // will never be used, in order not
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3003
                              // to change a signature for crc32c_IPL_Alg2_Alt2
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3004
                              // between 64/32 I'm just keeping it here
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3005
    assert_different_registers(crc, buf, len, d, g, h);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3006
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3007
    BLOCK_COMMENT("Entry:");
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3008
    __ enter(); // required for proper stackwalking of RuntimeStub frame
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3009
    Address crc_arg(rsp, 4 + 4 + 0); // ESP+4 +
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3010
                                     // we need to add additional 4 because __ enter
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3011
                                     // have just pushed ebp on a stack
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3012
    Address buf_arg(rsp, 4 + 4 + 4);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3013
    Address len_arg(rsp, 4 + 4 + 8);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3014
      // Load up:
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3015
      __ movl(crc, crc_arg);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3016
      __ movl(buf, buf_arg);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3017
      __ movl(len, len_arg);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3018
      __ push(d);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3019
      __ push(g);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3020
      __ push(h);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3021
      __ crc32c_ipl_alg2_alt2(crc, buf, len,
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3022
                              d, g, h,
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3023
                              empty, empty, empty,
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3024
                              xmm0, xmm1, xmm2,
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3025
                              is_pclmulqdq_supported);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3026
      __ pop(h);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3027
      __ pop(g);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3028
      __ pop(d);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3029
    __ leave(); // required for proper stackwalking of RuntimeStub frame
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3030
    __ ret(0);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3031
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3032
    return start;
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3033
  }
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3034
33089
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3035
 address generate_libmExp() {
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3036
    address start = __ pc();
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3037
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3038
    const XMMRegister x0  = xmm0;
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3039
    const XMMRegister x1  = xmm1;
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3040
    const XMMRegister x2  = xmm2;
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3041
    const XMMRegister x3  = xmm3;
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3042
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3043
    const XMMRegister x4  = xmm4;
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3044
    const XMMRegister x5  = xmm5;
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3045
    const XMMRegister x6  = xmm6;
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3046
    const XMMRegister x7  = xmm7;
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3047
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3048
    const Register tmp   = rbx;
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3049
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3050
    BLOCK_COMMENT("Entry:");
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3051
    __ enter(); // required for proper stackwalking of RuntimeStub frame
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3052
    __ fast_exp(x0, x1, x2, x3, x4, x5, x6, x7, rax, rcx, rdx, tmp);
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3053
    __ leave(); // required for proper stackwalking of RuntimeStub frame
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3054
    __ ret(0);
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3055
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3056
    return start;
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3057
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3058
  }
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3059
33465
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3060
 address generate_libmLog() {
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3061
   address start = __ pc();
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3062
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3063
   const XMMRegister x0 = xmm0;
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3064
   const XMMRegister x1 = xmm1;
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3065
   const XMMRegister x2 = xmm2;
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3066
   const XMMRegister x3 = xmm3;
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3067
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3068
   const XMMRegister x4 = xmm4;
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3069
   const XMMRegister x5 = xmm5;
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3070
   const XMMRegister x6 = xmm6;
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3071
   const XMMRegister x7 = xmm7;
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3072
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3073
   const Register tmp = rbx;
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3074
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3075
   BLOCK_COMMENT("Entry:");
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3076
   __ enter(); // required for proper stackwalking of RuntimeStub frame
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3077
   __ fast_log(x0, x1, x2, x3, x4, x5, x6, x7, rax, rcx, rdx, tmp);
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3078
   __ leave(); // required for proper stackwalking of RuntimeStub frame
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3079
   __ ret(0);
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3080
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3081
   return start;
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3082
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3083
 }
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3084
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3085
33089
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3086
18740
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3087
  // Safefetch stubs.
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3088
  void generate_safefetch(const char* name, int size, address* entry,
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3089
                          address* fault_pc, address* continuation_pc) {
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3090
    // safefetch signatures:
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3091
    //   int      SafeFetch32(int*      adr, int      errValue);
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3092
    //   intptr_t SafeFetchN (intptr_t* adr, intptr_t errValue);
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3093
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3094
    StubCodeMark mark(this, "StubRoutines", name);
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3095
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3096
    // Entry point, pc or function descriptor.
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3097
    *entry = __ pc();
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3098
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3099
    __ movl(rax, Address(rsp, 0x8));
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3100
    __ movl(rcx, Address(rsp, 0x4));
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3101
    // Load *adr into eax, may fault.
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3102
    *fault_pc = __ pc();
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3103
    switch (size) {
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3104
      case 4:
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3105
        // int32_t
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3106
        __ movl(rax, Address(rcx, 0));
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3107
        break;
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3108
      case 8:
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3109
        // int64_t
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3110
        Unimplemented();
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3111
        break;
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3112
      default:
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3113
        ShouldNotReachHere();
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3114
    }
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3115
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3116
    // Return errValue or *adr.
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3117
    *continuation_pc = __ pc();
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3118
    __ ret(0);
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3119
  }
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3120
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3121
 public:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3122
  // Information about frame layout at time of blocking runtime call.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3123
  // Note that we only have to preserve callee-saved registers since
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3124
  // the compilers are responsible for supplying a continuation point
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3125
  // if they expect all registers to be preserved.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3126
  enum layout {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3127
    thread_off,    // last_java_sp
10004
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8498
diff changeset
  3128
    arg1_off,
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8498
diff changeset
  3129
    arg2_off,
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3130
    rbp_off,       // callee saved register
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3131
    ret_pc,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3132
    framesize
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3133
  };
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3134
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3135
 private:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3136
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3137
#undef  __
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3138
#define __ masm->
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3139
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3140
  //------------------------------------------------------------------------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3141
  // Continuation point for throwing of implicit exceptions that are not handled in
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3142
  // the current activation. Fabricates an exception oop and initiates normal
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3143
  // exception dispatching in this frame.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3144
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3145
  // Previously the compiler (c2) allowed for callee save registers on Java calls.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3146
  // This is no longer true after adapter frames were removed but could possibly
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3147
  // be brought back in the future if the interpreter code was reworked and it
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3148
  // was deemed worthwhile. The comment below was left to describe what must
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3149
  // happen here if callee saves were resurrected. As it stands now this stub
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3150
  // could actually be a vanilla BufferBlob and have now oopMap at all.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3151
  // Since it doesn't make much difference we've chosen to leave it the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3152
  // way it was in the callee save days and keep the comment.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3153
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3154
  // If we need to preserve callee-saved values we need a callee-saved oop map and
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3155
  // therefore have to make these stubs into RuntimeStubs rather than BufferBlobs.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3156
  // If the compiler needs all registers to be preserved between the fault
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3157
  // point and the exception handler then it must assume responsibility for that in
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3158
  // AbstractCompiler::continuation_for_implicit_null_exception or
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3159
  // continuation_for_implicit_division_by_zero_exception. All other implicit
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3160
  // exceptions (e.g., NullPointerException or AbstractMethodError on entry) are
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3161
  // either at call sites or otherwise assume that stack unwinding will be initiated,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3162
  // so caller saved registers were assumed volatile in the compiler.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3163
  address generate_throw_exception(const char* name, address runtime_entry,
10545
fec876499aae 7088020: SEGV in JNIHandleBlock::release_block
never
parents: 10004
diff changeset
  3164
                                   Register arg1 = noreg, Register arg2 = noreg) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3165
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3166
    int insts_size = 256;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3167
    int locs_size  = 32;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3168
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3169
    CodeBuffer code(name, insts_size, locs_size);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3170
    OopMapSet* oop_maps  = new OopMapSet();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3171
    MacroAssembler* masm = new MacroAssembler(&code);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3172
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3173
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3174
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3175
    // This is an inlined and slightly modified version of call_VM
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3176
    // which has the ability to fetch the return PC out of
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3177
    // thread-local storage and also sets up last_Java_sp slightly
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3178
    // differently than the real call_VM
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3179
    Register java_thread = rbx;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3180
    __ get_thread(java_thread);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3181
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3182
    __ enter(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3183
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3184
    // pc and rbp, already pushed
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  3185
    __ subptr(rsp, (framesize-2) * wordSize); // prolog
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3186
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3187
    // Frame is now completed as far as size and linkage.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3188
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3189
    int frame_complete = __ pc() - start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3190
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3191
    // push java thread (becomes first argument of C function)
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  3192
    __ movptr(Address(rsp, thread_off * wordSize), java_thread);
10004
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8498
diff changeset
  3193
    if (arg1 != noreg) {
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8498
diff changeset
  3194
      __ movptr(Address(rsp, arg1_off * wordSize), arg1);
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8498
diff changeset
  3195
    }
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8498
diff changeset
  3196
    if (arg2 != noreg) {
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8498
diff changeset
  3197
      assert(arg1 != noreg, "missing reg arg");
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8498
diff changeset
  3198
      __ movptr(Address(rsp, arg2_off * wordSize), arg2);
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8498
diff changeset
  3199
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3200
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3201
    // Set up last_Java_sp and last_Java_fp
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3202
    __ set_last_Java_frame(java_thread, rsp, rbp, NULL);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3203
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3204
    // Call runtime
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3205
    BLOCK_COMMENT("call runtime_entry");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3206
    __ call(RuntimeAddress(runtime_entry));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3207
    // Generate oop map
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3208
    OopMap* map =  new OopMap(framesize, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3209
    oop_maps->add_gc_map(__ pc() - start, map);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3210
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3211
    // restore the thread (cannot use the pushed argument since arguments
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3212
    // may be overwritten by C code generated by an optimizing compiler);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3213
    // however can use the register value directly if it is callee saved.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3214
    __ get_thread(java_thread);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3215
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3216
    __ reset_last_Java_frame(java_thread, true, false);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3217
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3218
    __ leave(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3219
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3220
    // check for pending exceptions
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3221
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3222
    Label L;
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  3223
    __ cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3224
    __ jcc(Assembler::notEqual, L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3225
    __ should_not_reach_here();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3226
    __ bind(L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3227
#endif /* ASSERT */
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3228
    __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3229
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3230
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3231
    RuntimeStub* stub = RuntimeStub::new_runtime_stub(name, &code, frame_complete, framesize, oop_maps, false);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3232
    return stub->entry_point();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3233
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3234
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3235
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3236
  void create_control_words() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3237
    // Round to nearest, 53-bit mode, exceptions masked
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3238
    StubRoutines::_fpu_cntrl_wrd_std   = 0x027F;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3239
    // Round to zero, 53-bit mode, exception mased
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3240
    StubRoutines::_fpu_cntrl_wrd_trunc = 0x0D7F;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3241
    // Round to nearest, 24-bit mode, exceptions masked
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3242
    StubRoutines::_fpu_cntrl_wrd_24    = 0x007F;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3243
    // Round to nearest, 64-bit mode, exceptions masked
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3244
    StubRoutines::_fpu_cntrl_wrd_64    = 0x037F;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3245
    // Round to nearest, 64-bit mode, exceptions masked
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3246
    StubRoutines::_mxcsr_std           = 0x1F80;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3247
    // Note: the following two constants are 80-bit values
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3248
    //       layout is critical for correct loading by FPU.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3249
    // Bias for strict fp multiply/divide
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3250
    StubRoutines::_fpu_subnormal_bias1[0]= 0x00000000; // 2^(-15360) == 0x03ff 8000 0000 0000 0000
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3251
    StubRoutines::_fpu_subnormal_bias1[1]= 0x80000000;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3252
    StubRoutines::_fpu_subnormal_bias1[2]= 0x03ff;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3253
    // Un-Bias for strict fp multiply/divide
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3254
    StubRoutines::_fpu_subnormal_bias2[0]= 0x00000000; // 2^(+15360) == 0x7bff 8000 0000 0000 0000
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3255
    StubRoutines::_fpu_subnormal_bias2[1]= 0x80000000;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3256
    StubRoutines::_fpu_subnormal_bias2[2]= 0x7bff;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3257
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3258
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3259
  //---------------------------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3260
  // Initialization
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3261
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3262
  void generate_initial() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3263
    // Generates all stubs and initializes the entry points
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3264
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3265
    //------------------------------------------------------------------------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3266
    // entry points that exist in all platforms
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3267
    // Note: This is code that could be shared among different platforms - however the benefit seems to be smaller than
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3268
    //       the disadvantage of having a much more complicated generator structure. See also comment in stubRoutines.hpp.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3269
    StubRoutines::_forward_exception_entry      = generate_forward_exception();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3270
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3271
    StubRoutines::_call_stub_entry              =
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3272
      generate_call_stub(StubRoutines::_call_stub_return_address);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3273
    // is referenced by megamorphic call
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3274
    StubRoutines::_catch_exception_entry        = generate_catch_exception();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3275
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3276
    // These are currently used by Solaris/Intel
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3277
    StubRoutines::_atomic_xchg_entry            = generate_atomic_xchg();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3278
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3279
    StubRoutines::_handler_for_unsafe_access_entry =
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3280
      generate_handler_for_unsafe_access();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3281
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3282
    // platform dependent
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3283
    create_control_words();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3284
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  3285
    StubRoutines::x86::_verify_mxcsr_entry                 = generate_verify_mxcsr();
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  3286
    StubRoutines::x86::_verify_fpu_cntrl_wrd_entry         = generate_verify_fpu_cntrl_wrd();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3287
    StubRoutines::_d2i_wrapper                              = generate_d2i_wrapper(T_INT,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3288
                                                                                   CAST_FROM_FN_PTR(address, SharedRuntime::d2i));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3289
    StubRoutines::_d2l_wrapper                              = generate_d2i_wrapper(T_LONG,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3290
                                                                                   CAST_FROM_FN_PTR(address, SharedRuntime::d2l));
10004
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8498
diff changeset
  3291
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8498
diff changeset
  3292
    // Build this early so it's available for the interpreter
35071
a0910b1d3e0d 8046936: JEP 270: Reserved Stack Areas for Critical Sections
fparain
parents: 33465
diff changeset
  3293
    StubRoutines::_throw_StackOverflowError_entry          = generate_throw_exception("StackOverflowError throw_exception",
a0910b1d3e0d 8046936: JEP 270: Reserved Stack Areas for Critical Sections
fparain
parents: 33465
diff changeset
  3294
                                                                                      CAST_FROM_FN_PTR(address, SharedRuntime::throw_StackOverflowError));
a0910b1d3e0d 8046936: JEP 270: Reserved Stack Areas for Critical Sections
fparain
parents: 33465
diff changeset
  3295
    StubRoutines::_throw_delayed_StackOverflowError_entry  = generate_throw_exception("delayed StackOverflowError throw_exception",
a0910b1d3e0d 8046936: JEP 270: Reserved Stack Areas for Critical Sections
fparain
parents: 33465
diff changeset
  3296
                                                                                      CAST_FROM_FN_PTR(address, SharedRuntime::throw_delayed_StackOverflowError));
18507
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  3297
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  3298
    if (UseCRC32Intrinsics) {
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  3299
      // set table address before stub generation which use it
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  3300
      StubRoutines::_crc_table_adr = (address)StubRoutines::x86::_crc_table;
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  3301
      StubRoutines::_updateBytesCRC32 = generate_updateBytesCRC32();
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  3302
    }
33066
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3303
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3304
    if (UseCRC32CIntrinsics) {
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3305
      bool supports_clmul = VM_Version::supports_clmul();
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3306
      StubRoutines::x86::generate_CRC32C_table(supports_clmul);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3307
      StubRoutines::_crc32c_table_addr = (address)StubRoutines::x86::_crc32c_table;
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3308
      StubRoutines::_updateBytesCRC32C = generate_updateBytesCRC32C(supports_clmul);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  3309
    }
33089
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3310
    if (VM_Version::supports_sse2()) {
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3311
      StubRoutines::_dexp = generate_libmExp();
33465
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  3312
      StubRoutines::_dlog = generate_libmLog();
33089
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  3313
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3314
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3315
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3316
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3317
  void generate_all() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3318
    // Generates all stubs and initializes the entry points
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3319
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3320
    // These entry points require SharedInfo::stack0 to be set up in non-core builds
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3321
    // and need to be relocatable, so they each fabricate a RuntimeStub internally.
10545
fec876499aae 7088020: SEGV in JNIHandleBlock::release_block
never
parents: 10004
diff changeset
  3322
    StubRoutines::_throw_AbstractMethodError_entry         = generate_throw_exception("AbstractMethodError throw_exception",          CAST_FROM_FN_PTR(address, SharedRuntime::throw_AbstractMethodError));
fec876499aae 7088020: SEGV in JNIHandleBlock::release_block
never
parents: 10004
diff changeset
  3323
    StubRoutines::_throw_IncompatibleClassChangeError_entry= generate_throw_exception("IncompatibleClassChangeError throw_exception", CAST_FROM_FN_PTR(address, SharedRuntime::throw_IncompatibleClassChangeError));
fec876499aae 7088020: SEGV in JNIHandleBlock::release_block
never
parents: 10004
diff changeset
  3324
    StubRoutines::_throw_NullPointerException_at_call_entry= generate_throw_exception("NullPointerException at call throw_exception", CAST_FROM_FN_PTR(address, SharedRuntime::throw_NullPointerException_at_call));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3325
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3326
    //------------------------------------------------------------------------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3327
    // entry points that are platform specific
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3328
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3329
    // support for verify_oop (must happen after universe_init)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3330
    StubRoutines::_verify_oop_subroutine_entry     = generate_verify_oop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3331
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3332
    // arraycopy stubs used by compilers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3333
    generate_arraycopy_stubs();
2534
08dac9ce0cd7 6655638: dynamic languages need method handles
jrose
parents: 2259
diff changeset
  3334
4645
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 3262
diff changeset
  3335
    generate_math_stubs();
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3336
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3337
    // don't bother generating these AES intrinsic stubs unless global flag is set
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3338
    if (UseAESIntrinsics) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3339
      StubRoutines::x86::_key_shuffle_mask_addr = generate_key_shuffle_mask();  // might be needed by the others
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3340
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3341
      StubRoutines::_aescrypt_encryptBlock = generate_aescrypt_encryptBlock();
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3342
      StubRoutines::_aescrypt_decryptBlock = generate_aescrypt_decryptBlock();
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3343
      StubRoutines::_cipherBlockChaining_encryptAESCrypt = generate_cipherBlockChaining_encryptAESCrypt();
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3344
      StubRoutines::_cipherBlockChaining_decryptAESCrypt = generate_cipherBlockChaining_decryptAESCrypt();
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3345
    }
18740
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3346
31404
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  3347
    // Generate GHASH intrinsics code
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  3348
    if (UseGHASHIntrinsics) {
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  3349
      StubRoutines::x86::_ghash_long_swap_mask_addr = generate_ghash_long_swap_mask();
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  3350
      StubRoutines::x86::_ghash_byte_swap_mask_addr = generate_ghash_byte_swap_mask();
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  3351
      StubRoutines::_ghash_processBlocks = generate_ghash_processBlocks();
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  3352
    }
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 30624
diff changeset
  3353
18740
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3354
    // Safefetch stubs.
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3355
    generate_safefetch("SafeFetch32", sizeof(int), &StubRoutines::_safefetch32_entry,
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3356
                                                   &StubRoutines::_safefetch32_fault_pc,
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3357
                                                   &StubRoutines::_safefetch32_continuation_pc);
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3358
    StubRoutines::_safefetchN_entry           = StubRoutines::_safefetch32_entry;
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3359
    StubRoutines::_safefetchN_fault_pc        = StubRoutines::_safefetch32_fault_pc;
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3360
    StubRoutines::_safefetchN_continuation_pc = StubRoutines::_safefetch32_continuation_pc;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3361
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3362
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3363
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3364
 public:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3365
  StubGenerator(CodeBuffer* code, bool all) : StubCodeGenerator(code) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3366
    if (all) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3367
      generate_all();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3368
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3369
      generate_initial();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3370
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3371
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3372
}; // end class declaration
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3373
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3374
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3375
void StubGenerator_generate(CodeBuffer* code, bool all) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3376
  StubGenerator g(code, all);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3377
}