author | eosterlund |
Mon, 28 Aug 2017 13:31:20 +0200 | |
changeset 46993 | dd0f91c85ffc |
parent 46973 | 149e5319c938 |
child 47091 | 4cc46bb5057b |
permissions | -rw-r--r-- |
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/* |
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* Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. |
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* Copyright (c) 2012, 2014 SAP SE. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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|
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#ifndef OS_CPU_AIX_OJDKPPC_VM_ATOMIC_AIX_PPC_HPP |
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#define OS_CPU_AIX_OJDKPPC_VM_ATOMIC_AIX_PPC_HPP |
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|
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#ifndef _LP64 |
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#error "Atomic currently only impleneted for PPC64" |
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#endif |
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|
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#include "utilities/debug.hpp" |
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// Implementation of class atomic |
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|
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inline void Atomic::store (jbyte store_value, jbyte* dest) { *dest = store_value; } |
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inline void Atomic::store (jshort store_value, jshort* dest) { *dest = store_value; } |
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inline void Atomic::store (jint store_value, jint* dest) { *dest = store_value; } |
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inline void Atomic::store (jlong store_value, jlong* dest) { *dest = store_value; } |
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inline void Atomic::store_ptr(intptr_t store_value, intptr_t* dest) { *dest = store_value; } |
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inline void Atomic::store_ptr(void* store_value, void* dest) { *(void**)dest = store_value; } |
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|
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inline void Atomic::store (jbyte store_value, volatile jbyte* dest) { *dest = store_value; } |
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inline void Atomic::store (jshort store_value, volatile jshort* dest) { *dest = store_value; } |
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inline void Atomic::store (jint store_value, volatile jint* dest) { *dest = store_value; } |
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inline void Atomic::store (jlong store_value, volatile jlong* dest) { *dest = store_value; } |
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inline void Atomic::store_ptr(intptr_t store_value, volatile intptr_t* dest) { *dest = store_value; } |
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inline void Atomic::store_ptr(void* store_value, volatile void* dest) { *(void* volatile *)dest = store_value; } |
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inline jlong Atomic::load(const volatile jlong* src) { return *src; } |
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// |
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// machine barrier instructions: |
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// |
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// - ppc_sync two-way memory barrier, aka fence |
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// - ppc_lwsync orders Store|Store, |
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// Load|Store, |
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// Load|Load, |
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// but not Store|Load |
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// - ppc_eieio orders memory accesses for device memory (only) |
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// - ppc_isync invalidates speculatively executed instructions |
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// From the POWER ISA 2.06 documentation: |
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// "[...] an isync instruction prevents the execution of |
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// instructions following the isync until instructions |
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// preceding the isync have completed, [...]" |
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// From IBM's AIX assembler reference: |
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// "The isync [...] instructions causes the processor to |
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// refetch any instructions that might have been fetched |
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// prior to the isync instruction. The instruction isync |
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// causes the processor to wait for all previous instructions |
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// to complete. Then any instructions already fetched are |
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// discarded and instruction processing continues in the |
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// environment established by the previous instructions." |
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// |
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// semantic barrier instructions: |
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// (as defined in orderAccess.hpp) |
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// |
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// - ppc_release orders Store|Store, (maps to ppc_lwsync) |
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// Load|Store |
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// - ppc_acquire orders Load|Store, (maps to ppc_lwsync) |
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// Load|Load |
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// - ppc_fence orders Store|Store, (maps to ppc_sync) |
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// Load|Store, |
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// Load|Load, |
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// Store|Load |
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// |
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#define strasm_sync "\n sync \n" |
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#define strasm_lwsync "\n lwsync \n" |
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#define strasm_isync "\n isync \n" |
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#define strasm_release strasm_lwsync |
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#define strasm_acquire strasm_lwsync |
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#define strasm_fence strasm_sync |
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#define strasm_nobarrier "" |
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#define strasm_nobarrier_clobber_memory "" |
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template<size_t byte_size> |
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struct Atomic::PlatformAdd |
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: Atomic::AddAndFetch<Atomic::PlatformAdd<byte_size> > |
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{ |
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template<typename I, typename D> |
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D add_and_fetch(I add_value, D volatile* dest) const; |
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}; |
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template<> |
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template<typename I, typename D> |
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inline D Atomic::PlatformAdd<4>::add_and_fetch(I add_value, D volatile* dest) const { |
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STATIC_CAST(4 == sizeof(I)); |
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STATIC_CAST(4 == sizeof(D)); |
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D result; |
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|
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__asm__ __volatile__ ( |
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strasm_lwsync |
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"1: lwarx %0, 0, %2 \n" |
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" add %0, %0, %1 \n" |
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" stwcx. %0, 0, %2 \n" |
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" bne- 1b \n" |
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strasm_isync |
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: /*%0*/"=&r" (result) |
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: /*%1*/"r" (add_value), /*%2*/"r" (dest) |
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: "cc", "memory" ); |
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return result; |
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} |
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|
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template<> |
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template<typename I, typename D> |
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inline D Atomic::PlatformAdd<8>::add_and_fetch(I add_value, D volatile* dest) const { |
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STATIC_CAST(8 == sizeof(I)); |
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STATIC_CAST(8 == sizeof(D)); |
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D result; |
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|
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__asm__ __volatile__ ( |
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strasm_lwsync |
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"1: ldarx %0, 0, %2 \n" |
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" add %0, %0, %1 \n" |
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" stdcx. %0, 0, %2 \n" |
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" bne- 1b \n" |
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strasm_isync |
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: /*%0*/"=&r" (result) |
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: /*%1*/"r" (add_value), /*%2*/"r" (dest) |
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: "cc", "memory" ); |
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return result; |
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} |
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inline void Atomic::inc (volatile jint* dest) { |
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|
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unsigned int temp; |
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|
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__asm__ __volatile__ ( |
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strasm_nobarrier |
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"1: lwarx %0, 0, %2 \n" |
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" addic %0, %0, 1 \n" |
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" stwcx. %0, 0, %2 \n" |
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" bne- 1b \n" |
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strasm_nobarrier |
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: /*%0*/"=&r" (temp), "=m" (*dest) |
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: /*%2*/"r" (dest), "m" (*dest) |
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: "cc" strasm_nobarrier_clobber_memory); |
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|
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} |
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|
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inline void Atomic::inc_ptr(volatile intptr_t* dest) { |
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|
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long temp; |
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|
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__asm__ __volatile__ ( |
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strasm_nobarrier |
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"1: ldarx %0, 0, %2 \n" |
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" addic %0, %0, 1 \n" |
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" stdcx. %0, 0, %2 \n" |
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" bne- 1b \n" |
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strasm_nobarrier |
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: /*%0*/"=&r" (temp), "=m" (*dest) |
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: /*%2*/"r" (dest), "m" (*dest) |
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: "cc" strasm_nobarrier_clobber_memory); |
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|
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} |
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|
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inline void Atomic::inc_ptr(volatile void* dest) { |
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inc_ptr((volatile intptr_t*)dest); |
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} |
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|
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|
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inline void Atomic::dec (volatile jint* dest) { |
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|
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unsigned int temp; |
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|
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__asm__ __volatile__ ( |
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strasm_nobarrier |
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"1: lwarx %0, 0, %2 \n" |
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" addic %0, %0, -1 \n" |
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" stwcx. %0, 0, %2 \n" |
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" bne- 1b \n" |
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strasm_nobarrier |
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: /*%0*/"=&r" (temp), "=m" (*dest) |
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: /*%2*/"r" (dest), "m" (*dest) |
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: "cc" strasm_nobarrier_clobber_memory); |
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|
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} |
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|
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inline void Atomic::dec_ptr(volatile intptr_t* dest) { |
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|
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long temp; |
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|
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__asm__ __volatile__ ( |
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strasm_nobarrier |
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"1: ldarx %0, 0, %2 \n" |
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" addic %0, %0, -1 \n" |
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" stdcx. %0, 0, %2 \n" |
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" bne- 1b \n" |
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strasm_nobarrier |
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: /*%0*/"=&r" (temp), "=m" (*dest) |
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: /*%2*/"r" (dest), "m" (*dest) |
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: "cc" strasm_nobarrier_clobber_memory); |
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|
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} |
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|
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inline void Atomic::dec_ptr(volatile void* dest) { |
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dec_ptr((volatile intptr_t*)dest); |
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} |
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|
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inline jint Atomic::xchg(jint exchange_value, volatile jint* dest) { |
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|
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// Note that xchg_ptr doesn't necessarily do an acquire |
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// (see synchronizer.cpp). |
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|
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unsigned int old_value; |
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const uint64_t zero = 0; |
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|
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__asm__ __volatile__ ( |
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/* lwsync */ |
22867 | 239 |
strasm_lwsync |
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/* atomic loop */ |
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"1: \n" |
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" lwarx %[old_value], %[dest], %[zero] \n" |
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" stwcx. %[exchange_value], %[dest], %[zero] \n" |
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" bne- 1b \n" |
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/* isync */ |
22867 | 246 |
strasm_sync |
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/* exit */ |
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248 |
"2: \n" |
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/* out */ |
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: [old_value] "=&r" (old_value), |
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"=m" (*dest) |
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/* in */ |
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: [dest] "b" (dest), |
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[zero] "r" (zero), |
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[exchange_value] "r" (exchange_value), |
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"m" (*dest) |
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/* clobber */ |
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: "cc", |
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"memory" |
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); |
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|
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return (jint) old_value; |
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} |
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264 |
|
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inline intptr_t Atomic::xchg_ptr(intptr_t exchange_value, volatile intptr_t* dest) { |
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|
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// Note that xchg_ptr doesn't necessarily do an acquire |
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// (see synchronizer.cpp). |
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|
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long old_value; |
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const uint64_t zero = 0; |
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|
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__asm__ __volatile__ ( |
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/* lwsync */ |
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strasm_lwsync |
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/* atomic loop */ |
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"1: \n" |
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278 |
" ldarx %[old_value], %[dest], %[zero] \n" |
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" stdcx. %[exchange_value], %[dest], %[zero] \n" |
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280 |
" bne- 1b \n" |
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281 |
/* isync */ |
22867 | 282 |
strasm_sync |
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283 |
/* exit */ |
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284 |
"2: \n" |
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285 |
/* out */ |
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: [old_value] "=&r" (old_value), |
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287 |
"=m" (*dest) |
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288 |
/* in */ |
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289 |
: [dest] "b" (dest), |
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290 |
[zero] "r" (zero), |
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291 |
[exchange_value] "r" (exchange_value), |
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292 |
"m" (*dest) |
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293 |
/* clobber */ |
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294 |
: "cc", |
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295 |
"memory" |
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296 |
); |
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297 |
|
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298 |
return (intptr_t) old_value; |
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299 |
} |
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300 |
|
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301 |
inline void* Atomic::xchg_ptr(void* exchange_value, volatile void* dest) { |
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302 |
return (void*)xchg_ptr((intptr_t)exchange_value, (volatile intptr_t*)dest); |
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303 |
} |
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304 |
|
39404 | 305 |
inline void cmpxchg_pre_membar(cmpxchg_memory_order order) { |
306 |
if (order != memory_order_relaxed) { |
|
307 |
__asm__ __volatile__ ( |
|
308 |
/* fence */ |
|
309 |
strasm_sync |
|
310 |
); |
|
311 |
} |
|
312 |
} |
|
313 |
||
314 |
inline void cmpxchg_post_membar(cmpxchg_memory_order order) { |
|
315 |
if (order != memory_order_relaxed) { |
|
316 |
__asm__ __volatile__ ( |
|
317 |
/* fence */ |
|
318 |
strasm_sync |
|
319 |
); |
|
320 |
} |
|
321 |
} |
|
322 |
||
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323 |
template<> |
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324 |
template<typename T> |
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325 |
inline T Atomic::PlatformCmpxchg<1>::operator()(T exchange_value, |
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326 |
T volatile* dest, |
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327 |
T compare_value, |
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328 |
cmpxchg_memory_order order) const { |
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329 |
STATIC_ASSERT(1 == sizeof(T)); |
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330 |
|
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331 |
// Note that cmpxchg guarantees a two-way memory barrier across |
39404 | 332 |
// the cmpxchg, so it's really a a 'fence_cmpxchg_fence' if not |
333 |
// specified otherwise (see atomic.hpp). |
|
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334 |
|
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335 |
// Using 32 bit internally. |
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336 |
volatile int *dest_base = (volatile int*)((uintptr_t)dest & ~3); |
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337 |
|
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338 |
#ifdef VM_LITTLE_ENDIAN |
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339 |
const unsigned int shift_amount = ((uintptr_t)dest & 3) * 8; |
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340 |
#else |
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341 |
const unsigned int shift_amount = ((~(uintptr_t)dest) & 3) * 8; |
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342 |
#endif |
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343 |
const unsigned int masked_compare_val = ((unsigned int)(unsigned char)compare_value), |
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344 |
masked_exchange_val = ((unsigned int)(unsigned char)exchange_value), |
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345 |
xor_value = (masked_compare_val ^ masked_exchange_val) << shift_amount; |
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346 |
|
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347 |
unsigned int old_value, value32; |
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348 |
|
39404 | 349 |
cmpxchg_pre_membar(order); |
350 |
||
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351 |
__asm__ __volatile__ ( |
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352 |
/* simple guard */ |
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353 |
" lbz %[old_value], 0(%[dest]) \n" |
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354 |
" cmpw %[masked_compare_val], %[old_value] \n" |
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355 |
" bne- 2f \n" |
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356 |
/* atomic loop */ |
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357 |
"1: \n" |
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358 |
" lwarx %[value32], 0, %[dest_base] \n" |
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359 |
/* extract byte and compare */ |
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|
360 |
" srd %[old_value], %[value32], %[shift_amount] \n" |
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|
361 |
" clrldi %[old_value], %[old_value], 56 \n" |
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362 |
" cmpw %[masked_compare_val], %[old_value] \n" |
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363 |
" bne- 2f \n" |
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364 |
/* replace byte and try to store */ |
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|
365 |
" xor %[value32], %[xor_value], %[value32] \n" |
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|
366 |
" stwcx. %[value32], 0, %[dest_base] \n" |
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|
367 |
" bne- 1b \n" |
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|
368 |
/* exit */ |
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|
369 |
"2: \n" |
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|
370 |
/* out */ |
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|
371 |
: [old_value] "=&r" (old_value), |
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|
372 |
[value32] "=&r" (value32), |
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|
373 |
"=m" (*dest), |
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|
374 |
"=m" (*dest_base) |
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|
375 |
/* in */ |
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|
376 |
: [dest] "b" (dest), |
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|
377 |
[dest_base] "b" (dest_base), |
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|
378 |
[shift_amount] "r" (shift_amount), |
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|
379 |
[masked_compare_val] "r" (masked_compare_val), |
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|
380 |
[xor_value] "r" (xor_value), |
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|
381 |
"m" (*dest), |
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|
382 |
"m" (*dest_base) |
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|
383 |
/* clobber */ |
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|
384 |
: "cc", |
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|
385 |
"memory" |
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|
386 |
); |
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|
387 |
|
39404 | 388 |
cmpxchg_post_membar(order); |
389 |
||
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|
390 |
return PrimitiveConversions::cast<T>((unsigned char)old_value); |
35063
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|
391 |
} |
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|
392 |
|
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|
393 |
template<> |
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|
394 |
template<typename T> |
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|
395 |
inline T Atomic::PlatformCmpxchg<4>::operator()(T exchange_value, |
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|
396 |
T volatile* dest, |
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|
397 |
T compare_value, |
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|
398 |
cmpxchg_memory_order order) const { |
46973
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|
399 |
STATIC_ASSERT(4 == sizeof(T)); |
22831
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|
400 |
|
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|
401 |
// Note that cmpxchg guarantees a two-way memory barrier across |
39404 | 402 |
// the cmpxchg, so it's really a a 'fence_cmpxchg_fence' if not |
403 |
// specified otherwise (see atomic.hpp). |
|
22831
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|
404 |
|
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|
405 |
T old_value; |
22831
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|
406 |
const uint64_t zero = 0; |
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|
407 |
|
39404 | 408 |
cmpxchg_pre_membar(order); |
409 |
||
22831
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|
410 |
__asm__ __volatile__ ( |
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|
411 |
/* simple guard */ |
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|
412 |
" lwz %[old_value], 0(%[dest]) \n" |
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|
413 |
" cmpw %[compare_value], %[old_value] \n" |
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|
414 |
" bne- 2f \n" |
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|
415 |
/* atomic loop */ |
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|
416 |
"1: \n" |
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|
417 |
" lwarx %[old_value], %[dest], %[zero] \n" |
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|
418 |
" cmpw %[compare_value], %[old_value] \n" |
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|
419 |
" bne- 2f \n" |
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|
420 |
" stwcx. %[exchange_value], %[dest], %[zero] \n" |
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|
421 |
" bne- 1b \n" |
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|
422 |
/* exit */ |
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"2: \n" |
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424 |
/* out */ |
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: [old_value] "=&r" (old_value), |
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"=m" (*dest) |
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427 |
/* in */ |
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: [dest] "b" (dest), |
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[zero] "r" (zero), |
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[compare_value] "r" (compare_value), |
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[exchange_value] "r" (exchange_value), |
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"m" (*dest) |
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433 |
/* clobber */ |
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434 |
: "cc", |
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435 |
"memory" |
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436 |
); |
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437 |
|
39404 | 438 |
cmpxchg_post_membar(order); |
439 |
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return old_value; |
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441 |
} |
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442 |
|
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template<> |
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template<typename T> |
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inline T Atomic::PlatformCmpxchg<8>::operator()(T exchange_value, |
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T volatile* dest, |
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447 |
T compare_value, |
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cmpxchg_memory_order order) const { |
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STATIC_ASSERT(8 == sizeof(T)); |
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450 |
|
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// Note that cmpxchg guarantees a two-way memory barrier across |
39404 | 452 |
// the cmpxchg, so it's really a a 'fence_cmpxchg_fence' if not |
453 |
// specified otherwise (see atomic.hpp). |
|
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454 |
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T old_value; |
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const uint64_t zero = 0; |
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457 |
|
39404 | 458 |
cmpxchg_pre_membar(order); |
459 |
||
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__asm__ __volatile__ ( |
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/* simple guard */ |
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" ld %[old_value], 0(%[dest]) \n" |
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" cmpd %[compare_value], %[old_value] \n" |
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" bne- 2f \n" |
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465 |
/* atomic loop */ |
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"1: \n" |
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" ldarx %[old_value], %[dest], %[zero] \n" |
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" cmpd %[compare_value], %[old_value] \n" |
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" bne- 2f \n" |
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" stdcx. %[exchange_value], %[dest], %[zero] \n" |
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" bne- 1b \n" |
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/* exit */ |
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"2: \n" |
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/* out */ |
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475 |
: [old_value] "=&r" (old_value), |
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476 |
"=m" (*dest) |
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477 |
/* in */ |
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478 |
: [dest] "b" (dest), |
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479 |
[zero] "r" (zero), |
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480 |
[compare_value] "r" (compare_value), |
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481 |
[exchange_value] "r" (exchange_value), |
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482 |
"m" (*dest) |
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483 |
/* clobber */ |
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484 |
: "cc", |
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485 |
"memory" |
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486 |
); |
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487 |
|
39404 | 488 |
cmpxchg_post_membar(order); |
489 |
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490 |
return old_value; |
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491 |
} |
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492 |
|
22867 | 493 |
#undef strasm_sync |
494 |
#undef strasm_lwsync |
|
495 |
#undef strasm_isync |
|
496 |
#undef strasm_release |
|
497 |
#undef strasm_acquire |
|
498 |
#undef strasm_fence |
|
499 |
#undef strasm_nobarrier |
|
500 |
#undef strasm_nobarrier_clobber_memory |
|
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501 |
|
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502 |
#endif // OS_CPU_AIX_OJDKPPC_VM_ATOMIC_AIX_PPC_HPP |