/*

 * Copyright (c) 2016, 2017, Oracle and/or its affiliates. All rights reserved.

 * Copyright (c) 2016, 2017, SAP SE. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#ifndef CPU_S390_VM_MACROASSEMBLER_S390_HPP

#define CPU_S390_VM_MACROASSEMBLER_S390_HPP

#include "asm/assembler.hpp"

#define MODERN_IFUN(name)  ((void (MacroAssembler::*)(Register, int64_t, Register, Register))&MacroAssembler::name)

#define CLASSIC_IFUN(name) ((void (MacroAssembler::*)(Register, int64_t, Register, Register))&MacroAssembler::name)

#define MODERN_FFUN(name)  ((void (MacroAssembler::*)(FloatRegister, int64_t, Register, Register))&MacroAssembler::name)

#define CLASSIC_FFUN(name) ((void (MacroAssembler::*)(FloatRegister, int64_t, Register, Register))&MacroAssembler::name)

class MacroAssembler: public Assembler {

 public:

  MacroAssembler(CodeBuffer* code) : Assembler(code) {}

  //

  // Optimized instruction emitters

  //

  // Move register if destination register and target register are different.

  void lr_if_needed(Register rd, Register rs);

  void lgr_if_needed(Register rd, Register rs);

  void llgfr_if_needed(Register rd, Register rs);

  void ldr_if_needed(FloatRegister rd, FloatRegister rs);

  void move_reg_if_needed(Register dest, BasicType dest_type, Register src, BasicType src_type);

  void move_freg_if_needed(FloatRegister dest, BasicType dest_type, FloatRegister src, BasicType src_type);

  void freg2mem_opt(FloatRegister reg,

                    int64_t       disp,

                    Register      index,

                    Register      base,

                    void (MacroAssembler::*modern) (FloatRegister, int64_t, Register, Register),

                    void (MacroAssembler::*classic)(FloatRegister, int64_t, Register, Register),

                    Register      scratch = Z_R0);

  void freg2mem_opt(FloatRegister reg,

                    const Address &a, bool is_double = true);

  void mem2freg_opt(FloatRegister reg,

                    int64_t       disp,

                    Register      index,

                    Register      base,

                    void (MacroAssembler::*modern) (FloatRegister, int64_t, Register, Register),

                    void (MacroAssembler::*classic)(FloatRegister, int64_t, Register, Register),

                    Register      scratch = Z_R0);

  void mem2freg_opt(FloatRegister reg,

                    const Address &a, bool is_double = true);

  void reg2mem_opt(Register reg,

                   int64_t  disp,

                   Register index,

                   Register base,

                   void (MacroAssembler::*modern) (Register, int64_t, Register, Register),

                   void (MacroAssembler::*classic)(Register, int64_t, Register, Register),

                   Register scratch = Z_R0);

  // returns offset of the store instruction

  int reg2mem_opt(Register reg, const Address &a, bool is_double = true);

  void mem2reg_opt(Register reg,

                   int64_t  disp,

                   Register index,

                   Register base,

                   void (MacroAssembler::*modern) (Register, int64_t, Register, Register),

                   void (MacroAssembler::*classic)(Register, int64_t, Register, Register));

  void mem2reg_opt(Register reg, const Address &a, bool is_double = true);

  void mem2reg_signed_opt(Register reg, const Address &a);

  // AND immediate and set condition code, works for 64 bit immediates/operation as well.

   void and_imm(Register r, long mask, Register tmp = Z_R0, bool wide = false);

  // 1's complement, 32bit or 64bit. Optimized to exploit distinct operands facility.

  // Note: The condition code is neither preserved nor correctly set by this code!!!

  // Note: (wide == false) does not protect the high order half of the target register

  // from alternation. It only serves as optimization hint for 32-bit results.

  void not_(Register r1, Register r2 = noreg, bool wide = false);  // r1 = ~r2

  // Expanded support of all "rotate_then_<logicalOP>" instructions.

  //

  // Generalize and centralize rotate_then_<logicalOP> emitter.

  // Functional description. For details, see Principles of Operation, Chapter 7, "Rotate Then Insert..."

  //  - Bits  in a register are numbered left (most significant) to right (least significant), i.e. [0..63].

  //  - Bytes in a register are numbered left (most significant) to right (least significant), i.e. [0..7].

  //  - Register src is rotated to the left by (nRotate&0x3f) positions.

  //  - Negative values for nRotate result in a rotation to the right by abs(nRotate) positions.

  //  - The bits in positions [lBitPos..rBitPos] of the _ROTATED_ src operand take part in the

  //    logical operation performed on the contents (in those positions) of the dst operand.

  //  - The logical operation that is performed on the dst operand is one of

  //     o insert the selected bits (replacing the original contents of those bit positions)

  //     o and the selected bits with the corresponding bits of the dst operand

  //     o or  the selected bits with the corresponding bits of the dst operand

  //     o xor the selected bits with the corresponding bits of the dst operand

  //  - For clear_dst == true, the destination register is cleared before the bits are inserted.

  //    For clear_dst == false, only the bit positions that get data inserted from src

  //    are changed. All other bit positions remain unchanged.

  //  - For test_only == true,  the result of the logicalOP is only used to set the condition code, dst remains unchanged.

  //    For test_only == false, the result of the logicalOP replaces the selected bits of dst.

  //  - src32bit and dst32bit indicate the respective register is used as 32bit value only.

  //    Knowledge can simplify code generation.

  //

  // Here is an important performance note, valid for all <logicalOP>s except "insert":

  //   Due to the too complex nature of the operation, it cannot be done in a single cycle.

  //   Timing constraints require the instructions to be cracked into two micro-ops, taking

  //   one or two cycles each to execute. In some cases, an additional pipeline bubble might get added.

  //   Macroscopically, that makes up for a three- or four-cycle instruction where you would

  //   expect just a single cycle.

  //   It is thus not beneficial from a performance point of view to exploit those instructions.

  //   Other reasons (code compactness, register pressure, ...) might outweigh this penalty.

  //

  unsigned long create_mask(int lBitPos, int rBitPos);

  void rotate_then_mask(Register dst, Register src, int lBitPos, int rBitPos,

                        int nRotate, bool src32bit, bool dst32bit, bool oneBits);

  void rotate_then_insert(Register dst, Register src, int lBitPos, int rBitPos, int nRotate,

                          bool clear_dst);

  void rotate_then_and(Register dst, Register src, int lBitPos, int rBitPos, int nRotate,

                       bool test_only);

  void rotate_then_or(Register dst, Register src, int lBitPos, int rBitPos, int nRotate,

                      bool test_onlyt);

  void rotate_then_xor(Register dst, Register src, int lBitPos, int rBitPos, int nRotate,

                       bool test_only);

  void add64(Register r1, RegisterOrConstant inc);

  // Helper function to multiply the 64bit contents of a register by a 16bit constant.

  // The optimization tries to avoid the mghi instruction, since it uses the FPU for

  // calculation and is thus rather slow.

  //

  // There is no handling for special cases, e.g. cval==0 or cval==1.

  //

  // Returns len of generated code block.

  unsigned int mul_reg64_const16(Register rval, Register work, int cval);

  // Generic operation r1 := r2 + imm.

  void add2reg(Register r1, int64_t imm, Register r2 = noreg);

  // Generic operation r := b + x + d.

  void add2reg_with_index(Register r, int64_t d, Register x, Register b = noreg);

  // Add2mem* methods for direct memory increment.

  void add2mem_32(const Address &a, int64_t imm, Register tmp);

  void add2mem_64(const Address &a, int64_t imm, Register tmp);

  // *((int8_t*)(dst)) |= imm8

  inline void or2mem_8(Address& dst, int64_t imm8);

  // Load values by size and signedness.

  void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);

  void store_sized_value(Register src, Address dst, size_t size_in_bytes);

  // Load values with large offsets to base address.

 private:

  int  split_largeoffset(int64_t si20_offset, Register tmp, bool fixed_codelen, bool accumulate);

 public:

  void load_long_largeoffset(Register t, int64_t si20, Register a, Register tmp);

  void load_float_largeoffset(FloatRegister t, int64_t si20, Register a, Register tmp);

  void load_double_largeoffset(FloatRegister t, int64_t si20, Register a, Register tmp);

 private:

  long toc_distance();

 public:

  void load_toc(Register Rtoc);

  void load_long_pcrelative(Register Rdst, address dataLocation);

  static int load_long_pcrelative_size() { return 6; }

  void load_addr_pcrelative(Register Rdst, address dataLocation);

  static int load_addr_pcrel_size() { return 6; } // Just a LARL.

  // Load a value from memory and test (set CC).

  void load_and_test_byte    (Register dst, const Address &a);

  void load_and_test_short   (Register dst, const Address &a);

  void load_and_test_int     (Register dst, const Address &a);

  void load_and_test_int2long(Register dst, const Address &a);

  void load_and_test_long    (Register dst, const Address &a);

  // Test a bit in memory. Result is reflected in CC.

  void testbit(const Address &a, unsigned int bit);

  // Test a bit in a register. Result is reflected in CC.

  void testbit(Register r, unsigned int bitPos);

  void prefetch_read(Address a);

  void prefetch_update(Address a);

  // Clear a register, i.e. load const zero into reg. Return len (in bytes) of

  // generated instruction(s).

  //   whole_reg: Clear 64 bits if true, 32 bits otherwise.

  //   set_cc: Use instruction that sets the condition code, if true.

  int clear_reg(Register r, bool whole_reg = true, bool set_cc = true);

#ifdef ASSERT

  int preset_reg(Register r, unsigned long pattern, int pattern_len);

#endif

  // Clear (store zeros) a small piece of memory.

  // CAUTION: Do not use this for atomic memory clearing. Use store_const() instead.

  //   addr: Address descriptor of memory to clear.

  //         Index register will not be used!

  //   size: Number of bytes to clear.

  void clear_mem(const Address& addr, unsigned size);

  // Move immediate values to memory. Currently supports 32 and 64 bit stores,

  // but may be extended to 16 bit store operation, if needed.

  // For details, see implementation in *.cpp file.

         int store_const(const Address &dest, long imm,

                         unsigned int lm, unsigned int lc,

                         Register scratch = Z_R0);

  inline int store_const(const Address &dest, long imm,

                         Register scratch = Z_R0, bool is_long = true);

  // Move/initialize arbitrarily large memory area. No check for destructive overlap.

  // Being interruptible, these instructions need a retry-loop.

  void move_long_ext(Register dst, Register src, unsigned int pad);

  void compare_long_ext(Register left, Register right, unsigned int pad);

  void compare_long_uni(Register left, Register right, unsigned int pad);

  void search_string(Register end, Register start);

  void search_string_uni(Register end, Register start);

  // Translate instructions

  // Being interruptible, these instructions need a retry-loop.

  void translate_oo(Register dst, Register src, uint mask);

  void translate_ot(Register dst, Register src, uint mask);

  void translate_to(Register dst, Register src, uint mask);

  void translate_tt(Register dst, Register src, uint mask);

  // Crypto instructions.

  // Being interruptible, these instructions need a retry-loop.

  void cksm(Register crcBuff, Register srcBuff);

  void km( Register dstBuff, Register srcBuff);

  void kmc(Register dstBuff, Register srcBuff);

  void kimd(Register srcBuff);

  void klmd(Register srcBuff);

  void kmac(Register srcBuff);

  // nop padding

  void align(int modulus);

  void align_address(int modulus);

  //

  // Constants, loading constants, TOC support

  //

  // Load generic address: d <- base(a) + index(a) + disp(a).

  inline void load_address(Register d, const Address &a);

  // Load absolute address (and try to optimize).

  void load_absolute_address(Register d, address addr);

  // Address of Z_ARG1 and argument_offset.

  // If temp_reg == arg_slot, arg_slot will be overwritten.

  Address argument_address(RegisterOrConstant arg_slot,

                           Register temp_reg = noreg,

                           int64_t extra_slot_offset = 0);

  // Load a narrow ptr constant (oop or klass ptr).

  void load_narrow_oop( Register t, narrowOop a);

  void load_narrow_klass(Register t, Klass* k);

  static bool is_load_const_32to64(address pos);

  static bool is_load_narrow_oop(address pos)   { return is_load_const_32to64(pos); }

  static bool is_load_narrow_klass(address pos) { return is_load_const_32to64(pos); }

  static int  load_const_32to64_size()          { return 6; }

  static bool load_narrow_oop_size()            { return load_const_32to64_size(); }

  static bool load_narrow_klass_size()          { return load_const_32to64_size(); }

  static int  patch_load_const_32to64(address pos, int64_t a);

  static int  patch_load_narrow_oop(address pos, oop o);

  static int  patch_load_narrow_klass(address pos, Klass* k);

  // cOops. CLFI exploit.

  void compare_immediate_narrow_oop(Register oop1, narrowOop oop2);

  void compare_immediate_narrow_klass(Register op1, Klass* op2);

  static bool is_compare_immediate32(address pos);

  static bool is_compare_immediate_narrow_oop(address pos);

  static bool is_compare_immediate_narrow_klass(address pos);

  static int  compare_immediate_narrow_size()       { return 6; }

  static int  compare_immediate_narrow_oop_size()   { return compare_immediate_narrow_size(); }

  static int  compare_immediate_narrow_klass_size() { return compare_immediate_narrow_size(); }

  static int  patch_compare_immediate_32(address pos, int64_t a);

  static int  patch_compare_immediate_narrow_oop(address pos, oop o);

  static int  patch_compare_immediate_narrow_klass(address pos, Klass* k);

  // Load a 32bit constant into a 64bit register.

  void load_const_32to64(Register t, int64_t x, bool sign_extend=true);

  // Load a 64 bit constant.

         void load_const(Register t, long a);

  inline void load_const(Register t, void* a);

  inline void load_const(Register t, Label& L);

  inline void load_const(Register t, const AddressLiteral& a);

  // Get the 64 bit constant from a `load_const' sequence.

  static long get_const(address load_const);

  // Patch the 64 bit constant of a `load_const' sequence. This is a low level

  // procedure. It neither flushes the instruction cache nor is it atomic.

  static void patch_const(address load_const, long x);

  static int load_const_size() { return 12; }

  // Turn a char into boolean. NOTE: destroys r.

  void c2bool(Register r, Register t = Z_R0);

  // Optimized version of load_const for constants that do not need to be

  // loaded by a sequence of instructions of fixed length and that do not

  // need to be patched.

  int load_const_optimized_rtn_len(Register t, long x, bool emit);

  inline void load_const_optimized(Register t, long x);

  inline void load_const_optimized(Register t, void* a);

  inline void load_const_optimized(Register t, Label& L);

  inline void load_const_optimized(Register t, const AddressLiteral& a);

 public:

  //----------------------------------------------------------

  //            oops in code             -------------

  //  including compressed oops support  -------------

  //----------------------------------------------------------

  // Metadata in code that we have to keep track of.

  AddressLiteral allocate_metadata_address(Metadata* obj); // allocate_index

  AddressLiteral constant_metadata_address(Metadata* obj); // find_index

  // allocate_index

  AddressLiteral allocate_oop_address(jobject obj);

  // find_index

  AddressLiteral constant_oop_address(jobject obj);

  // Uses allocate_oop_address.

  inline void set_oop         (jobject obj, Register d);

  // Uses constant_oop_address.

  inline void set_oop_constant(jobject obj, Register d);

  // Uses constant_metadata_address.

  inline bool set_metadata_constant(Metadata* md, Register d);

  virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,

                                                Register tmp,

                                                int offset);

  //

  // branch, jump

  //

  // Use one generic function for all branch patches.

  static unsigned long patched_branch(address dest_pos, unsigned long inst, address inst_pos);

  void pd_patch_instruction(address branch, address target);

  // Extract relative address from "relative" instructions.

  static long get_pcrel_offset(unsigned long inst);

  static long get_pcrel_offset(address pc);

  static address get_target_addr_pcrel(address pc);

  static inline bool is_call_pcrelative_short(unsigned long inst);

  static inline bool is_call_pcrelative_long(unsigned long inst);

  static inline bool is_branch_pcrelative_short(unsigned long inst);

  static inline bool is_branch_pcrelative_long(unsigned long inst);

  static inline bool is_compareandbranch_pcrelative_short(unsigned long inst);

  static inline bool is_branchoncount_pcrelative_short(unsigned long inst);

  static inline bool is_branchonindex32_pcrelative_short(unsigned long inst);

  static inline bool is_branchonindex64_pcrelative_short(unsigned long inst);

  static inline bool is_branchonindex_pcrelative_short(unsigned long inst);

  static inline bool is_branch_pcrelative16(unsigned long inst);

  static inline bool is_branch_pcrelative32(unsigned long inst);

  static inline bool is_branch_pcrelative(unsigned long inst);

  static inline bool is_load_pcrelative_long(unsigned long inst);

  static inline bool is_misc_pcrelative_long(unsigned long inst);

  static inline bool is_pcrelative_short(unsigned long inst);

  static inline bool is_pcrelative_long(unsigned long inst);

  // PCrelative TOC access. Variants with address argument.

  static inline bool is_load_pcrelative_long(address iLoc);

  static inline bool is_pcrelative_short(address iLoc);

  static inline bool is_pcrelative_long(address iLoc);

  static inline bool is_pcrelative_instruction(address iloc);

  static inline bool is_load_addr_pcrel(address a);

  static void patch_target_addr_pcrel(address pc, address con);

  static void patch_addr_pcrel(address pc, address con) {

    patch_target_addr_pcrel(pc, con); // Just delegate. This is only for nativeInst_s390.cpp.

  }

  //---------------------------------------------------------

  //  Some macros for more comfortable assembler programming.

  //---------------------------------------------------------

  // NOTE: pass NearLabel T to signal that the branch target T will be bound to a near address.

  void compare32_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& target);

  void compareU32_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& target);

  void compare64_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& target);

  void compareU64_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& target);

  void branch_optimized(Assembler::branch_condition cond, address branch_target);

  void branch_optimized(Assembler::branch_condition cond, Label&  branch_target);

  void compare_and_branch_optimized(Register r1,

                                    Register r2,

                                    Assembler::branch_condition cond,

                                    address  branch_addr,

                                    bool     len64,

                                    bool     has_sign);

  void compare_and_branch_optimized(Register r1,

                                    jlong    x2,

                                    Assembler::branch_condition cond,

                                    Label&   branch_target,

                                    bool     len64,

                                    bool     has_sign);

  void compare_and_branch_optimized(Register r1,

                                    Register r2,

                                    Assembler::branch_condition cond,

                                    Label&   branch_target,

                                    bool     len64,

                                    bool     has_sign);

  //

  // Support for frame handling

  //

  // Specify the register that should be stored as the return pc in the

  // current frame (default is R14).

  inline void save_return_pc(Register pc = Z_R14);

  inline void restore_return_pc();

  // Get current PC.

  address get_PC(Register result);

  // Get current PC + offset. Offset given in bytes, must be even!

  address get_PC(Register result, int64_t offset);

  // Get size of instruction at pc (which must point to valid code).

  void instr_size(Register size, Register pc);

  // Accessing, and in particular modifying, a stack location is only safe if

  // the stack pointer (Z_SP) is set such that the accessed stack location is

  // in the reserved range.

  //

  // From a performance point of view, it is desirable not to change the SP

  // first and then immediately use it to access the freshly reserved space.

  // That opens a small gap, though. If, just after storing some value (the

  // frame pointer) into the to-be-reserved space, an interrupt is caught,

  // the handler might use the space beyond Z_SP for it's own purpose.

  // If that happens, the stored value might get altered.

  // Resize current frame either relatively wrt to current SP or absolute.

  void resize_frame_sub(Register offset, Register fp, bool load_fp=true);

  void resize_frame_abs_with_offset(Register newSP, Register fp, int offset, bool load_fp);

  void resize_frame_absolute(Register addr, Register fp, bool load_fp);

  void resize_frame(RegisterOrConstant offset, Register fp, bool load_fp=true);

  // Push a frame of size bytes, if copy_sp is false, old_sp must already

  // contain a copy of Z_SP.

  void push_frame(Register bytes, Register old_sp, bool copy_sp = true, bool bytes_with_inverted_sign = false);

  // Push a frame of size `bytes'. no abi space provided.

  // Don't rely on register locking, instead pass a scratch register

  // (Z_R0 by default).

  // CAUTION! passing registers >= Z_R2 may produce bad results on

  // old CPUs!

  unsigned int push_frame(unsigned int bytes, Register scratch = Z_R0);

  // Push a frame of size `bytes' with abi160 on top.

  unsigned int push_frame_abi160(unsigned int bytes);

  // Pop current C frame.

  void pop_frame();

  // Pop current C frame and restore return PC register (Z_R14).

  void pop_frame_restore_retPC(int frame_size_in_bytes);

  //

  // Calls

  //

 private:

  address _last_calls_return_pc;

 public:

  // Support for VM calls. This is the base routine called by the

  // different versions of call_VM_leaf. The interpreter may customize

  // this version by overriding it for its purposes (e.g., to

  // save/restore additional registers when doing a VM call).

  void call_VM_leaf_base(address entry_point);

  void call_VM_leaf_base(address entry_point, bool allow_relocation);

  // It is imperative that all calls into the VM are handled via the

  // call_VM macros. They make sure that the stack linkage is setup

  // correctly. Call_VM's correspond to ENTRY/ENTRY_X entry points

  // while call_VM_leaf's correspond to LEAF entry points.

  //

  // This is the base routine called by the different versions of

  // call_VM. The interpreter may customize this version by overriding

  // it for its purposes (e.g., to save/restore additional registers

  // when doing a VM call).

  // If no last_java_sp is specified (noreg) then SP will be used instead.

  virtual void call_VM_base(

    Register        oop_result,        // Where an oop-result ends up if any; use noreg otherwise.

    Register        last_java_sp,      // To set up last_Java_frame in stubs; use noreg otherwise.

    address         entry_point,       // The entry point.

    bool            check_exception);  // Flag which indicates if exception should be checked.

  virtual void call_VM_base(

    Register        oop_result,       // Where an oop-result ends up if any; use noreg otherwise.

    Register        last_java_sp,     // To set up last_Java_frame in stubs; use noreg otherwise.

    address         entry_point,      // The entry point.

    bool            allow_relocation, // Flag to request generation of relocatable code.

    bool            check_exception); // Flag which indicates if exception should be checked.

  // Call into the VM.

  // Passes the thread pointer (in Z_ARG1) as a prepended argument.

  // Makes sure oop return values are visible to the GC.

  void call_VM(Register oop_result, address entry_point, bool check_exceptions = true);

  void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);