/*

 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#include "precompiled.hpp"

#include "assembler_sparc.inline.hpp"

#include "gc_interface/collectedHeap.inline.hpp"

#include "interpreter/interpreter.hpp"

#include "memory/cardTableModRefBS.hpp"

#include "memory/resourceArea.hpp"

#include "prims/methodHandles.hpp"

#include "runtime/biasedLocking.hpp"

#include "runtime/interfaceSupport.hpp"

#include "runtime/objectMonitor.hpp"

#include "runtime/os.hpp"

#include "runtime/sharedRuntime.hpp"

#include "runtime/stubRoutines.hpp"

#ifndef SERIALGC

#include "gc_implementation/g1/g1CollectedHeap.inline.hpp"

#include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"

#include "gc_implementation/g1/heapRegion.hpp"

#endif

// Convert the raw encoding form into the form expected by the

// constructor for Address.

Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) {

  assert(scale == 0, "not supported");

  RelocationHolder rspec;

  if (disp_is_oop) {

    rspec = Relocation::spec_simple(relocInfo::oop_type);

  }

  Register rindex = as_Register(index);

  if (rindex != G0) {

    Address madr(as_Register(base), rindex);

    madr._rspec = rspec;

    return madr;

  } else {

    Address madr(as_Register(base), disp);

    madr._rspec = rspec;

    return madr;

  }

}

Address Argument::address_in_frame() const {

  // Warning: In LP64 mode disp will occupy more than 10 bits, but

  //          op codes such as ld or ldx, only access disp() to get

  //          their simm13 argument.

  int disp = ((_number - Argument::n_register_parameters + frame::memory_parameter_word_sp_offset) * BytesPerWord) + STACK_BIAS;

  if (is_in())

    return Address(FP, disp); // In argument.

  else

    return Address(SP, disp); // Out argument.

}

static const char* argumentNames[][2] = {

  {"A0","P0"}, {"A1","P1"}, {"A2","P2"}, {"A3","P3"}, {"A4","P4"},

  {"A5","P5"}, {"A6","P6"}, {"A7","P7"}, {"A8","P8"}, {"A9","P9"},

  {"A(n>9)","P(n>9)"}

};

const char* Argument::name() const {

  int nofArgs = sizeof argumentNames / sizeof argumentNames[0];

  int num = number();

  if (num >= nofArgs)  num = nofArgs - 1;

  return argumentNames[num][is_in() ? 1 : 0];

}

void Assembler::print_instruction(int inst) {

  const char* s;

  switch (inv_op(inst)) {

  default:         s = "????"; break;

  case call_op:    s = "call"; break;

  case branch_op:

    switch (inv_op2(inst)) {

      case bpr_op2:    s = "bpr";  break;

      case fb_op2:     s = "fb";   break;

      case fbp_op2:    s = "fbp";  break;

      case br_op2:     s = "br";   break;

      case bp_op2:     s = "bp";   break;

      case cb_op2:     s = "cb";   break;

      default:         s = "????"; break;

    }

  }

  ::tty->print("%s", s);

}

// Patch instruction inst at offset inst_pos to refer to dest_pos

// and return the resulting instruction.

// We should have pcs, not offsets, but since all is relative, it will work out

// OK.

int Assembler::patched_branch(int dest_pos, int inst, int inst_pos) {

  int m; // mask for displacement field

  int v; // new value for displacement field

  const int word_aligned_ones = -4;

  switch (inv_op(inst)) {

  default: ShouldNotReachHere();

  case call_op:    m = wdisp(word_aligned_ones, 0, 30);  v = wdisp(dest_pos, inst_pos, 30); break;

  case branch_op:

    switch (inv_op2(inst)) {

      case bpr_op2:    m = wdisp16(word_aligned_ones, 0);      v = wdisp16(dest_pos, inst_pos);     break;

      case fbp_op2:    m = wdisp(  word_aligned_ones, 0, 19);  v = wdisp(  dest_pos, inst_pos, 19); break;

      case bp_op2:     m = wdisp(  word_aligned_ones, 0, 19);  v = wdisp(  dest_pos, inst_pos, 19); break;

      case fb_op2:     m = wdisp(  word_aligned_ones, 0, 22);  v = wdisp(  dest_pos, inst_pos, 22); break;

      case br_op2:     m = wdisp(  word_aligned_ones, 0, 22);  v = wdisp(  dest_pos, inst_pos, 22); break;

      case cb_op2:     m = wdisp(  word_aligned_ones, 0, 22);  v = wdisp(  dest_pos, inst_pos, 22); break;

      default: ShouldNotReachHere();

    }

  }

  return  inst & ~m  |  v;

}

// Return the offset of the branch destionation of instruction inst

// at offset pos.

// Should have pcs, but since all is relative, it works out.

int Assembler::branch_destination(int inst, int pos) {

  int r;

  switch (inv_op(inst)) {

  default: ShouldNotReachHere();

  case call_op:        r = inv_wdisp(inst, pos, 30);  break;

  case branch_op:

    switch (inv_op2(inst)) {

      case bpr_op2:    r = inv_wdisp16(inst, pos);    break;

      case fbp_op2:    r = inv_wdisp(  inst, pos, 19);  break;

      case bp_op2:     r = inv_wdisp(  inst, pos, 19);  break;

      case fb_op2:     r = inv_wdisp(  inst, pos, 22);  break;

      case br_op2:     r = inv_wdisp(  inst, pos, 22);  break;

      case cb_op2:     r = inv_wdisp(  inst, pos, 22);  break;

      default: ShouldNotReachHere();

    }

  }

  return r;

}

int AbstractAssembler::code_fill_byte() {

  return 0x00;                  // illegal instruction 0x00000000

}

Assembler::Condition Assembler::reg_cond_to_cc_cond(Assembler::RCondition in) {

  switch (in) {

  case rc_z:   return equal;

  case rc_lez: return lessEqual;

  case rc_lz:  return less;

  case rc_nz:  return notEqual;

  case rc_gz:  return greater;

  case rc_gez: return greaterEqual;

  default:

    ShouldNotReachHere();

  }

  return equal;

}

// Generate a bunch 'o stuff (including v9's

#ifndef PRODUCT

void Assembler::test_v9() {

  add(    G0, G1, G2 );

  add(    G3,  0, G4 );

  addcc(  G5, G6, G7 );

  addcc(  I0,  1, I1 );

  addc(   I2, I3, I4 );

  addc(   I5, -1, I6 );

  addccc( I7, L0, L1 );

  addccc( L2, (1 << 12) - 2, L3 );

  Label lbl1, lbl2, lbl3;

  bind(lbl1);

  bpr( rc_z,    true, pn, L4, pc(),  relocInfo::oop_type );

  delayed()->nop();

  bpr( rc_lez, false, pt, L5, lbl1);

  delayed()->nop();

  fb( f_never,     true, pc() + 4,  relocInfo::none);

  delayed()->nop();

  fb( f_notEqual, false, lbl2 );

  delayed()->nop();

  fbp( f_notZero,        true, fcc0, pn, pc() - 4,  relocInfo::none);

  delayed()->nop();

  fbp( f_lessOrGreater, false, fcc1, pt, lbl3 );

  delayed()->nop();

  br( equal,  true, pc() + 1024, relocInfo::none);

  delayed()->nop();

  br( lessEqual, false, lbl1 );

  delayed()->nop();

  br( never, false, lbl1 );

  delayed()->nop();

  bp( less,               true, icc, pn, pc(), relocInfo::none);

  delayed()->nop();

  bp( lessEqualUnsigned, false, xcc, pt, lbl2 );

  delayed()->nop();

  call( pc(), relocInfo::none);

  delayed()->nop();

  call( lbl3 );

  delayed()->nop();

  casa(  L6, L7, O0 );

  casxa( O1, O2, O3, 0 );

  udiv(   O4, O5, O7 );

  udiv(   G0, (1 << 12) - 1, G1 );

  sdiv(   G1, G2, G3 );

  sdiv(   G4, -((1 << 12) - 1), G5 );

  udivcc( G6, G7, I0 );

  udivcc( I1, -((1 << 12) - 2), I2 );

  sdivcc( I3, I4, I5 );

  sdivcc( I6, -((1 << 12) - 0), I7 );

  done();

  retry();

  fadd( FloatRegisterImpl::S, F0,  F1, F2 );

  fsub( FloatRegisterImpl::D, F34, F0, F62 );

  fcmp(  FloatRegisterImpl::Q, fcc0, F0, F60);

  fcmpe( FloatRegisterImpl::S, fcc1, F31, F30);

  ftox( FloatRegisterImpl::D, F2, F4 );

  ftoi( FloatRegisterImpl::Q, F4, F8 );

  ftof( FloatRegisterImpl::S, FloatRegisterImpl::Q, F3, F12 );

  fxtof( FloatRegisterImpl::S, F4, F5 );

  fitof( FloatRegisterImpl::D, F6, F8 );

  fmov( FloatRegisterImpl::Q, F16, F20 );

  fneg( FloatRegisterImpl::S, F6, F7 );

  fabs( FloatRegisterImpl::D, F10, F12 );

  fmul( FloatRegisterImpl::Q,  F24, F28, F32 );

  fmul( FloatRegisterImpl::S,  FloatRegisterImpl::D,  F8, F9, F14 );

  fdiv( FloatRegisterImpl::S,  F10, F11, F12 );

  fsqrt( FloatRegisterImpl::S, F13, F14 );

  flush( L0, L1 );

  flush( L2, -1 );

  flushw();

  illtrap( (1 << 22) - 2);

  impdep1( 17, (1 << 19) - 1 );

  impdep2( 3,  0 );

  jmpl( L3, L4, L5 );

  delayed()->nop();

  jmpl( L6, -1, L7, Relocation::spec_simple(relocInfo::none));

  delayed()->nop();

  ldf(    FloatRegisterImpl::S, O0, O1, F15 );

  ldf(    FloatRegisterImpl::D, O2, -1, F14 );

  ldfsr(  O3, O4 );

  ldfsr(  O5, -1 );

  ldxfsr( O6, O7 );

  ldxfsr( I0, -1 );

  ldfa(  FloatRegisterImpl::D, I1, I2, 1, F16 );

  ldfa(  FloatRegisterImpl::Q, I3, -1,    F36 );

  ldsb(  I4, I5, I6 );

  ldsb(  I7, -1, G0 );

  ldsh(  G1, G3, G4 );

  ldsh(  G5, -1, G6 );

  ldsw(  G7, L0, L1 );

  ldsw(  L2, -1, L3 );

  ldub(  L4, L5, L6 );

  ldub(  L7, -1, O0 );

  lduh(  O1, O2, O3 );

  lduh(  O4, -1, O5 );

  lduw(  O6, O7, G0 );

  lduw(  G1, -1, G2 );

  ldx(   G3, G4, G5 );

  ldx(   G6, -1, G7 );

  ldd(   I0, I1, I2 );

  ldd(   I3, -1, I4 );

  ldsba(  I5, I6, 2, I7 );

  ldsba(  L0, -1, L1 );

  ldsha(  L2, L3, 3, L4 );

  ldsha(  L5, -1, L6 );

  ldswa(  L7, O0, (1 << 8) - 1, O1 );

  ldswa(  O2, -1, O3 );

  lduba(  O4, O5, 0, O6 );

  lduba(  O7, -1, I0 );

  lduha(  I1, I2, 1, I3 );

  lduha(  I4, -1, I5 );

  lduwa(  I6, I7, 2, L0 );

  lduwa(  L1, -1, L2 );

  ldxa(   L3, L4, 3, L5 );

  ldxa(   L6, -1, L7 );

  ldda(   G0, G1, 4, G2 );

  ldda(   G3, -1, G4 );

  ldstub(  G5, G6, G7 );

  ldstub(  O0, -1, O1 );

  ldstuba( O2, O3, 5, O4 );

  ldstuba( O5, -1, O6 );

  and3(    I0, L0, O0 );

  and3(    G7, -1, O7 );

  andcc(   L2, I2, G2 );

  andcc(   L4, -1, G4 );

  andn(    I5, I6, I7 );

  andn(    I6, -1, I7 );

  andncc(  I5, I6, I7 );

  andncc(  I7, -1, I6 );

  or3(     I5, I6, I7 );

  or3(     I7, -1, I6 );

  orcc(    I5, I6, I7 );

  orcc(    I7, -1, I6 );

  orn(     I5, I6, I7 );

  orn(     I7, -1, I6 );

  orncc(   I5, I6, I7 );

  orncc(   I7, -1, I6 );

  xor3(    I5, I6, I7 );

  xor3(    I7, -1, I6 );

  xorcc(   I5, I6, I7 );

  xorcc(   I7, -1, I6 );

  xnor(    I5, I6, I7 );

  xnor(    I7, -1, I6 );

  xnorcc(  I5, I6, I7 );

  xnorcc(  I7, -1, I6 );

  membar( Membar_mask_bits(StoreStore | LoadStore | StoreLoad | LoadLoad | Sync | MemIssue | Lookaside ) );

  membar( StoreStore );

  membar( LoadStore );

  membar( StoreLoad );

  membar( LoadLoad );

  membar( Sync );

  membar( MemIssue );

  membar( Lookaside );

  fmov( FloatRegisterImpl::S, f_ordered,  true, fcc2, F16, F17 );

  fmov( FloatRegisterImpl::D, rc_lz, L5, F18, F20 );

  movcc( overflowClear,  false, icc, I6, L4 );

  movcc( f_unorderedOrEqual, true, fcc2, (1 << 10) - 1, O0 );

  movr( rc_nz, I5, I6, I7 );

  movr( rc_gz, L1, -1,  L2 );

  mulx(  I5, I6, I7 );

  mulx(  I7, -1, I6 );

  sdivx( I5, I6, I7 );

  sdivx( I7, -1, I6 );

  udivx( I5, I6, I7 );

  udivx( I7, -1, I6 );

  umul(   I5, I6, I7 );

  umul(   I7, -1, I6 );

  smul(   I5, I6, I7 );

  smul(   I7, -1, I6 );

  umulcc( I5, I6, I7 );

  umulcc( I7, -1, I6 );

  smulcc( I5, I6, I7 );

  smulcc( I7, -1, I6 );

  mulscc(   I5, I6, I7 );

  mulscc(   I7, -1, I6 );

  nop();

  popc( G0,  G1);

  popc( -1, G2);

  prefetch(   L1, L2,    severalReads );

  prefetch(   L3, -1,    oneRead );

  prefetcha(  O3, O2, 6, severalWritesAndPossiblyReads );

  prefetcha(  G2, -1,    oneWrite );

  rett( I7, I7);

  delayed()->nop();

  rett( G0, -1, relocInfo::none);

  delayed()->nop();

  save(    I5, I6, I7 );

  save(    I7, -1, I6 );

  restore( I5, I6, I7 );

  restore( I7, -1, I6 );

  saved();

  restored();

  sethi( 0xaaaaaaaa, I3, Relocation::spec_simple(relocInfo::none));

  sll(  I5, I6, I7 );

  sll(  I7, 31, I6 );

  srl(  I5, I6, I7 );

  srl(  I7,  0, I6 );

  sra(  I5, I6, I7 );

  sra(  I7, 30, I6 );

  sllx( I5, I6, I7 );

  sllx( I7, 63, I6 );

  srlx( I5, I6, I7 );

  srlx( I7,  0, I6 );

  srax( I5, I6, I7 );

  srax( I7, 62, I6 );

  sir( -1 );

  stbar();

  stf(    FloatRegisterImpl::Q, F40, G0, I7 );

  stf(    FloatRegisterImpl::S, F18, I3, -1 );

  stfsr(  L1, L2 );

  stfsr(  I7, -1 );

  stxfsr( I6, I5 );

  stxfsr( L4, -1 );

  stfa(  FloatRegisterImpl::D, F22, I6, I7, 7 );

  stfa(  FloatRegisterImpl::Q, F44, G0, -1 );

  stb(  L5, O2, I7 );

  stb(  I7, I6, -1 );

  sth(  L5, O2, I7 );

  sth(  I7, I6, -1 );

  stw(  L5, O2, I7 );

  stw(  I7, I6, -1 );

  stx(  L5, O2, I7 );

  stx(  I7, I6, -1 );

  std(  L5, O2, I7 );

  std(  I7, I6, -1 );

  stba(  L5, O2, I7, 8 );

  stba(  I7, I6, -1    );

  stha(  L5, O2, I7, 9 );

  stha(  I7, I6, -1    );

  stwa(  L5, O2, I7, 0 );

  stwa(  I7, I6, -1    );

  stxa(  L5, O2, I7, 11 );

  stxa(  I7, I6, -1     );

  stda(  L5, O2, I7, 12 );

  stda(  I7, I6, -1     );

  sub(    I5, I6, I7 );

  sub(    I7, -1, I6 );

  subcc(  I5, I6, I7 );

  subcc(  I7, -1, I6 );

  subc(   I5, I6, I7 );

  subc(   I7, -1, I6 );

  subccc( I5, I6, I7 );

  subccc( I7, -1, I6 );

  swap( I5, I6, I7 );

  swap( I7, -1, I6 );

  swapa(   G0, G1, 13, G2 );

  swapa(   I7, -1,     I6 );

  taddcc(    I5, I6, I7 );

  taddcc(    I7, -1, I6 );

  taddcctv(  I5, I6, I7 );

  taddcctv(  I7, -1, I6 );

  tsubcc(    I5, I6, I7 );

  tsubcc(    I7, -1, I6 );

  tsubcctv(  I5, I6, I7 );

  tsubcctv(  I7, -1, I6 );

  trap( overflowClear, xcc, G0, G1 );

  trap( lessEqual,     icc, I7, 17 );

  bind(lbl2);

  bind(lbl3);

  code()->decode();

}

// Generate a bunch 'o stuff unique to V8

void Assembler::test_v8_onlys() {

  Label lbl1;

  cb( cp_0or1or2, false, pc() - 4, relocInfo::none);

  delayed()->nop();

  cb( cp_never,    true, lbl1);

  delayed()->nop();

  cpop1(1, 2, 3, 4);

  cpop2(5, 6, 7, 8);

  ldc( I0, I1, 31);

  ldc( I2, -1,  0);

  lddc( I4, I4, 30);

  lddc( I6,  0, 1 );

  ldcsr( L0, L1, 0);

  ldcsr( L1, (1 << 12) - 1, 17 );