/*

 * Copyright (c) 2000, 2011, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#ifndef SHARE_VM_C1_C1_LIR_HPP

#define SHARE_VM_C1_C1_LIR_HPP

#include "c1/c1_ValueType.hpp"

class BlockBegin;

class BlockList;

class LIR_Assembler;

class CodeEmitInfo;

class CodeStub;

class CodeStubList;

class ArrayCopyStub;

class LIR_Op;

class ciType;

class ValueType;

class LIR_OpVisitState;

class FpuStackSim;

//---------------------------------------------------------------------

//                 LIR Operands

//  LIR_OprDesc

//    LIR_OprPtr

//      LIR_Const

//      LIR_Address

//---------------------------------------------------------------------

class LIR_OprDesc;

class LIR_OprPtr;

class LIR_Const;

class LIR_Address;

class LIR_OprVisitor;

typedef LIR_OprDesc* LIR_Opr;

typedef int          RegNr;

define_array(LIR_OprArray, LIR_Opr)

define_stack(LIR_OprList, LIR_OprArray)

define_array(LIR_OprRefArray, LIR_Opr*)

define_stack(LIR_OprRefList, LIR_OprRefArray)

define_array(CodeEmitInfoArray, CodeEmitInfo*)

define_stack(CodeEmitInfoList, CodeEmitInfoArray)

define_array(LIR_OpArray, LIR_Op*)

define_stack(LIR_OpList, LIR_OpArray)

// define LIR_OprPtr early so LIR_OprDesc can refer to it

class LIR_OprPtr: public CompilationResourceObj {

 public:

  bool is_oop_pointer() const                    { return (type() == T_OBJECT); }

  bool is_float_kind() const                     { BasicType t = type(); return (t == T_FLOAT) || (t == T_DOUBLE); }

  virtual LIR_Const*  as_constant()              { return NULL; }

  virtual LIR_Address* as_address()              { return NULL; }

  virtual BasicType type() const                 = 0;

  virtual void print_value_on(outputStream* out) const = 0;

};

// LIR constants

class LIR_Const: public LIR_OprPtr {

 private:

  JavaValue _value;

  void type_check(BasicType t) const   { assert(type() == t, "type check"); }

  void type_check(BasicType t1, BasicType t2) const   { assert(type() == t1 || type() == t2, "type check"); }

  void type_check(BasicType t1, BasicType t2, BasicType t3) const   { assert(type() == t1 || type() == t2 || type() == t3, "type check"); }

 public:

  LIR_Const(jint i, bool is_address=false)       { _value.set_type(is_address?T_ADDRESS:T_INT); _value.set_jint(i); }

  LIR_Const(jlong l)                             { _value.set_type(T_LONG);    _value.set_jlong(l); }

  LIR_Const(jfloat f)                            { _value.set_type(T_FLOAT);   _value.set_jfloat(f); }

  LIR_Const(jdouble d)                           { _value.set_type(T_DOUBLE);  _value.set_jdouble(d); }

  LIR_Const(jobject o)                           { _value.set_type(T_OBJECT);  _value.set_jobject(o); }

  LIR_Const(void* p) {

#ifdef _LP64

    assert(sizeof(jlong) >= sizeof(p), "too small");;

    _value.set_type(T_LONG);    _value.set_jlong((jlong)p);

#else

    assert(sizeof(jint) >= sizeof(p), "too small");;

    _value.set_type(T_INT);     _value.set_jint((jint)p);

#endif

  }

  virtual BasicType type()       const { return _value.get_type(); }

  virtual LIR_Const* as_constant()     { return this; }

  jint      as_jint()    const         { type_check(T_INT, T_ADDRESS); return _value.get_jint(); }

  jlong     as_jlong()   const         { type_check(T_LONG  ); return _value.get_jlong(); }

  jfloat    as_jfloat()  const         { type_check(T_FLOAT ); return _value.get_jfloat(); }

  jdouble   as_jdouble() const         { type_check(T_DOUBLE); return _value.get_jdouble(); }

  jobject   as_jobject() const         { type_check(T_OBJECT); return _value.get_jobject(); }

  jint      as_jint_lo() const         { type_check(T_LONG  ); return low(_value.get_jlong()); }

  jint      as_jint_hi() const         { type_check(T_LONG  ); return high(_value.get_jlong()); }

#ifdef _LP64

  address   as_pointer() const         { type_check(T_LONG  ); return (address)_value.get_jlong(); }

#else

  address   as_pointer() const         { type_check(T_INT   ); return (address)_value.get_jint(); }

#endif

  jint      as_jint_bits() const       { type_check(T_FLOAT, T_INT, T_ADDRESS); return _value.get_jint(); }

  jint      as_jint_lo_bits() const    {

    if (type() == T_DOUBLE) {

      return low(jlong_cast(_value.get_jdouble()));

    } else {

      return as_jint_lo();

    }

  }

  jint      as_jint_hi_bits() const    {

    if (type() == T_DOUBLE) {

      return high(jlong_cast(_value.get_jdouble()));

    } else {

      return as_jint_hi();

    }

  }

  jlong      as_jlong_bits() const    {

    if (type() == T_DOUBLE) {

      return jlong_cast(_value.get_jdouble());

    } else {

      return as_jlong();

    }

  }

  virtual void print_value_on(outputStream* out) const PRODUCT_RETURN;

  bool is_zero_float() {

    jfloat f = as_jfloat();

    jfloat ok = 0.0f;

    return jint_cast(f) == jint_cast(ok);

  }

  bool is_one_float() {

    jfloat f = as_jfloat();

    return !g_isnan(f) && g_isfinite(f) && f == 1.0;

  }

  bool is_zero_double() {

    jdouble d = as_jdouble();

    jdouble ok = 0.0;

    return jlong_cast(d) == jlong_cast(ok);

  }

  bool is_one_double() {

    jdouble d = as_jdouble();

    return !g_isnan(d) && g_isfinite(d) && d == 1.0;

  }

};

//---------------------LIR Operand descriptor------------------------------------

//

// The class LIR_OprDesc represents a LIR instruction operand;

// it can be a register (ALU/FPU), stack location or a constant;

// Constants and addresses are represented as resource area allocated

// structures (see above).

// Registers and stack locations are inlined into the this pointer

// (see value function).

class LIR_OprDesc: public CompilationResourceObj {

 public:

  // value structure:

  //     data       opr-type opr-kind

  // +--------------+-------+-------+

  // [max...........|7 6 5 4|3 2 1 0]

  //                             ^

  //                    is_pointer bit

  //

  // lowest bit cleared, means it is a structure pointer

  // we need  4 bits to represent types

 private:

  friend class LIR_OprFact;

  // Conversion

  intptr_t value() const                         { return (intptr_t) this; }

  bool check_value_mask(intptr_t mask, intptr_t masked_value) const {

    return (value() & mask) == masked_value;

  }

  enum OprKind {

      pointer_value      = 0

    , stack_value        = 1

    , cpu_register       = 3

    , fpu_register       = 5

    , illegal_value      = 7

  };

  enum OprBits {

      pointer_bits   = 1

    , kind_bits      = 3

    , type_bits      = 4

    , size_bits      = 2

    , destroys_bits  = 1

    , virtual_bits   = 1

    , is_xmm_bits    = 1

    , last_use_bits  = 1

    , is_fpu_stack_offset_bits = 1        // used in assertion checking on x86 for FPU stack slot allocation

    , non_data_bits  = kind_bits + type_bits + size_bits + destroys_bits + last_use_bits +

                       is_fpu_stack_offset_bits + virtual_bits + is_xmm_bits

    , data_bits      = BitsPerInt - non_data_bits

    , reg_bits       = data_bits / 2      // for two registers in one value encoding

  };

  enum OprShift {

      kind_shift     = 0

    , type_shift     = kind_shift     + kind_bits

    , size_shift     = type_shift     + type_bits

    , destroys_shift = size_shift     + size_bits

    , last_use_shift = destroys_shift + destroys_bits

    , is_fpu_stack_offset_shift = last_use_shift + last_use_bits

    , virtual_shift  = is_fpu_stack_offset_shift + is_fpu_stack_offset_bits

    , is_xmm_shift   = virtual_shift + virtual_bits

    , data_shift     = is_xmm_shift + is_xmm_bits

    , reg1_shift = data_shift

    , reg2_shift = data_shift + reg_bits

  };

  enum OprSize {

      single_size = 0 << size_shift

    , double_size = 1 << size_shift

  };

  enum OprMask {

      kind_mask      = right_n_bits(kind_bits)

    , type_mask      = right_n_bits(type_bits) << type_shift

    , size_mask      = right_n_bits(size_bits) << size_shift

    , last_use_mask  = right_n_bits(last_use_bits) << last_use_shift

    , is_fpu_stack_offset_mask = right_n_bits(is_fpu_stack_offset_bits) << is_fpu_stack_offset_shift

    , virtual_mask   = right_n_bits(virtual_bits) << virtual_shift

    , is_xmm_mask    = right_n_bits(is_xmm_bits) << is_xmm_shift

    , pointer_mask   = right_n_bits(pointer_bits)

    , lower_reg_mask = right_n_bits(reg_bits)

    , no_type_mask   = (int)(~(type_mask | last_use_mask | is_fpu_stack_offset_mask))

  };

  uintptr_t data() const                         { return value() >> data_shift; }

  int lo_reg_half() const                        { return data() & lower_reg_mask; }

  int hi_reg_half() const                        { return (data() >> reg_bits) & lower_reg_mask; }

  OprKind kind_field() const                     { return (OprKind)(value() & kind_mask); }

  OprSize size_field() const                     { return (OprSize)(value() & size_mask); }

  static char type_char(BasicType t);

 public:

  enum {

    vreg_base = ConcreteRegisterImpl::number_of_registers,

    vreg_max = (1 << data_bits) - 1

  };

  static inline LIR_Opr illegalOpr();

  enum OprType {

      unknown_type  = 0 << type_shift    // means: not set (catch uninitialized types)

    , int_type      = 1 << type_shift

    , long_type     = 2 << type_shift

    , object_type   = 3 << type_shift

    , address_type  = 4 << type_shift

    , float_type    = 5 << type_shift

    , double_type   = 6 << type_shift

  };

  friend OprType as_OprType(BasicType t);

  friend BasicType as_BasicType(OprType t);

  OprType type_field_valid() const               { assert(is_register() || is_stack(), "should not be called otherwise"); return (OprType)(value() & type_mask); }

  OprType type_field() const                     { return is_illegal() ? unknown_type : (OprType)(value() & type_mask); }

  static OprSize size_for(BasicType t) {

    switch (t) {

      case T_LONG:

      case T_DOUBLE:

        return double_size;

        break;

      case T_FLOAT:

      case T_BOOLEAN:

      case T_CHAR:

      case T_BYTE:

      case T_SHORT:

      case T_INT:

      case T_ADDRESS:

      case T_OBJECT:

      case T_ARRAY:

        return single_size;

        break;

      default:

        ShouldNotReachHere();

        return single_size;

      }

  }

  void validate_type() const PRODUCT_RETURN;

  BasicType type() const {

    if (is_pointer()) {

      return pointer()->type();

    }

    return as_BasicType(type_field());

  }

  ValueType* value_type() const                  { return as_ValueType(type()); }

  char type_char() const                         { return type_char((is_pointer()) ? pointer()->type() : type()); }

  bool is_equal(LIR_Opr opr) const         { return this == opr; }

  // checks whether types are same

  bool is_same_type(LIR_Opr opr) const     {

    assert(type_field() != unknown_type &&

           opr->type_field() != unknown_type, "shouldn't see unknown_type");

    return type_field() == opr->type_field();

  }

  bool is_same_register(LIR_Opr opr) {

    return (is_register() && opr->is_register() &&

            kind_field() == opr->kind_field() &&

            (value() & no_type_mask) == (opr->value() & no_type_mask));

  }

  bool is_pointer() const      { return check_value_mask(pointer_mask, pointer_value); }

  bool is_illegal() const      { return kind_field() == illegal_value; }

  bool is_valid() const        { return kind_field() != illegal_value; }

  bool is_register() const     { return is_cpu_register() || is_fpu_register(); }

  bool is_virtual() const      { return is_virtual_cpu()  || is_virtual_fpu();  }

  bool is_constant() const     { return is_pointer() && pointer()->as_constant() != NULL; }

  bool is_address() const      { return is_pointer() && pointer()->as_address() != NULL; }

  bool is_float_kind() const   { return is_pointer() ? pointer()->is_float_kind() : (kind_field() == fpu_register); }

  bool is_oop() const;

  // semantic for fpu- and xmm-registers:

  // * is_float and is_double return true for xmm_registers

  //   (so is_single_fpu and is_single_xmm are true)

  // * So you must always check for is_???_xmm prior to is_???_fpu to

  //   distinguish between fpu- and xmm-registers

  bool is_stack() const        { validate_type(); return check_value_mask(kind_mask,                stack_value);                 }

  bool is_single_stack() const { validate_type(); return check_value_mask(kind_mask | size_mask,    stack_value  | single_size);  }

  bool is_double_stack() const { validate_type(); return check_value_mask(kind_mask | size_mask,    stack_value  | double_size);  }

  bool is_cpu_register() const { validate_type(); return check_value_mask(kind_mask,                cpu_register);                }

  bool is_virtual_cpu() const  { validate_type(); return check_value_mask(kind_mask | virtual_mask, cpu_register | virtual_mask); }

  bool is_fixed_cpu() const    { validate_type(); return check_value_mask(kind_mask | virtual_mask, cpu_register);                }

  bool is_single_cpu() const   { validate_type(); return check_value_mask(kind_mask | size_mask,    cpu_register | single_size);  }

  bool is_double_cpu() const   { validate_type(); return check_value_mask(kind_mask | size_mask,    cpu_register | double_size);  }

  bool is_fpu_register() const { validate_type(); return check_value_mask(kind_mask,                fpu_register);                }

  bool is_virtual_fpu() const  { validate_type(); return check_value_mask(kind_mask | virtual_mask, fpu_register | virtual_mask); }

  bool is_fixed_fpu() const    { validate_type(); return check_value_mask(kind_mask | virtual_mask, fpu_register);                }

  bool is_single_fpu() const   { validate_type(); return check_value_mask(kind_mask | size_mask,    fpu_register | single_size);  }

  bool is_double_fpu() const   { validate_type(); return check_value_mask(kind_mask | size_mask,    fpu_register | double_size);  }

  bool is_xmm_register() const { validate_type(); return check_value_mask(kind_mask | is_xmm_mask,             fpu_register | is_xmm_mask); }

  bool is_single_xmm() const   { validate_type(); return check_value_mask(kind_mask | size_mask | is_xmm_mask, fpu_register | single_size | is_xmm_mask); }

  bool is_double_xmm() const   { validate_type(); return check_value_mask(kind_mask | size_mask | is_xmm_mask, fpu_register | double_size | is_xmm_mask); }

  // fast accessor functions for special bits that do not work for pointers

  // (in this functions, the check for is_pointer() is omitted)

  bool is_single_word() const      { assert(is_register() || is_stack(), "type check"); return check_value_mask(size_mask, single_size); }

  bool is_double_word() const      { assert(is_register() || is_stack(), "type check"); return check_value_mask(size_mask, double_size); }

  bool is_virtual_register() const { assert(is_register(),               "type check"); return check_value_mask(virtual_mask, virtual_mask); }

  bool is_oop_register() const     { assert(is_register() || is_stack(), "type check"); return type_field_valid() == object_type; }

  BasicType type_register() const  { assert(is_register() || is_stack(), "type check"); return as_BasicType(type_field_valid());  }

  bool is_last_use() const         { assert(is_register(), "only works for registers"); return (value() & last_use_mask) != 0; }

  bool is_fpu_stack_offset() const { assert(is_register(), "only works for registers"); return (value() & is_fpu_stack_offset_mask) != 0; }

  LIR_Opr make_last_use()          { assert(is_register(), "only works for registers"); return (LIR_Opr)(value() | last_use_mask); }

  LIR_Opr make_fpu_stack_offset()  { assert(is_register(), "only works for registers"); return (LIR_Opr)(value() | is_fpu_stack_offset_mask); }

  int single_stack_ix() const  { assert(is_single_stack() && !is_virtual(), "type check"); return (int)data(); }

  int double_stack_ix() const  { assert(is_double_stack() && !is_virtual(), "type check"); return (int)data(); }

  RegNr cpu_regnr() const      { assert(is_single_cpu()   && !is_virtual(), "type check"); return (RegNr)data(); }

  RegNr cpu_regnrLo() const    { assert(is_double_cpu()   && !is_virtual(), "type check"); return (RegNr)lo_reg_half(); }

  RegNr cpu_regnrHi() const    { assert(is_double_cpu()   && !is_virtual(), "type check"); return (RegNr)hi_reg_half(); }

  RegNr fpu_regnr() const      { assert(is_single_fpu()   && !is_virtual(), "type check"); return (RegNr)data(); }

  RegNr fpu_regnrLo() const    { assert(is_double_fpu()   && !is_virtual(), "type check"); return (RegNr)lo_reg_half(); }

  RegNr fpu_regnrHi() const    { assert(is_double_fpu()   && !is_virtual(), "type check"); return (RegNr)hi_reg_half(); }

  RegNr xmm_regnr() const      { assert(is_single_xmm()   && !is_virtual(), "type check"); return (RegNr)data(); }

  RegNr xmm_regnrLo() const    { assert(is_double_xmm()   && !is_virtual(), "type check"); return (RegNr)lo_reg_half(); }

  RegNr xmm_regnrHi() const    { assert(is_double_xmm()   && !is_virtual(), "type check"); return (RegNr)hi_reg_half(); }

  int   vreg_number() const    { assert(is_virtual(),                       "type check"); return (RegNr)data(); }

  LIR_OprPtr* pointer()  const                   { assert(is_pointer(), "type check");      return (LIR_OprPtr*)this; }

  LIR_Const* as_constant_ptr() const             { return pointer()->as_constant(); }

  LIR_Address* as_address_ptr() const            { return pointer()->as_address(); }

  Register as_register()    const;

  Register as_register_lo() const;

  Register as_register_hi() const;

  Register as_pointer_register() {

#ifdef _LP64

    if (is_double_cpu()) {

      assert(as_register_lo() == as_register_hi(), "should be a single register");

      return as_register_lo();

    }

#endif

    return as_register();

  }

#ifdef X86

  XMMRegister as_xmm_float_reg() const;

  XMMRegister as_xmm_double_reg() const;

  // for compatibility with RInfo

  int fpu () const                                  { return lo_reg_half(); }

#endif // X86

#if defined(SPARC) || defined(ARM) || defined(PPC)

  FloatRegister as_float_reg   () const;

  FloatRegister as_double_reg  () const;

#endif

  jint      as_jint()    const { return as_constant_ptr()->as_jint(); }

  jlong     as_jlong()   const { return as_constant_ptr()->as_jlong(); }

  jfloat    as_jfloat()  const { return as_constant_ptr()->as_jfloat(); }

  jdouble   as_jdouble() const { return as_constant_ptr()->as_jdouble(); }

  jobject   as_jobject() const { return as_constant_ptr()->as_jobject(); }

  void print() const PRODUCT_RETURN;

  void print(outputStream* out) const PRODUCT_RETURN;

};

inline LIR_OprDesc::OprType as_OprType(BasicType type) {

  switch (type) {

  case T_INT:      return LIR_OprDesc::int_type;

  case T_LONG:     return LIR_OprDesc::long_type;

  case T_FLOAT:    return LIR_OprDesc::float_type;

  case T_DOUBLE:   return LIR_OprDesc::double_type;

  case T_OBJECT:

  case T_ARRAY:    return LIR_OprDesc::object_type;

  case T_ADDRESS:  return LIR_OprDesc::address_type;

  case T_ILLEGAL:  // fall through

  default: ShouldNotReachHere(); return LIR_OprDesc::unknown_type;

  }

}

inline BasicType as_BasicType(LIR_OprDesc::OprType t) {

  switch (t) {

  case LIR_OprDesc::int_type:     return T_INT;

  case LIR_OprDesc::long_type:    return T_LONG;

  case LIR_OprDesc::float_type:   return T_FLOAT;

  case LIR_OprDesc::double_type:  return T_DOUBLE;

  case LIR_OprDesc::object_type:  return T_OBJECT;

  case LIR_OprDesc::address_type: return T_ADDRESS;

  case LIR_OprDesc::unknown_type: // fall through

  default: ShouldNotReachHere();  return T_ILLEGAL;

  }

}

// LIR_Address

class LIR_Address: public LIR_OprPtr {

 friend class LIR_OpVisitState;

 public:

  // NOTE: currently these must be the log2 of the scale factor (and

  // must also be equivalent to the ScaleFactor enum in

  // assembler_i486.hpp)

  enum Scale {

    times_1  =  0,

    times_2  =  1,

    times_4  =  2,

    times_8  =  3

  };

 private:

  LIR_Opr   _base;

  LIR_Opr   _index;

  Scale     _scale;

  intx      _disp;

  BasicType _type;

 public:

  LIR_Address(LIR_Opr base, LIR_Opr index, BasicType type):

       _base(base)

     , _index(index)

     , _scale(times_1)

     , _type(type)

     , _disp(0) { verify(); }

  LIR_Address(LIR_Opr base, intx disp, BasicType type):

       _base(base)

     , _index(LIR_OprDesc::illegalOpr())

     , _scale(times_1)

     , _type(type)

     , _disp(disp) { verify(); }

  LIR_Address(LIR_Opr base, BasicType type):

       _base(base)

     , _index(LIR_OprDesc::illegalOpr())