author | dpochepk |
Wed, 22 May 2019 20:12:19 +0300 | |
changeset 54990 | cbc557f166f2 |
parent 54979 | f982c1a6582c |
child 54991 | 82fd8793ba5e |
permissions | -rw-r--r-- |
29183 | 1 |
/* |
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* Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved. |
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* Copyright (c) 2014, 2019, Red Hat Inc. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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#include "precompiled.hpp" |
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#include "asm/macroAssembler.hpp" |
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#include "asm/macroAssembler.inline.hpp" |
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#include "gc/shared/barrierSet.hpp" |
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#include "gc/shared/barrierSetAssembler.hpp" |
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#include "interpreter/interpreter.hpp" |
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#include "memory/universe.hpp" |
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#include "nativeInst_aarch64.hpp" |
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#include "oops/instanceOop.hpp" |
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#include "oops/method.hpp" |
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#include "oops/objArrayKlass.hpp" |
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#include "oops/oop.inline.hpp" |
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#include "prims/methodHandles.hpp" |
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#include "runtime/frame.inline.hpp" |
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#include "runtime/handles.inline.hpp" |
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#include "runtime/sharedRuntime.hpp" |
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#include "runtime/stubCodeGenerator.hpp" |
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#include "runtime/stubRoutines.hpp" |
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#include "runtime/thread.inline.hpp" |
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#include "utilities/align.hpp" |
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#ifdef COMPILER2 |
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#include "opto/runtime.hpp" |
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#endif |
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#ifdef BUILTIN_SIM |
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#include "../../../../../../simulator/simulator.hpp" |
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#endif |
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// Declaration and definition of StubGenerator (no .hpp file). |
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// For a more detailed description of the stub routine structure |
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// see the comment in stubRoutines.hpp |
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#undef __ |
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#define __ _masm-> |
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#define TIMES_OOP Address::sxtw(exact_log2(UseCompressedOops ? 4 : 8)) |
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#ifdef PRODUCT |
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#define BLOCK_COMMENT(str) /* nothing */ |
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#else |
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#define BLOCK_COMMENT(str) __ block_comment(str) |
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#endif |
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#define BIND(label) bind(label); BLOCK_COMMENT(#label ":") |
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// Stub Code definitions |
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class StubGenerator: public StubCodeGenerator { |
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private: |
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#ifdef PRODUCT |
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#define inc_counter_np(counter) ((void)0) |
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#else |
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void inc_counter_np_(int& counter) { |
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__ lea(rscratch2, ExternalAddress((address)&counter)); |
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__ ldrw(rscratch1, Address(rscratch2)); |
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__ addw(rscratch1, rscratch1, 1); |
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__ strw(rscratch1, Address(rscratch2)); |
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} |
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#define inc_counter_np(counter) \ |
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BLOCK_COMMENT("inc_counter " #counter); \ |
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inc_counter_np_(counter); |
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#endif |
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// Call stubs are used to call Java from C |
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// |
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// Arguments: |
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// c_rarg0: call wrapper address address |
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// c_rarg1: result address |
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// c_rarg2: result type BasicType |
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// c_rarg3: method Method* |
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// c_rarg4: (interpreter) entry point address |
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// c_rarg5: parameters intptr_t* |
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// c_rarg6: parameter size (in words) int |
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// c_rarg7: thread Thread* |
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// |
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// There is no return from the stub itself as any Java result |
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// is written to result |
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// |
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// we save r30 (lr) as the return PC at the base of the frame and |
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// link r29 (fp) below it as the frame pointer installing sp (r31) |
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// into fp. |
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// |
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// we save r0-r7, which accounts for all the c arguments. |
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// |
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// TODO: strictly do we need to save them all? they are treated as |
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// volatile by C so could we omit saving the ones we are going to |
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// place in global registers (thread? method?) or those we only use |
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// during setup of the Java call? |
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// |
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// we don't need to save r8 which C uses as an indirect result location |
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// return register. |
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// |
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// we don't need to save r9-r15 which both C and Java treat as |
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// volatile |
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// |
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// we don't need to save r16-18 because Java does not use them |
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// |
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// we save r19-r28 which Java uses as scratch registers and C |
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// expects to be callee-save |
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// |
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// we save the bottom 64 bits of each value stored in v8-v15; it is |
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// the responsibility of the caller to preserve larger values. |
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// |
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// so the stub frame looks like this when we enter Java code |
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// |
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// [ return_from_Java ] <--- sp |
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// [ argument word n ] |
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// ... |
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// -27 [ argument word 1 ] |
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// -26 [ saved v15 ] <--- sp_after_call |
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// -25 [ saved v14 ] |
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// -24 [ saved v13 ] |
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// -23 [ saved v12 ] |
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// -22 [ saved v11 ] |
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// -21 [ saved v10 ] |
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// -20 [ saved v9 ] |
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// -19 [ saved v8 ] |
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// -18 [ saved r28 ] |
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// -17 [ saved r27 ] |
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// -16 [ saved r26 ] |
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// -15 [ saved r25 ] |
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// -14 [ saved r24 ] |
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// -13 [ saved r23 ] |
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// -12 [ saved r22 ] |
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// -11 [ saved r21 ] |
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// -10 [ saved r20 ] |
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// -9 [ saved r19 ] |
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// -8 [ call wrapper (r0) ] |
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// -7 [ result (r1) ] |
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// -6 [ result type (r2) ] |
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// -5 [ method (r3) ] |
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// -4 [ entry point (r4) ] |
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// -3 [ parameters (r5) ] |
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// -2 [ parameter size (r6) ] |
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// -1 [ thread (r7) ] |
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// 0 [ saved fp (r29) ] <--- fp == saved sp (r31) |
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// 1 [ saved lr (r30) ] |
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// Call stub stack layout word offsets from fp |
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enum call_stub_layout { |
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sp_after_call_off = -26, |
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d15_off = -26, |
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d13_off = -24, |
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d11_off = -22, |
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d9_off = -20, |
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r28_off = -18, |
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r26_off = -16, |
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r24_off = -14, |
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r22_off = -12, |
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r20_off = -10, |
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call_wrapper_off = -8, |
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result_off = -7, |
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result_type_off = -6, |
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method_off = -5, |
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entry_point_off = -4, |
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parameter_size_off = -2, |
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thread_off = -1, |
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fp_f = 0, |
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retaddr_off = 1, |
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}; |
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address generate_call_stub(address& return_address) { |
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assert((int)frame::entry_frame_after_call_words == -(int)sp_after_call_off + 1 && |
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(int)frame::entry_frame_call_wrapper_offset == (int)call_wrapper_off, |
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"adjust this code"); |
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StubCodeMark mark(this, "StubRoutines", "call_stub"); |
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address start = __ pc(); |
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const Address sp_after_call(rfp, sp_after_call_off * wordSize); |
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const Address call_wrapper (rfp, call_wrapper_off * wordSize); |
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const Address result (rfp, result_off * wordSize); |
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const Address result_type (rfp, result_type_off * wordSize); |
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const Address method (rfp, method_off * wordSize); |
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const Address entry_point (rfp, entry_point_off * wordSize); |
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const Address parameter_size(rfp, parameter_size_off * wordSize); |
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const Address thread (rfp, thread_off * wordSize); |
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const Address d15_save (rfp, d15_off * wordSize); |
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const Address d13_save (rfp, d13_off * wordSize); |
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const Address d11_save (rfp, d11_off * wordSize); |
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const Address d9_save (rfp, d9_off * wordSize); |
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const Address r28_save (rfp, r28_off * wordSize); |
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const Address r26_save (rfp, r26_off * wordSize); |
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const Address r24_save (rfp, r24_off * wordSize); |
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const Address r22_save (rfp, r22_off * wordSize); |
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const Address r20_save (rfp, r20_off * wordSize); |
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// stub code |
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// we need a C prolog to bootstrap the x86 caller into the sim |
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__ c_stub_prolog(8, 0, MacroAssembler::ret_type_void); |
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address aarch64_entry = __ pc(); |
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#ifdef BUILTIN_SIM |
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// Save sender's SP for stack traces. |
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__ mov(rscratch1, sp); |
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__ str(rscratch1, Address(__ pre(sp, -2 * wordSize))); |
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#endif |
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// set up frame and move sp to end of save area |
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__ enter(); |
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__ sub(sp, rfp, -sp_after_call_off * wordSize); |
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// save register parameters and Java scratch/global registers |
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// n.b. we save thread even though it gets installed in |
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// rthread because we want to sanity check rthread later |
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__ str(c_rarg7, thread); |
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__ strw(c_rarg6, parameter_size); |
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__ stp(c_rarg4, c_rarg5, entry_point); |
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__ stp(c_rarg2, c_rarg3, result_type); |
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__ stp(c_rarg0, c_rarg1, call_wrapper); |
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__ stp(r20, r19, r20_save); |
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__ stp(r22, r21, r22_save); |
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__ stp(r24, r23, r24_save); |
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__ stp(r26, r25, r26_save); |
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__ stp(r28, r27, r28_save); |
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__ stpd(v9, v8, d9_save); |
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__ stpd(v11, v10, d11_save); |
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__ stpd(v13, v12, d13_save); |
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__ stpd(v15, v14, d15_save); |
29183 | 254 |
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// install Java thread in global register now we have saved |
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// whatever value it held |
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__ mov(rthread, c_rarg7); |
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// And method |
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__ mov(rmethod, c_rarg3); |
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260 |
||
261 |
// set up the heapbase register |
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__ reinit_heapbase(); |
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263 |
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264 |
#ifdef ASSERT |
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// make sure we have no pending exceptions |
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{ |
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Label L; |
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__ ldr(rscratch1, Address(rthread, in_bytes(Thread::pending_exception_offset()))); |
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269 |
__ cmp(rscratch1, (u1)NULL_WORD); |
29183 | 270 |
__ br(Assembler::EQ, L); |
271 |
__ stop("StubRoutines::call_stub: entered with pending exception"); |
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__ BIND(L); |
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} |
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274 |
#endif |
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// pass parameters if any |
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__ mov(esp, sp); |
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__ sub(rscratch1, sp, c_rarg6, ext::uxtw, LogBytesPerWord); // Move SP out of the way |
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__ andr(sp, rscratch1, -2 * wordSize); |
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279 |
||
280 |
BLOCK_COMMENT("pass parameters if any"); |
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Label parameters_done; |
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282 |
// parameter count is still in c_rarg6 |
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283 |
// and parameter pointer identifying param 1 is in c_rarg5 |
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284 |
__ cbzw(c_rarg6, parameters_done); |
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285 |
||
286 |
address loop = __ pc(); |
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287 |
__ ldr(rscratch1, Address(__ post(c_rarg5, wordSize))); |
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288 |
__ subsw(c_rarg6, c_rarg6, 1); |
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289 |
__ push(rscratch1); |
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290 |
__ br(Assembler::GT, loop); |
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291 |
||
292 |
__ BIND(parameters_done); |
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293 |
||
294 |
// call Java entry -- passing methdoOop, and current sp |
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295 |
// rmethod: Method* |
|
296 |
// r13: sender sp |
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297 |
BLOCK_COMMENT("call Java function"); |
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298 |
__ mov(r13, sp); |
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299 |
__ blr(c_rarg4); |
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300 |
||
301 |
// tell the simulator we have returned to the stub |
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302 |
||
303 |
// we do this here because the notify will already have been done |
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304 |
// if we get to the next instruction via an exception |
|
305 |
// |
|
306 |
// n.b. adding this instruction here affects the calculation of |
|
307 |
// whether or not a routine returns to the call stub (used when |
|
308 |
// doing stack walks) since the normal test is to check the return |
|
309 |
// pc against the address saved below. so we may need to allow for |
|
310 |
// this extra instruction in the check. |
|
311 |
||
312 |
if (NotifySimulator) { |
|
313 |
__ notify(Assembler::method_reentry); |
|
314 |
} |
|
315 |
// save current address for use by exception handling code |
|
316 |
||
317 |
return_address = __ pc(); |
|
318 |
||
319 |
// store result depending on type (everything that is not |
|
320 |
// T_OBJECT, T_LONG, T_FLOAT or T_DOUBLE is treated as T_INT) |
|
321 |
// n.b. this assumes Java returns an integral result in r0 |
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322 |
// and a floating result in j_farg0 |
|
323 |
__ ldr(j_rarg2, result); |
|
324 |
Label is_long, is_float, is_double, exit; |
|
325 |
__ ldr(j_rarg1, result_type); |
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__ cmp(j_rarg1, (u1)T_OBJECT); |
29183 | 327 |
__ br(Assembler::EQ, is_long); |
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__ cmp(j_rarg1, (u1)T_LONG); |
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__ br(Assembler::EQ, is_long); |
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330 |
__ cmp(j_rarg1, (u1)T_FLOAT); |
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__ br(Assembler::EQ, is_float); |
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332 |
__ cmp(j_rarg1, (u1)T_DOUBLE); |
29183 | 333 |
__ br(Assembler::EQ, is_double); |
334 |
||
335 |
// handle T_INT case |
|
336 |
__ strw(r0, Address(j_rarg2)); |
|
337 |
||
338 |
__ BIND(exit); |
|
339 |
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340 |
// pop parameters |
|
341 |
__ sub(esp, rfp, -sp_after_call_off * wordSize); |
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342 |
||
343 |
#ifdef ASSERT |
|
344 |
// verify that threads correspond |
|
345 |
{ |
|
346 |
Label L, S; |
|
347 |
__ ldr(rscratch1, thread); |
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348 |
__ cmp(rthread, rscratch1); |
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349 |
__ br(Assembler::NE, S); |
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350 |
__ get_thread(rscratch1); |
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351 |
__ cmp(rthread, rscratch1); |
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352 |
__ br(Assembler::EQ, L); |
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353 |
__ BIND(S); |
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354 |
__ stop("StubRoutines::call_stub: threads must correspond"); |
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355 |
__ BIND(L); |
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356 |
} |
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357 |
#endif |
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358 |
||
359 |
// restore callee-save registers |
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__ ldpd(v15, v14, d15_save); |
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__ ldpd(v13, v12, d13_save); |
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parents:
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changeset
|
362 |
__ ldpd(v11, v10, d11_save); |
f1401b7f2d58
8149907: aarch64: use load/store pair instructions in call_stub
fyang
parents:
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diff
changeset
|
363 |
__ ldpd(v9, v8, d9_save); |
f1401b7f2d58
8149907: aarch64: use load/store pair instructions in call_stub
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parents:
36326
diff
changeset
|
364 |
|
f1401b7f2d58
8149907: aarch64: use load/store pair instructions in call_stub
fyang
parents:
36326
diff
changeset
|
365 |
__ ldp(r28, r27, r28_save); |
f1401b7f2d58
8149907: aarch64: use load/store pair instructions in call_stub
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parents:
36326
diff
changeset
|
366 |
__ ldp(r26, r25, r26_save); |
f1401b7f2d58
8149907: aarch64: use load/store pair instructions in call_stub
fyang
parents:
36326
diff
changeset
|
367 |
__ ldp(r24, r23, r24_save); |
f1401b7f2d58
8149907: aarch64: use load/store pair instructions in call_stub
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36326
diff
changeset
|
368 |
__ ldp(r22, r21, r22_save); |
f1401b7f2d58
8149907: aarch64: use load/store pair instructions in call_stub
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36326
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changeset
|
369 |
__ ldp(r20, r19, r20_save); |
f1401b7f2d58
8149907: aarch64: use load/store pair instructions in call_stub
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changeset
|
370 |
|
f1401b7f2d58
8149907: aarch64: use load/store pair instructions in call_stub
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diff
changeset
|
371 |
__ ldp(c_rarg0, c_rarg1, call_wrapper); |
29183 | 372 |
__ ldrw(c_rarg2, result_type); |
373 |
__ ldr(c_rarg3, method); |
|
36340
f1401b7f2d58
8149907: aarch64: use load/store pair instructions in call_stub
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parents:
36326
diff
changeset
|
374 |
__ ldp(c_rarg4, c_rarg5, entry_point); |
f1401b7f2d58
8149907: aarch64: use load/store pair instructions in call_stub
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changeset
|
375 |
__ ldp(c_rarg6, c_rarg7, parameter_size); |
29183 | 376 |
|
377 |
#ifndef PRODUCT |
|
378 |
// tell the simulator we are about to end Java execution |
|
379 |
if (NotifySimulator) { |
|
380 |
__ notify(Assembler::method_exit); |
|
381 |
} |
|
382 |
#endif |
|
383 |
// leave frame and return to caller |
|
384 |
__ leave(); |
|
385 |
__ ret(lr); |
|
386 |
||
387 |
// handle return types different from T_INT |
|
388 |
||
389 |
__ BIND(is_long); |
|
390 |
__ str(r0, Address(j_rarg2, 0)); |
|
391 |
__ br(Assembler::AL, exit); |
|
392 |
||
393 |
__ BIND(is_float); |
|
394 |
__ strs(j_farg0, Address(j_rarg2, 0)); |
|
395 |
__ br(Assembler::AL, exit); |
|
396 |
||
397 |
__ BIND(is_double); |
|
398 |
__ strd(j_farg0, Address(j_rarg2, 0)); |
|
399 |
__ br(Assembler::AL, exit); |
|
400 |
||
401 |
return start; |
|
402 |
} |
|
403 |
||
404 |
// Return point for a Java call if there's an exception thrown in |
|
405 |
// Java code. The exception is caught and transformed into a |
|
406 |
// pending exception stored in JavaThread that can be tested from |
|
407 |
// within the VM. |
|
408 |
// |
|
409 |
// Note: Usually the parameters are removed by the callee. In case |
|
410 |
// of an exception crossing an activation frame boundary, that is |
|
411 |
// not the case if the callee is compiled code => need to setup the |
|
412 |
// rsp. |
|
413 |
// |
|
414 |
// r0: exception oop |
|
415 |
||
416 |
// NOTE: this is used as a target from the signal handler so it |
|
417 |
// needs an x86 prolog which returns into the current simulator |
|
418 |
// executing the generated catch_exception code. so the prolog |
|
419 |
// needs to install rax in a sim register and adjust the sim's |
|
420 |
// restart pc to enter the generated code at the start position |
|
421 |
// then return from native to simulated execution. |
|
422 |
||
423 |
address generate_catch_exception() { |
|
424 |
StubCodeMark mark(this, "StubRoutines", "catch_exception"); |
|
425 |
address start = __ pc(); |
|
426 |
||
427 |
// same as in generate_call_stub(): |
|
428 |
const Address sp_after_call(rfp, sp_after_call_off * wordSize); |
|
429 |
const Address thread (rfp, thread_off * wordSize); |
|
430 |
||
431 |
#ifdef ASSERT |
|
432 |
// verify that threads correspond |
|
433 |
{ |
|
434 |
Label L, S; |
|
435 |
__ ldr(rscratch1, thread); |
|
436 |
__ cmp(rthread, rscratch1); |
|
437 |
__ br(Assembler::NE, S); |
|
438 |
__ get_thread(rscratch1); |
|
439 |
__ cmp(rthread, rscratch1); |
|
440 |
__ br(Assembler::EQ, L); |
|
441 |
__ bind(S); |
|
442 |
__ stop("StubRoutines::catch_exception: threads must correspond"); |
|
443 |
__ bind(L); |
|
444 |
} |
|
445 |
#endif |
|
446 |
||
447 |
// set pending exception |
|
448 |
__ verify_oop(r0); |
|
449 |
||
450 |
__ str(r0, Address(rthread, Thread::pending_exception_offset())); |
|
451 |
__ mov(rscratch1, (address)__FILE__); |
|
452 |
__ str(rscratch1, Address(rthread, Thread::exception_file_offset())); |
|
453 |
__ movw(rscratch1, (int)__LINE__); |
|
454 |
__ strw(rscratch1, Address(rthread, Thread::exception_line_offset())); |
|
455 |
||
456 |
// complete return to VM |
|
457 |
assert(StubRoutines::_call_stub_return_address != NULL, |
|
458 |
"_call_stub_return_address must have been generated before"); |
|
459 |
__ b(StubRoutines::_call_stub_return_address); |
|
460 |
||
461 |
return start; |
|
462 |
} |
|
463 |
||
464 |
// Continuation point for runtime calls returning with a pending |
|
465 |
// exception. The pending exception check happened in the runtime |
|
466 |
// or native call stub. The pending exception in Thread is |
|
467 |
// converted into a Java-level exception. |
|
468 |
// |
|
469 |
// Contract with Java-level exception handlers: |
|
470 |
// r0: exception |
|
471 |
// r3: throwing pc |
|
472 |
// |
|
473 |
// NOTE: At entry of this stub, exception-pc must be in LR !! |
|
474 |
||
475 |
// NOTE: this is always used as a jump target within generated code |
|
476 |
// so it just needs to be generated code wiht no x86 prolog |
|
477 |
||
478 |
address generate_forward_exception() { |
|
479 |
StubCodeMark mark(this, "StubRoutines", "forward exception"); |
|
480 |
address start = __ pc(); |
|
481 |
||
482 |
// Upon entry, LR points to the return address returning into |
|
483 |
// Java (interpreted or compiled) code; i.e., the return address |
|
484 |
// becomes the throwing pc. |
|
485 |
// |
|
486 |
// Arguments pushed before the runtime call are still on the stack |
|
487 |
// but the exception handler will reset the stack pointer -> |
|
488 |
// ignore them. A potential result in registers can be ignored as |
|
489 |
// well. |
|
490 |
||
491 |
#ifdef ASSERT |
|
492 |
// make sure this code is only executed if there is a pending exception |
|
493 |
{ |
|
494 |
Label L; |
|
495 |
__ ldr(rscratch1, Address(rthread, Thread::pending_exception_offset())); |
|
496 |
__ cbnz(rscratch1, L); |
|
497 |
__ stop("StubRoutines::forward exception: no pending exception (1)"); |
|
498 |
__ bind(L); |
|
499 |
} |
|
500 |
#endif |
|
501 |
||
502 |
// compute exception handler into r19 |
|
503 |
||
504 |
// call the VM to find the handler address associated with the |
|
505 |
// caller address. pass thread in r0 and caller pc (ret address) |
|
506 |
// in r1. n.b. the caller pc is in lr, unlike x86 where it is on |
|
507 |
// the stack. |
|
508 |
__ mov(c_rarg1, lr); |
|
509 |
// lr will be trashed by the VM call so we move it to R19 |
|
510 |
// (callee-saved) because we also need to pass it to the handler |
|
511 |
// returned by this call. |
|
512 |
__ mov(r19, lr); |
|
513 |
BLOCK_COMMENT("call exception_handler_for_return_address"); |
|
514 |
__ call_VM_leaf(CAST_FROM_FN_PTR(address, |
|
515 |
SharedRuntime::exception_handler_for_return_address), |
|
516 |
rthread, c_rarg1); |
|
517 |
// we should not really care that lr is no longer the callee |
|
518 |
// address. we saved the value the handler needs in r19 so we can |
|
519 |
// just copy it to r3. however, the C2 handler will push its own |
|
520 |
// frame and then calls into the VM and the VM code asserts that |
|
521 |
// the PC for the frame above the handler belongs to a compiled |
|
522 |
// Java method. So, we restore lr here to satisfy that assert. |
|
523 |
__ mov(lr, r19); |
|
524 |
// setup r0 & r3 & clear pending exception |
|
525 |
__ mov(r3, r19); |
|
526 |
__ mov(r19, r0); |
|
527 |
__ ldr(r0, Address(rthread, Thread::pending_exception_offset())); |
|
528 |
__ str(zr, Address(rthread, Thread::pending_exception_offset())); |
|
529 |
||
530 |
#ifdef ASSERT |
|
531 |
// make sure exception is set |
|
532 |
{ |
|
533 |
Label L; |
|
534 |
__ cbnz(r0, L); |
|
535 |
__ stop("StubRoutines::forward exception: no pending exception (2)"); |
|
536 |
__ bind(L); |
|
537 |
} |
|
538 |
#endif |
|
539 |
||
540 |
// continue at exception handler |
|
541 |
// r0: exception |
|
542 |
// r3: throwing pc |
|
543 |
// r19: exception handler |
|
544 |
__ verify_oop(r0); |
|
545 |
__ br(r19); |
|
546 |
||
547 |
return start; |
|
548 |
} |
|
549 |
||
550 |
// Non-destructive plausibility checks for oops |
|
551 |
// |
|
552 |
// Arguments: |
|
553 |
// r0: oop to verify |
|
554 |
// rscratch1: error message |
|
555 |
// |
|
556 |
// Stack after saving c_rarg3: |
|
557 |
// [tos + 0]: saved c_rarg3 |
|
558 |
// [tos + 1]: saved c_rarg2 |
|
559 |
// [tos + 2]: saved lr |
|
560 |
// [tos + 3]: saved rscratch2 |
|
561 |
// [tos + 4]: saved r0 |
|
562 |
// [tos + 5]: saved rscratch1 |
|
563 |
address generate_verify_oop() { |
|
564 |
||
565 |
StubCodeMark mark(this, "StubRoutines", "verify_oop"); |
|
566 |
address start = __ pc(); |
|
567 |
||
568 |
Label exit, error; |
|
569 |
||
570 |
// save c_rarg2 and c_rarg3 |
|
571 |
__ stp(c_rarg3, c_rarg2, Address(__ pre(sp, -16))); |
|
572 |
||
573 |
// __ incrementl(ExternalAddress((address) StubRoutines::verify_oop_count_addr())); |
|
574 |
__ lea(c_rarg2, ExternalAddress((address) StubRoutines::verify_oop_count_addr())); |
|
575 |
__ ldr(c_rarg3, Address(c_rarg2)); |
|
576 |
__ add(c_rarg3, c_rarg3, 1); |
|
577 |
__ str(c_rarg3, Address(c_rarg2)); |
|
578 |
||
579 |
// object is in r0 |
|
580 |
// make sure object is 'reasonable' |
|
581 |
__ cbz(r0, exit); // if obj is NULL it is OK |
|
582 |
||
583 |
// Check if the oop is in the right area of memory |
|
584 |
__ mov(c_rarg3, (intptr_t) Universe::verify_oop_mask()); |
|
585 |
__ andr(c_rarg2, r0, c_rarg3); |
|
586 |
__ mov(c_rarg3, (intptr_t) Universe::verify_oop_bits()); |
|
587 |
||
588 |
// Compare c_rarg2 and c_rarg3. We don't use a compare |
|
589 |
// instruction here because the flags register is live. |
|
590 |
__ eor(c_rarg2, c_rarg2, c_rarg3); |
|
591 |
__ cbnz(c_rarg2, error); |
|
592 |
||
593 |
// make sure klass is 'reasonable', which is not zero. |
|
594 |
__ load_klass(r0, r0); // get klass |
|
595 |
__ cbz(r0, error); // if klass is NULL it is broken |
|
596 |
||
597 |
// return if everything seems ok |
|
598 |
__ bind(exit); |
|
599 |
||
600 |
__ ldp(c_rarg3, c_rarg2, Address(__ post(sp, 16))); |
|
601 |
__ ret(lr); |
|
602 |
||
603 |
// handle errors |
|
604 |
__ bind(error); |
|
605 |
__ ldp(c_rarg3, c_rarg2, Address(__ post(sp, 16))); |
|
606 |
||
607 |
__ push(RegSet::range(r0, r29), sp); |
|
608 |
// debug(char* msg, int64_t pc, int64_t regs[]) |
|
609 |
__ mov(c_rarg0, rscratch1); // pass address of error message |
|
610 |
__ mov(c_rarg1, lr); // pass return address |
|
611 |
__ mov(c_rarg2, sp); // pass address of regs on stack |
|
612 |
#ifndef PRODUCT |
|
613 |
assert(frame::arg_reg_save_area_bytes == 0, "not expecting frame reg save area"); |
|
614 |
#endif |
|
615 |
BLOCK_COMMENT("call MacroAssembler::debug"); |
|
616 |
__ mov(rscratch1, CAST_FROM_FN_PTR(address, MacroAssembler::debug64)); |
|
617 |
__ blrt(rscratch1, 3, 0, 1); |
|
618 |
||
619 |
return start; |
|
620 |
} |
|
621 |
||
622 |
void array_overlap_test(Label& L_no_overlap, Address::sxtw sf) { __ b(L_no_overlap); } |
|
623 |
||
45054 | 624 |
// The inner part of zero_words(). This is the bulk operation, |
625 |
// zeroing words in blocks, possibly using DC ZVA to do it. The |
|
626 |
// caller is responsible for zeroing the last few words. |
|
627 |
// |
|
628 |
// Inputs: |
|
629 |
// r10: the HeapWord-aligned base address of an array to zero. |
|
630 |
// r11: the count in HeapWords, r11 > 0. |
|
631 |
// |
|
632 |
// Returns r10 and r11, adjusted for the caller to clear. |
|
633 |
// r10: the base address of the tail of words left to clear. |
|
634 |
// r11: the number of words in the tail. |
|
635 |
// r11 < MacroAssembler::zero_words_block_size. |
|
636 |
||
637 |
address generate_zero_blocks() { |
|
51756 | 638 |
Label done; |
45054 | 639 |
Label base_aligned; |
640 |
||
641 |
Register base = r10, cnt = r11; |
|
38143 | 642 |
|
643 |
__ align(CodeEntryAlignment); |
|
45054 | 644 |
StubCodeMark mark(this, "StubRoutines", "zero_blocks"); |
38143 | 645 |
address start = __ pc(); |
646 |
||
45054 | 647 |
if (UseBlockZeroing) { |
648 |
int zva_length = VM_Version::zva_length(); |
|
649 |
||
650 |
// Ensure ZVA length can be divided by 16. This is required by |
|
651 |
// the subsequent operations. |
|
652 |
assert (zva_length % 16 == 0, "Unexpected ZVA Length"); |
|
653 |
||
654 |
__ tbz(base, 3, base_aligned); |
|
655 |
__ str(zr, Address(__ post(base, 8))); |
|
656 |
__ sub(cnt, cnt, 1); |
|
657 |
__ bind(base_aligned); |
|
658 |
||
659 |
// Ensure count >= zva_length * 2 so that it still deserves a zva after |
|
660 |
// alignment. |
|
661 |
Label small; |
|
662 |
int low_limit = MAX2(zva_length * 2, (int)BlockZeroingLowLimit); |
|
46720
5c3f87b90eff
8184900: AArch64: Fix overflow in immediate cmp instruction
yzhang
parents:
46695
diff
changeset
|
663 |
__ subs(rscratch1, cnt, low_limit >> 3); |
45054 | 664 |
__ br(Assembler::LT, small); |
665 |
__ zero_dcache_blocks(base, cnt); |
|
666 |
__ bind(small); |
|
667 |
} |
|
668 |
||
669 |
{ |
|
670 |
// Number of stp instructions we'll unroll |
|
671 |
const int unroll = |
|
672 |
MacroAssembler::zero_words_block_size / 2; |
|
673 |
// Clear the remaining blocks. |
|
674 |
Label loop; |
|
675 |
__ subs(cnt, cnt, unroll * 2); |
|
676 |
__ br(Assembler::LT, done); |
|
677 |
__ bind(loop); |
|
678 |
for (int i = 0; i < unroll; i++) |
|
679 |
__ stp(zr, zr, __ post(base, 16)); |
|
680 |
__ subs(cnt, cnt, unroll * 2); |
|
681 |
__ br(Assembler::GE, loop); |
|
682 |
__ bind(done); |
|
683 |
__ add(cnt, cnt, unroll * 2); |
|
684 |
} |
|
685 |
||
38143 | 686 |
__ ret(lr); |
687 |
||
688 |
return start; |
|
689 |
} |
|
690 |
||
45054 | 691 |
|
29183 | 692 |
typedef enum { |
693 |
copy_forwards = 1, |
|
694 |
copy_backwards = -1 |
|
695 |
} copy_direction; |
|
696 |
||
697 |
// Bulk copy of blocks of 8 words. |
|
698 |
// |
|
699 |
// count is a count of words. |
|
700 |
// |
|
36563 | 701 |
// Precondition: count >= 8 |
29183 | 702 |
// |
703 |
// Postconditions: |
|
704 |
// |
|
705 |
// The least significant bit of count contains the remaining count |
|
706 |
// of words to copy. The rest of count is trash. |
|
707 |
// |
|
708 |
// s and d are adjusted to point to the remaining words to copy |
|
709 |
// |
|
710 |
void generate_copy_longs(Label &start, Register s, Register d, Register count, |
|
711 |
copy_direction direction) { |
|
712 |
int unit = wordSize * direction; |
|
36564
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
713 |
int bias = (UseSIMDForMemoryOps ? 4:2) * wordSize; |
29183 | 714 |
|
715 |
int offset; |
|
716 |
const Register t0 = r3, t1 = r4, t2 = r5, t3 = r6, |
|
717 |
t4 = r7, t5 = r10, t6 = r11, t7 = r12; |
|
35841
39f8dc1df42b
8149365: aarch64: memory copy does not prefetch on backwards copy
enevill
parents:
35839
diff
changeset
|
718 |
const Register stride = r13; |
29183 | 719 |
|
720 |
assert_different_registers(rscratch1, t0, t1, t2, t3, t4, t5, t6, t7); |
|
721 |
assert_different_registers(s, d, count, rscratch1); |
|
722 |
||
36563 | 723 |
Label again, drain; |
35843
67b6050f5ce8
8149080: AArch64: Recognise disjoint array copy in stub code
hshi
parents:
35841
diff
changeset
|
724 |
const char *stub_name; |
67b6050f5ce8
8149080: AArch64: Recognise disjoint array copy in stub code
hshi
parents:
35841
diff
changeset
|
725 |
if (direction == copy_forwards) |
46695
aaaac1d98bc5
8183533: AArch64: redundent registers saving in arraycopy stubs
njian
parents:
46625
diff
changeset
|
726 |
stub_name = "forward_copy_longs"; |
35843
67b6050f5ce8
8149080: AArch64: Recognise disjoint array copy in stub code
hshi
parents:
35841
diff
changeset
|
727 |
else |
67b6050f5ce8
8149080: AArch64: Recognise disjoint array copy in stub code
hshi
parents:
35841
diff
changeset
|
728 |
stub_name = "backward_copy_longs"; |
52977
2e4903f83295
8205421: AARCH64: StubCodeMark should be placed after alignment
dpochepk
parents:
52927
diff
changeset
|
729 |
|
2e4903f83295
8205421: AARCH64: StubCodeMark should be placed after alignment
dpochepk
parents:
52927
diff
changeset
|
730 |
__ align(CodeEntryAlignment); |
2e4903f83295
8205421: AARCH64: StubCodeMark should be placed after alignment
dpochepk
parents:
52927
diff
changeset
|
731 |
|
35843
67b6050f5ce8
8149080: AArch64: Recognise disjoint array copy in stub code
hshi
parents:
35841
diff
changeset
|
732 |
StubCodeMark mark(this, "StubRoutines", stub_name); |
52977
2e4903f83295
8205421: AARCH64: StubCodeMark should be placed after alignment
dpochepk
parents:
52927
diff
changeset
|
733 |
|
29183 | 734 |
__ bind(start); |
40023
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
735 |
|
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
736 |
Label unaligned_copy_long; |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
737 |
if (AvoidUnalignedAccesses) { |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
738 |
__ tbnz(d, 3, unaligned_copy_long); |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
739 |
} |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
740 |
|
29183 | 741 |
if (direction == copy_forwards) { |
36564
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
742 |
__ sub(s, s, bias); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
743 |
__ sub(d, d, bias); |
29183 | 744 |
} |
36563 | 745 |
|
746 |
#ifdef ASSERT |
|
747 |
// Make sure we are never given < 8 words |
|
29183 | 748 |
{ |
36563 | 749 |
Label L; |
51374
7be0084191ed
8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents:
50758
diff
changeset
|
750 |
__ cmp(count, (u1)8); |
36563 | 751 |
__ br(Assembler::GE, L); |
752 |
__ stop("genrate_copy_longs called with < 8 words"); |
|
753 |
__ bind(L); |
|
29183 | 754 |
} |
36563 | 755 |
#endif |
29183 | 756 |
|
757 |
// Fill 8 registers |
|
36564
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
758 |
if (UseSIMDForMemoryOps) { |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
759 |
__ ldpq(v0, v1, Address(s, 4 * unit)); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
760 |
__ ldpq(v2, v3, Address(__ pre(s, 8 * unit))); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
761 |
} else { |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
762 |
__ ldp(t0, t1, Address(s, 2 * unit)); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
763 |
__ ldp(t2, t3, Address(s, 4 * unit)); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
764 |
__ ldp(t4, t5, Address(s, 6 * unit)); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
765 |
__ ldp(t6, t7, Address(__ pre(s, 8 * unit))); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
766 |
} |
29183 | 767 |
|
36563 | 768 |
__ subs(count, count, 16); |
769 |
__ br(Assembler::LO, drain); |
|
770 |
||
35841
39f8dc1df42b
8149365: aarch64: memory copy does not prefetch on backwards copy
enevill
parents:
35839
diff
changeset
|
771 |
int prefetch = PrefetchCopyIntervalInBytes; |
39f8dc1df42b
8149365: aarch64: memory copy does not prefetch on backwards copy
enevill
parents:
35839
diff
changeset
|
772 |
bool use_stride = false; |
39f8dc1df42b
8149365: aarch64: memory copy does not prefetch on backwards copy
enevill
parents:
35839
diff
changeset
|
773 |
if (direction == copy_backwards) { |
39f8dc1df42b
8149365: aarch64: memory copy does not prefetch on backwards copy
enevill
parents:
35839
diff
changeset
|
774 |
use_stride = prefetch > 256; |
39f8dc1df42b
8149365: aarch64: memory copy does not prefetch on backwards copy
enevill
parents:
35839
diff
changeset
|
775 |
prefetch = -prefetch; |
39f8dc1df42b
8149365: aarch64: memory copy does not prefetch on backwards copy
enevill
parents:
35839
diff
changeset
|
776 |
if (use_stride) __ mov(stride, prefetch); |
39f8dc1df42b
8149365: aarch64: memory copy does not prefetch on backwards copy
enevill
parents:
35839
diff
changeset
|
777 |
} |
39f8dc1df42b
8149365: aarch64: memory copy does not prefetch on backwards copy
enevill
parents:
35839
diff
changeset
|
778 |
|
29183 | 779 |
__ bind(again); |
780 |
||
35841
39f8dc1df42b
8149365: aarch64: memory copy does not prefetch on backwards copy
enevill
parents:
35839
diff
changeset
|
781 |
if (PrefetchCopyIntervalInBytes > 0) |
39f8dc1df42b
8149365: aarch64: memory copy does not prefetch on backwards copy
enevill
parents:
35839
diff
changeset
|
782 |
__ prfm(use_stride ? Address(s, stride) : Address(s, prefetch), PLDL1KEEP); |
29183 | 783 |
|
36564
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
784 |
if (UseSIMDForMemoryOps) { |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
785 |
__ stpq(v0, v1, Address(d, 4 * unit)); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
786 |
__ ldpq(v0, v1, Address(s, 4 * unit)); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
787 |
__ stpq(v2, v3, Address(__ pre(d, 8 * unit))); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
788 |
__ ldpq(v2, v3, Address(__ pre(s, 8 * unit))); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
789 |
} else { |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
790 |
__ stp(t0, t1, Address(d, 2 * unit)); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
791 |
__ ldp(t0, t1, Address(s, 2 * unit)); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
792 |
__ stp(t2, t3, Address(d, 4 * unit)); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
793 |
__ ldp(t2, t3, Address(s, 4 * unit)); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
794 |
__ stp(t4, t5, Address(d, 6 * unit)); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
795 |
__ ldp(t4, t5, Address(s, 6 * unit)); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
796 |
__ stp(t6, t7, Address(__ pre(d, 8 * unit))); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
797 |
__ ldp(t6, t7, Address(__ pre(s, 8 * unit))); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
798 |
} |
29183 | 799 |
|
800 |
__ subs(count, count, 8); |
|
801 |
__ br(Assembler::HS, again); |
|
802 |
||
803 |
// Drain |
|
36563 | 804 |
__ bind(drain); |
36564
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
805 |
if (UseSIMDForMemoryOps) { |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
806 |
__ stpq(v0, v1, Address(d, 4 * unit)); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
807 |
__ stpq(v2, v3, Address(__ pre(d, 8 * unit))); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
808 |
} else { |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
809 |
__ stp(t0, t1, Address(d, 2 * unit)); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
810 |
__ stp(t2, t3, Address(d, 4 * unit)); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
811 |
__ stp(t4, t5, Address(d, 6 * unit)); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
812 |
__ stp(t6, t7, Address(__ pre(d, 8 * unit))); |
29183 | 813 |
} |
814 |
||
815 |
{ |
|
816 |
Label L1, L2; |
|
817 |
__ tbz(count, exact_log2(4), L1); |
|
36564
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
818 |
if (UseSIMDForMemoryOps) { |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
819 |
__ ldpq(v0, v1, Address(__ pre(s, 4 * unit))); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
820 |
__ stpq(v0, v1, Address(__ pre(d, 4 * unit))); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
821 |
} else { |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
822 |
__ ldp(t0, t1, Address(s, 2 * unit)); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
823 |
__ ldp(t2, t3, Address(__ pre(s, 4 * unit))); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
824 |
__ stp(t0, t1, Address(d, 2 * unit)); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
825 |
__ stp(t2, t3, Address(__ pre(d, 4 * unit))); |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
826 |
} |
29183 | 827 |
__ bind(L1); |
828 |
||
36564
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
829 |
if (direction == copy_forwards) { |
36595
3322a76f3a00
8151502: optimize pd_disjoint_words and pd_conjoint_words
enevill
parents:
36564
diff
changeset
|
830 |
__ add(s, s, bias); |
3322a76f3a00
8151502: optimize pd_disjoint_words and pd_conjoint_words
enevill
parents:
36564
diff
changeset
|
831 |
__ add(d, d, bias); |
36564
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
832 |
} |
9442bb67de26
8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents:
36563
diff
changeset
|
833 |
|
29183 | 834 |
__ tbz(count, 1, L2); |
835 |
__ ldp(t0, t1, Address(__ adjust(s, 2 * unit, direction == copy_backwards))); |
|
836 |
__ stp(t0, t1, Address(__ adjust(d, 2 * unit, direction == copy_backwards))); |
|
837 |
__ bind(L2); |
|
838 |
} |
|
839 |
||
840 |
__ ret(lr); |
|
40023
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
841 |
|
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
842 |
if (AvoidUnalignedAccesses) { |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
843 |
Label drain, again; |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
844 |
// Register order for storing. Order is different for backward copy. |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
845 |
|
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
846 |
__ bind(unaligned_copy_long); |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
847 |
|
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
848 |
// source address is even aligned, target odd aligned |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
849 |
// |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
850 |
// when forward copying word pairs we read long pairs at offsets |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
851 |
// {0, 2, 4, 6} (in long words). when backwards copying we read |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
852 |
// long pairs at offsets {-2, -4, -6, -8}. We adjust the source |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
853 |
// address by -2 in the forwards case so we can compute the |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
854 |
// source offsets for both as {2, 4, 6, 8} * unit where unit = 1 |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
855 |
// or -1. |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
856 |
// |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
857 |
// when forward copying we need to store 1 word, 3 pairs and |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
858 |
// then 1 word at offsets {0, 1, 3, 5, 7}. Rather thna use a |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
859 |
// zero offset We adjust the destination by -1 which means we |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
860 |
// have to use offsets { 1, 2, 4, 6, 8} * unit for the stores. |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
861 |
// |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
862 |
// When backwards copyng we need to store 1 word, 3 pairs and |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
863 |
// then 1 word at offsets {-1, -3, -5, -7, -8} i.e. we use |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
864 |
// offsets {1, 3, 5, 7, 8} * unit. |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
865 |
|
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
866 |
if (direction == copy_forwards) { |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
867 |
__ sub(s, s, 16); |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
868 |
__ sub(d, d, 8); |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
869 |
} |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
870 |
|
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
871 |
// Fill 8 registers |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
872 |
// |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
873 |
// for forwards copy s was offset by -16 from the original input |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
874 |
// value of s so the register contents are at these offsets |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
875 |
// relative to the 64 bit block addressed by that original input |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
876 |
// and so on for each successive 64 byte block when s is updated |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
877 |
// |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
878 |
// t0 at offset 0, t1 at offset 8 |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
879 |
// t2 at offset 16, t3 at offset 24 |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
880 |
// t4 at offset 32, t5 at offset 40 |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
881 |
// t6 at offset 48, t7 at offset 56 |
49d647eeb7f0
8159063: aarch64: optimise unaligned array copy long
enevill
parents:
39265
diff
changeset
|
882 |
|
49d647eeb7f0
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|
883 |
// for backwards copy s was not offset so the register contents |
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|
884 |
// are at these offsets into the preceding 64 byte block |
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|
885 |
// relative to that original input and so on for each successive |
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|
886 |
// preceding 64 byte block when s is updated. this explains the |
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|
887 |
// slightly counter-intuitive looking pattern of register usage |
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|
888 |
// in the stp instructions for backwards copy. |
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|
889 |
// |
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|
890 |
// t0 at offset -16, t1 at offset -8 |
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|
891 |
// t2 at offset -32, t3 at offset -24 |
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|
892 |
// t4 at offset -48, t5 at offset -40 |
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|
893 |
// t6 at offset -64, t7 at offset -56 |
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|
894 |
|
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|
895 |
__ ldp(t0, t1, Address(s, 2 * unit)); |
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|
896 |
__ ldp(t2, t3, Address(s, 4 * unit)); |
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|
897 |
__ ldp(t4, t5, Address(s, 6 * unit)); |
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|
898 |
__ ldp(t6, t7, Address(__ pre(s, 8 * unit))); |
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|
899 |
|
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|
900 |
__ subs(count, count, 16); |
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|
901 |
__ br(Assembler::LO, drain); |
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|
902 |
|
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|
903 |
int prefetch = PrefetchCopyIntervalInBytes; |
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|
904 |
bool use_stride = false; |
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|
905 |
if (direction == copy_backwards) { |
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|
906 |
use_stride = prefetch > 256; |
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|
907 |
prefetch = -prefetch; |
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|
908 |
if (use_stride) __ mov(stride, prefetch); |
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|
909 |
} |
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|
910 |
|
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|
911 |
__ bind(again); |
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|
912 |
|
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|
913 |
if (PrefetchCopyIntervalInBytes > 0) |
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|
914 |
__ prfm(use_stride ? Address(s, stride) : Address(s, prefetch), PLDL1KEEP); |
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|
915 |
|
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|
916 |
if (direction == copy_forwards) { |
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|
917 |
// allowing for the offset of -8 the store instructions place |
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|
918 |
// registers into the target 64 bit block at the following |
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|
919 |
// offsets |
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|
920 |
// |
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|
921 |
// t0 at offset 0 |
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|
922 |
// t1 at offset 8, t2 at offset 16 |
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|
923 |
// t3 at offset 24, t4 at offset 32 |
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|
924 |
// t5 at offset 40, t6 at offset 48 |
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|
925 |
// t7 at offset 56 |
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|
926 |
|
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|
927 |
__ str(t0, Address(d, 1 * unit)); |
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|
928 |
__ stp(t1, t2, Address(d, 2 * unit)); |
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|
929 |
__ ldp(t0, t1, Address(s, 2 * unit)); |
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|
930 |
__ stp(t3, t4, Address(d, 4 * unit)); |
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|
931 |
__ ldp(t2, t3, Address(s, 4 * unit)); |
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|
932 |
__ stp(t5, t6, Address(d, 6 * unit)); |
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|
933 |
__ ldp(t4, t5, Address(s, 6 * unit)); |
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|
934 |
__ str(t7, Address(__ pre(d, 8 * unit))); |
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|
935 |
__ ldp(t6, t7, Address(__ pre(s, 8 * unit))); |
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|
936 |
} else { |
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|
937 |
// d was not offset when we started so the registers are |
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|
938 |
// written into the 64 bit block preceding d with the following |
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|
939 |
// offsets |
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|
940 |
// |
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|
941 |
// t1 at offset -8 |
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|
942 |
// t3 at offset -24, t0 at offset -16 |
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|
943 |
// t5 at offset -48, t2 at offset -32 |
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|
944 |
// t7 at offset -56, t4 at offset -48 |
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|
945 |
// t6 at offset -64 |
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|
946 |
// |
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|
947 |
// note that this matches the offsets previously noted for the |
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|
948 |
// loads |
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|
949 |
|
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|
950 |
__ str(t1, Address(d, 1 * unit)); |
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|
951 |
__ stp(t3, t0, Address(d, 3 * unit)); |
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|
952 |
__ ldp(t0, t1, Address(s, 2 * unit)); |
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|
953 |
__ stp(t5, t2, Address(d, 5 * unit)); |
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|
954 |
__ ldp(t2, t3, Address(s, 4 * unit)); |
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|
955 |
__ stp(t7, t4, Address(d, 7 * unit)); |
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|
956 |
__ ldp(t4, t5, Address(s, 6 * unit)); |
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|
957 |
__ str(t6, Address(__ pre(d, 8 * unit))); |
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|
958 |
__ ldp(t6, t7, Address(__ pre(s, 8 * unit))); |
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|
959 |
} |
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|
960 |
|
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|
961 |
__ subs(count, count, 8); |
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|
962 |
__ br(Assembler::HS, again); |
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changeset
|
963 |
|
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changeset
|
964 |
// Drain |
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changeset
|
965 |
// |
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changeset
|
966 |
// this uses the same pattern of offsets and register arguments |
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|
967 |
// as above |
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|
968 |
__ bind(drain); |
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changeset
|
969 |
if (direction == copy_forwards) { |
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|
970 |
__ str(t0, Address(d, 1 * unit)); |
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changeset
|
971 |
__ stp(t1, t2, Address(d, 2 * unit)); |
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|
972 |
__ stp(t3, t4, Address(d, 4 * unit)); |
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|
973 |
__ stp(t5, t6, Address(d, 6 * unit)); |
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|
974 |
__ str(t7, Address(__ pre(d, 8 * unit))); |
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changeset
|
975 |
} else { |
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changeset
|
976 |
__ str(t1, Address(d, 1 * unit)); |
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changeset
|
977 |
__ stp(t3, t0, Address(d, 3 * unit)); |
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|
978 |
__ stp(t5, t2, Address(d, 5 * unit)); |
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|
979 |
__ stp(t7, t4, Address(d, 7 * unit)); |
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|
980 |
__ str(t6, Address(__ pre(d, 8 * unit))); |
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changeset
|
981 |
} |
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changeset
|
982 |
// now we need to copy any remaining part block which may |
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changeset
|
983 |
// include a 4 word block subblock and/or a 2 word subblock. |
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changeset
|
984 |
// bits 2 and 1 in the count are the tell-tale for whetehr we |
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changeset
|
985 |
// have each such subblock |
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changeset
|
986 |
{ |
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|
987 |
Label L1, L2; |
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|
988 |
__ tbz(count, exact_log2(4), L1); |
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|
989 |
// this is the same as above but copying only 4 longs hence |
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|
990 |
// with ony one intervening stp between the str instructions |
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changeset
|
991 |
// but note that the offsets and registers still follow the |
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changeset
|
992 |
// same pattern |
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|
993 |
__ ldp(t0, t1, Address(s, 2 * unit)); |
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|
994 |
__ ldp(t2, t3, Address(__ pre(s, 4 * unit))); |
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changeset
|
995 |
if (direction == copy_forwards) { |
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changeset
|
996 |
__ str(t0, Address(d, 1 * unit)); |
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changeset
|
997 |
__ stp(t1, t2, Address(d, 2 * unit)); |
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changeset
|
998 |
__ str(t3, Address(__ pre(d, 4 * unit))); |
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changeset
|
999 |
} else { |
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|
1000 |
__ str(t1, Address(d, 1 * unit)); |
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1001 |
__ stp(t3, t0, Address(d, 3 * unit)); |
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1002 |
__ str(t2, Address(__ pre(d, 4 * unit))); |
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1003 |
} |
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|
1004 |
__ bind(L1); |
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|
1005 |
|
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1006 |
__ tbz(count, 1, L2); |
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|
1007 |
// this is the same as above but copying only 2 longs hence |
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|
1008 |
// there is no intervening stp between the str instructions |
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|
1009 |
// but note that the offset and register patterns are still |
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|
1010 |
// the same |
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|
1011 |
__ ldp(t0, t1, Address(__ pre(s, 2 * unit))); |
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|
1012 |
if (direction == copy_forwards) { |
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1013 |
__ str(t0, Address(d, 1 * unit)); |
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|
1014 |
__ str(t1, Address(__ pre(d, 2 * unit))); |
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|
1015 |
} else { |
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|
1016 |
__ str(t1, Address(d, 1 * unit)); |
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|
1017 |
__ str(t0, Address(__ pre(d, 2 * unit))); |
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|
1018 |
} |
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|
1019 |
__ bind(L2); |
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|
1020 |
|
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|
1021 |
// for forwards copy we need to re-adjust the offsets we |
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|
1022 |
// applied so that s and d are follow the last words written |
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|
1023 |
|
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|
1024 |
if (direction == copy_forwards) { |
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|
1025 |
__ add(s, s, 16); |
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|
1026 |
__ add(d, d, 8); |
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|
1027 |
} |
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|
1028 |
|
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|
1029 |
} |
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|
1030 |
|
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|
1031 |
__ ret(lr); |
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|
1032 |
} |
29183 | 1033 |
} |
1034 |
||
1035 |
// Small copy: less than 16 bytes. |
|
1036 |
// |
|
1037 |
// NB: Ignores all of the bits of count which represent more than 15 |
|
1038 |
// bytes, so a caller doesn't have to mask them. |
|
1039 |
||
1040 |
void copy_memory_small(Register s, Register d, Register count, Register tmp, int step) { |
|
1041 |
bool is_backwards = step < 0; |
|
1042 |
size_t granularity = uabs(step); |
|
1043 |
int direction = is_backwards ? -1 : 1; |
|
1044 |
int unit = wordSize * direction; |
|
1045 |
||
51756 | 1046 |
Label Lword, Lint, Lshort, Lbyte; |
29183 | 1047 |
|
1048 |
assert(granularity |
|
1049 |
&& granularity <= sizeof (jlong), "Impossible granularity in copy_memory_small"); |
|
1050 |
||
1051 |
const Register t0 = r3, t1 = r4, t2 = r5, t3 = r6; |
|
1052 |
||
1053 |
// ??? I don't know if this bit-test-and-branch is the right thing |
|
1054 |
// to do. It does a lot of jumping, resulting in several |
|
1055 |
// mispredicted branches. It might make more sense to do this |
|
1056 |
// with something like Duff's device with a single computed branch. |
|
1057 |
||
1058 |
__ tbz(count, 3 - exact_log2(granularity), Lword); |
|
1059 |
__ ldr(tmp, Address(__ adjust(s, unit, is_backwards))); |
|
1060 |
__ str(tmp, Address(__ adjust(d, unit, is_backwards))); |
|
1061 |
__ bind(Lword); |
|
1062 |
||
1063 |
if (granularity <= sizeof (jint)) { |
|
1064 |
__ tbz(count, 2 - exact_log2(granularity), Lint); |
|
1065 |
__ ldrw(tmp, Address(__ adjust(s, sizeof (jint) * direction, is_backwards))); |
|
1066 |
__ strw(tmp, Address(__ adjust(d, sizeof (jint) * direction, is_backwards))); |
|
1067 |
__ bind(Lint); |
|
1068 |
} |
|
1069 |
||
1070 |
if (granularity <= sizeof (jshort)) { |
|
1071 |
__ tbz(count, 1 - exact_log2(granularity), Lshort); |
|
1072 |
__ ldrh(tmp, Address(__ adjust(s, sizeof (jshort) * direction, is_backwards))); |
|
1073 |
__ strh(tmp, Address(__ adjust(d, sizeof (jshort) * direction, is_backwards))); |
|
1074 |
__ bind(Lshort); |
|
1075 |
} |
|
1076 |
||
1077 |
if (granularity <= sizeof (jbyte)) { |
|
1078 |
__ tbz(count, 0, Lbyte); |
|
1079 |
__ ldrb(tmp, Address(__ adjust(s, sizeof (jbyte) * direction, is_backwards))); |
|
1080 |
__ strb(tmp, Address(__ adjust(d, sizeof (jbyte) * direction, is_backwards))); |
|
1081 |
__ bind(Lbyte); |
|
1082 |
} |
|
1083 |
} |
|
1084 |
||
1085 |
Label copy_f, copy_b; |
|
1086 |
||
1087 |
// All-singing all-dancing memory copy. |
|
1088 |
// |
|
1089 |
// Copy count units of memory from s to d. The size of a unit is |
|
1090 |
// step, which can be positive or negative depending on the direction |
|
1091 |
// of copy. If is_aligned is false, we align the source address. |
|
1092 |
// |
|
1093 |
||
1094 |
void copy_memory(bool is_aligned, Register s, Register d, |
|
1095 |
Register count, Register tmp, int step) { |
|
1096 |
copy_direction direction = step < 0 ? copy_backwards : copy_forwards; |
|
1097 |
bool is_backwards = step < 0; |
|
1098 |
int granularity = uabs(step); |
|
1099 |
const Register t0 = r3, t1 = r4; |
|
1100 |
||
36563 | 1101 |
// <= 96 bytes do inline. Direction doesn't matter because we always |
1102 |
// load all the data before writing anything |
|
51756 | 1103 |
Label copy4, copy8, copy16, copy32, copy80, copy_big, finish; |
36563 | 1104 |
const Register t2 = r5, t3 = r6, t4 = r7, t5 = r8; |
1105 |
const Register t6 = r9, t7 = r10, t8 = r11, t9 = r12; |
|
1106 |
const Register send = r17, dend = r18; |
|
1107 |
||
1108 |
if (PrefetchCopyIntervalInBytes > 0) |
|
1109 |
__ prfm(Address(s, 0), PLDL1KEEP); |
|
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|
1110 |
__ cmp(count, u1((UseSIMDForMemoryOps ? 96:80)/granularity)); |
36563 | 1111 |
__ br(Assembler::HI, copy_big); |
1112 |
||
1113 |
__ lea(send, Address(s, count, Address::lsl(exact_log2(granularity)))); |
|
1114 |
__ lea(dend, Address(d, count, Address::lsl(exact_log2(granularity)))); |
|
1115 |
||
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|
1116 |
__ cmp(count, u1(16/granularity)); |
36563 | 1117 |
__ br(Assembler::LS, copy16); |
1118 |
||
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|
1119 |
__ cmp(count, u1(64/granularity)); |
36563 | 1120 |
__ br(Assembler::HI, copy80); |
1121 |
||
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|
1122 |
__ cmp(count, u1(32/granularity)); |
36563 | 1123 |
__ br(Assembler::LS, copy32); |
1124 |
||
1125 |
// 33..64 bytes |
|
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|
1126 |
if (UseSIMDForMemoryOps) { |
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|
1127 |
__ ldpq(v0, v1, Address(s, 0)); |
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|
1128 |
__ ldpq(v2, v3, Address(send, -32)); |
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|
1129 |
__ stpq(v0, v1, Address(d, 0)); |
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|
1130 |
__ stpq(v2, v3, Address(dend, -32)); |
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|
1131 |
} else { |
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|
1132 |
__ ldp(t0, t1, Address(s, 0)); |
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|
1133 |
__ ldp(t2, t3, Address(s, 16)); |
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|
1134 |
__ ldp(t4, t5, Address(send, -32)); |
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|
1135 |
__ ldp(t6, t7, Address(send, -16)); |
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|
1136 |
|
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|
1137 |
__ stp(t0, t1, Address(d, 0)); |
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|
1138 |
__ stp(t2, t3, Address(d, 16)); |
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|
1139 |
__ stp(t4, t5, Address(dend, -32)); |
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|
1140 |
__ stp(t6, t7, Address(dend, -16)); |
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|
1141 |
} |
36563 | 1142 |
__ b(finish); |
1143 |
||
1144 |
// 17..32 bytes |
|
1145 |
__ bind(copy32); |
|
1146 |
__ ldp(t0, t1, Address(s, 0)); |
|
1147 |
__ ldp(t2, t3, Address(send, -16)); |
|
1148 |
__ stp(t0, t1, Address(d, 0)); |
|
1149 |
__ stp(t2, t3, Address(dend, -16)); |
|
1150 |
__ b(finish); |
|
1151 |
||
36564
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|
1152 |
// 65..80/96 bytes |
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|
1153 |
// (96 bytes if SIMD because we do 32 byes per instruction) |
36563 | 1154 |
__ bind(copy80); |
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|
1155 |
if (UseSIMDForMemoryOps) { |
40023
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|
1156 |
__ ld4(v0, v1, v2, v3, __ T16B, Address(s, 0)); |
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|
1157 |
__ ldpq(v4, v5, Address(send, -32)); |
40023
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|
1158 |
__ st4(v0, v1, v2, v3, __ T16B, Address(d, 0)); |
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|
1159 |
__ stpq(v4, v5, Address(dend, -32)); |
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|
1160 |
} else { |
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|
1161 |
__ ldp(t0, t1, Address(s, 0)); |
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|
1162 |
__ ldp(t2, t3, Address(s, 16)); |
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|
1163 |
__ ldp(t4, t5, Address(s, 32)); |
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|
1164 |
__ ldp(t6, t7, Address(s, 48)); |
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|
1165 |
__ ldp(t8, t9, Address(send, -16)); |
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|
1166 |
|
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|
1167 |
__ stp(t0, t1, Address(d, 0)); |
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|
1168 |
__ stp(t2, t3, Address(d, 16)); |
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|
1169 |
__ stp(t4, t5, Address(d, 32)); |
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|
1170 |
__ stp(t6, t7, Address(d, 48)); |
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|
1171 |
__ stp(t8, t9, Address(dend, -16)); |
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|
1172 |
} |
36563 | 1173 |
__ b(finish); |
1174 |
||
1175 |
// 0..16 bytes |
|
1176 |
__ bind(copy16); |
|
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|
1177 |
__ cmp(count, u1(8/granularity)); |
36563 | 1178 |
__ br(Assembler::LO, copy8); |
1179 |
||
1180 |
// 8..16 bytes |
|
1181 |
__ ldr(t0, Address(s, 0)); |
|
1182 |
__ ldr(t1, Address(send, -8)); |
|
1183 |
__ str(t0, Address(d, 0)); |
|
1184 |
__ str(t1, Address(dend, -8)); |
|
1185 |
__ b(finish); |
|
1186 |
||
1187 |
if (granularity < 8) { |
|
1188 |
// 4..7 bytes |
|
1189 |
__ bind(copy8); |
|
1190 |
__ tbz(count, 2 - exact_log2(granularity), copy4); |
|
1191 |
__ ldrw(t0, Address(s, 0)); |
|
1192 |
__ ldrw(t1, Address(send, -4)); |
|
1193 |
__ strw(t0, Address(d, 0)); |
|
1194 |
__ strw(t1, Address(dend, -4)); |
|
1195 |
__ b(finish); |
|
1196 |
if (granularity < 4) { |
|
1197 |
// 0..3 bytes |
|
1198 |
__ bind(copy4); |
|
1199 |
__ cbz(count, finish); // get rid of 0 case |
|
1200 |
if (granularity == 2) { |
|
1201 |
__ ldrh(t0, Address(s, 0)); |
|
1202 |
__ strh(t0, Address(d, 0)); |
|
1203 |
} else { // granularity == 1 |
|
1204 |
// Now 1..3 bytes. Handle the 1 and 2 byte case by copying |
|
1205 |
// the first and last byte. |
|
1206 |
// Handle the 3 byte case by loading and storing base + count/2 |
|
1207 |
// (count == 1 (s+0)->(d+0), count == 2,3 (s+1) -> (d+1)) |
|
1208 |
// This does means in the 1 byte case we load/store the same |
|
1209 |
// byte 3 times. |
|
1210 |
__ lsr(count, count, 1); |
|
1211 |
__ ldrb(t0, Address(s, 0)); |
|
1212 |
__ ldrb(t1, Address(send, -1)); |
|
1213 |
__ ldrb(t2, Address(s, count)); |
|
1214 |
__ strb(t0, Address(d, 0)); |
|
1215 |
__ strb(t1, Address(dend, -1)); |
|
1216 |
__ strb(t2, Address(d, count)); |
|
1217 |
} |
|
1218 |
__ b(finish); |
|
1219 |
} |
|
1220 |
} |
|
1221 |
||
1222 |
__ bind(copy_big); |
|
29183 | 1223 |
if (is_backwards) { |
35119
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
1224 |
__ lea(s, Address(s, count, Address::lsl(exact_log2(-step)))); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
1225 |
__ lea(d, Address(d, count, Address::lsl(exact_log2(-step)))); |
29183 | 1226 |
} |
1227 |
||
1228 |
// Now we've got the small case out of the way we can align the |
|
1229 |
// source address on a 2-word boundary. |
|
1230 |
||
1231 |
Label aligned; |
|
1232 |
||
1233 |
if (is_aligned) { |
|
1234 |
// We may have to adjust by 1 word to get s 2-word-aligned. |
|
1235 |
__ tbz(s, exact_log2(wordSize), aligned); |
|
1236 |
__ ldr(tmp, Address(__ adjust(s, direction * wordSize, is_backwards))); |
|
1237 |
__ str(tmp, Address(__ adjust(d, direction * wordSize, is_backwards))); |
|
1238 |
__ sub(count, count, wordSize/granularity); |
|
1239 |
} else { |
|
1240 |
if (is_backwards) { |
|
1241 |
__ andr(rscratch2, s, 2 * wordSize - 1); |
|
1242 |
} else { |
|
1243 |
__ neg(rscratch2, s); |
|
1244 |
__ andr(rscratch2, rscratch2, 2 * wordSize - 1); |
|
1245 |
} |
|
1246 |
// rscratch2 is the byte adjustment needed to align s. |
|
1247 |
__ cbz(rscratch2, aligned); |
|
35752
16265e7c7a53
8148328: aarch64: redundant lsr instructions in stub code.
fyang
parents:
35579
diff
changeset
|
1248 |
int shift = exact_log2(granularity); |
16265e7c7a53
8148328: aarch64: redundant lsr instructions in stub code.
fyang
parents:
35579
diff
changeset
|
1249 |
if (shift) __ lsr(rscratch2, rscratch2, shift); |
29183 | 1250 |
__ sub(count, count, rscratch2); |
1251 |
||
1252 |
#if 0 |
|
1253 |
// ?? This code is only correct for a disjoint copy. It may or |
|
1254 |
// may not make sense to use it in that case. |
|
1255 |
||
1256 |
// Copy the first pair; s and d may not be aligned. |
|
1257 |
__ ldp(t0, t1, Address(s, is_backwards ? -2 * wordSize : 0)); |
|
1258 |
__ stp(t0, t1, Address(d, is_backwards ? -2 * wordSize : 0)); |
|
1259 |
||
1260 |
// Align s and d, adjust count |
|
1261 |
if (is_backwards) { |
|
1262 |
__ sub(s, s, rscratch2); |
|
1263 |
__ sub(d, d, rscratch2); |
|
1264 |
} else { |
|
1265 |
__ add(s, s, rscratch2); |
|
1266 |
__ add(d, d, rscratch2); |
|
1267 |
} |
|
1268 |
#else |
|
1269 |
copy_memory_small(s, d, rscratch2, rscratch1, step); |
|
1270 |
#endif |
|
1271 |
} |
|
1272 |
||
1273 |
__ bind(aligned); |
|
1274 |
||
1275 |
// s is now 2-word-aligned. |
|
1276 |
||
1277 |
// We have a count of units and some trailing bytes. Adjust the |
|
1278 |
// count and do a bulk copy of words. |
|
1279 |
__ lsr(rscratch2, count, exact_log2(wordSize/granularity)); |
|
1280 |
if (direction == copy_forwards) |
|
1281 |
__ bl(copy_f); |
|
1282 |
else |
|
1283 |
__ bl(copy_b); |
|
1284 |
||
1285 |
// And the tail. |
|
1286 |
copy_memory_small(s, d, count, tmp, step); |
|
36563 | 1287 |
|
1288 |
if (granularity >= 8) __ bind(copy8); |
|
1289 |
if (granularity >= 4) __ bind(copy4); |
|
1290 |
__ bind(finish); |
|
29183 | 1291 |
} |
1292 |
||
1293 |
||
1294 |
void clobber_registers() { |
|
1295 |
#ifdef ASSERT |
|
1296 |
__ mov(rscratch1, (uint64_t)0xdeadbeef); |
|
1297 |
__ orr(rscratch1, rscratch1, rscratch1, Assembler::LSL, 32); |
|
1298 |
for (Register r = r3; r <= r18; r++) |
|
1299 |
if (r != rscratch1) __ mov(r, rscratch1); |
|
1300 |
#endif |
|
1301 |
} |
|
1302 |
||
1303 |
// Scan over array at a for count oops, verifying each one. |
|
1304 |
// Preserves a and count, clobbers rscratch1 and rscratch2. |
|
1305 |
void verify_oop_array (size_t size, Register a, Register count, Register temp) { |
|
1306 |
Label loop, end; |
|
1307 |
__ mov(rscratch1, a); |
|
1308 |
__ mov(rscratch2, zr); |
|
1309 |
__ bind(loop); |
|
1310 |
__ cmp(rscratch2, count); |
|
1311 |
__ br(Assembler::HS, end); |
|
1312 |
if (size == (size_t)wordSize) { |
|
35119
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
1313 |
__ ldr(temp, Address(a, rscratch2, Address::lsl(exact_log2(size)))); |
29183 | 1314 |
__ verify_oop(temp); |
1315 |
} else { |
|
35119
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
1316 |
__ ldrw(r16, Address(a, rscratch2, Address::lsl(exact_log2(size)))); |
29183 | 1317 |
__ decode_heap_oop(temp); // calls verify_oop |
1318 |
} |
|
1319 |
__ add(rscratch2, rscratch2, size); |
|
1320 |
__ b(loop); |
|
1321 |
__ bind(end); |
|
1322 |
} |
|
1323 |
||
1324 |
// Arguments: |
|
1325 |
// aligned - true => Input and output aligned on a HeapWord == 8-byte boundary |
|
1326 |
// ignored |
|
1327 |
// is_oop - true => oop array, so generate store check code |
|
1328 |
// name - stub name string |
|
1329 |
// |
|
1330 |
// Inputs: |
|
1331 |
// c_rarg0 - source array address |
|
1332 |
// c_rarg1 - destination array address |
|
1333 |
// c_rarg2 - element count, treated as ssize_t, can be zero |
|
1334 |
// |
|
1335 |
// If 'from' and/or 'to' are aligned on 4-byte boundaries, we let |
|
1336 |
// the hardware handle it. The two dwords within qwords that span |
|
1337 |
// cache line boundaries will still be loaded and stored atomicly. |
|
1338 |
// |
|
1339 |
// Side Effects: |
|
1340 |
// disjoint_int_copy_entry is set to the no-overlap entry point |
|
1341 |
// used by generate_conjoint_int_oop_copy(). |
|
1342 |
// |
|
1343 |
address generate_disjoint_copy(size_t size, bool aligned, bool is_oop, address *entry, |
|
1344 |
const char *name, bool dest_uninitialized = false) { |
|
1345 |
Register s = c_rarg0, d = c_rarg1, count = c_rarg2; |
|
46695
aaaac1d98bc5
8183533: AArch64: redundent registers saving in arraycopy stubs
njian
parents:
46625
diff
changeset
|
1346 |
RegSet saved_reg = RegSet::of(s, d, count); |
29183 | 1347 |
__ align(CodeEntryAlignment); |
1348 |
StubCodeMark mark(this, "StubRoutines", name); |
|
1349 |
address start = __ pc(); |
|
35119
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
1350 |
__ enter(); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
1351 |
|
29183 | 1352 |
if (entry != NULL) { |
1353 |
*entry = __ pc(); |
|
1354 |
// caller can pass a 64-bit byte count here (from Unsafe.copyMemory) |
|
1355 |
BLOCK_COMMENT("Entry:"); |
|
1356 |
} |
|
35119
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
1357 |
|
50728 | 1358 |
DecoratorSet decorators = IN_HEAP | IS_ARRAY | ARRAYCOPY_DISJOINT; |
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1359 |
if (dest_uninitialized) { |
50728 | 1360 |
decorators |= IS_DEST_UNINITIALIZED; |
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1361 |
} |
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1362 |
if (aligned) { |
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1363 |
decorators |= ARRAYCOPY_ALIGNED; |
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1364 |
} |
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1365 |
|
49754 | 1366 |
BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler(); |
54979
f982c1a6582c
8224187: Refactor arraycopy_prologue to allow ZGC read barriers on arraycopy
smonteith
parents:
54786
diff
changeset
|
1367 |
bs->arraycopy_prologue(_masm, decorators, is_oop, s, d, count, saved_reg); |
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1368 |
|
29183 | 1369 |
if (is_oop) { |
46695
aaaac1d98bc5
8183533: AArch64: redundent registers saving in arraycopy stubs
njian
parents:
46625
diff
changeset
|
1370 |
// save regs before copy_memory |
29183 | 1371 |
__ push(RegSet::of(d, count), sp); |
1372 |
} |
|
1373 |
copy_memory(aligned, s, d, count, rscratch1, size); |
|
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1374 |
|
29183 | 1375 |
if (is_oop) { |
1376 |
__ pop(RegSet::of(d, count), sp); |
|
1377 |
if (VerifyOops) |
|
1378 |
verify_oop_array(size, d, count, r16); |
|
1379 |
} |
|
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1380 |
|
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1381 |
bs->arraycopy_epilogue(_masm, decorators, is_oop, d, count, rscratch1, RegSet()); |
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1382 |
|
29183 | 1383 |
__ leave(); |
35119
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
1384 |
__ mov(r0, zr); // return 0 |
29183 | 1385 |
__ ret(lr); |
1386 |
#ifdef BUILTIN_SIM |
|
1387 |
{ |
|
1388 |
AArch64Simulator *sim = AArch64Simulator::get_current(UseSimulatorCache, DisableBCCheck); |
|
1389 |
sim->notifyCompile(const_cast<char*>(name), start); |
|
1390 |
} |
|
1391 |
#endif |
|
1392 |
return start; |
|
1393 |
} |
|
1394 |
||
1395 |
// Arguments: |
|
1396 |
// aligned - true => Input and output aligned on a HeapWord == 8-byte boundary |
|
1397 |
// ignored |
|
1398 |
// is_oop - true => oop array, so generate store check code |
|
1399 |
// name - stub name string |
|
1400 |
// |
|
1401 |
// Inputs: |
|
1402 |
// c_rarg0 - source array address |
|
1403 |
// c_rarg1 - destination array address |
|
1404 |
// c_rarg2 - element count, treated as ssize_t, can be zero |
|
1405 |
// |
|
1406 |
// If 'from' and/or 'to' are aligned on 4-byte boundaries, we let |
|
1407 |
// the hardware handle it. The two dwords within qwords that span |
|
1408 |
// cache line boundaries will still be loaded and stored atomicly. |
|
1409 |
// |
|
1410 |
address generate_conjoint_copy(size_t size, bool aligned, bool is_oop, address nooverlap_target, |
|
1411 |
address *entry, const char *name, |
|
1412 |
bool dest_uninitialized = false) { |
|
1413 |
Register s = c_rarg0, d = c_rarg1, count = c_rarg2; |
|
46695
aaaac1d98bc5
8183533: AArch64: redundent registers saving in arraycopy stubs
njian
parents:
46625
diff
changeset
|
1414 |
RegSet saved_regs = RegSet::of(s, d, count); |
29183 | 1415 |
StubCodeMark mark(this, "StubRoutines", name); |
1416 |
address start = __ pc(); |
|
35119
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
1417 |
__ enter(); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
1418 |
|
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
1419 |
if (entry != NULL) { |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
1420 |
*entry = __ pc(); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
1421 |
// caller can pass a 64-bit byte count here (from Unsafe.copyMemory) |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
1422 |
BLOCK_COMMENT("Entry:"); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
1423 |
} |
35843
67b6050f5ce8
8149080: AArch64: Recognise disjoint array copy in stub code
hshi
parents:
35841
diff
changeset
|
1424 |
|
67b6050f5ce8
8149080: AArch64: Recognise disjoint array copy in stub code
hshi
parents:
35841
diff
changeset
|
1425 |
// use fwd copy when (d-s) above_equal (count*size) |
67b6050f5ce8
8149080: AArch64: Recognise disjoint array copy in stub code
hshi
parents:
35841
diff
changeset
|
1426 |
__ sub(rscratch1, d, s); |
67b6050f5ce8
8149080: AArch64: Recognise disjoint array copy in stub code
hshi
parents:
35841
diff
changeset
|
1427 |
__ cmp(rscratch1, count, Assembler::LSL, exact_log2(size)); |
67b6050f5ce8
8149080: AArch64: Recognise disjoint array copy in stub code
hshi
parents:
35841
diff
changeset
|
1428 |
__ br(Assembler::HS, nooverlap_target); |
29183 | 1429 |
|
50728 | 1430 |
DecoratorSet decorators = IN_HEAP | IS_ARRAY; |
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1431 |
if (dest_uninitialized) { |
50728 | 1432 |
decorators |= IS_DEST_UNINITIALIZED; |
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1433 |
} |
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1434 |
if (aligned) { |
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1435 |
decorators |= ARRAYCOPY_ALIGNED; |
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1436 |
} |
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1437 |
|
49754 | 1438 |
BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler(); |
54979
f982c1a6582c
8224187: Refactor arraycopy_prologue to allow ZGC read barriers on arraycopy
smonteith
parents:
54786
diff
changeset
|
1439 |
bs->arraycopy_prologue(_masm, decorators, is_oop, s, d, count, saved_regs); |
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1440 |
|
29183 | 1441 |
if (is_oop) { |
46695
aaaac1d98bc5
8183533: AArch64: redundent registers saving in arraycopy stubs
njian
parents:
46625
diff
changeset
|
1442 |
// save regs before copy_memory |
29183 | 1443 |
__ push(RegSet::of(d, count), sp); |
1444 |
} |
|
1445 |
copy_memory(aligned, s, d, count, rscratch1, -size); |
|
1446 |
if (is_oop) { |
|
1447 |
__ pop(RegSet::of(d, count), sp); |
|
1448 |
if (VerifyOops) |
|
1449 |
verify_oop_array(size, d, count, r16); |
|
1450 |
} |
|
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1451 |
bs->arraycopy_epilogue(_masm, decorators, is_oop, d, count, rscratch1, RegSet()); |
29183 | 1452 |
__ leave(); |
35119
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
1453 |
__ mov(r0, zr); // return 0 |
29183 | 1454 |
__ ret(lr); |
1455 |
#ifdef BUILTIN_SIM |
|
1456 |
{ |
|
1457 |
AArch64Simulator *sim = AArch64Simulator::get_current(UseSimulatorCache, DisableBCCheck); |
|
1458 |
sim->notifyCompile(const_cast<char*>(name), start); |
|
1459 |
} |
|
1460 |
#endif |
|
1461 |
return start; |
|
1462 |
} |
|
1463 |
||
1464 |
// Arguments: |
|
1465 |
// aligned - true => Input and output aligned on a HeapWord == 8-byte boundary |
|
1466 |
// ignored |
|
1467 |
// name - stub name string |
|
1468 |
// |
|
1469 |
// Inputs: |
|
1470 |
// c_rarg0 - source array address |
|
1471 |
// c_rarg1 - destination array address |
|
1472 |
// c_rarg2 - element count, treated as ssize_t, can be zero |
|
1473 |
// |
|
1474 |
// If 'from' and/or 'to' are aligned on 4-, 2-, or 1-byte boundaries, |
|
1475 |
// we let the hardware handle it. The one to eight bytes within words, |
|
1476 |
// dwords or qwords that span cache line boundaries will still be loaded |
|
1477 |
// and stored atomically. |
|
1478 |
// |
|
1479 |
// Side Effects: |
|
1480 |
// disjoint_byte_copy_entry is set to the no-overlap entry point // |
|
1481 |
// If 'from' and/or 'to' are aligned on 4-, 2-, or 1-byte boundaries, |
|
1482 |
// we let the hardware handle it. The one to eight bytes within words, |
|
1483 |
// dwords or qwords that span cache line boundaries will still be loaded |
|
1484 |
// and stored atomically. |
|
1485 |
// |
|
1486 |
// Side Effects: |
|
1487 |
// disjoint_byte_copy_entry is set to the no-overlap entry point |
|
1488 |
// used by generate_conjoint_byte_copy(). |
|
1489 |
// |
|
1490 |
address generate_disjoint_byte_copy(bool aligned, address* entry, const char *name) { |
|
1491 |
const bool not_oop = false; |
|
1492 |
return generate_disjoint_copy(sizeof (jbyte), aligned, not_oop, entry, name); |
|
1493 |
} |
|
1494 |
||
1495 |
// Arguments: |
|
1496 |
// aligned - true => Input and output aligned on a HeapWord == 8-byte boundary |
|
1497 |
// ignored |
|
1498 |
// name - stub name string |
|
1499 |
// |
|
1500 |
// Inputs: |
|
1501 |
// c_rarg0 - source array address |
|
1502 |
// c_rarg1 - destination array address |
|
1503 |
// c_rarg2 - element count, treated as ssize_t, can be zero |
|
1504 |
// |
|
1505 |
// If 'from' and/or 'to' are aligned on 4-, 2-, or 1-byte boundaries, |
|
1506 |
// we let the hardware handle it. The one to eight bytes within words, |
|
1507 |
// dwords or qwords that span cache line boundaries will still be loaded |
|
1508 |
// and stored atomically. |
|
1509 |
// |
|
1510 |
address generate_conjoint_byte_copy(bool aligned, address nooverlap_target, |
|
1511 |
address* entry, const char *name) { |
|
1512 |
const bool not_oop = false; |
|
1513 |
return generate_conjoint_copy(sizeof (jbyte), aligned, not_oop, nooverlap_target, entry, name); |
|
1514 |
} |
|
1515 |
||
1516 |
// Arguments: |
|
1517 |
// aligned - true => Input and output aligned on a HeapWord == 8-byte boundary |
|
1518 |
// ignored |
|
1519 |
// name - stub name string |
|
1520 |
// |
|
1521 |
// Inputs: |
|
1522 |
// c_rarg0 - source array address |
|
1523 |
// c_rarg1 - destination array address |
|
1524 |
// c_rarg2 - element count, treated as ssize_t, can be zero |
|
1525 |
// |
|
1526 |
// If 'from' and/or 'to' are aligned on 4- or 2-byte boundaries, we |
|
1527 |
// let the hardware handle it. The two or four words within dwords |
|
1528 |
// or qwords that span cache line boundaries will still be loaded |
|
1529 |
// and stored atomically. |
|
1530 |
// |
|
1531 |
// Side Effects: |
|
1532 |
// disjoint_short_copy_entry is set to the no-overlap entry point |
|
1533 |
// used by generate_conjoint_short_copy(). |
|
1534 |
// |
|
1535 |
address generate_disjoint_short_copy(bool aligned, |
|
1536 |
address* entry, const char *name) { |
|
1537 |
const bool not_oop = false; |
|
1538 |
return generate_disjoint_copy(sizeof (jshort), aligned, not_oop, entry, name); |
|
1539 |
} |
|
1540 |
||
1541 |
// Arguments: |
|
1542 |
// aligned - true => Input and output aligned on a HeapWord == 8-byte boundary |
|
1543 |
// ignored |
|
1544 |
// name - stub name string |
|
1545 |
// |
|
1546 |
// Inputs: |
|
1547 |
// c_rarg0 - source array address |
|
1548 |
// c_rarg1 - destination array address |
|
1549 |
// c_rarg2 - element count, treated as ssize_t, can be zero |
|
1550 |
// |
|
1551 |
// If 'from' and/or 'to' are aligned on 4- or 2-byte boundaries, we |
|
1552 |
// let the hardware handle it. The two or four words within dwords |
|
1553 |
// or qwords that span cache line boundaries will still be loaded |
|
1554 |
// and stored atomically. |
|
1555 |
// |
|
1556 |
address generate_conjoint_short_copy(bool aligned, address nooverlap_target, |
|
1557 |
address *entry, const char *name) { |
|
1558 |
const bool not_oop = false; |
|
1559 |
return generate_conjoint_copy(sizeof (jshort), aligned, not_oop, nooverlap_target, entry, name); |
|
1560 |
||
1561 |
} |
|
1562 |
// Arguments: |
|
1563 |
// aligned - true => Input and output aligned on a HeapWord == 8-byte boundary |
|
1564 |
// ignored |
|
1565 |
// name - stub name string |
|
1566 |
// |
|
1567 |
// Inputs: |
|
1568 |
// c_rarg0 - source array address |
|
1569 |
// c_rarg1 - destination array address |
|
1570 |
// c_rarg2 - element count, treated as ssize_t, can be zero |
|
1571 |
// |
|
1572 |
// If 'from' and/or 'to' are aligned on 4-byte boundaries, we let |
|
1573 |
// the hardware handle it. The two dwords within qwords that span |
|
1574 |
// cache line boundaries will still be loaded and stored atomicly. |
|
1575 |
// |
|
1576 |
// Side Effects: |
|
1577 |
// disjoint_int_copy_entry is set to the no-overlap entry point |
|
1578 |
// used by generate_conjoint_int_oop_copy(). |
|
1579 |
// |
|
1580 |
address generate_disjoint_int_copy(bool aligned, address *entry, |
|
1581 |
const char *name, bool dest_uninitialized = false) { |
|
1582 |
const bool not_oop = false; |
|
1583 |
return generate_disjoint_copy(sizeof (jint), aligned, not_oop, entry, name); |
|
1584 |
} |
|
1585 |
||
1586 |
// Arguments: |
|
1587 |
// aligned - true => Input and output aligned on a HeapWord == 8-byte boundary |
|
1588 |
// ignored |
|
1589 |
// name - stub name string |
|
1590 |
// |
|
1591 |
// Inputs: |
|
1592 |
// c_rarg0 - source array address |
|
1593 |
// c_rarg1 - destination array address |
|
1594 |
// c_rarg2 - element count, treated as ssize_t, can be zero |
|
1595 |
// |
|
1596 |
// If 'from' and/or 'to' are aligned on 4-byte boundaries, we let |
|
1597 |
// the hardware handle it. The two dwords within qwords that span |
|
1598 |
// cache line boundaries will still be loaded and stored atomicly. |
|
1599 |
// |
|
1600 |
address generate_conjoint_int_copy(bool aligned, address nooverlap_target, |
|
1601 |
address *entry, const char *name, |
|
1602 |
bool dest_uninitialized = false) { |
|
1603 |
const bool not_oop = false; |
|
1604 |
return generate_conjoint_copy(sizeof (jint), aligned, not_oop, nooverlap_target, entry, name); |
|
1605 |
} |
|
1606 |
||
1607 |
||
1608 |
// Arguments: |
|
1609 |
// aligned - true => Input and output aligned on a HeapWord boundary == 8 bytes |
|
1610 |
// ignored |
|
1611 |
// name - stub name string |
|
1612 |
// |
|
1613 |
// Inputs: |
|
1614 |
// c_rarg0 - source array address |
|
1615 |
// c_rarg1 - destination array address |
|
1616 |
// c_rarg2 - element count, treated as size_t, can be zero |
|
1617 |
// |
|
1618 |
// Side Effects: |
|
1619 |
// disjoint_oop_copy_entry or disjoint_long_copy_entry is set to the |
|
1620 |
// no-overlap entry point used by generate_conjoint_long_oop_copy(). |
|
1621 |
// |
|
1622 |
address generate_disjoint_long_copy(bool aligned, address *entry, |
|
1623 |
const char *name, bool dest_uninitialized = false) { |
|
1624 |
const bool not_oop = false; |
|
1625 |
return generate_disjoint_copy(sizeof (jlong), aligned, not_oop, entry, name); |
|
1626 |
} |
|
1627 |
||
1628 |
// Arguments: |
|
1629 |
// aligned - true => Input and output aligned on a HeapWord boundary == 8 bytes |
|
1630 |
// ignored |
|
1631 |
// name - stub name string |
|
1632 |
// |
|
1633 |
// Inputs: |
|
1634 |
// c_rarg0 - source array address |
|
1635 |
// c_rarg1 - destination array address |
|
1636 |
// c_rarg2 - element count, treated as size_t, can be zero |
|
1637 |
// |
|
1638 |
address generate_conjoint_long_copy(bool aligned, |
|
1639 |
address nooverlap_target, address *entry, |
|
1640 |
const char *name, bool dest_uninitialized = false) { |
|
1641 |
const bool not_oop = false; |
|
1642 |
return generate_conjoint_copy(sizeof (jlong), aligned, not_oop, nooverlap_target, entry, name); |
|
1643 |
} |
|
1644 |
||
1645 |
// Arguments: |
|
1646 |
// aligned - true => Input and output aligned on a HeapWord boundary == 8 bytes |
|
1647 |
// ignored |
|
1648 |
// name - stub name string |
|
1649 |
// |
|
1650 |
// Inputs: |
|
1651 |
// c_rarg0 - source array address |
|
1652 |
// c_rarg1 - destination array address |
|
1653 |
// c_rarg2 - element count, treated as size_t, can be zero |
|
1654 |
// |
|
1655 |
// Side Effects: |
|
1656 |
// disjoint_oop_copy_entry or disjoint_long_copy_entry is set to the |
|
1657 |
// no-overlap entry point used by generate_conjoint_long_oop_copy(). |
|
1658 |
// |
|
1659 |
address generate_disjoint_oop_copy(bool aligned, address *entry, |
|
36326
d25af58cfc94
8150045: arraycopy causes segfaults in SATB during garbage collection
aph
parents:
35843
diff
changeset
|
1660 |
const char *name, bool dest_uninitialized) { |
29183 | 1661 |
const bool is_oop = true; |
1662 |
const size_t size = UseCompressedOops ? sizeof (jint) : sizeof (jlong); |
|
36326
d25af58cfc94
8150045: arraycopy causes segfaults in SATB during garbage collection
aph
parents:
35843
diff
changeset
|
1663 |
return generate_disjoint_copy(size, aligned, is_oop, entry, name, dest_uninitialized); |
29183 | 1664 |
} |
1665 |
||
1666 |
// Arguments: |
|
1667 |
// aligned - true => Input and output aligned on a HeapWord boundary == 8 bytes |
|
1668 |
// ignored |
|
1669 |
// name - stub name string |
|
1670 |
// |
|
1671 |
// Inputs: |
|
1672 |
// c_rarg0 - source array address |
|
1673 |
// c_rarg1 - destination array address |
|
1674 |
// c_rarg2 - element count, treated as size_t, can be zero |
|
1675 |
// |
|
1676 |
address generate_conjoint_oop_copy(bool aligned, |
|
1677 |
address nooverlap_target, address *entry, |
|
36326
d25af58cfc94
8150045: arraycopy causes segfaults in SATB during garbage collection
aph
parents:
35843
diff
changeset
|
1678 |
const char *name, bool dest_uninitialized) { |
29183 | 1679 |
const bool is_oop = true; |
1680 |
const size_t size = UseCompressedOops ? sizeof (jint) : sizeof (jlong); |
|
36326
d25af58cfc94
8150045: arraycopy causes segfaults in SATB during garbage collection
aph
parents:
35843
diff
changeset
|
1681 |
return generate_conjoint_copy(size, aligned, is_oop, nooverlap_target, entry, |
d25af58cfc94
8150045: arraycopy causes segfaults in SATB during garbage collection
aph
parents:
35843
diff
changeset
|
1682 |
name, dest_uninitialized); |
29183 | 1683 |
} |
1684 |
||
1685 |
||
1686 |
// Helper for generating a dynamic type check. |
|
53777
9bfeac2ee88a
8219006: AArch64: Register corruption in slow subtype check
aph
parents:
52977
diff
changeset
|
1687 |
// Smashes rscratch1, rscratch2. |
29183 | 1688 |
void generate_type_check(Register sub_klass, |
1689 |
Register super_check_offset, |
|
1690 |
Register super_klass, |
|
1691 |
Label& L_success) { |
|
1692 |
assert_different_registers(sub_klass, super_check_offset, super_klass); |
|
1693 |
||
1694 |
BLOCK_COMMENT("type_check:"); |
|
1695 |
||
1696 |
Label L_miss; |
|
1697 |
||
1698 |
__ check_klass_subtype_fast_path(sub_klass, super_klass, noreg, &L_success, &L_miss, NULL, |
|
1699 |
super_check_offset); |
|
1700 |
__ check_klass_subtype_slow_path(sub_klass, super_klass, noreg, noreg, &L_success, NULL); |
|
1701 |
||
1702 |
// Fall through on failure! |
|
1703 |
__ BIND(L_miss); |
|
1704 |
} |
|
1705 |
||
1706 |
// |
|
1707 |
// Generate checkcasting array copy stub |
|
1708 |
// |
|
1709 |
// Input: |
|
1710 |
// c_rarg0 - source array address |
|
1711 |
// c_rarg1 - destination array address |
|
1712 |
// c_rarg2 - element count, treated as ssize_t, can be zero |
|
1713 |
// c_rarg3 - size_t ckoff (super_check_offset) |
|
1714 |
// c_rarg4 - oop ckval (super_klass) |
|
1715 |
// |
|
1716 |
// Output: |
|
1717 |
// r0 == 0 - success |
|
1718 |
// r0 == -1^K - failure, where K is partial transfer count |
|
1719 |
// |
|
1720 |
address generate_checkcast_copy(const char *name, address *entry, |
|
1721 |
bool dest_uninitialized = false) { |
|
1722 |
||
1723 |
Label L_load_element, L_store_element, L_do_card_marks, L_done, L_done_pop; |
|
1724 |
||
1725 |
// Input registers (after setup_arg_regs) |
|
1726 |
const Register from = c_rarg0; // source array address |
|
1727 |
const Register to = c_rarg1; // destination array address |
|
1728 |
const Register count = c_rarg2; // elementscount |
|
1729 |
const Register ckoff = c_rarg3; // super_check_offset |
|
1730 |
const Register ckval = c_rarg4; // super_klass |
|
1731 |
||
46695
aaaac1d98bc5
8183533: AArch64: redundent registers saving in arraycopy stubs
njian
parents:
46625
diff
changeset
|
1732 |
RegSet wb_pre_saved_regs = RegSet::range(c_rarg0, c_rarg4); |
aaaac1d98bc5
8183533: AArch64: redundent registers saving in arraycopy stubs
njian
parents:
46625
diff
changeset
|
1733 |
RegSet wb_post_saved_regs = RegSet::of(count); |
aaaac1d98bc5
8183533: AArch64: redundent registers saving in arraycopy stubs
njian
parents:
46625
diff
changeset
|
1734 |
|
29183 | 1735 |
// Registers used as temps (r18, r19, r20 are save-on-entry) |
1736 |
const Register count_save = r21; // orig elementscount |
|
1737 |
const Register start_to = r20; // destination array start address |
|
1738 |
const Register copied_oop = r18; // actual oop copied |
|
1739 |
const Register r19_klass = r19; // oop._klass |
|
1740 |
||
1741 |
//--------------------------------------------------------------- |
|
1742 |
// Assembler stub will be used for this call to arraycopy |
|
1743 |
// if the two arrays are subtypes of Object[] but the |
|
1744 |
// destination array type is not equal to or a supertype |
|
1745 |
// of the source type. Each element must be separately |
|
1746 |
// checked. |
|
1747 |
||
1748 |
assert_different_registers(from, to, count, ckoff, ckval, start_to, |
|
1749 |
copied_oop, r19_klass, count_save); |
|
1750 |
||
1751 |
__ align(CodeEntryAlignment); |
|
1752 |
StubCodeMark mark(this, "StubRoutines", name); |
|
1753 |
address start = __ pc(); |
|
1754 |
||
1755 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
|
1756 |
||
1757 |
#ifdef ASSERT |
|
1758 |
// caller guarantees that the arrays really are different |
|
1759 |
// otherwise, we would have to make conjoint checks |
|
1760 |
{ Label L; |
|
1761 |
array_overlap_test(L, TIMES_OOP); |
|
1762 |
__ stop("checkcast_copy within a single array"); |
|
1763 |
__ bind(L); |
|
1764 |
} |
|
1765 |
#endif //ASSERT |
|
1766 |
||
1767 |
// Caller of this entry point must set up the argument registers. |
|
1768 |
if (entry != NULL) { |
|
1769 |
*entry = __ pc(); |
|
1770 |
BLOCK_COMMENT("Entry:"); |
|
1771 |
} |
|
1772 |
||
1773 |
// Empty array: Nothing to do. |
|
1774 |
__ cbz(count, L_done); |
|
1775 |
||
1776 |
__ push(RegSet::of(r18, r19, r20, r21), sp); |
|
1777 |
||
1778 |
#ifdef ASSERT |
|
1779 |
BLOCK_COMMENT("assert consistent ckoff/ckval"); |
|
1780 |
// The ckoff and ckval must be mutually consistent, |
|
1781 |
// even though caller generates both. |
|
1782 |
{ Label L; |
|
1783 |
int sco_offset = in_bytes(Klass::super_check_offset_offset()); |
|
1784 |
__ ldrw(start_to, Address(ckval, sco_offset)); |
|
1785 |
__ cmpw(ckoff, start_to); |
|
1786 |
__ br(Assembler::EQ, L); |
|
1787 |
__ stop("super_check_offset inconsistent"); |
|
1788 |
__ bind(L); |
|
1789 |
} |
|
1790 |
#endif //ASSERT |
|
1791 |
||
54755
de34f4b370b0
8223244: Fix usage of ARRAYCOPY_DISJOINT decorator
rkennke
parents:
54266
diff
changeset
|
1792 |
DecoratorSet decorators = IN_HEAP | IS_ARRAY | ARRAYCOPY_CHECKCAST | ARRAYCOPY_DISJOINT; |
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1793 |
bool is_oop = true; |
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1794 |
if (dest_uninitialized) { |
50728 | 1795 |
decorators |= IS_DEST_UNINITIALIZED; |
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1796 |
} |
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1797 |
|
49754 | 1798 |
BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler(); |
54979
f982c1a6582c
8224187: Refactor arraycopy_prologue to allow ZGC read barriers on arraycopy
smonteith
parents:
54786
diff
changeset
|
1799 |
bs->arraycopy_prologue(_masm, decorators, is_oop, from, to, count, wb_pre_saved_regs); |
36326
d25af58cfc94
8150045: arraycopy causes segfaults in SATB during garbage collection
aph
parents:
35843
diff
changeset
|
1800 |
|
29183 | 1801 |
// save the original count |
1802 |
__ mov(count_save, count); |
|
1803 |
||
1804 |
// Copy from low to high addresses |
|
1805 |
__ mov(start_to, to); // Save destination array start address |
|
1806 |
__ b(L_load_element); |
|
1807 |
||
1808 |
// ======== begin loop ======== |
|
1809 |
// (Loop is rotated; its entry is L_load_element.) |
|
1810 |
// Loop control: |
|
1811 |
// for (; count != 0; count--) { |
|
1812 |
// copied_oop = load_heap_oop(from++); |
|
1813 |
// ... generate_type_check ...; |
|
1814 |
// store_heap_oop(to++, copied_oop); |
|
1815 |
// } |
|
1816 |
__ align(OptoLoopAlignment); |
|
1817 |
||
1818 |
__ BIND(L_store_element); |
|
50110
3d98842c8677
8202714: Create a MacroAssembler::access_load/store_at wrapper for AArch64
rkennke
parents:
49754
diff
changeset
|
1819 |
__ store_heap_oop(__ post(to, UseCompressedOops ? 4 : 8), copied_oop, noreg, noreg, AS_RAW); // store the oop |
29183 | 1820 |
__ sub(count, count, 1); |
1821 |
__ cbz(count, L_do_card_marks); |
|
1822 |
||
1823 |
// ======== loop entry is here ======== |
|
1824 |
__ BIND(L_load_element); |
|
50110
3d98842c8677
8202714: Create a MacroAssembler::access_load/store_at wrapper for AArch64
rkennke
parents:
49754
diff
changeset
|
1825 |
__ load_heap_oop(copied_oop, __ post(from, UseCompressedOops ? 4 : 8), noreg, noreg, AS_RAW); // load the oop |
29183 | 1826 |
__ cbz(copied_oop, L_store_element); |
1827 |
||
1828 |
__ load_klass(r19_klass, copied_oop);// query the object klass |
|
1829 |
generate_type_check(r19_klass, ckoff, ckval, L_store_element); |
|
1830 |
// ======== end loop ======== |
|
1831 |
||
1832 |
// It was a real error; we must depend on the caller to finish the job. |
|
1833 |
// Register count = remaining oops, count_orig = total oops. |
|
1834 |
// Emit GC store barriers for the oops we have copied and report |
|
1835 |
// their number to the caller. |
|
1836 |
||
1837 |
__ subs(count, count_save, count); // K = partially copied oop count |
|
1838 |
__ eon(count, count, zr); // report (-1^K) to caller |
|
1839 |
__ br(Assembler::EQ, L_done_pop); |
|
1840 |
||
1841 |
__ BIND(L_do_card_marks); |
|
54266
7816d989bf21
8216989: CardTableBarrierSetAssembler::gen_write_ref_array_post_barrier() does not check for zero length on AARCH64
dpochepk
parents:
53967
diff
changeset
|
1842 |
bs->arraycopy_epilogue(_masm, decorators, is_oop, start_to, count_save, rscratch1, wb_post_saved_regs); |
29183 | 1843 |
|
1844 |
__ bind(L_done_pop); |
|
1845 |
__ pop(RegSet::of(r18, r19, r20, r21), sp); |
|
1846 |
inc_counter_np(SharedRuntime::_checkcast_array_copy_ctr); |
|
1847 |
||
1848 |
__ bind(L_done); |
|
1849 |
__ mov(r0, count); |
|
1850 |
__ leave(); |
|
1851 |
__ ret(lr); |
|
1852 |
||
1853 |
return start; |
|
1854 |
} |
|
1855 |
||
1856 |
// Perform range checks on the proposed arraycopy. |
|
1857 |
// Kills temp, but nothing else. |
|
1858 |
// Also, clean the sign bits of src_pos and dst_pos. |
|
1859 |
void arraycopy_range_checks(Register src, // source array oop (c_rarg0) |
|
1860 |
Register src_pos, // source position (c_rarg1) |
|
1861 |
Register dst, // destination array oo (c_rarg2) |
|
1862 |
Register dst_pos, // destination position (c_rarg3) |
|
1863 |
Register length, |
|
1864 |
Register temp, |
|
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|
1865 |
Label& L_failed) { |
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|
1866 |
BLOCK_COMMENT("arraycopy_range_checks:"); |
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|
1867 |
|
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|
1868 |
assert_different_registers(rscratch1, temp); |
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|
1869 |
|
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|
1870 |
// if (src_pos + length > arrayOop(src)->length()) FAIL; |
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|
1871 |
__ ldrw(rscratch1, Address(src, arrayOopDesc::length_offset_in_bytes())); |
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|
1872 |
__ addw(temp, length, src_pos); |
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|
1873 |
__ cmpw(temp, rscratch1); |
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|
1874 |
__ br(Assembler::HI, L_failed); |
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|
1875 |
|
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|
1876 |
// if (dst_pos + length > arrayOop(dst)->length()) FAIL; |
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|
1877 |
__ ldrw(rscratch1, Address(dst, arrayOopDesc::length_offset_in_bytes())); |
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|
1878 |
__ addw(temp, length, dst_pos); |
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|
1879 |
__ cmpw(temp, rscratch1); |
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|
1880 |
__ br(Assembler::HI, L_failed); |
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|
1881 |
|
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|
1882 |
// Have to clean up high 32 bits of 'src_pos' and 'dst_pos'. |
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|
1883 |
__ movw(src_pos, src_pos); |
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|
1884 |
__ movw(dst_pos, dst_pos); |
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|
1885 |
|
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|
1886 |
BLOCK_COMMENT("arraycopy_range_checks done"); |
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|
1887 |
} |
29183 | 1888 |
|
1889 |
// These stubs get called from some dumb test routine. |
|
1890 |
// I'll write them properly when they're called from |
|
1891 |
// something that's actually doing something. |
|
1892 |
static void fake_arraycopy_stub(address src, address dst, int count) { |
|
1893 |
assert(count == 0, "huh?"); |
|
1894 |
} |
|
1895 |
||
1896 |
||
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|
1897 |
// |
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|
1898 |
// Generate 'unsafe' array copy stub |
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|
1899 |
// Though just as safe as the other stubs, it takes an unscaled |
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|
1900 |
// size_t argument instead of an element count. |
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|
1901 |
// |
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|
1902 |
// Input: |
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|
1903 |
// c_rarg0 - source array address |
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|
1904 |
// c_rarg1 - destination array address |
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|
1905 |
// c_rarg2 - byte count, treated as ssize_t, can be zero |
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|
1906 |
// |
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|
1907 |
// Examines the alignment of the operands and dispatches |
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|
1908 |
// to a long, int, short, or byte copy loop. |
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|
1909 |
// |
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|
1910 |
address generate_unsafe_copy(const char *name, |
37271
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|
1911 |
address byte_copy_entry, |
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|
1912 |
address short_copy_entry, |
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|
1913 |
address int_copy_entry, |
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|
1914 |
address long_copy_entry) { |
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|
1915 |
Label L_long_aligned, L_int_aligned, L_short_aligned; |
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|
1916 |
Register s = c_rarg0, d = c_rarg1, count = c_rarg2; |
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|
1917 |
|
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|
1918 |
__ align(CodeEntryAlignment); |
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|
1919 |
StubCodeMark mark(this, "StubRoutines", name); |
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|
1920 |
address start = __ pc(); |
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|
1921 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
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|
1922 |
|
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|
1923 |
// bump this on entry, not on exit: |
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|
1924 |
inc_counter_np(SharedRuntime::_unsafe_array_copy_ctr); |
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|
1925 |
|
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|
1926 |
__ orr(rscratch1, s, d); |
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|
1927 |
__ orr(rscratch1, rscratch1, count); |
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|
1928 |
|
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|
1929 |
__ andr(rscratch1, rscratch1, BytesPerLong-1); |
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|
1930 |
__ cbz(rscratch1, L_long_aligned); |
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|
1931 |
__ andr(rscratch1, rscratch1, BytesPerInt-1); |
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|
1932 |
__ cbz(rscratch1, L_int_aligned); |
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|
1933 |
__ tbz(rscratch1, 0, L_short_aligned); |
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|
1934 |
__ b(RuntimeAddress(byte_copy_entry)); |
37271
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|
1935 |
|
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|
1936 |
__ BIND(L_short_aligned); |
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|
1937 |
__ lsr(count, count, LogBytesPerShort); // size => short_count |
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|
1938 |
__ b(RuntimeAddress(short_copy_entry)); |
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|
1939 |
__ BIND(L_int_aligned); |
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changeset
|
1940 |
__ lsr(count, count, LogBytesPerInt); // size => int_count |
95774d8b3cc2
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changeset
|
1941 |
__ b(RuntimeAddress(int_copy_entry)); |
95774d8b3cc2
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changeset
|
1942 |
__ BIND(L_long_aligned); |
95774d8b3cc2
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changeset
|
1943 |
__ lsr(count, count, LogBytesPerLong); // size => long_count |
95774d8b3cc2
8152840: aarch64: improve _unsafe_arraycopy stub routine
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changeset
|
1944 |
__ b(RuntimeAddress(long_copy_entry)); |
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|
1945 |
|
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|
1946 |
return start; |
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|
1947 |
} |
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|
1948 |
|
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|
1949 |
// |
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|
1950 |
// Generate generic array copy stubs |
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|
1951 |
// |
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|
1952 |
// Input: |
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|
1953 |
// c_rarg0 - src oop |
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|
1954 |
// c_rarg1 - src_pos (32-bits) |
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|
1955 |
// c_rarg2 - dst oop |
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|
1956 |
// c_rarg3 - dst_pos (32-bits) |
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|
1957 |
// c_rarg4 - element count (32-bits) |
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|
1958 |
// |
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|
1959 |
// Output: |
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|
1960 |
// r0 == 0 - success |
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|
1961 |
// r0 == -1^K - failure, where K is partial transfer count |
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|
1962 |
// |
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|
1963 |
address generate_generic_copy(const char *name, |
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|
1964 |
address byte_copy_entry, address short_copy_entry, |
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|
1965 |
address int_copy_entry, address oop_copy_entry, |
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|
1966 |
address long_copy_entry, address checkcast_copy_entry) { |
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|
1967 |
|
51756 | 1968 |
Label L_failed, L_objArray; |
35119
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|
1969 |
Label L_copy_bytes, L_copy_shorts, L_copy_ints, L_copy_longs; |
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|
1970 |
|
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|
1971 |
// Input registers |
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|
1972 |
const Register src = c_rarg0; // source array oop |
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|
1973 |
const Register src_pos = c_rarg1; // source position |
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|
1974 |
const Register dst = c_rarg2; // destination array oop |
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|
1975 |
const Register dst_pos = c_rarg3; // destination position |
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|
1976 |
const Register length = c_rarg4; |
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changeset
|
1977 |
|
53777
9bfeac2ee88a
8219006: AArch64: Register corruption in slow subtype check
aph
parents:
52977
diff
changeset
|
1978 |
|
9bfeac2ee88a
8219006: AArch64: Register corruption in slow subtype check
aph
parents:
52977
diff
changeset
|
1979 |
// Registers used as temps |
9bfeac2ee88a
8219006: AArch64: Register corruption in slow subtype check
aph
parents:
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diff
changeset
|
1980 |
const Register dst_klass = c_rarg5; |
9bfeac2ee88a
8219006: AArch64: Register corruption in slow subtype check
aph
parents:
52977
diff
changeset
|
1981 |
|
52977
2e4903f83295
8205421: AARCH64: StubCodeMark should be placed after alignment
dpochepk
parents:
52927
diff
changeset
|
1982 |
__ align(CodeEntryAlignment); |
2e4903f83295
8205421: AARCH64: StubCodeMark should be placed after alignment
dpochepk
parents:
52927
diff
changeset
|
1983 |
|
35119
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changeset
|
1984 |
StubCodeMark mark(this, "StubRoutines", name); |
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changeset
|
1985 |
|
7af8d9f08a25
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changeset
|
1986 |
address start = __ pc(); |
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changeset
|
1987 |
|
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1988 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
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|
1989 |
|
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|
1990 |
// bump this on entry, not on exit: |
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|
1991 |
inc_counter_np(SharedRuntime::_generic_array_copy_ctr); |
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|
1992 |
|
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|
1993 |
//----------------------------------------------------------------------- |
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|
1994 |
// Assembler stub will be used for this call to arraycopy |
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|
1995 |
// if the following conditions are met: |
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|
1996 |
// |
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|
1997 |
// (1) src and dst must not be null. |
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|
1998 |
// (2) src_pos must not be negative. |
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|
1999 |
// (3) dst_pos must not be negative. |
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|
2000 |
// (4) length must not be negative. |
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|
2001 |
// (5) src klass and dst klass should be the same and not NULL. |
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|
2002 |
// (6) src and dst should be arrays. |
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|
2003 |
// (7) src_pos + length must not exceed length of src. |
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|
2004 |
// (8) dst_pos + length must not exceed length of dst. |
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|
2005 |
// |
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|
2006 |
|
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|
2007 |
// if (src == NULL) return -1; |
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|
2008 |
__ cbz(src, L_failed); |
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|
2009 |
|
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|
2010 |
// if (src_pos < 0) return -1; |
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|
2011 |
__ tbnz(src_pos, 31, L_failed); // i.e. sign bit set |
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|
2012 |
|
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|
2013 |
// if (dst == NULL) return -1; |
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|
2014 |
__ cbz(dst, L_failed); |
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|
2015 |
|
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|
2016 |
// if (dst_pos < 0) return -1; |
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|
2017 |
__ tbnz(dst_pos, 31, L_failed); // i.e. sign bit set |
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|
2018 |
|
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|
2019 |
// registers used as temp |
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|
2020 |
const Register scratch_length = r16; // elements count to copy |
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|
2021 |
const Register scratch_src_klass = r17; // array klass |
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|
2022 |
const Register lh = r18; // layout helper |
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|
2023 |
|
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|
2024 |
// if (length < 0) return -1; |
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|
2025 |
__ movw(scratch_length, length); // length (elements count, 32-bits value) |
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|
2026 |
__ tbnz(scratch_length, 31, L_failed); // i.e. sign bit set |
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|
2027 |
|
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|
2028 |
__ load_klass(scratch_src_klass, src); |
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|
2029 |
#ifdef ASSERT |
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|
2030 |
// assert(src->klass() != NULL); |
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|
2031 |
{ |
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|
2032 |
BLOCK_COMMENT("assert klasses not null {"); |
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|
2033 |
Label L1, L2; |
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|
2034 |
__ cbnz(scratch_src_klass, L2); // it is broken if klass is NULL |
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|
2035 |
__ bind(L1); |
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|
2036 |
__ stop("broken null klass"); |
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|
2037 |
__ bind(L2); |
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|
2038 |
__ load_klass(rscratch1, dst); |
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|
2039 |
__ cbz(rscratch1, L1); // this would be broken also |
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|
2040 |
BLOCK_COMMENT("} assert klasses not null done"); |
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|
2041 |
} |
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|
2042 |
#endif |
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|
2043 |
|
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|
2044 |
// Load layout helper (32-bits) |
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|
2045 |
// |
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|
2046 |
// |array_tag| | header_size | element_type | |log2_element_size| |
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|
2047 |
// 32 30 24 16 8 2 0 |
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|
2048 |
// |
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|
2049 |
// array_tag: typeArray = 0x3, objArray = 0x2, non-array = 0x0 |
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|
2050 |
// |
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changeset
|
2051 |
|
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|
2052 |
const int lh_offset = in_bytes(Klass::layout_helper_offset()); |
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changeset
|
2053 |
|
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|
2054 |
// Handle objArrays completely differently... |
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|
2055 |
const jint objArray_lh = Klass::array_layout_helper(T_OBJECT); |
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|
2056 |
__ ldrw(lh, Address(scratch_src_klass, lh_offset)); |
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|
2057 |
__ movw(rscratch1, objArray_lh); |
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|
2058 |
__ eorw(rscratch2, lh, rscratch1); |
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|
2059 |
__ cbzw(rscratch2, L_objArray); |
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changeset
|
2060 |
|
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changeset
|
2061 |
// if (src->klass() != dst->klass()) return -1; |
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changeset
|
2062 |
__ load_klass(rscratch2, dst); |
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changeset
|
2063 |
__ eor(rscratch2, rscratch2, scratch_src_klass); |
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|
2064 |
__ cbnz(rscratch2, L_failed); |
7af8d9f08a25
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changeset
|
2065 |
|
7af8d9f08a25
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changeset
|
2066 |
// if (!src->is_Array()) return -1; |
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changeset
|
2067 |
__ tbz(lh, 31, L_failed); // i.e. (lh >= 0) |
7af8d9f08a25
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parents:
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changeset
|
2068 |
|
7af8d9f08a25
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changeset
|
2069 |
// At this point, it is known to be a typeArray (array_tag 0x3). |
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parents:
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changeset
|
2070 |
#ifdef ASSERT |
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parents:
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changeset
|
2071 |
{ |
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changeset
|
2072 |
BLOCK_COMMENT("assert primitive array {"); |
7af8d9f08a25
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changeset
|
2073 |
Label L; |
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parents:
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diff
changeset
|
2074 |
__ movw(rscratch2, Klass::_lh_array_tag_type_value << Klass::_lh_array_tag_shift); |
7af8d9f08a25
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changeset
|
2075 |
__ cmpw(lh, rscratch2); |
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changeset
|
2076 |
__ br(Assembler::GE, L); |
7af8d9f08a25
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changeset
|
2077 |
__ stop("must be a primitive array"); |
7af8d9f08a25
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changeset
|
2078 |
__ bind(L); |
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changeset
|
2079 |
BLOCK_COMMENT("} assert primitive array done"); |
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changeset
|
2080 |
} |
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parents:
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diff
changeset
|
2081 |
#endif |
7af8d9f08a25
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parents:
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diff
changeset
|
2082 |
|
7af8d9f08a25
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changeset
|
2083 |
arraycopy_range_checks(src, src_pos, dst, dst_pos, scratch_length, |
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changeset
|
2084 |
rscratch2, L_failed); |
7af8d9f08a25
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changeset
|
2085 |
|
7af8d9f08a25
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changeset
|
2086 |
// TypeArrayKlass |
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changeset
|
2087 |
// |
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changeset
|
2088 |
// src_addr = (src + array_header_in_bytes()) + (src_pos << log2elemsize); |
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changeset
|
2089 |
// dst_addr = (dst + array_header_in_bytes()) + (dst_pos << log2elemsize); |
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changeset
|
2090 |
// |
7af8d9f08a25
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parents:
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diff
changeset
|
2091 |
|
7af8d9f08a25
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changeset
|
2092 |
const Register rscratch1_offset = rscratch1; // array offset |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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changeset
|
2093 |
const Register r18_elsize = lh; // element size |
7af8d9f08a25
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parents:
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changeset
|
2094 |
|
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2095 |
__ ubfx(rscratch1_offset, lh, Klass::_lh_header_size_shift, |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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diff
changeset
|
2096 |
exact_log2(Klass::_lh_header_size_mask+1)); // array_offset |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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diff
changeset
|
2097 |
__ add(src, src, rscratch1_offset); // src array offset |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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diff
changeset
|
2098 |
__ add(dst, dst, rscratch1_offset); // dst array offset |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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diff
changeset
|
2099 |
BLOCK_COMMENT("choose copy loop based on element size"); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2100 |
|
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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diff
changeset
|
2101 |
// next registers should be set before the jump to corresponding stub |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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changeset
|
2102 |
const Register from = c_rarg0; // source array address |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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changeset
|
2103 |
const Register to = c_rarg1; // destination array address |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
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diff
changeset
|
2104 |
const Register count = c_rarg2; // elements count |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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diff
changeset
|
2105 |
|
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2106 |
// 'from', 'to', 'count' registers should be set in such order |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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diff
changeset
|
2107 |
// since they are the same as 'src', 'src_pos', 'dst'. |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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diff
changeset
|
2108 |
|
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2109 |
assert(Klass::_lh_log2_element_size_shift == 0, "fix this code"); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2110 |
|
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2111 |
// The possible values of elsize are 0-3, i.e. exact_log2(element |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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diff
changeset
|
2112 |
// size in bytes). We do a simple bitwise binary search. |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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diff
changeset
|
2113 |
__ BIND(L_copy_bytes); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2114 |
__ tbnz(r18_elsize, 1, L_copy_ints); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2115 |
__ tbnz(r18_elsize, 0, L_copy_shorts); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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diff
changeset
|
2116 |
__ lea(from, Address(src, src_pos));// src_addr |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2117 |
__ lea(to, Address(dst, dst_pos));// dst_addr |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2118 |
__ movw(count, scratch_length); // length |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2119 |
__ b(RuntimeAddress(byte_copy_entry)); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2120 |
|
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2121 |
__ BIND(L_copy_shorts); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2122 |
__ lea(from, Address(src, src_pos, Address::lsl(1)));// src_addr |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2123 |
__ lea(to, Address(dst, dst_pos, Address::lsl(1)));// dst_addr |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2124 |
__ movw(count, scratch_length); // length |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2125 |
__ b(RuntimeAddress(short_copy_entry)); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2126 |
|
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2127 |
__ BIND(L_copy_ints); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2128 |
__ tbnz(r18_elsize, 0, L_copy_longs); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2129 |
__ lea(from, Address(src, src_pos, Address::lsl(2)));// src_addr |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2130 |
__ lea(to, Address(dst, dst_pos, Address::lsl(2)));// dst_addr |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2131 |
__ movw(count, scratch_length); // length |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2132 |
__ b(RuntimeAddress(int_copy_entry)); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2133 |
|
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2134 |
__ BIND(L_copy_longs); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2135 |
#ifdef ASSERT |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
33198
diff
changeset
|
2136 |
{ |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
33198
diff
changeset
|
2137 |
BLOCK_COMMENT("assert long copy {"); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2138 |
Label L; |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2139 |
__ andw(lh, lh, Klass::_lh_log2_element_size_mask); // lh -> r18_elsize |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2140 |
__ cmpw(r18_elsize, LogBytesPerLong); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
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diff
changeset
|
2141 |
__ br(Assembler::EQ, L); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2142 |
__ stop("must be long copy, but elsize is wrong"); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
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diff
changeset
|
2143 |
__ bind(L); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2144 |
BLOCK_COMMENT("} assert long copy done"); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2145 |
} |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2146 |
#endif |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2147 |
__ lea(from, Address(src, src_pos, Address::lsl(3)));// src_addr |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2148 |
__ lea(to, Address(dst, dst_pos, Address::lsl(3)));// dst_addr |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2149 |
__ movw(count, scratch_length); // length |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2150 |
__ b(RuntimeAddress(long_copy_entry)); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2151 |
|
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2152 |
// ObjArrayKlass |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2153 |
__ BIND(L_objArray); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
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diff
changeset
|
2154 |
// live at this point: scratch_src_klass, scratch_length, src[_pos], dst[_pos] |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
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diff
changeset
|
2155 |
|
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
33198
diff
changeset
|
2156 |
Label L_plain_copy, L_checkcast_copy; |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
33198
diff
changeset
|
2157 |
// test array classes for subtyping |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2158 |
__ load_klass(r18, dst); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2159 |
__ cmp(scratch_src_klass, r18); // usual case is exact equality |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2160 |
__ br(Assembler::NE, L_checkcast_copy); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2161 |
|
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
33198
diff
changeset
|
2162 |
// Identically typed arrays can be copied without element-wise checks. |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2163 |
arraycopy_range_checks(src, src_pos, dst, dst_pos, scratch_length, |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
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diff
changeset
|
2164 |
rscratch2, L_failed); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2165 |
|
39232
118d17fef4f9
8156731: aarch64: java/util/Arrays/Correct.java fails due to _generic_arraycopy stub routine
fyang
parents:
38233
diff
changeset
|
2166 |
__ lea(from, Address(src, src_pos, Address::lsl(LogBytesPerHeapOop))); |
35119
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
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parents:
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diff
changeset
|
2167 |
__ add(from, from, arrayOopDesc::base_offset_in_bytes(T_OBJECT)); |
39232
118d17fef4f9
8156731: aarch64: java/util/Arrays/Correct.java fails due to _generic_arraycopy stub routine
fyang
parents:
38233
diff
changeset
|
2168 |
__ lea(to, Address(dst, dst_pos, Address::lsl(LogBytesPerHeapOop))); |
35119
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2169 |
__ add(to, to, arrayOopDesc::base_offset_in_bytes(T_OBJECT)); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2170 |
__ movw(count, scratch_length); // length |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2171 |
__ BIND(L_plain_copy); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2172 |
__ b(RuntimeAddress(oop_copy_entry)); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2173 |
|
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2174 |
__ BIND(L_checkcast_copy); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2175 |
// live at this point: scratch_src_klass, scratch_length, r18 (dst_klass) |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2176 |
{ |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2177 |
// Before looking at dst.length, make sure dst is also an objArray. |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2178 |
__ ldrw(rscratch1, Address(r18, lh_offset)); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2179 |
__ movw(rscratch2, objArray_lh); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2180 |
__ eorw(rscratch1, rscratch1, rscratch2); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2181 |
__ cbnzw(rscratch1, L_failed); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2182 |
|
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2183 |
// It is safe to examine both src.length and dst.length. |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2184 |
arraycopy_range_checks(src, src_pos, dst, dst_pos, scratch_length, |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2185 |
r18, L_failed); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2186 |
|
53777
9bfeac2ee88a
8219006: AArch64: Register corruption in slow subtype check
aph
parents:
52977
diff
changeset
|
2187 |
__ load_klass(dst_klass, dst); // reload |
35119
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2188 |
|
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2189 |
// Marshal the base address arguments now, freeing registers. |
39232
118d17fef4f9
8156731: aarch64: java/util/Arrays/Correct.java fails due to _generic_arraycopy stub routine
fyang
parents:
38233
diff
changeset
|
2190 |
__ lea(from, Address(src, src_pos, Address::lsl(LogBytesPerHeapOop))); |
35119
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2191 |
__ add(from, from, arrayOopDesc::base_offset_in_bytes(T_OBJECT)); |
39232
118d17fef4f9
8156731: aarch64: java/util/Arrays/Correct.java fails due to _generic_arraycopy stub routine
fyang
parents:
38233
diff
changeset
|
2192 |
__ lea(to, Address(dst, dst_pos, Address::lsl(LogBytesPerHeapOop))); |
35119
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2193 |
__ add(to, to, arrayOopDesc::base_offset_in_bytes(T_OBJECT)); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2194 |
__ movw(count, length); // length (reloaded) |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2195 |
Register sco_temp = c_rarg3; // this register is free now |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2196 |
assert_different_registers(from, to, count, sco_temp, |
53777
9bfeac2ee88a
8219006: AArch64: Register corruption in slow subtype check
aph
parents:
52977
diff
changeset
|
2197 |
dst_klass, scratch_src_klass); |
35119
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2198 |
// assert_clean_int(count, sco_temp); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2199 |
|
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2200 |
// Generate the type check. |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2201 |
const int sco_offset = in_bytes(Klass::super_check_offset_offset()); |
53777
9bfeac2ee88a
8219006: AArch64: Register corruption in slow subtype check
aph
parents:
52977
diff
changeset
|
2202 |
__ ldrw(sco_temp, Address(dst_klass, sco_offset)); |
9bfeac2ee88a
8219006: AArch64: Register corruption in slow subtype check
aph
parents:
52977
diff
changeset
|
2203 |
|
9bfeac2ee88a
8219006: AArch64: Register corruption in slow subtype check
aph
parents:
52977
diff
changeset
|
2204 |
// Smashes rscratch1, rscratch2 |
9bfeac2ee88a
8219006: AArch64: Register corruption in slow subtype check
aph
parents:
52977
diff
changeset
|
2205 |
generate_type_check(scratch_src_klass, sco_temp, dst_klass, L_plain_copy); |
35119
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2206 |
|
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2207 |
// Fetch destination element klass from the ObjArrayKlass header. |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2208 |
int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset()); |
53777
9bfeac2ee88a
8219006: AArch64: Register corruption in slow subtype check
aph
parents:
52977
diff
changeset
|
2209 |
__ ldr(dst_klass, Address(dst_klass, ek_offset)); |
9bfeac2ee88a
8219006: AArch64: Register corruption in slow subtype check
aph
parents:
52977
diff
changeset
|
2210 |
__ ldrw(sco_temp, Address(dst_klass, sco_offset)); |
35119
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2211 |
|
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2212 |
// the checkcast_copy loop needs two extra arguments: |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2213 |
assert(c_rarg3 == sco_temp, "#3 already in place"); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2214 |
// Set up arguments for checkcast_copy_entry. |
53777
9bfeac2ee88a
8219006: AArch64: Register corruption in slow subtype check
aph
parents:
52977
diff
changeset
|
2215 |
__ mov(c_rarg4, dst_klass); // dst.klass.element_klass |
35119
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2216 |
__ b(RuntimeAddress(checkcast_copy_entry)); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2217 |
} |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2218 |
|
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2219 |
__ BIND(L_failed); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2220 |
__ mov(r0, -1); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2221 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2222 |
__ ret(lr); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2223 |
|
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2224 |
return start; |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2225 |
} |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2226 |
|
38028 | 2227 |
// |
2228 |
// Generate stub for array fill. If "aligned" is true, the |
|
2229 |
// "to" address is assumed to be heapword aligned. |
|
2230 |
// |
|
2231 |
// Arguments for generated stub: |
|
2232 |
// to: c_rarg0 |
|
2233 |
// value: c_rarg1 |
|
2234 |
// count: c_rarg2 treated as signed |
|
2235 |
// |
|
2236 |
address generate_fill(BasicType t, bool aligned, const char *name) { |
|
2237 |
__ align(CodeEntryAlignment); |
|
2238 |
StubCodeMark mark(this, "StubRoutines", name); |
|
2239 |
address start = __ pc(); |
|
2240 |
||
2241 |
BLOCK_COMMENT("Entry:"); |
|
2242 |
||
2243 |
const Register to = c_rarg0; // source array address |
|
2244 |
const Register value = c_rarg1; // value |
|
2245 |
const Register count = c_rarg2; // elements count |
|
38233
9f784c50b967
8155967: aarch64: fix register usage in block zeroing
enevill
parents:
38225
diff
changeset
|
2246 |
|
9f784c50b967
8155967: aarch64: fix register usage in block zeroing
enevill
parents:
38225
diff
changeset
|
2247 |
const Register bz_base = r10; // base for block_zero routine |
9f784c50b967
8155967: aarch64: fix register usage in block zeroing
enevill
parents:
38225
diff
changeset
|
2248 |
const Register cnt_words = r11; // temp register |
38028 | 2249 |
|
2250 |
__ enter(); |
|
2251 |
||
2252 |
Label L_fill_elements, L_exit1; |
|
2253 |
||
2254 |
int shift = -1; |
|
2255 |
switch (t) { |
|
2256 |
case T_BYTE: |
|
2257 |
shift = 0; |
|
2258 |
__ cmpw(count, 8 >> shift); // Short arrays (< 8 bytes) fill by element |
|
2259 |
__ bfi(value, value, 8, 8); // 8 bit -> 16 bit |
|
2260 |
__ bfi(value, value, 16, 16); // 16 bit -> 32 bit |
|
2261 |
__ br(Assembler::LO, L_fill_elements); |
|
2262 |
break; |
|
2263 |
case T_SHORT: |
|
2264 |
shift = 1; |
|
2265 |
__ cmpw(count, 8 >> shift); // Short arrays (< 8 bytes) fill by element |
|
2266 |
__ bfi(value, value, 16, 16); // 16 bit -> 32 bit |
|
2267 |
__ br(Assembler::LO, L_fill_elements); |
|
2268 |
break; |
|
2269 |
case T_INT: |
|
2270 |
shift = 2; |
|
2271 |
__ cmpw(count, 8 >> shift); // Short arrays (< 8 bytes) fill by element |
|
2272 |
__ br(Assembler::LO, L_fill_elements); |
|
2273 |
break; |
|
2274 |
default: ShouldNotReachHere(); |
|
2275 |
} |
|
2276 |
||
2277 |
// Align source address at 8 bytes address boundary. |
|
2278 |
Label L_skip_align1, L_skip_align2, L_skip_align4; |
|
2279 |
if (!aligned) { |
|
2280 |
switch (t) { |
|
2281 |
case T_BYTE: |
|
2282 |
// One byte misalignment happens only for byte arrays. |
|
2283 |
__ tbz(to, 0, L_skip_align1); |
|
2284 |
__ strb(value, Address(__ post(to, 1))); |
|
2285 |
__ subw(count, count, 1); |
|
2286 |
__ bind(L_skip_align1); |
|
2287 |
// Fallthrough |
|
2288 |
case T_SHORT: |
|
2289 |
// Two bytes misalignment happens only for byte and short (char) arrays. |
|
2290 |
__ tbz(to, 1, L_skip_align2); |
|
2291 |
__ strh(value, Address(__ post(to, 2))); |
|
2292 |
__ subw(count, count, 2 >> shift); |
|
2293 |
__ bind(L_skip_align2); |
|
2294 |
// Fallthrough |
|
2295 |
case T_INT: |
|
2296 |
// Align to 8 bytes, we know we are 4 byte aligned to start. |
|
2297 |
__ tbz(to, 2, L_skip_align4); |
|
2298 |
__ strw(value, Address(__ post(to, 4))); |
|
2299 |
__ subw(count, count, 4 >> shift); |
|
2300 |
__ bind(L_skip_align4); |
|
2301 |
break; |
|
2302 |
default: ShouldNotReachHere(); |
|
2303 |
} |
|
2304 |
} |
|
2305 |
||
2306 |
// |
|
2307 |
// Fill large chunks |
|
2308 |
// |
|
2309 |
__ lsrw(cnt_words, count, 3 - shift); // number of words |
|
2310 |
__ bfi(value, value, 32, 32); // 32 bit -> 64 bit |
|
2311 |
__ subw(count, count, cnt_words, Assembler::LSL, 3 - shift); |
|
38143 | 2312 |
if (UseBlockZeroing) { |
2313 |
Label non_block_zeroing, rest; |
|
45054 | 2314 |
// If the fill value is zero we can use the fast zero_words(). |
2315 |
__ cbnz(value, non_block_zeroing); |
|
38233
9f784c50b967
8155967: aarch64: fix register usage in block zeroing
enevill
parents:
38225
diff
changeset
|
2316 |
__ mov(bz_base, to); |
45054 | 2317 |
__ add(to, to, cnt_words, Assembler::LSL, LogBytesPerWord); |
2318 |
__ zero_words(bz_base, cnt_words); |
|
38143 | 2319 |
__ b(rest); |
2320 |
__ bind(non_block_zeroing); |
|
2321 |
__ fill_words(to, cnt_words, value); |
|
2322 |
__ bind(rest); |
|
45054 | 2323 |
} else { |
38143 | 2324 |
__ fill_words(to, cnt_words, value); |
2325 |
} |
|
38028 | 2326 |
|
2327 |
// Remaining count is less than 8 bytes. Fill it by a single store. |
|
2328 |
// Note that the total length is no less than 8 bytes. |
|
2329 |
if (t == T_BYTE || t == T_SHORT) { |
|
2330 |
Label L_exit1; |
|
2331 |
__ cbzw(count, L_exit1); |
|
2332 |
__ add(to, to, count, Assembler::LSL, shift); // points to the end |
|
2333 |
__ str(value, Address(to, -8)); // overwrite some elements |
|
2334 |
__ bind(L_exit1); |
|
2335 |
__ leave(); |
|
2336 |
__ ret(lr); |
|
2337 |
} |
|
2338 |
||
2339 |
// Handle copies less than 8 bytes. |
|
2340 |
Label L_fill_2, L_fill_4, L_exit2; |
|
2341 |
__ bind(L_fill_elements); |
|
2342 |
switch (t) { |
|
2343 |
case T_BYTE: |
|
2344 |
__ tbz(count, 0, L_fill_2); |
|
2345 |
__ strb(value, Address(__ post(to, 1))); |
|
2346 |
__ bind(L_fill_2); |
|
2347 |
__ tbz(count, 1, L_fill_4); |
|
2348 |
__ strh(value, Address(__ post(to, 2))); |
|
2349 |
__ bind(L_fill_4); |
|
2350 |
__ tbz(count, 2, L_exit2); |
|
2351 |
__ strw(value, Address(to)); |
|
2352 |
break; |
|
2353 |
case T_SHORT: |
|
2354 |
__ tbz(count, 0, L_fill_4); |
|
2355 |
__ strh(value, Address(__ post(to, 2))); |
|
2356 |
__ bind(L_fill_4); |
|
2357 |
__ tbz(count, 1, L_exit2); |
|
2358 |
__ strw(value, Address(to)); |
|
2359 |
break; |
|
2360 |
case T_INT: |
|
2361 |
__ cbzw(count, L_exit2); |
|
2362 |
__ strw(value, Address(to)); |
|
2363 |
break; |
|
2364 |
default: ShouldNotReachHere(); |
|
2365 |
} |
|
2366 |
__ bind(L_exit2); |
|
2367 |
__ leave(); |
|
2368 |
__ ret(lr); |
|
2369 |
return start; |
|
2370 |
} |
|
2371 |
||
29183 | 2372 |
void generate_arraycopy_stubs() { |
2373 |
address entry; |
|
2374 |
address entry_jbyte_arraycopy; |
|
2375 |
address entry_jshort_arraycopy; |
|
2376 |
address entry_jint_arraycopy; |
|
2377 |
address entry_oop_arraycopy; |
|
2378 |
address entry_jlong_arraycopy; |
|
2379 |
address entry_checkcast_arraycopy; |
|
2380 |
||
2381 |
generate_copy_longs(copy_f, r0, r1, rscratch2, copy_forwards); |
|
2382 |
generate_copy_longs(copy_b, r0, r1, rscratch2, copy_backwards); |
|
2383 |
||
45054 | 2384 |
StubRoutines::aarch64::_zero_blocks = generate_zero_blocks(); |
38143 | 2385 |
|
29183 | 2386 |
//*** jbyte |
2387 |
// Always need aligned and unaligned versions |
|
2388 |
StubRoutines::_jbyte_disjoint_arraycopy = generate_disjoint_byte_copy(false, &entry, |
|
2389 |
"jbyte_disjoint_arraycopy"); |
|
2390 |
StubRoutines::_jbyte_arraycopy = generate_conjoint_byte_copy(false, entry, |
|
2391 |
&entry_jbyte_arraycopy, |
|
2392 |
"jbyte_arraycopy"); |
|
2393 |
StubRoutines::_arrayof_jbyte_disjoint_arraycopy = generate_disjoint_byte_copy(true, &entry, |
|
2394 |
"arrayof_jbyte_disjoint_arraycopy"); |
|
2395 |
StubRoutines::_arrayof_jbyte_arraycopy = generate_conjoint_byte_copy(true, entry, NULL, |
|
2396 |
"arrayof_jbyte_arraycopy"); |
|
2397 |
||
2398 |
//*** jshort |
|
2399 |
// Always need aligned and unaligned versions |
|
2400 |
StubRoutines::_jshort_disjoint_arraycopy = generate_disjoint_short_copy(false, &entry, |
|
2401 |
"jshort_disjoint_arraycopy"); |
|
2402 |
StubRoutines::_jshort_arraycopy = generate_conjoint_short_copy(false, entry, |
|
2403 |
&entry_jshort_arraycopy, |
|
2404 |
"jshort_arraycopy"); |
|
2405 |
StubRoutines::_arrayof_jshort_disjoint_arraycopy = generate_disjoint_short_copy(true, &entry, |
|
2406 |
"arrayof_jshort_disjoint_arraycopy"); |
|
2407 |
StubRoutines::_arrayof_jshort_arraycopy = generate_conjoint_short_copy(true, entry, NULL, |
|
2408 |
"arrayof_jshort_arraycopy"); |
|
2409 |
||
2410 |
//*** jint |
|
2411 |
// Aligned versions |
|
2412 |
StubRoutines::_arrayof_jint_disjoint_arraycopy = generate_disjoint_int_copy(true, &entry, |
|
2413 |
"arrayof_jint_disjoint_arraycopy"); |
|
2414 |
StubRoutines::_arrayof_jint_arraycopy = generate_conjoint_int_copy(true, entry, &entry_jint_arraycopy, |
|
2415 |
"arrayof_jint_arraycopy"); |
|
2416 |
// In 64 bit we need both aligned and unaligned versions of jint arraycopy. |
|
2417 |
// entry_jint_arraycopy always points to the unaligned version |
|
2418 |
StubRoutines::_jint_disjoint_arraycopy = generate_disjoint_int_copy(false, &entry, |
|
2419 |
"jint_disjoint_arraycopy"); |
|
2420 |
StubRoutines::_jint_arraycopy = generate_conjoint_int_copy(false, entry, |
|
2421 |
&entry_jint_arraycopy, |
|
2422 |
"jint_arraycopy"); |
|
2423 |
||
2424 |
//*** jlong |
|
2425 |
// It is always aligned |
|
2426 |
StubRoutines::_arrayof_jlong_disjoint_arraycopy = generate_disjoint_long_copy(true, &entry, |
|
2427 |
"arrayof_jlong_disjoint_arraycopy"); |
|
2428 |
StubRoutines::_arrayof_jlong_arraycopy = generate_conjoint_long_copy(true, entry, &entry_jlong_arraycopy, |
|
2429 |
"arrayof_jlong_arraycopy"); |
|
2430 |
StubRoutines::_jlong_disjoint_arraycopy = StubRoutines::_arrayof_jlong_disjoint_arraycopy; |
|
2431 |
StubRoutines::_jlong_arraycopy = StubRoutines::_arrayof_jlong_arraycopy; |
|
2432 |
||
2433 |
//*** oops |
|
2434 |
{ |
|
2435 |
// With compressed oops we need unaligned versions; notice that |
|
2436 |
// we overwrite entry_oop_arraycopy. |
|
2437 |
bool aligned = !UseCompressedOops; |
|
2438 |
||
2439 |
StubRoutines::_arrayof_oop_disjoint_arraycopy |
|
36326
d25af58cfc94
8150045: arraycopy causes segfaults in SATB during garbage collection
aph
parents:
35843
diff
changeset
|
2440 |
= generate_disjoint_oop_copy(aligned, &entry, "arrayof_oop_disjoint_arraycopy", |
d25af58cfc94
8150045: arraycopy causes segfaults in SATB during garbage collection
aph
parents:
35843
diff
changeset
|
2441 |
/*dest_uninitialized*/false); |
29183 | 2442 |
StubRoutines::_arrayof_oop_arraycopy |
36326
d25af58cfc94
8150045: arraycopy causes segfaults in SATB during garbage collection
aph
parents:
35843
diff
changeset
|
2443 |
= generate_conjoint_oop_copy(aligned, entry, &entry_oop_arraycopy, "arrayof_oop_arraycopy", |
d25af58cfc94
8150045: arraycopy causes segfaults in SATB during garbage collection
aph
parents:
35843
diff
changeset
|
2444 |
/*dest_uninitialized*/false); |
29183 | 2445 |
// Aligned versions without pre-barriers |
2446 |
StubRoutines::_arrayof_oop_disjoint_arraycopy_uninit |
|
2447 |
= generate_disjoint_oop_copy(aligned, &entry, "arrayof_oop_disjoint_arraycopy_uninit", |
|
2448 |
/*dest_uninitialized*/true); |
|
2449 |
StubRoutines::_arrayof_oop_arraycopy_uninit |
|
2450 |
= generate_conjoint_oop_copy(aligned, entry, NULL, "arrayof_oop_arraycopy_uninit", |
|
2451 |
/*dest_uninitialized*/true); |
|
2452 |
} |
|
2453 |
||
2454 |
StubRoutines::_oop_disjoint_arraycopy = StubRoutines::_arrayof_oop_disjoint_arraycopy; |
|
2455 |
StubRoutines::_oop_arraycopy = StubRoutines::_arrayof_oop_arraycopy; |
|
2456 |
StubRoutines::_oop_disjoint_arraycopy_uninit = StubRoutines::_arrayof_oop_disjoint_arraycopy_uninit; |
|
2457 |
StubRoutines::_oop_arraycopy_uninit = StubRoutines::_arrayof_oop_arraycopy_uninit; |
|
2458 |
||
2459 |
StubRoutines::_checkcast_arraycopy = generate_checkcast_copy("checkcast_arraycopy", &entry_checkcast_arraycopy); |
|
2460 |
StubRoutines::_checkcast_arraycopy_uninit = generate_checkcast_copy("checkcast_arraycopy_uninit", NULL, |
|
2461 |
/*dest_uninitialized*/true); |
|
35119
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2462 |
|
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2463 |
StubRoutines::_unsafe_arraycopy = generate_unsafe_copy("unsafe_arraycopy", |
37271
95774d8b3cc2
8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents:
36595
diff
changeset
|
2464 |
entry_jbyte_arraycopy, |
95774d8b3cc2
8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents:
36595
diff
changeset
|
2465 |
entry_jshort_arraycopy, |
95774d8b3cc2
8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents:
36595
diff
changeset
|
2466 |
entry_jint_arraycopy, |
95774d8b3cc2
8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents:
36595
diff
changeset
|
2467 |
entry_jlong_arraycopy); |
35119
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2468 |
|
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2469 |
StubRoutines::_generic_arraycopy = generate_generic_copy("generic_arraycopy", |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2470 |
entry_jbyte_arraycopy, |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2471 |
entry_jshort_arraycopy, |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2472 |
entry_jint_arraycopy, |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2473 |
entry_oop_arraycopy, |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2474 |
entry_jlong_arraycopy, |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2475 |
entry_checkcast_arraycopy); |
7af8d9f08a25
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents:
33198
diff
changeset
|
2476 |
|
38028 | 2477 |
StubRoutines::_jbyte_fill = generate_fill(T_BYTE, false, "jbyte_fill"); |
2478 |
StubRoutines::_jshort_fill = generate_fill(T_SHORT, false, "jshort_fill"); |
|
2479 |
StubRoutines::_jint_fill = generate_fill(T_INT, false, "jint_fill"); |
|
2480 |
StubRoutines::_arrayof_jbyte_fill = generate_fill(T_BYTE, true, "arrayof_jbyte_fill"); |
|
2481 |
StubRoutines::_arrayof_jshort_fill = generate_fill(T_SHORT, true, "arrayof_jshort_fill"); |
|
2482 |
StubRoutines::_arrayof_jint_fill = generate_fill(T_INT, true, "arrayof_jint_fill"); |
|
29183 | 2483 |
} |
2484 |
||
2485 |
void generate_math_stubs() { Unimplemented(); } |
|
2486 |
||
2487 |
// Arguments: |
|
2488 |
// |
|
2489 |
// Inputs: |
|
2490 |
// c_rarg0 - source byte array address |
|
2491 |
// c_rarg1 - destination byte array address |
|
2492 |
// c_rarg2 - K (key) in little endian int array |
|
2493 |
// |
|
2494 |
address generate_aescrypt_encryptBlock() { |
|
2495 |
__ align(CodeEntryAlignment); |
|
2496 |
StubCodeMark mark(this, "StubRoutines", "aescrypt_encryptBlock"); |
|
2497 |
||
2498 |
Label L_doLast; |
|
2499 |
||
2500 |
const Register from = c_rarg0; // source array address |
|
2501 |
const Register to = c_rarg1; // destination array address |
|
2502 |
const Register key = c_rarg2; // key array address |
|
2503 |
const Register keylen = rscratch1; |
|
2504 |
||
2505 |
address start = __ pc(); |
|
2506 |
__ enter(); |
|
2507 |
||
2508 |
__ ldrw(keylen, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT))); |
|
2509 |
||
2510 |
__ ld1(v0, __ T16B, from); // get 16 bytes of input |
|
2511 |
||
2512 |
__ ld1(v1, v2, v3, v4, __ T16B, __ post(key, 64)); |
|
2513 |
__ rev32(v1, __ T16B, v1); |
|
2514 |
__ rev32(v2, __ T16B, v2); |
|
2515 |
__ rev32(v3, __ T16B, v3); |
|
2516 |
__ rev32(v4, __ T16B, v4); |
|
2517 |
__ aese(v0, v1); |
|
2518 |
__ aesmc(v0, v0); |
|
2519 |
__ aese(v0, v2); |
|
2520 |
__ aesmc(v0, v0); |
|
2521 |
__ aese(v0, v3); |
|
2522 |
__ aesmc(v0, v0); |
|
2523 |
__ aese(v0, v4); |
|
2524 |
__ aesmc(v0, v0); |
|
2525 |
||
2526 |
__ ld1(v1, v2, v3, v4, __ T16B, __ post(key, 64)); |
|
2527 |
__ rev32(v1, __ T16B, v1); |
|
2528 |
__ rev32(v2, __ T16B, v2); |
|
2529 |
__ rev32(v3, __ T16B, v3); |
|
2530 |
__ rev32(v4, __ T16B, v4); |
|
2531 |
__ aese(v0, v1); |
|
2532 |
__ aesmc(v0, v0); |
|
2533 |
__ aese(v0, v2); |
|
2534 |
__ aesmc(v0, v0); |
|
2535 |
__ aese(v0, v3); |
|
2536 |
__ aesmc(v0, v0); |
|
2537 |
__ aese(v0, v4); |
|
2538 |
__ aesmc(v0, v0); |
|
2539 |
||
2540 |
__ ld1(v1, v2, __ T16B, __ post(key, 32)); |
|
2541 |
__ rev32(v1, __ T16B, v1); |
|
2542 |
__ rev32(v2, __ T16B, v2); |
|
2543 |
||
2544 |
__ cmpw(keylen, 44); |
|
2545 |
__ br(Assembler::EQ, L_doLast); |
|
2546 |
||
2547 |
__ aese(v0, v1); |
|
2548 |
__ aesmc(v0, v0); |
|
2549 |
__ aese(v0, v2); |
|
2550 |
__ aesmc(v0, v0); |
|
2551 |
||
2552 |
__ ld1(v1, v2, __ T16B, __ post(key, 32)); |
|
2553 |
__ rev32(v1, __ T16B, v1); |
|
2554 |
__ rev32(v2, __ T16B, v2); |
|
2555 |
||
2556 |
__ cmpw(keylen, 52); |
|
2557 |
__ br(Assembler::EQ, L_doLast); |
|
2558 |
||
2559 |
__ aese(v0, v1); |
|
2560 |
__ aesmc(v0, v0); |
|
2561 |
__ aese(v0, v2); |
|
2562 |
__ aesmc(v0, v0); |
|
2563 |
||
2564 |
__ ld1(v1, v2, __ T16B, __ post(key, 32)); |
|
2565 |
__ rev32(v1, __ T16B, v1); |
|
2566 |
__ rev32(v2, __ T16B, v2); |
|
2567 |
||
2568 |
__ BIND(L_doLast); |
|
2569 |
||
2570 |
__ aese(v0, v1); |
|
2571 |
__ aesmc(v0, v0); |
|
2572 |
__ aese(v0, v2); |
|
2573 |
||
2574 |
__ ld1(v1, __ T16B, key); |
|
2575 |
__ rev32(v1, __ T16B, v1); |
|
2576 |
__ eor(v0, __ T16B, v0, v1); |
|
2577 |
||
2578 |
__ st1(v0, __ T16B, to); |
|
2579 |
||
2580 |
__ mov(r0, 0); |
|
2581 |
||
2582 |
__ leave(); |
|
2583 |
__ ret(lr); |
|
2584 |
||
2585 |
return start; |
|
2586 |
} |
|
2587 |
||
2588 |
// Arguments: |
|
2589 |
// |
|
2590 |
// Inputs: |
|
2591 |
// c_rarg0 - source byte array address |
|
2592 |
// c_rarg1 - destination byte array address |
|
2593 |
// c_rarg2 - K (key) in little endian int array |
|
2594 |
// |
|
2595 |
address generate_aescrypt_decryptBlock() { |
|
2596 |
assert(UseAES, "need AES instructions and misaligned SSE support"); |
|
2597 |
__ align(CodeEntryAlignment); |
|
2598 |
StubCodeMark mark(this, "StubRoutines", "aescrypt_decryptBlock"); |
|
2599 |
Label L_doLast; |
|
2600 |
||
2601 |
const Register from = c_rarg0; // source array address |
|
2602 |
const Register to = c_rarg1; // destination array address |
|
2603 |
const Register key = c_rarg2; // key array address |
|
2604 |
const Register keylen = rscratch1; |
|
2605 |
||
2606 |
address start = __ pc(); |
|
2607 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
|
2608 |
||
2609 |
__ ldrw(keylen, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT))); |
|
2610 |
||
2611 |
__ ld1(v0, __ T16B, from); // get 16 bytes of input |
|
2612 |
||
2613 |
__ ld1(v5, __ T16B, __ post(key, 16)); |
|
2614 |
__ rev32(v5, __ T16B, v5); |
|
2615 |
||
2616 |
__ ld1(v1, v2, v3, v4, __ T16B, __ post(key, 64)); |
|
2617 |
__ rev32(v1, __ T16B, v1); |
|
2618 |
__ rev32(v2, __ T16B, v2); |
|
2619 |
__ rev32(v3, __ T16B, v3); |
|
2620 |
__ rev32(v4, __ T16B, v4); |
|
2621 |
__ aesd(v0, v1); |
|
2622 |
__ aesimc(v0, v0); |
|
2623 |
__ aesd(v0, v2); |
|
2624 |
__ aesimc(v0, v0); |
|
2625 |
__ aesd(v0, v3); |
|
2626 |
__ aesimc(v0, v0); |
|
2627 |
__ aesd(v0, v4); |
|
2628 |
__ aesimc(v0, v0); |
|
2629 |
||
2630 |
__ ld1(v1, v2, v3, v4, __ T16B, __ post(key, 64)); |
|
2631 |
__ rev32(v1, __ T16B, v1); |
|
2632 |
__ rev32(v2, __ T16B, v2); |
|
2633 |
__ rev32(v3, __ T16B, v3); |
|
2634 |
__ rev32(v4, __ T16B, v4); |
|
2635 |
__ aesd(v0, v1); |
|
2636 |
__ aesimc(v0, v0); |
|
2637 |
__ aesd(v0, v2); |
|
2638 |
__ aesimc(v0, v0); |
|
2639 |
__ aesd(v0, v3); |
|
2640 |
__ aesimc(v0, v0); |
|
2641 |
__ aesd(v0, v4); |
|
2642 |
__ aesimc(v0, v0); |
|
2643 |
||
2644 |
__ ld1(v1, v2, __ T16B, __ post(key, 32)); |
|
2645 |
__ rev32(v1, __ T16B, v1); |
|
2646 |
__ rev32(v2, __ T16B, v2); |
|
2647 |
||
2648 |
__ cmpw(keylen, 44); |
|
2649 |
__ br(Assembler::EQ, L_doLast); |
|
2650 |
||
2651 |
__ aesd(v0, v1); |
|
2652 |
__ aesimc(v0, v0); |
|
2653 |
__ aesd(v0, v2); |
|
2654 |
__ aesimc(v0, v0); |
|
2655 |
||
2656 |
__ ld1(v1, v2, __ T16B, __ post(key, 32)); |
|
2657 |
__ rev32(v1, __ T16B, v1); |
|
2658 |
__ rev32(v2, __ T16B, v2); |
|
2659 |
||
2660 |
__ cmpw(keylen, 52); |
|
2661 |
__ br(Assembler::EQ, L_doLast); |
|
2662 |
||
2663 |
__ aesd(v0, v1); |
|
2664 |
__ aesimc(v0, v0); |
|
2665 |
__ aesd(v0, v2); |
|
2666 |
__ aesimc(v0, v0); |
|
2667 |
||
2668 |
__ ld1(v1, v2, __ T16B, __ post(key, 32)); |
|
2669 |
__ rev32(v1, __ T16B, v1); |
|
2670 |
__ rev32(v2, __ T16B, v2); |
|
2671 |
||
2672 |
__ BIND(L_doLast); |
|
2673 |
||
2674 |
__ aesd(v0, v1); |
|
2675 |
__ aesimc(v0, v0); |
|
2676 |
__ aesd(v0, v2); |
|
2677 |
||
2678 |
__ eor(v0, __ T16B, v0, v5); |
|
2679 |
||
2680 |
__ st1(v0, __ T16B, to); |
|
2681 |
||
2682 |
__ mov(r0, 0); |
|
2683 |
||
2684 |
__ leave(); |
|
2685 |
__ ret(lr); |
|
2686 |
||
2687 |
return start; |
|
2688 |
} |
|
2689 |
||
2690 |
// Arguments: |
|
2691 |
// |
|
2692 |
// Inputs: |
|
2693 |
// c_rarg0 - source byte array address |
|
2694 |
// c_rarg1 - destination byte array address |
|
2695 |
// c_rarg2 - K (key) in little endian int array |
|
2696 |
// c_rarg3 - r vector byte array address |
|
2697 |
// c_rarg4 - input length |
|
2698 |
// |
|
2699 |
// Output: |
|
2700 |
// x0 - input length |
|
2701 |
// |
|
2702 |
address generate_cipherBlockChaining_encryptAESCrypt() { |
|
2703 |
assert(UseAES, "need AES instructions and misaligned SSE support"); |
|
2704 |
__ align(CodeEntryAlignment); |
|
2705 |
StubCodeMark mark(this, "StubRoutines", "cipherBlockChaining_encryptAESCrypt"); |
|
2706 |
||
42577
c47121f6307d
8169529: AArch64: Revert old JDK-8167595 changes after JDK-8159035 fix is pushed
rraghavan
parents:
41729
diff
changeset
|
2707 |
Label L_loadkeys_44, L_loadkeys_52, L_aes_loop, L_rounds_44, L_rounds_52; |
29183 | 2708 |
|
2709 |
const Register from = c_rarg0; // source array address |
|
2710 |
const Register to = c_rarg1; // destination array address |
|
2711 |
const Register key = c_rarg2; // key array address |
|
2712 |
const Register rvec = c_rarg3; // r byte array initialized from initvector array address |
|
2713 |
// and left with the results of the last encryption block |
|
2714 |
const Register len_reg = c_rarg4; // src len (must be multiple of blocksize 16) |
|
2715 |
const Register keylen = rscratch1; |
|
2716 |
||
2717 |
address start = __ pc(); |
|
41729
d852f04fa9df
8167595: AArch64: SEGV in stub code cipherBlockChaining_decryptAESCrypt
aph
parents:
40643
diff
changeset
|
2718 |
|
29183 | 2719 |
__ enter(); |
2720 |
||
42577
c47121f6307d
8169529: AArch64: Revert old JDK-8167595 changes after JDK-8159035 fix is pushed
rraghavan
parents:
41729
diff
changeset
|
2721 |
__ movw(rscratch2, len_reg); |
41729
d852f04fa9df
8167595: AArch64: SEGV in stub code cipherBlockChaining_decryptAESCrypt
aph
parents:
40643
diff
changeset
|
2722 |
|
29183 | 2723 |
__ ldrw(keylen, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT))); |
2724 |
||
2725 |
__ ld1(v0, __ T16B, rvec); |
|
2726 |
||
2727 |
__ cmpw(keylen, 52); |
|
2728 |
__ br(Assembler::CC, L_loadkeys_44); |
|
2729 |
__ br(Assembler::EQ, L_loadkeys_52); |
|
2730 |
||
2731 |
__ ld1(v17, v18, __ T16B, __ post(key, 32)); |
|
2732 |
__ rev32(v17, __ T16B, v17); |
|
2733 |
__ rev32(v18, __ T16B, v18); |
|
2734 |
__ BIND(L_loadkeys_52); |
|
2735 |
__ ld1(v19, v20, __ T16B, __ post(key, 32)); |
|
2736 |
__ rev32(v19, __ T16B, v19); |
|
2737 |
__ rev32(v20, __ T16B, v20); |
|
2738 |
__ BIND(L_loadkeys_44); |
|
2739 |
__ ld1(v21, v22, v23, v24, __ T16B, __ post(key, 64)); |
|
2740 |
__ rev32(v21, __ T16B, v21); |
|
2741 |
__ rev32(v22, __ T16B, v22); |
|
2742 |
__ rev32(v23, __ T16B, v23); |
|
2743 |
__ rev32(v24, __ T16B, v24); |
|
2744 |
__ ld1(v25, v26, v27, v28, __ T16B, __ post(key, 64)); |
|
2745 |
__ rev32(v25, __ T16B, v25); |
|
2746 |
__ rev32(v26, __ T16B, v26); |
|
2747 |
__ rev32(v27, __ T16B, v27); |
|
2748 |
__ rev32(v28, __ T16B, v28); |
|
2749 |
__ ld1(v29, v30, v31, __ T16B, key); |
|
2750 |
__ rev32(v29, __ T16B, v29); |
|
2751 |
__ rev32(v30, __ T16B, v30); |
|
2752 |
__ rev32(v31, __ T16B, v31); |
|
2753 |
||
2754 |
__ BIND(L_aes_loop); |
|
2755 |
__ ld1(v1, __ T16B, __ post(from, 16)); |
|
2756 |
__ eor(v0, __ T16B, v0, v1); |
|
2757 |
||
2758 |
__ br(Assembler::CC, L_rounds_44); |
|
2759 |
__ br(Assembler::EQ, L_rounds_52); |
|
2760 |
||
2761 |
__ aese(v0, v17); __ aesmc(v0, v0); |
|
2762 |
__ aese(v0, v18); __ aesmc(v0, v0); |
|
2763 |
__ BIND(L_rounds_52); |
|
2764 |
__ aese(v0, v19); __ aesmc(v0, v0); |
|
2765 |
__ aese(v0, v20); __ aesmc(v0, v0); |
|
2766 |
__ BIND(L_rounds_44); |
|
2767 |
__ aese(v0, v21); __ aesmc(v0, v0); |
|
2768 |
__ aese(v0, v22); __ aesmc(v0, v0); |
|
2769 |
__ aese(v0, v23); __ aesmc(v0, v0); |
|
2770 |
__ aese(v0, v24); __ aesmc(v0, v0); |
|
2771 |
__ aese(v0, v25); __ aesmc(v0, v0); |
|
2772 |
__ aese(v0, v26); __ aesmc(v0, v0); |
|
2773 |
__ aese(v0, v27); __ aesmc(v0, v0); |
|
2774 |
__ aese(v0, v28); __ aesmc(v0, v0); |
|
2775 |
__ aese(v0, v29); __ aesmc(v0, v0); |
|
2776 |
__ aese(v0, v30); |
|
2777 |
__ eor(v0, __ T16B, v0, v31); |
|
2778 |
||
2779 |
__ st1(v0, __ T16B, __ post(to, 16)); |
|
41729
d852f04fa9df
8167595: AArch64: SEGV in stub code cipherBlockChaining_decryptAESCrypt
aph
parents:
40643
diff
changeset
|
2780 |
|
d852f04fa9df
8167595: AArch64: SEGV in stub code cipherBlockChaining_decryptAESCrypt
aph
parents:
40643
diff
changeset
|
2781 |
__ subw(len_reg, len_reg, 16); |
d852f04fa9df
8167595: AArch64: SEGV in stub code cipherBlockChaining_decryptAESCrypt
aph
parents:
40643
diff
changeset
|
2782 |
__ cbnzw(len_reg, L_aes_loop); |
29183 | 2783 |
|
2784 |
__ st1(v0, __ T16B, rvec); |
|
2785 |
||
2786 |
__ mov(r0, rscratch2); |
|
2787 |
||
2788 |
__ leave(); |
|
2789 |
__ ret(lr); |
|
2790 |
||
2791 |
return start; |
|
2792 |
} |
|
2793 |
||
2794 |
// Arguments: |
|
2795 |
// |
|
2796 |
// Inputs: |
|
2797 |
// c_rarg0 - source byte array address |
|
2798 |
// c_rarg1 - destination byte array address |
|
2799 |
// c_rarg2 - K (key) in little endian int array |
|
2800 |
// c_rarg3 - r vector byte array address |
|
2801 |
// c_rarg4 - input length |
|
2802 |
// |
|
2803 |
// Output: |
|
35135 | 2804 |
// r0 - input length |
29183 | 2805 |
// |
2806 |
address generate_cipherBlockChaining_decryptAESCrypt() { |
|
2807 |
assert(UseAES, "need AES instructions and misaligned SSE support"); |
|
2808 |
__ align(CodeEntryAlignment); |
|
2809 |
StubCodeMark mark(this, "StubRoutines", "cipherBlockChaining_decryptAESCrypt"); |
|
2810 |
||
42577
c47121f6307d
8169529: AArch64: Revert old JDK-8167595 changes after JDK-8159035 fix is pushed
rraghavan
parents:
41729
diff
changeset
|
2811 |
Label L_loadkeys_44, L_loadkeys_52, L_aes_loop, L_rounds_44, L_rounds_52; |
29183 | 2812 |
|
2813 |
const Register from = c_rarg0; // source array address |
|
2814 |
const Register to = c_rarg1; // destination array address |
|
2815 |
const Register key = c_rarg2; // key array address |
|
2816 |
const Register rvec = c_rarg3; // r byte array initialized from initvector array address |
|
2817 |
// and left with the results of the last encryption block |
|
2818 |
const Register len_reg = c_rarg4; // src len (must be multiple of blocksize 16) |
|
2819 |
const Register keylen = rscratch1; |
|
2820 |
||
2821 |
address start = __ pc(); |
|
41729
d852f04fa9df
8167595: AArch64: SEGV in stub code cipherBlockChaining_decryptAESCrypt
aph
parents:
40643
diff
changeset
|
2822 |
|
29183 | 2823 |
__ enter(); |
2824 |
||
42577
c47121f6307d
8169529: AArch64: Revert old JDK-8167595 changes after JDK-8159035 fix is pushed
rraghavan
parents:
41729
diff
changeset
|
2825 |
__ movw(rscratch2, len_reg); |
41729
d852f04fa9df
8167595: AArch64: SEGV in stub code cipherBlockChaining_decryptAESCrypt
aph
parents:
40643
diff
changeset
|
2826 |
|
29183 | 2827 |
__ ldrw(keylen, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT))); |
2828 |
||
2829 |
__ ld1(v2, __ T16B, rvec); |
|
2830 |
||
2831 |
__ ld1(v31, __ T16B, __ post(key, 16)); |
|
2832 |
__ rev32(v31, __ T16B, v31); |
|
2833 |
||
2834 |
__ cmpw(keylen, 52); |
|
2835 |
__ br(Assembler::CC, L_loadkeys_44); |
|
2836 |
__ br(Assembler::EQ, L_loadkeys_52); |
|
2837 |
||
2838 |
__ ld1(v17, v18, __ T16B, __ post(key, 32)); |
|
2839 |
__ rev32(v17, __ T16B, v17); |
|
2840 |
__ rev32(v18, __ T16B, v18); |
|
2841 |
__ BIND(L_loadkeys_52); |
|
2842 |
__ ld1(v19, v20, __ T16B, __ post(key, 32)); |
|
2843 |
__ rev32(v19, __ T16B, v19); |
|
2844 |
__ rev32(v20, __ T16B, v20); |
|
2845 |
__ BIND(L_loadkeys_44); |
|
2846 |
__ ld1(v21, v22, v23, v24, __ T16B, __ post(key, 64)); |
|
2847 |
__ rev32(v21, __ T16B, v21); |
|
2848 |
__ rev32(v22, __ T16B, v22); |
|
2849 |
__ rev32(v23, __ T16B, v23); |
|
2850 |
__ rev32(v24, __ T16B, v24); |
|
2851 |
__ ld1(v25, v26, v27, v28, __ T16B, __ post(key, 64)); |
|
2852 |
__ rev32(v25, __ T16B, v25); |
|
2853 |
__ rev32(v26, __ T16B, v26); |
|
2854 |
__ rev32(v27, __ T16B, v27); |
|
2855 |
__ rev32(v28, __ T16B, v28); |
|
2856 |
__ ld1(v29, v30, __ T16B, key); |
|
2857 |
__ rev32(v29, __ T16B, v29); |
|
2858 |
__ rev32(v30, __ T16B, v30); |
|
2859 |
||
2860 |
__ BIND(L_aes_loop); |
|
2861 |
__ ld1(v0, __ T16B, __ post(from, 16)); |
|
2862 |
__ orr(v1, __ T16B, v0, v0); |
|
2863 |
||
2864 |
__ br(Assembler::CC, L_rounds_44); |
|
2865 |
__ br(Assembler::EQ, L_rounds_52); |
|
2866 |
||
2867 |
__ aesd(v0, v17); __ aesimc(v0, v0); |
|
34664
41c821224dd7
8144201: aarch64: jdk/test/com/sun/net/httpserver/Test6a.java fails with --enable-unlimited-crypto
fyang
parents:
33198
diff
changeset
|
2868 |
__ aesd(v0, v18); __ aesimc(v0, v0); |
29183 | 2869 |
__ BIND(L_rounds_52); |
2870 |
__ aesd(v0, v19); __ aesimc(v0, v0); |
|
2871 |
__ aesd(v0, v20); __ aesimc(v0, v0); |
|
2872 |
__ BIND(L_rounds_44); |
|
2873 |
__ aesd(v0, v21); __ aesimc(v0, v0); |
|
2874 |
__ aesd(v0, v22); __ aesimc(v0, v0); |
|
2875 |
__ aesd(v0, v23); __ aesimc(v0, v0); |
|
2876 |
__ aesd(v0, v24); __ aesimc(v0, v0); |
|
2877 |
__ aesd(v0, v25); __ aesimc(v0, v0); |
|
2878 |
__ aesd(v0, v26); __ aesimc(v0, v0); |
|
2879 |
__ aesd(v0, v27); __ aesimc(v0, v0); |
|
2880 |
__ aesd(v0, v28); __ aesimc(v0, v0); |
|
2881 |
__ aesd(v0, v29); __ aesimc(v0, v0); |
|
2882 |
__ aesd(v0, v30); |
|
2883 |
__ eor(v0, __ T16B, v0, v31); |
|
2884 |
__ eor(v0, __ T16B, v0, v2); |
|
2885 |
||
2886 |
__ st1(v0, __ T16B, __ post(to, 16)); |
|
2887 |
__ orr(v2, __ T16B, v1, v1); |
|
2888 |
||
41729
d852f04fa9df
8167595: AArch64: SEGV in stub code cipherBlockChaining_decryptAESCrypt
aph
parents:
40643
diff
changeset
|
2889 |
__ subw(len_reg, len_reg, 16); |
d852f04fa9df
8167595: AArch64: SEGV in stub code cipherBlockChaining_decryptAESCrypt
aph
parents:
40643
diff
changeset
|
2890 |
__ cbnzw(len_reg, L_aes_loop); |
29183 | 2891 |
|
2892 |
__ st1(v2, __ T16B, rvec); |
|
2893 |
||
2894 |
__ mov(r0, rscratch2); |
|
2895 |
||
2896 |
__ leave(); |
|
2897 |
__ ret(lr); |
|
2898 |
||
2899 |
return start; |
|
2900 |
} |
|
2901 |
||
2902 |
// Arguments: |
|
2903 |
// |
|
2904 |
// Inputs: |
|
2905 |
// c_rarg0 - byte[] source+offset |
|
2906 |
// c_rarg1 - int[] SHA.state |
|
2907 |
// c_rarg2 - int offset |
|
2908 |
// c_rarg3 - int limit |
|
2909 |
// |
|
2910 |
address generate_sha1_implCompress(bool multi_block, const char *name) { |
|
2911 |
__ align(CodeEntryAlignment); |
|
2912 |
StubCodeMark mark(this, "StubRoutines", name); |
|
2913 |
address start = __ pc(); |
|
2914 |
||
2915 |
Register buf = c_rarg0; |
|
2916 |
Register state = c_rarg1; |
|
2917 |
Register ofs = c_rarg2; |
|
2918 |
Register limit = c_rarg3; |
|
2919 |
||
2920 |
Label keys; |
|
2921 |
Label sha1_loop; |
|
2922 |
||
2923 |
// load the keys into v0..v3 |
|
2924 |
__ adr(rscratch1, keys); |
|
2925 |
__ ld4r(v0, v1, v2, v3, __ T4S, Address(rscratch1)); |
|
2926 |
// load 5 words state into v6, v7 |
|
2927 |
__ ldrq(v6, Address(state, 0)); |
|
2928 |
__ ldrs(v7, Address(state, 16)); |
|
2929 |
||
2930 |
||
2931 |
__ BIND(sha1_loop); |
|
2932 |
// load 64 bytes of data into v16..v19 |
|
2933 |
__ ld1(v16, v17, v18, v19, __ T4S, multi_block ? __ post(buf, 64) : buf); |
|
2934 |
__ rev32(v16, __ T16B, v16); |
|
2935 |
__ rev32(v17, __ T16B, v17); |
|
2936 |
__ rev32(v18, __ T16B, v18); |
|
2937 |
__ rev32(v19, __ T16B, v19); |
|
2938 |
||
2939 |
// do the sha1 |
|
2940 |
__ addv(v4, __ T4S, v16, v0); |
|
2941 |
__ orr(v20, __ T16B, v6, v6); |
|
2942 |
||
2943 |
FloatRegister d0 = v16; |
|
2944 |
FloatRegister d1 = v17; |
|
2945 |
FloatRegister d2 = v18; |
|
2946 |
FloatRegister d3 = v19; |
|
2947 |
||
2948 |
for (int round = 0; round < 20; round++) { |
|
2949 |
FloatRegister tmp1 = (round & 1) ? v4 : v5; |
|
2950 |
FloatRegister tmp2 = (round & 1) ? v21 : v22; |
|
2951 |
FloatRegister tmp3 = round ? ((round & 1) ? v22 : v21) : v7; |
|
2952 |
FloatRegister tmp4 = (round & 1) ? v5 : v4; |
|
2953 |
FloatRegister key = (round < 4) ? v0 : ((round < 9) ? v1 : ((round < 14) ? v2 : v3)); |
|
2954 |
||
2955 |
if (round < 16) __ sha1su0(d0, __ T4S, d1, d2); |
|
2956 |
if (round < 19) __ addv(tmp1, __ T4S, d1, key); |
|
2957 |
__ sha1h(tmp2, __ T4S, v20); |
|
2958 |
if (round < 5) |
|
2959 |
__ sha1c(v20, __ T4S, tmp3, tmp4); |
|
2960 |
else if (round < 10 || round >= 15) |
|
2961 |
__ sha1p(v20, __ T4S, tmp3, tmp4); |
|
2962 |
else |
|
2963 |
__ sha1m(v20, __ T4S, tmp3, tmp4); |
|
2964 |
if (round < 16) __ sha1su1(d0, __ T4S, d3); |
|
2965 |
||
2966 |
tmp1 = d0; d0 = d1; d1 = d2; d2 = d3; d3 = tmp1; |
|
2967 |
} |
|
2968 |
||
2969 |
__ addv(v7, __ T2S, v7, v21); |
|
2970 |
__ addv(v6, __ T4S, v6, v20); |
|
2971 |
||
2972 |
if (multi_block) { |
|
2973 |
__ add(ofs, ofs, 64); |
|
2974 |
__ cmp(ofs, limit); |
|
2975 |
__ br(Assembler::LE, sha1_loop); |
|
2976 |
__ mov(c_rarg0, ofs); // return ofs |
|
2977 |
} |
|
2978 |
||
2979 |
__ strq(v6, Address(state, 0)); |
|
2980 |
__ strs(v7, Address(state, 16)); |
|
2981 |
||
2982 |
__ ret(lr); |
|
2983 |
||
2984 |
__ bind(keys); |
|
2985 |
__ emit_int32(0x5a827999); |
|
2986 |
__ emit_int32(0x6ed9eba1); |
|
2987 |
__ emit_int32(0x8f1bbcdc); |
|
2988 |
__ emit_int32(0xca62c1d6); |
|
2989 |
||
2990 |
return start; |
|
2991 |
} |
|
2992 |
||
2993 |
||
2994 |
// Arguments: |
|
2995 |
// |
|
2996 |
// Inputs: |
|
2997 |
// c_rarg0 - byte[] source+offset |
|
2998 |
// c_rarg1 - int[] SHA.state |
|
2999 |
// c_rarg2 - int offset |
|
3000 |
// c_rarg3 - int limit |
|
3001 |
// |
|
3002 |
address generate_sha256_implCompress(bool multi_block, const char *name) { |
|
3003 |
static const uint32_t round_consts[64] = { |
|
3004 |
0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5, |
|
3005 |
0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5, |
|
3006 |
0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3, |
|
3007 |
0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174, |
|
3008 |
0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc, |
|
3009 |
0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da, |
|
3010 |
0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7, |
|
3011 |
0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967, |
|
3012 |
0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13, |
|
3013 |
0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85, |
|
3014 |
0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3, |
|
3015 |
0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070, |
|
3016 |
0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5, |
|
3017 |
0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3, |
|
3018 |
0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208, |
|
3019 |
0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2, |
|
3020 |
}; |
|
3021 |
__ align(CodeEntryAlignment); |
|
3022 |
StubCodeMark mark(this, "StubRoutines", name); |
|
3023 |
address start = __ pc(); |
|
3024 |
||
3025 |
Register buf = c_rarg0; |
|
3026 |
Register state = c_rarg1; |
|
3027 |
Register ofs = c_rarg2; |
|
3028 |
Register limit = c_rarg3; |
|
3029 |
||
3030 |
Label sha1_loop; |
|
3031 |
||
3032 |
__ stpd(v8, v9, __ pre(sp, -32)); |
|
3033 |
__ stpd(v10, v11, Address(sp, 16)); |
|
3034 |
||
3035 |
// dga == v0 |
|
3036 |
// dgb == v1 |
|
3037 |
// dg0 == v2 |
|
3038 |
// dg1 == v3 |
|
3039 |
// dg2 == v4 |
|
3040 |
// t0 == v6 |
|
3041 |
// t1 == v7 |
|
3042 |
||
3043 |
// load 16 keys to v16..v31 |
|
3044 |
__ lea(rscratch1, ExternalAddress((address)round_consts)); |
|
3045 |
__ ld1(v16, v17, v18, v19, __ T4S, __ post(rscratch1, 64)); |
|
3046 |
__ ld1(v20, v21, v22, v23, __ T4S, __ post(rscratch1, 64)); |
|
3047 |
__ ld1(v24, v25, v26, v27, __ T4S, __ post(rscratch1, 64)); |
|
3048 |
__ ld1(v28, v29, v30, v31, __ T4S, rscratch1); |
|
3049 |
||
3050 |
// load 8 words (256 bits) state |
|
3051 |
__ ldpq(v0, v1, state); |
|
3052 |
||
3053 |
__ BIND(sha1_loop); |
|
3054 |
// load 64 bytes of data into v8..v11 |
|
3055 |
__ ld1(v8, v9, v10, v11, __ T4S, multi_block ? __ post(buf, 64) : buf); |
|
3056 |
__ rev32(v8, __ T16B, v8); |
|
3057 |
__ rev32(v9, __ T16B, v9); |
|
3058 |
__ rev32(v10, __ T16B, v10); |
|
3059 |
__ rev32(v11, __ T16B, v11); |
|
3060 |
||
3061 |
__ addv(v6, __ T4S, v8, v16); |
|
3062 |
__ orr(v2, __ T16B, v0, v0); |
|
3063 |
__ orr(v3, __ T16B, v1, v1); |
|
3064 |
||
3065 |
FloatRegister d0 = v8; |
|
3066 |
FloatRegister d1 = v9; |
|
3067 |
FloatRegister d2 = v10; |
|
3068 |
FloatRegister d3 = v11; |
|
3069 |
||
3070 |
||
3071 |
for (int round = 0; round < 16; round++) { |
|
3072 |
FloatRegister tmp1 = (round & 1) ? v6 : v7; |
|
3073 |
FloatRegister tmp2 = (round & 1) ? v7 : v6; |
|
3074 |
FloatRegister tmp3 = (round & 1) ? v2 : v4; |
|
3075 |
FloatRegister tmp4 = (round & 1) ? v4 : v2; |
|
3076 |
||
3077 |
if (round < 12) __ sha256su0(d0, __ T4S, d1); |
|
3078 |
__ orr(v4, __ T16B, v2, v2); |
|
3079 |
if (round < 15) |
|
3080 |
__ addv(tmp1, __ T4S, d1, as_FloatRegister(round + 17)); |
|
3081 |
__ sha256h(v2, __ T4S, v3, tmp2); |
|
3082 |
__ sha256h2(v3, __ T4S, v4, tmp2); |
|
3083 |
if (round < 12) __ sha256su1(d0, __ T4S, d2, d3); |
|
3084 |
||
3085 |
tmp1 = d0; d0 = d1; d1 = d2; d2 = d3; d3 = tmp1; |
|
3086 |
} |
|
3087 |
||
3088 |
__ addv(v0, __ T4S, v0, v2); |
|
3089 |
__ addv(v1, __ T4S, v1, v3); |
|
3090 |
||
3091 |
if (multi_block) { |
|
3092 |
__ add(ofs, ofs, 64); |
|
3093 |
__ cmp(ofs, limit); |
|
3094 |
__ br(Assembler::LE, sha1_loop); |
|
3095 |
__ mov(c_rarg0, ofs); // return ofs |
|
3096 |
} |
|
3097 |
||
3098 |
__ ldpd(v10, v11, Address(sp, 16)); |
|
3099 |
__ ldpd(v8, v9, __ post(sp, 32)); |
|
3100 |
||
3101 |
__ stpq(v0, v1, state); |
|
3102 |
||
3103 |
__ ret(lr); |
|
3104 |
||
3105 |
return start; |
|
3106 |
} |
|
3107 |
||
3108 |
#ifndef BUILTIN_SIM |
|
3109 |
// Safefetch stubs. |
|
3110 |
void generate_safefetch(const char* name, int size, address* entry, |
|
3111 |
address* fault_pc, address* continuation_pc) { |
|
3112 |
// safefetch signatures: |
|
3113 |
// int SafeFetch32(int* adr, int errValue); |
|
3114 |
// intptr_t SafeFetchN (intptr_t* adr, intptr_t errValue); |
|
3115 |
// |
|
3116 |
// arguments: |
|
3117 |
// c_rarg0 = adr |
|
3118 |
// c_rarg1 = errValue |
|
3119 |
// |
|
3120 |
// result: |
|
3121 |
// PPC_RET = *adr or errValue |
|
3122 |
||
3123 |
StubCodeMark mark(this, "StubRoutines", name); |
|
3124 |
||
3125 |
// Entry point, pc or function descriptor. |
|
3126 |
*entry = __ pc(); |
|
3127 |
||
3128 |
// Load *adr into c_rarg1, may fault. |
|
3129 |
*fault_pc = __ pc(); |
|
3130 |
switch (size) { |
|
3131 |
case 4: |
|
3132 |
// int32_t |
|
3133 |
__ ldrw(c_rarg1, Address(c_rarg0, 0)); |
|
3134 |
break; |
|
3135 |
case 8: |
|
3136 |
// int64_t |
|
3137 |
__ ldr(c_rarg1, Address(c_rarg0, 0)); |
|
3138 |
break; |
|
3139 |
default: |
|
3140 |
ShouldNotReachHere(); |
|
3141 |
} |
|
3142 |
||
3143 |
// return errValue or *adr |
|
3144 |
*continuation_pc = __ pc(); |
|
3145 |
__ mov(r0, c_rarg1); |
|
3146 |
__ ret(lr); |
|
3147 |
} |
|
3148 |
#endif |
|
3149 |
||
3150 |
/** |
|
3151 |
* Arguments: |
|
3152 |
* |
|
3153 |
* Inputs: |
|
3154 |
* c_rarg0 - int crc |
|
3155 |
* c_rarg1 - byte* buf |
|
3156 |
* c_rarg2 - int length |
|
3157 |
* |
|
3158 |
* Ouput: |
|
3159 |
* rax - int crc result |
|
3160 |
*/ |
|
3161 |
address generate_updateBytesCRC32() { |
|
3162 |
assert(UseCRC32Intrinsics, "what are we doing here?"); |
|
3163 |
||
3164 |
__ align(CodeEntryAlignment); |
|
3165 |
StubCodeMark mark(this, "StubRoutines", "updateBytesCRC32"); |
|
3166 |
||
3167 |
address start = __ pc(); |
|
3168 |
||
3169 |
const Register crc = c_rarg0; // crc |
|
3170 |
const Register buf = c_rarg1; // source java byte array address |
|
3171 |
const Register len = c_rarg2; // length |
|
3172 |
const Register table0 = c_rarg3; // crc_table address |
|
3173 |
const Register table1 = c_rarg4; |
|
3174 |
const Register table2 = c_rarg5; |
|
3175 |
const Register table3 = c_rarg6; |
|
3176 |
const Register tmp3 = c_rarg7; |
|
3177 |
||
3178 |
BLOCK_COMMENT("Entry:"); |
|
3179 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
|
3180 |
||
3181 |
__ kernel_crc32(crc, buf, len, |
|
3182 |
table0, table1, table2, table3, rscratch1, rscratch2, tmp3); |
|
3183 |
||
3184 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
|
3185 |
__ ret(lr); |
|
3186 |
||
3187 |
return start; |
|
3188 |
} |
|
3189 |
||
30225
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3190 |
/** |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3191 |
* Arguments: |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3192 |
* |
31591
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
30553
diff
changeset
|
3193 |
* Inputs: |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
30553
diff
changeset
|
3194 |
* c_rarg0 - int crc |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
30553
diff
changeset
|
3195 |
* c_rarg1 - byte* buf |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
30553
diff
changeset
|
3196 |
* c_rarg2 - int length |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
30553
diff
changeset
|
3197 |
* c_rarg3 - int* table |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
30553
diff
changeset
|
3198 |
* |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
30553
diff
changeset
|
3199 |
* Ouput: |
32574 | 3200 |
* r0 - int crc result |
31591
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
30553
diff
changeset
|
3201 |
*/ |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
30553
diff
changeset
|
3202 |
address generate_updateBytesCRC32C() { |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
30553
diff
changeset
|
3203 |
assert(UseCRC32CIntrinsics, "what are we doing here?"); |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
30553
diff
changeset
|
3204 |
|
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
30553
diff
changeset
|
3205 |
__ align(CodeEntryAlignment); |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
30553
diff
changeset
|
3206 |
StubCodeMark mark(this, "StubRoutines", "updateBytesCRC32C"); |
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diff
changeset
|
3207 |
|
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diff
changeset
|
3208 |
address start = __ pc(); |
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diff
changeset
|
3209 |
|
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diff
changeset
|
3210 |
const Register crc = c_rarg0; // crc |
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changeset
|
3211 |
const Register buf = c_rarg1; // source java byte array address |
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changeset
|
3212 |
const Register len = c_rarg2; // length |
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changeset
|
3213 |
const Register table0 = c_rarg3; // crc_table address |
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|
3214 |
const Register table1 = c_rarg4; |
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changeset
|
3215 |
const Register table2 = c_rarg5; |
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|
3216 |
const Register table3 = c_rarg6; |
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changeset
|
3217 |
const Register tmp3 = c_rarg7; |
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diff
changeset
|
3218 |
|
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diff
changeset
|
3219 |
BLOCK_COMMENT("Entry:"); |
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diff
changeset
|
3220 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
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diff
changeset
|
3221 |
|
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diff
changeset
|
3222 |
__ kernel_crc32c(crc, buf, len, |
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8130687: aarch64: add support for hardware crc32c
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diff
changeset
|
3223 |
table0, table1, table2, table3, rscratch1, rscratch2, tmp3); |
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diff
changeset
|
3224 |
|
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changeset
|
3225 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
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diff
changeset
|
3226 |
__ ret(lr); |
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diff
changeset
|
3227 |
|
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diff
changeset
|
3228 |
return start; |
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diff
changeset
|
3229 |
} |
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diff
changeset
|
3230 |
|
33176
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changeset
|
3231 |
/*** |
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diff
changeset
|
3232 |
* Arguments: |
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diff
changeset
|
3233 |
* |
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8139043: aarch64: add support for adler32 intrinsic
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changeset
|
3234 |
* Inputs: |
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changeset
|
3235 |
* c_rarg0 - int adler |
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|
3236 |
* c_rarg1 - byte* buff |
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|
3237 |
* c_rarg2 - int len |
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changeset
|
3238 |
* |
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8139043: aarch64: add support for adler32 intrinsic
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changeset
|
3239 |
* Output: |
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changeset
|
3240 |
* c_rarg0 - int adler result |
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diff
changeset
|
3241 |
*/ |
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changeset
|
3242 |
address generate_updateBytesAdler32() { |
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changeset
|
3243 |
__ align(CodeEntryAlignment); |
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changeset
|
3244 |
StubCodeMark mark(this, "StubRoutines", "updateBytesAdler32"); |
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changeset
|
3245 |
address start = __ pc(); |
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diff
changeset
|
3246 |
|
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changeset
|
3247 |
Label L_simple_by1_loop, L_nmax, L_nmax_loop, L_by16, L_by16_loop, L_by1_loop, L_do_mod, L_combine, L_by1; |
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changeset
|
3248 |
|
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diff
changeset
|
3249 |
// Aliases |
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8139043: aarch64: add support for adler32 intrinsic
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changeset
|
3250 |
Register adler = c_rarg0; |
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changeset
|
3251 |
Register s1 = c_rarg0; |
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|
3252 |
Register s2 = c_rarg3; |
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changeset
|
3253 |
Register buff = c_rarg1; |
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changeset
|
3254 |
Register len = c_rarg2; |
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changeset
|
3255 |
Register nmax = r4; |
53950 | 3256 |
Register base = r5; |
33176
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changeset
|
3257 |
Register count = r6; |
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changeset
|
3258 |
Register temp0 = rscratch1; |
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changeset
|
3259 |
Register temp1 = rscratch2; |
53950 | 3260 |
FloatRegister vbytes = v0; |
3261 |
FloatRegister vs1acc = v1; |
|
3262 |
FloatRegister vs2acc = v2; |
|
3263 |
FloatRegister vtable = v3; |
|
33176
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diff
changeset
|
3264 |
|
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8139043: aarch64: add support for adler32 intrinsic
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changeset
|
3265 |
// Max number of bytes we can process before having to take the mod |
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changeset
|
3266 |
// 0x15B0 is 5552 in decimal, the largest n such that 255n(n+1)/2 + (n+1)(BASE-1) <= 2^32-1 |
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changeset
|
3267 |
unsigned long BASE = 0xfff1; |
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diff
changeset
|
3268 |
unsigned long NMAX = 0x15B0; |
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diff
changeset
|
3269 |
|
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diff
changeset
|
3270 |
__ mov(base, BASE); |
54393049bf1e
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changeset
|
3271 |
__ mov(nmax, NMAX); |
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diff
changeset
|
3272 |
|
53950 | 3273 |
// Load accumulation coefficients for the upper 16 bits |
3274 |
__ lea(temp0, ExternalAddress((address) StubRoutines::aarch64::_adler_table)); |
|
3275 |
__ ld1(vtable, __ T16B, Address(temp0)); |
|
3276 |
||
33176
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8139043: aarch64: add support for adler32 intrinsic
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diff
changeset
|
3277 |
// s1 is initialized to the lower 16 bits of adler |
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changeset
|
3278 |
// s2 is initialized to the upper 16 bits of adler |
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changeset
|
3279 |
__ ubfx(s2, adler, 16, 16); // s2 = ((adler >> 16) & 0xffff) |
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changeset
|
3280 |
__ uxth(s1, adler); // s1 = (adler & 0xffff) |
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diff
changeset
|
3281 |
|
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
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diff
changeset
|
3282 |
// The pipelined loop needs at least 16 elements for 1 iteration |
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diff
changeset
|
3283 |
// It does check this, but it is more effective to skip to the cleanup loop |
51374
7be0084191ed
8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents:
50758
diff
changeset
|
3284 |
__ cmp(len, (u1)16); |
33176
54393049bf1e
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diff
changeset
|
3285 |
__ br(Assembler::HS, L_nmax); |
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changeset
|
3286 |
__ cbz(len, L_combine); |
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diff
changeset
|
3287 |
|
54393049bf1e
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diff
changeset
|
3288 |
__ bind(L_simple_by1_loop); |
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diff
changeset
|
3289 |
__ ldrb(temp0, Address(__ post(buff, 1))); |
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diff
changeset
|
3290 |
__ add(s1, s1, temp0); |
54393049bf1e
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diff
changeset
|
3291 |
__ add(s2, s2, s1); |
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changeset
|
3292 |
__ subs(len, len, 1); |
54393049bf1e
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diff
changeset
|
3293 |
__ br(Assembler::HI, L_simple_by1_loop); |
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diff
changeset
|
3294 |
|
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
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32627
diff
changeset
|
3295 |
// s1 = s1 % BASE |
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changeset
|
3296 |
__ subs(temp0, s1, base); |
54393049bf1e
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diff
changeset
|
3297 |
__ csel(s1, temp0, s1, Assembler::HS); |
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diff
changeset
|
3298 |
|
54393049bf1e
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diff
changeset
|
3299 |
// s2 = s2 % BASE |
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diff
changeset
|
3300 |
__ lsr(temp0, s2, 16); |
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diff
changeset
|
3301 |
__ lsl(temp1, temp0, 4); |
54393049bf1e
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diff
changeset
|
3302 |
__ sub(temp1, temp1, temp0); |
54393049bf1e
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diff
changeset
|
3303 |
__ add(s2, temp1, s2, ext::uxth); |
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diff
changeset
|
3304 |
|
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diff
changeset
|
3305 |
__ subs(temp0, s2, base); |
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diff
changeset
|
3306 |
__ csel(s2, temp0, s2, Assembler::HS); |
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diff
changeset
|
3307 |
|
54393049bf1e
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diff
changeset
|
3308 |
__ b(L_combine); |
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diff
changeset
|
3309 |
|
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diff
changeset
|
3310 |
__ bind(L_nmax); |
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changeset
|
3311 |
__ subs(len, len, nmax); |
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changeset
|
3312 |
__ sub(count, nmax, 16); |
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diff
changeset
|
3313 |
__ br(Assembler::LO, L_by16); |
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32627
diff
changeset
|
3314 |
|
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diff
changeset
|
3315 |
__ bind(L_nmax_loop); |
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changeset
|
3316 |
|
53950 | 3317 |
generate_updateBytesAdler32_accum(s1, s2, buff, temp0, temp1, |
3318 |
vbytes, vs1acc, vs2acc, vtable); |
|
33176
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diff
changeset
|
3319 |
|
54393049bf1e
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diff
changeset
|
3320 |
__ subs(count, count, 16); |
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diff
changeset
|
3321 |
__ br(Assembler::HS, L_nmax_loop); |
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diff
changeset
|
3322 |
|
54393049bf1e
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diff
changeset
|
3323 |
// s1 = s1 % BASE |
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changeset
|
3324 |
__ lsr(temp0, s1, 16); |
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diff
changeset
|
3325 |
__ lsl(temp1, temp0, 4); |
54393049bf1e
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diff
changeset
|
3326 |
__ sub(temp1, temp1, temp0); |
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parents:
32627
diff
changeset
|
3327 |
__ add(temp1, temp1, s1, ext::uxth); |
54393049bf1e
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parents:
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diff
changeset
|
3328 |
|
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
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parents:
32627
diff
changeset
|
3329 |
__ lsr(temp0, temp1, 16); |
54393049bf1e
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diff
changeset
|
3330 |
__ lsl(s1, temp0, 4); |
54393049bf1e
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diff
changeset
|
3331 |
__ sub(s1, s1, temp0); |
54393049bf1e
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diff
changeset
|
3332 |
__ add(s1, s1, temp1, ext:: uxth); |
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parents:
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diff
changeset
|
3333 |
|
54393049bf1e
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diff
changeset
|
3334 |
__ subs(temp0, s1, base); |
54393049bf1e
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diff
changeset
|
3335 |
__ csel(s1, temp0, s1, Assembler::HS); |
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changeset
|
3336 |
|
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
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parents:
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diff
changeset
|
3337 |
// s2 = s2 % BASE |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
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parents:
32627
diff
changeset
|
3338 |
__ lsr(temp0, s2, 16); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
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parents:
32627
diff
changeset
|
3339 |
__ lsl(temp1, temp0, 4); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
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parents:
32627
diff
changeset
|
3340 |
__ sub(temp1, temp1, temp0); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
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parents:
32627
diff
changeset
|
3341 |
__ add(temp1, temp1, s2, ext::uxth); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
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parents:
32627
diff
changeset
|
3342 |
|
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3343 |
__ lsr(temp0, temp1, 16); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3344 |
__ lsl(s2, temp0, 4); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3345 |
__ sub(s2, s2, temp0); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3346 |
__ add(s2, s2, temp1, ext:: uxth); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3347 |
|
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3348 |
__ subs(temp0, s2, base); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
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parents:
32627
diff
changeset
|
3349 |
__ csel(s2, temp0, s2, Assembler::HS); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
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parents:
32627
diff
changeset
|
3350 |
|
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3351 |
__ subs(len, len, nmax); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3352 |
__ sub(count, nmax, 16); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3353 |
__ br(Assembler::HS, L_nmax_loop); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
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parents:
32627
diff
changeset
|
3354 |
|
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3355 |
__ bind(L_by16); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3356 |
__ adds(len, len, count); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3357 |
__ br(Assembler::LO, L_by1); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
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parents:
32627
diff
changeset
|
3358 |
|
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3359 |
__ bind(L_by16_loop); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3360 |
|
53950 | 3361 |
generate_updateBytesAdler32_accum(s1, s2, buff, temp0, temp1, |
3362 |
vbytes, vs1acc, vs2acc, vtable); |
|
33176
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
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parents:
32627
diff
changeset
|
3363 |
|
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3364 |
__ subs(len, len, 16); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3365 |
__ br(Assembler::HS, L_by16_loop); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3366 |
|
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3367 |
__ bind(L_by1); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3368 |
__ adds(len, len, 15); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3369 |
__ br(Assembler::LO, L_do_mod); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
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parents:
32627
diff
changeset
|
3370 |
|
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3371 |
__ bind(L_by1_loop); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3372 |
__ ldrb(temp0, Address(__ post(buff, 1))); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3373 |
__ add(s1, temp0, s1); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3374 |
__ add(s2, s2, s1); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3375 |
__ subs(len, len, 1); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3376 |
__ br(Assembler::HS, L_by1_loop); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3377 |
|
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3378 |
__ bind(L_do_mod); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3379 |
// s1 = s1 % BASE |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3380 |
__ lsr(temp0, s1, 16); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3381 |
__ lsl(temp1, temp0, 4); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3382 |
__ sub(temp1, temp1, temp0); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3383 |
__ add(temp1, temp1, s1, ext::uxth); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3384 |
|
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3385 |
__ lsr(temp0, temp1, 16); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3386 |
__ lsl(s1, temp0, 4); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3387 |
__ sub(s1, s1, temp0); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3388 |
__ add(s1, s1, temp1, ext:: uxth); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3389 |
|
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3390 |
__ subs(temp0, s1, base); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3391 |
__ csel(s1, temp0, s1, Assembler::HS); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3392 |
|
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3393 |
// s2 = s2 % BASE |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3394 |
__ lsr(temp0, s2, 16); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3395 |
__ lsl(temp1, temp0, 4); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3396 |
__ sub(temp1, temp1, temp0); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3397 |
__ add(temp1, temp1, s2, ext::uxth); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3398 |
|
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3399 |
__ lsr(temp0, temp1, 16); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3400 |
__ lsl(s2, temp0, 4); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3401 |
__ sub(s2, s2, temp0); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3402 |
__ add(s2, s2, temp1, ext:: uxth); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3403 |
|
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3404 |
__ subs(temp0, s2, base); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3405 |
__ csel(s2, temp0, s2, Assembler::HS); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3406 |
|
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3407 |
// Combine lower bits and higher bits |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3408 |
__ bind(L_combine); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3409 |
__ orr(s1, s1, s2, Assembler::LSL, 16); // adler = s1 | (s2 << 16) |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3410 |
|
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3411 |
__ ret(lr); |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3412 |
|
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3413 |
return start; |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3414 |
} |
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
enevill
parents:
32627
diff
changeset
|
3415 |
|
53950 | 3416 |
void generate_updateBytesAdler32_accum(Register s1, Register s2, Register buff, |
3417 |
Register temp0, Register temp1, FloatRegister vbytes, |
|
3418 |
FloatRegister vs1acc, FloatRegister vs2acc, FloatRegister vtable) { |
|
3419 |
// Below is a vectorized implementation of updating s1 and s2 for 16 bytes. |
|
3420 |
// We use b1, b2, ..., b16 to denote the 16 bytes loaded in each iteration. |
|
3421 |
// In non-vectorized code, we update s1 and s2 as: |
|
3422 |
// s1 <- s1 + b1 |
|
3423 |
// s2 <- s2 + s1 |
|
3424 |
// s1 <- s1 + b2 |
|
3425 |
// s2 <- s2 + b1 |
|
3426 |
// ... |
|
3427 |
// s1 <- s1 + b16 |
|
3428 |
// s2 <- s2 + s1 |
|
3429 |
// Putting above assignments together, we have: |
|
3430 |
// s1_new = s1 + b1 + b2 + ... + b16 |
|
3431 |
// s2_new = s2 + (s1 + b1) + (s1 + b1 + b2) + ... + (s1 + b1 + b2 + ... + b16) |
|
3432 |
// = s2 + s1 * 16 + (b1 * 16 + b2 * 15 + ... + b16 * 1) |
|
3433 |
// = s2 + s1 * 16 + (b1, b2, ... b16) dot (16, 15, ... 1) |
|
3434 |
__ ld1(vbytes, __ T16B, Address(__ post(buff, 16))); |
|
3435 |
||
3436 |
// s2 = s2 + s1 * 16 |
|
3437 |
__ add(s2, s2, s1, Assembler::LSL, 4); |
|
3438 |
||
3439 |
// vs1acc = b1 + b2 + b3 + ... + b16 |
|
3440 |
// vs2acc = (b1 * 16) + (b2 * 15) + (b3 * 14) + ... + (b16 * 1) |
|
3441 |
__ umullv(vs2acc, __ T8B, vtable, vbytes); |
|
3442 |
__ umlalv(vs2acc, __ T16B, vtable, vbytes); |
|
3443 |
__ uaddlv(vs1acc, __ T16B, vbytes); |
|
3444 |
__ uaddlv(vs2acc, __ T8H, vs2acc); |
|
3445 |
||
3446 |
// s1 = s1 + vs1acc, s2 = s2 + vs2acc |
|
3447 |
__ fmovd(temp0, vs1acc); |
|
3448 |
__ fmovd(temp1, vs2acc); |
|
3449 |
__ add(s1, s1, temp0); |
|
3450 |
__ add(s2, s2, temp1); |
|
3451 |
} |
|
3452 |
||
31591
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
30553
diff
changeset
|
3453 |
/** |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
30553
diff
changeset
|
3454 |
* Arguments: |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
30553
diff
changeset
|
3455 |
* |
30225
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3456 |
* Input: |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3457 |
* c_rarg0 - x address |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3458 |
* c_rarg1 - x length |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3459 |
* c_rarg2 - y address |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3460 |
* c_rarg3 - y lenth |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3461 |
* c_rarg4 - z address |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3462 |
* c_rarg5 - z length |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3463 |
*/ |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3464 |
address generate_multiplyToLen() { |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3465 |
__ align(CodeEntryAlignment); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3466 |
StubCodeMark mark(this, "StubRoutines", "multiplyToLen"); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3467 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3468 |
address start = __ pc(); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3469 |
const Register x = r0; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3470 |
const Register xlen = r1; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3471 |
const Register y = r2; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3472 |
const Register ylen = r3; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3473 |
const Register z = r4; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3474 |
const Register zlen = r5; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3475 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3476 |
const Register tmp1 = r10; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3477 |
const Register tmp2 = r11; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3478 |
const Register tmp3 = r12; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3479 |
const Register tmp4 = r13; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3480 |
const Register tmp5 = r14; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3481 |
const Register tmp6 = r15; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3482 |
const Register tmp7 = r16; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3483 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3484 |
BLOCK_COMMENT("Entry:"); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3485 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3486 |
__ multiply_to_len(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3487 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3488 |
__ ret(lr); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3489 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3490 |
return start; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
3491 |
} |
29183 | 3492 |
|
47571
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3493 |
address generate_squareToLen() { |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3494 |
// squareToLen algorithm for sizes 1..127 described in java code works |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3495 |
// faster than multiply_to_len on some CPUs and slower on others, but |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3496 |
// multiply_to_len shows a bit better overall results |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3497 |
__ align(CodeEntryAlignment); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3498 |
StubCodeMark mark(this, "StubRoutines", "squareToLen"); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3499 |
address start = __ pc(); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3500 |
|
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3501 |
const Register x = r0; |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3502 |
const Register xlen = r1; |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3503 |
const Register z = r2; |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3504 |
const Register zlen = r3; |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3505 |
const Register y = r4; // == x |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3506 |
const Register ylen = r5; // == xlen |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3507 |
|
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3508 |
const Register tmp1 = r10; |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3509 |
const Register tmp2 = r11; |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3510 |
const Register tmp3 = r12; |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3511 |
const Register tmp4 = r13; |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3512 |
const Register tmp5 = r14; |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3513 |
const Register tmp6 = r15; |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3514 |
const Register tmp7 = r16; |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3515 |
|
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3516 |
RegSet spilled_regs = RegSet::of(y, ylen); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3517 |
BLOCK_COMMENT("Entry:"); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3518 |
__ enter(); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3519 |
__ push(spilled_regs, sp); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3520 |
__ mov(y, x); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3521 |
__ mov(ylen, xlen); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3522 |
__ multiply_to_len(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3523 |
__ pop(spilled_regs, sp); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3524 |
__ leave(); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3525 |
__ ret(lr); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3526 |
return start; |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3527 |
} |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3528 |
|
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3529 |
address generate_mulAdd() { |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3530 |
__ align(CodeEntryAlignment); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3531 |
StubCodeMark mark(this, "StubRoutines", "mulAdd"); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3532 |
|
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3533 |
address start = __ pc(); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3534 |
|
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3535 |
const Register out = r0; |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3536 |
const Register in = r1; |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3537 |
const Register offset = r2; |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3538 |
const Register len = r3; |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3539 |
const Register k = r4; |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3540 |
|
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3541 |
BLOCK_COMMENT("Entry:"); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3542 |
__ enter(); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3543 |
__ mul_add(out, in, offset, len, k); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3544 |
__ leave(); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3545 |
__ ret(lr); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3546 |
|
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3547 |
return start; |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3548 |
} |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3549 |
|
32574 | 3550 |
void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi, |
3551 |
FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0, |
|
3552 |
FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3, FloatRegister tmp4) { |
|
3553 |
// Karatsuba multiplication performs a 128*128 -> 256-bit |
|
3554 |
// multiplication in three 128-bit multiplications and a few |
|
3555 |
// additions. |
|
3556 |
// |
|
3557 |
// (C1:C0) = A1*B1, (D1:D0) = A0*B0, (E1:E0) = (A0+A1)(B0+B1) |
|
3558 |
// (A1:A0)(B1:B0) = C1:(C0+C1+D1+E1):(D1+C0+D0+E0):D0 |
|
3559 |
// |
|
3560 |
// Inputs: |
|
3561 |
// |
|
3562 |
// A0 in a.d[0] (subkey) |
|
3563 |
// A1 in a.d[1] |
|
3564 |
// (A1+A0) in a1_xor_a0.d[0] |
|
3565 |
// |
|
3566 |
// B0 in b.d[0] (state) |
|
3567 |
// B1 in b.d[1] |
|
3568 |
||
3569 |
__ ext(tmp1, __ T16B, b, b, 0x08); |
|
3570 |
__ pmull2(result_hi, __ T1Q, b, a, __ T2D); // A1*B1 |
|
3571 |
__ eor(tmp1, __ T16B, tmp1, b); // (B1+B0) |
|
3572 |
__ pmull(result_lo, __ T1Q, b, a, __ T1D); // A0*B0 |
|
3573 |
__ pmull(tmp2, __ T1Q, tmp1, a1_xor_a0, __ T1D); // (A1+A0)(B1+B0) |
|
3574 |
||
3575 |
__ ext(tmp4, __ T16B, result_lo, result_hi, 0x08); |
|
3576 |
__ eor(tmp3, __ T16B, result_hi, result_lo); // A1*B1+A0*B0 |
|
3577 |
__ eor(tmp2, __ T16B, tmp2, tmp4); |
|
3578 |
__ eor(tmp2, __ T16B, tmp2, tmp3); |
|
3579 |
||
3580 |
// Register pair <result_hi:result_lo> holds the result of carry-less multiplication |
|
3581 |
__ ins(result_hi, __ D, tmp2, 0, 1); |
|
3582 |
__ ins(result_lo, __ D, tmp2, 1, 0); |
|
3583 |
} |
|
3584 |
||
3585 |
void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi, |
|
3586 |
FloatRegister p, FloatRegister z, FloatRegister t1) { |
|
3587 |
const FloatRegister t0 = result; |
|
3588 |
||
3589 |
// The GCM field polynomial f is z^128 + p(z), where p = |
|
3590 |
// z^7+z^2+z+1. |
|
3591 |
// |
|
3592 |
// z^128 === -p(z) (mod (z^128 + p(z))) |
|
3593 |
// |
|
3594 |
// so, given that the product we're reducing is |
|
3595 |
// a == lo + hi * z^128 |
|
3596 |
// substituting, |
|
3597 |
// === lo - hi * p(z) (mod (z^128 + p(z))) |
|
3598 |
// |
|
3599 |
// we reduce by multiplying hi by p(z) and subtracting the result |
|
3600 |
// from (i.e. XORing it with) lo. Because p has no nonzero high |
|
3601 |
// bits we can do this with two 64-bit multiplications, lo*p and |
|
3602 |
// hi*p. |
|
3603 |
||
3604 |
__ pmull2(t0, __ T1Q, hi, p, __ T2D); |
|
3605 |
__ ext(t1, __ T16B, t0, z, 8); |
|
3606 |
__ eor(hi, __ T16B, hi, t1); |
|
3607 |
__ ext(t1, __ T16B, z, t0, 8); |
|
3608 |
__ eor(lo, __ T16B, lo, t1); |
|
3609 |
__ pmull(t0, __ T1Q, hi, p, __ T1D); |
|
3610 |
__ eor(result, __ T16B, lo, t0); |
|
3611 |
} |
|
3612 |
||
46814 | 3613 |
address generate_has_negatives(address &has_negatives_long) { |
51374
7be0084191ed
8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents:
50758
diff
changeset
|
3614 |
const u1 large_loop_size = 64; |
46814 | 3615 |
const uint64_t UPPER_BIT_MASK=0x8080808080808080; |
3616 |
int dcache_line = VM_Version::dcache_line_size(); |
|
3617 |
||
3618 |
Register ary1 = r1, len = r2, result = r0; |
|
3619 |
||
3620 |
__ align(CodeEntryAlignment); |
|
52977
2e4903f83295
8205421: AARCH64: StubCodeMark should be placed after alignment
dpochepk
parents:
52927
diff
changeset
|
3621 |
|
2e4903f83295
8205421: AARCH64: StubCodeMark should be placed after alignment
dpochepk
parents:
52927
diff
changeset
|
3622 |
StubCodeMark mark(this, "StubRoutines", "has_negatives"); |
2e4903f83295
8205421: AARCH64: StubCodeMark should be placed after alignment
dpochepk
parents:
52927
diff
changeset
|
3623 |
|
46814 | 3624 |
address entry = __ pc(); |
3625 |
||
3626 |
__ enter(); |
|
3627 |
||
3628 |
Label RET_TRUE, RET_TRUE_NO_POP, RET_FALSE, ALIGNED, LOOP16, CHECK_16, DONE, |
|
3629 |
LARGE_LOOP, POST_LOOP16, LEN_OVER_15, LEN_OVER_8, POST_LOOP16_LOAD_TAIL; |
|
3630 |
||
51374
7be0084191ed
8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents:
50758
diff
changeset
|
3631 |
__ cmp(len, (u1)15); |
46814 | 3632 |
__ br(Assembler::GT, LEN_OVER_15); |
3633 |
// The only case when execution falls into this code is when pointer is near |
|
3634 |
// the end of memory page and we have to avoid reading next page |
|
3635 |
__ add(ary1, ary1, len); |
|
3636 |
__ subs(len, len, 8); |
|
3637 |
__ br(Assembler::GT, LEN_OVER_8); |
|
3638 |
__ ldr(rscratch2, Address(ary1, -8)); |
|
3639 |
__ sub(rscratch1, zr, len, __ LSL, 3); // LSL 3 is to get bits from bytes. |
|
3640 |
__ lsrv(rscratch2, rscratch2, rscratch1); |
|
3641 |
__ tst(rscratch2, UPPER_BIT_MASK); |
|
3642 |
__ cset(result, Assembler::NE); |
|
3643 |
__ leave(); |
|
3644 |
__ ret(lr); |
|
3645 |
__ bind(LEN_OVER_8); |
|
3646 |
__ ldp(rscratch1, rscratch2, Address(ary1, -16)); |
|
3647 |
__ sub(len, len, 8); // no data dep., then sub can be executed while loading |
|
3648 |
__ tst(rscratch2, UPPER_BIT_MASK); |
|
3649 |
__ br(Assembler::NE, RET_TRUE_NO_POP); |
|
3650 |
__ sub(rscratch2, zr, len, __ LSL, 3); // LSL 3 is to get bits from bytes |
|
3651 |
__ lsrv(rscratch1, rscratch1, rscratch2); |
|
3652 |
__ tst(rscratch1, UPPER_BIT_MASK); |
|
3653 |
__ cset(result, Assembler::NE); |
|
3654 |
__ leave(); |
|
3655 |
__ ret(lr); |
|
3656 |
||
3657 |
Register tmp1 = r3, tmp2 = r4, tmp3 = r5, tmp4 = r6, tmp5 = r7, tmp6 = r10; |
|
3658 |
const RegSet spilled_regs = RegSet::range(tmp1, tmp5) + tmp6; |
|
3659 |
||
3660 |
has_negatives_long = __ pc(); // 2nd entry point |
|
3661 |
||
3662 |
__ enter(); |
|
3663 |
||
3664 |
__ bind(LEN_OVER_15); |
|
3665 |
__ push(spilled_regs, sp); |
|
3666 |
__ andr(rscratch2, ary1, 15); // check pointer for 16-byte alignment |
|
3667 |
__ cbz(rscratch2, ALIGNED); |
|
3668 |
__ ldp(tmp6, tmp1, Address(ary1)); |
|
3669 |
__ mov(tmp5, 16); |
|
3670 |
__ sub(rscratch1, tmp5, rscratch2); // amount of bytes until aligned address |
|
3671 |
__ add(ary1, ary1, rscratch1); |
|
3672 |
__ sub(len, len, rscratch1); |
|
3673 |
__ orr(tmp6, tmp6, tmp1); |
|
3674 |
__ tst(tmp6, UPPER_BIT_MASK); |
|
3675 |
__ br(Assembler::NE, RET_TRUE); |
|
3676 |
||
3677 |
__ bind(ALIGNED); |
|
3678 |
__ cmp(len, large_loop_size); |
|
3679 |
__ br(Assembler::LT, CHECK_16); |
|
3680 |
// Perform 16-byte load as early return in pre-loop to handle situation |
|
3681 |
// when initially aligned large array has negative values at starting bytes, |
|
3682 |
// so LARGE_LOOP would do 4 reads instead of 1 (in worst case), which is |
|
3683 |
// slower. Cases with negative bytes further ahead won't be affected that |
|
3684 |
// much. In fact, it'll be faster due to early loads, less instructions and |
|
3685 |
// less branches in LARGE_LOOP. |
|
3686 |
__ ldp(tmp6, tmp1, Address(__ post(ary1, 16))); |
|
3687 |
__ sub(len, len, 16); |
|
3688 |
__ orr(tmp6, tmp6, tmp1); |
|
3689 |
__ tst(tmp6, UPPER_BIT_MASK); |
|
3690 |
__ br(Assembler::NE, RET_TRUE); |
|
3691 |
__ cmp(len, large_loop_size); |
|
3692 |
__ br(Assembler::LT, CHECK_16); |
|
3693 |
||
3694 |
if (SoftwarePrefetchHintDistance >= 0 |
|
3695 |
&& SoftwarePrefetchHintDistance >= dcache_line) { |
|
3696 |
// initial prefetch |
|
3697 |
__ prfm(Address(ary1, SoftwarePrefetchHintDistance - dcache_line)); |
|
3698 |
} |
|
3699 |
__ bind(LARGE_LOOP); |
|
3700 |
if (SoftwarePrefetchHintDistance >= 0) { |
|
3701 |
__ prfm(Address(ary1, SoftwarePrefetchHintDistance)); |
|
3702 |
} |
|
3703 |
// Issue load instructions first, since it can save few CPU/MEM cycles, also |
|
3704 |
// instead of 4 triples of "orr(...), addr(...);cbnz(...);" (for each ldp) |
|
3705 |
// better generate 7 * orr(...) + 1 andr(...) + 1 cbnz(...) which saves 3 |
|
3706 |
// instructions per cycle and have less branches, but this approach disables |
|
3707 |
// early return, thus, all 64 bytes are loaded and checked every time. |
|
3708 |
__ ldp(tmp2, tmp3, Address(ary1)); |
|
3709 |
__ ldp(tmp4, tmp5, Address(ary1, 16)); |
|
3710 |
__ ldp(rscratch1, rscratch2, Address(ary1, 32)); |
|
3711 |
__ ldp(tmp6, tmp1, Address(ary1, 48)); |
|
3712 |
__ add(ary1, ary1, large_loop_size); |
|
3713 |
__ sub(len, len, large_loop_size); |
|
3714 |
__ orr(tmp2, tmp2, tmp3); |
|
3715 |
__ orr(tmp4, tmp4, tmp5); |
|
3716 |
__ orr(rscratch1, rscratch1, rscratch2); |
|
3717 |
__ orr(tmp6, tmp6, tmp1); |
|
3718 |
__ orr(tmp2, tmp2, tmp4); |
|
3719 |
__ orr(rscratch1, rscratch1, tmp6); |
|
3720 |
__ orr(tmp2, tmp2, rscratch1); |
|
3721 |
__ tst(tmp2, UPPER_BIT_MASK); |
|
3722 |
__ br(Assembler::NE, RET_TRUE); |
|
3723 |
__ cmp(len, large_loop_size); |
|
3724 |
__ br(Assembler::GE, LARGE_LOOP); |
|
3725 |
||
3726 |
__ bind(CHECK_16); // small 16-byte load pre-loop |
|
51374
7be0084191ed
8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents:
50758
diff
changeset
|
3727 |
__ cmp(len, (u1)16); |
46814 | 3728 |
__ br(Assembler::LT, POST_LOOP16); |
3729 |
||
3730 |
__ bind(LOOP16); // small 16-byte load loop |
|
3731 |
__ ldp(tmp2, tmp3, Address(__ post(ary1, 16))); |
|
3732 |
__ sub(len, len, 16); |
|
3733 |
__ orr(tmp2, tmp2, tmp3); |
|
3734 |
__ tst(tmp2, UPPER_BIT_MASK); |
|
3735 |
__ br(Assembler::NE, RET_TRUE); |
|
51374
7be0084191ed
8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents:
50758
diff
changeset
|
3736 |
__ cmp(len, (u1)16); |
46814 | 3737 |
__ br(Assembler::GE, LOOP16); // 16-byte load loop end |
3738 |
||
3739 |
__ bind(POST_LOOP16); // 16-byte aligned, so we can read unconditionally |
|
51374
7be0084191ed
8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents:
50758
diff
changeset
|
3740 |
__ cmp(len, (u1)8); |
46814 | 3741 |
__ br(Assembler::LE, POST_LOOP16_LOAD_TAIL); |
3742 |
__ ldr(tmp3, Address(__ post(ary1, 8))); |
|
3743 |
__ sub(len, len, 8); |
|
3744 |
__ tst(tmp3, UPPER_BIT_MASK); |
|
3745 |
__ br(Assembler::NE, RET_TRUE); |
|
3746 |
||
3747 |
__ bind(POST_LOOP16_LOAD_TAIL); |
|
3748 |
__ cbz(len, RET_FALSE); // Can't shift left by 64 when len==0 |
|
3749 |
__ ldr(tmp1, Address(ary1)); |
|
3750 |
__ mov(tmp2, 64); |
|
3751 |
__ sub(tmp4, tmp2, len, __ LSL, 3); |
|
3752 |
__ lslv(tmp1, tmp1, tmp4); |
|
3753 |
__ tst(tmp1, UPPER_BIT_MASK); |
|
3754 |
__ br(Assembler::NE, RET_TRUE); |
|
3755 |
// Fallthrough |
|
3756 |
||
3757 |
__ bind(RET_FALSE); |
|
3758 |
__ pop(spilled_regs, sp); |
|
3759 |
__ leave(); |
|
3760 |
__ mov(result, zr); |
|
3761 |
__ ret(lr); |
|
3762 |
||
3763 |
__ bind(RET_TRUE); |
|
3764 |
__ pop(spilled_regs, sp); |
|
3765 |
__ bind(RET_TRUE_NO_POP); |
|
3766 |
__ leave(); |
|
3767 |
__ mov(result, 1); |
|
3768 |
__ ret(lr); |
|
3769 |
||
3770 |
__ bind(DONE); |
|
3771 |
__ pop(spilled_regs, sp); |
|
3772 |
__ leave(); |
|
3773 |
__ ret(lr); |
|
3774 |
return entry; |
|
3775 |
} |
|
49724
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3776 |
|
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3777 |
void generate_large_array_equals_loop_nonsimd(int loopThreshold, |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3778 |
bool usePrefetch, Label &NOT_EQUAL) { |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3779 |
Register a1 = r1, a2 = r2, result = r0, cnt1 = r10, tmp1 = rscratch1, |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3780 |
tmp2 = rscratch2, tmp3 = r3, tmp4 = r4, tmp5 = r5, tmp6 = r11, |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3781 |
tmp7 = r12, tmp8 = r13; |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3782 |
Label LOOP; |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3783 |
|
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3784 |
__ ldp(tmp1, tmp3, Address(__ post(a1, 2 * wordSize))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3785 |
__ ldp(tmp2, tmp4, Address(__ post(a2, 2 * wordSize))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3786 |
__ bind(LOOP); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3787 |
if (usePrefetch) { |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3788 |
__ prfm(Address(a1, SoftwarePrefetchHintDistance)); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3789 |
__ prfm(Address(a2, SoftwarePrefetchHintDistance)); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3790 |
} |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3791 |
__ ldp(tmp5, tmp7, Address(__ post(a1, 2 * wordSize))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3792 |
__ eor(tmp1, tmp1, tmp2); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3793 |
__ eor(tmp3, tmp3, tmp4); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3794 |
__ ldp(tmp6, tmp8, Address(__ post(a2, 2 * wordSize))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3795 |
__ orr(tmp1, tmp1, tmp3); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3796 |
__ cbnz(tmp1, NOT_EQUAL); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3797 |
__ ldp(tmp1, tmp3, Address(__ post(a1, 2 * wordSize))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3798 |
__ eor(tmp5, tmp5, tmp6); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3799 |
__ eor(tmp7, tmp7, tmp8); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3800 |
__ ldp(tmp2, tmp4, Address(__ post(a2, 2 * wordSize))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3801 |
__ orr(tmp5, tmp5, tmp7); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3802 |
__ cbnz(tmp5, NOT_EQUAL); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3803 |
__ ldp(tmp5, tmp7, Address(__ post(a1, 2 * wordSize))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3804 |
__ eor(tmp1, tmp1, tmp2); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3805 |
__ eor(tmp3, tmp3, tmp4); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3806 |
__ ldp(tmp6, tmp8, Address(__ post(a2, 2 * wordSize))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3807 |
__ orr(tmp1, tmp1, tmp3); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3808 |
__ cbnz(tmp1, NOT_EQUAL); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3809 |
__ ldp(tmp1, tmp3, Address(__ post(a1, 2 * wordSize))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3810 |
__ eor(tmp5, tmp5, tmp6); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3811 |
__ sub(cnt1, cnt1, 8 * wordSize); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3812 |
__ eor(tmp7, tmp7, tmp8); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3813 |
__ ldp(tmp2, tmp4, Address(__ post(a2, 2 * wordSize))); |
50242
9a87afc49148
8203041: AArch64: fix overflow in immediate cmp/cmn instruction
fyang
parents:
50179
diff
changeset
|
3814 |
// tmp6 is not used. MacroAssembler::subs is used here (rather than |
9a87afc49148
8203041: AArch64: fix overflow in immediate cmp/cmn instruction
fyang
parents:
50179
diff
changeset
|
3815 |
// cmp) because subs allows an unlimited range of immediate operand. |
9a87afc49148
8203041: AArch64: fix overflow in immediate cmp/cmn instruction
fyang
parents:
50179
diff
changeset
|
3816 |
__ subs(tmp6, cnt1, loopThreshold); |
49724
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3817 |
__ orr(tmp5, tmp5, tmp7); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3818 |
__ cbnz(tmp5, NOT_EQUAL); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3819 |
__ br(__ GE, LOOP); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3820 |
// post-loop |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3821 |
__ eor(tmp1, tmp1, tmp2); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3822 |
__ eor(tmp3, tmp3, tmp4); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3823 |
__ orr(tmp1, tmp1, tmp3); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3824 |
__ sub(cnt1, cnt1, 2 * wordSize); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3825 |
__ cbnz(tmp1, NOT_EQUAL); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3826 |
} |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3827 |
|
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3828 |
void generate_large_array_equals_loop_simd(int loopThreshold, |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3829 |
bool usePrefetch, Label &NOT_EQUAL) { |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3830 |
Register a1 = r1, a2 = r2, result = r0, cnt1 = r10, tmp1 = rscratch1, |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3831 |
tmp2 = rscratch2; |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3832 |
Label LOOP; |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3833 |
|
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3834 |
__ bind(LOOP); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3835 |
if (usePrefetch) { |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3836 |
__ prfm(Address(a1, SoftwarePrefetchHintDistance)); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3837 |
__ prfm(Address(a2, SoftwarePrefetchHintDistance)); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3838 |
} |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3839 |
__ ld1(v0, v1, v2, v3, __ T2D, Address(__ post(a1, 4 * 2 * wordSize))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3840 |
__ sub(cnt1, cnt1, 8 * wordSize); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3841 |
__ ld1(v4, v5, v6, v7, __ T2D, Address(__ post(a2, 4 * 2 * wordSize))); |
50242
9a87afc49148
8203041: AArch64: fix overflow in immediate cmp/cmn instruction
fyang
parents:
50179
diff
changeset
|
3842 |
__ subs(tmp1, cnt1, loopThreshold); |
49724
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3843 |
__ eor(v0, __ T16B, v0, v4); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3844 |
__ eor(v1, __ T16B, v1, v5); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3845 |
__ eor(v2, __ T16B, v2, v6); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3846 |
__ eor(v3, __ T16B, v3, v7); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3847 |
__ orr(v0, __ T16B, v0, v1); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3848 |
__ orr(v1, __ T16B, v2, v3); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3849 |
__ orr(v0, __ T16B, v0, v1); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3850 |
__ umov(tmp1, v0, __ D, 0); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3851 |
__ umov(tmp2, v0, __ D, 1); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3852 |
__ orr(tmp1, tmp1, tmp2); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3853 |
__ cbnz(tmp1, NOT_EQUAL); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3854 |
__ br(__ GE, LOOP); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3855 |
} |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3856 |
|
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3857 |
// a1 = r1 - array1 address |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3858 |
// a2 = r2 - array2 address |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3859 |
// result = r0 - return value. Already contains "false" |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3860 |
// cnt1 = r10 - amount of elements left to check, reduced by wordSize |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3861 |
// r3-r5 are reserved temporary registers |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3862 |
address generate_large_array_equals() { |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3863 |
Register a1 = r1, a2 = r2, result = r0, cnt1 = r10, tmp1 = rscratch1, |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3864 |
tmp2 = rscratch2, tmp3 = r3, tmp4 = r4, tmp5 = r5, tmp6 = r11, |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3865 |
tmp7 = r12, tmp8 = r13; |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3866 |
Label TAIL, NOT_EQUAL, EQUAL, NOT_EQUAL_NO_POP, NO_PREFETCH_LARGE_LOOP, |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3867 |
SMALL_LOOP, POST_LOOP; |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3868 |
const int PRE_LOOP_SIZE = UseSIMDForArrayEquals ? 0 : 16; |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3869 |
// calculate if at least 32 prefetched bytes are used |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3870 |
int prefetchLoopThreshold = SoftwarePrefetchHintDistance + 32; |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3871 |
int nonPrefetchLoopThreshold = (64 + PRE_LOOP_SIZE); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3872 |
RegSet spilled_regs = RegSet::range(tmp6, tmp8); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3873 |
assert_different_registers(a1, a2, result, cnt1, tmp1, tmp2, tmp3, tmp4, |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3874 |
tmp5, tmp6, tmp7, tmp8); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3875 |
|
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3876 |
__ align(CodeEntryAlignment); |
52977
2e4903f83295
8205421: AARCH64: StubCodeMark should be placed after alignment
dpochepk
parents:
52927
diff
changeset
|
3877 |
|
2e4903f83295
8205421: AARCH64: StubCodeMark should be placed after alignment
dpochepk
parents:
52927
diff
changeset
|
3878 |
StubCodeMark mark(this, "StubRoutines", "large_array_equals"); |
2e4903f83295
8205421: AARCH64: StubCodeMark should be placed after alignment
dpochepk
parents:
52927
diff
changeset
|
3879 |
|
49724
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3880 |
address entry = __ pc(); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3881 |
__ enter(); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3882 |
__ sub(cnt1, cnt1, wordSize); // first 8 bytes were loaded outside of stub |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3883 |
// also advance pointers to use post-increment instead of pre-increment |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3884 |
__ add(a1, a1, wordSize); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3885 |
__ add(a2, a2, wordSize); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3886 |
if (AvoidUnalignedAccesses) { |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3887 |
// both implementations (SIMD/nonSIMD) are using relatively large load |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3888 |
// instructions (ld1/ldp), which has huge penalty (up to x2 exec time) |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3889 |
// on some CPUs in case of address is not at least 16-byte aligned. |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3890 |
// Arrays are 8-byte aligned currently, so, we can make additional 8-byte |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3891 |
// load if needed at least for 1st address and make if 16-byte aligned. |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3892 |
Label ALIGNED16; |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3893 |
__ tbz(a1, 3, ALIGNED16); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3894 |
__ ldr(tmp1, Address(__ post(a1, wordSize))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3895 |
__ ldr(tmp2, Address(__ post(a2, wordSize))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3896 |
__ sub(cnt1, cnt1, wordSize); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3897 |
__ eor(tmp1, tmp1, tmp2); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3898 |
__ cbnz(tmp1, NOT_EQUAL_NO_POP); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3899 |
__ bind(ALIGNED16); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3900 |
} |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3901 |
if (UseSIMDForArrayEquals) { |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3902 |
if (SoftwarePrefetchHintDistance >= 0) { |
50242
9a87afc49148
8203041: AArch64: fix overflow in immediate cmp/cmn instruction
fyang
parents:
50179
diff
changeset
|
3903 |
__ subs(tmp1, cnt1, prefetchLoopThreshold); |
49724
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3904 |
__ br(__ LE, NO_PREFETCH_LARGE_LOOP); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3905 |
generate_large_array_equals_loop_simd(prefetchLoopThreshold, |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3906 |
/* prfm = */ true, NOT_EQUAL); |
51374
7be0084191ed
8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents:
50758
diff
changeset
|
3907 |
__ subs(zr, cnt1, nonPrefetchLoopThreshold); |
49724
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3908 |
__ br(__ LT, TAIL); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3909 |
} |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3910 |
__ bind(NO_PREFETCH_LARGE_LOOP); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3911 |
generate_large_array_equals_loop_simd(nonPrefetchLoopThreshold, |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3912 |
/* prfm = */ false, NOT_EQUAL); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3913 |
} else { |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3914 |
__ push(spilled_regs, sp); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3915 |
if (SoftwarePrefetchHintDistance >= 0) { |
50242
9a87afc49148
8203041: AArch64: fix overflow in immediate cmp/cmn instruction
fyang
parents:
50179
diff
changeset
|
3916 |
__ subs(tmp1, cnt1, prefetchLoopThreshold); |
49724
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3917 |
__ br(__ LE, NO_PREFETCH_LARGE_LOOP); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3918 |
generate_large_array_equals_loop_nonsimd(prefetchLoopThreshold, |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3919 |
/* prfm = */ true, NOT_EQUAL); |
51374
7be0084191ed
8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents:
50758
diff
changeset
|
3920 |
__ subs(zr, cnt1, nonPrefetchLoopThreshold); |
49724
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3921 |
__ br(__ LT, TAIL); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3922 |
} |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3923 |
__ bind(NO_PREFETCH_LARGE_LOOP); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3924 |
generate_large_array_equals_loop_nonsimd(nonPrefetchLoopThreshold, |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3925 |
/* prfm = */ false, NOT_EQUAL); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3926 |
} |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3927 |
__ bind(TAIL); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3928 |
__ cbz(cnt1, EQUAL); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3929 |
__ subs(cnt1, cnt1, wordSize); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3930 |
__ br(__ LE, POST_LOOP); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3931 |
__ bind(SMALL_LOOP); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3932 |
__ ldr(tmp1, Address(__ post(a1, wordSize))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3933 |
__ ldr(tmp2, Address(__ post(a2, wordSize))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3934 |
__ subs(cnt1, cnt1, wordSize); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3935 |
__ eor(tmp1, tmp1, tmp2); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3936 |
__ cbnz(tmp1, NOT_EQUAL); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3937 |
__ br(__ GT, SMALL_LOOP); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3938 |
__ bind(POST_LOOP); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3939 |
__ ldr(tmp1, Address(a1, cnt1)); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3940 |
__ ldr(tmp2, Address(a2, cnt1)); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3941 |
__ eor(tmp1, tmp1, tmp2); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3942 |
__ cbnz(tmp1, NOT_EQUAL); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3943 |
__ bind(EQUAL); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3944 |
__ mov(result, true); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3945 |
__ bind(NOT_EQUAL); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3946 |
if (!UseSIMDForArrayEquals) { |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3947 |
__ pop(spilled_regs, sp); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3948 |
} |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3949 |
__ bind(NOT_EQUAL_NO_POP); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3950 |
__ leave(); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3951 |
__ ret(lr); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3952 |
return entry; |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3953 |
} |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3954 |
|
50754
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
3955 |
address generate_dsin_dcos(bool isCos) { |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
3956 |
__ align(CodeEntryAlignment); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
3957 |
StubCodeMark mark(this, "StubRoutines", isCos ? "libmDcos" : "libmDsin"); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
3958 |
address start = __ pc(); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
3959 |
__ generate_dsin_dcos(isCos, (address)StubRoutines::aarch64::_npio2_hw, |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
3960 |
(address)StubRoutines::aarch64::_two_over_pi, |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
3961 |
(address)StubRoutines::aarch64::_pio2, |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
3962 |
(address)StubRoutines::aarch64::_dsin_coef, |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
3963 |
(address)StubRoutines::aarch64::_dcos_coef); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
3964 |
return start; |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
3965 |
} |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
3966 |
|
50753 | 3967 |
address generate_dlog() { |
3968 |
__ align(CodeEntryAlignment); |
|
3969 |
StubCodeMark mark(this, "StubRoutines", "dlog"); |
|
3970 |
address entry = __ pc(); |
|
3971 |
FloatRegister vtmp0 = v0, vtmp1 = v1, vtmp2 = v2, vtmp3 = v3, vtmp4 = v4, |
|
3972 |
vtmp5 = v5, tmpC1 = v16, tmpC2 = v17, tmpC3 = v18, tmpC4 = v19; |
|
3973 |
Register tmp1 = r0, tmp2 = r1, tmp3 = r2, tmp4 = r3, tmp5 = r4; |
|
3974 |
__ fast_log(vtmp0, vtmp1, vtmp2, vtmp3, vtmp4, vtmp5, tmpC1, tmpC2, tmpC3, |
|
3975 |
tmpC4, tmp1, tmp2, tmp3, tmp4, tmp5); |
|
3976 |
return entry; |
|
3977 |
} |
|
49724
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
3978 |
|
50756
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
3979 |
// code for comparing 16 bytes of strings with same encoding |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
3980 |
void compare_string_16_bytes_same(Label &DIFF1, Label &DIFF2) { |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
3981 |
Register result = r0, str1 = r1, cnt1 = r2, str2 = r3, tmp1 = r10, tmp2 = r11; |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
3982 |
__ ldr(rscratch1, Address(__ post(str1, 8))); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
3983 |
__ eor(rscratch2, tmp1, tmp2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
3984 |
__ ldr(cnt1, Address(__ post(str2, 8))); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
3985 |
__ cbnz(rscratch2, DIFF1); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
3986 |
__ ldr(tmp1, Address(__ post(str1, 8))); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
3987 |
__ eor(rscratch2, rscratch1, cnt1); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
3988 |
__ ldr(tmp2, Address(__ post(str2, 8))); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
3989 |
__ cbnz(rscratch2, DIFF2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
3990 |
} |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
3991 |
|
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
3992 |
// code for comparing 16 characters of strings with Latin1 and Utf16 encoding |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
3993 |
void compare_string_16_x_LU(Register tmpL, Register tmpU, Label &DIFF1, |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
3994 |
Label &DIFF2) { |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
3995 |
Register cnt1 = r2, tmp1 = r10, tmp2 = r11, tmp3 = r12; |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
3996 |
FloatRegister vtmp = v1, vtmpZ = v0, vtmp3 = v2; |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
3997 |
|
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
3998 |
__ ldrq(vtmp, Address(__ post(tmp2, 16))); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
3999 |
__ ldr(tmpU, Address(__ post(cnt1, 8))); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4000 |
__ zip1(vtmp3, __ T16B, vtmp, vtmpZ); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4001 |
// now we have 32 bytes of characters (converted to U) in vtmp:vtmp3 |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4002 |
|
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4003 |
__ fmovd(tmpL, vtmp3); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4004 |
__ eor(rscratch2, tmp3, tmpL); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4005 |
__ cbnz(rscratch2, DIFF2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4006 |
|
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4007 |
__ ldr(tmp3, Address(__ post(cnt1, 8))); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4008 |
__ umov(tmpL, vtmp3, __ D, 1); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4009 |
__ eor(rscratch2, tmpU, tmpL); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4010 |
__ cbnz(rscratch2, DIFF1); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4011 |
|
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4012 |
__ zip2(vtmp, __ T16B, vtmp, vtmpZ); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4013 |
__ ldr(tmpU, Address(__ post(cnt1, 8))); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4014 |
__ fmovd(tmpL, vtmp); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4015 |
__ eor(rscratch2, tmp3, tmpL); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4016 |
__ cbnz(rscratch2, DIFF2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4017 |
|
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4018 |
__ ldr(tmp3, Address(__ post(cnt1, 8))); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4019 |
__ umov(tmpL, vtmp, __ D, 1); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4020 |
__ eor(rscratch2, tmpU, tmpL); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4021 |
__ cbnz(rscratch2, DIFF1); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4022 |
} |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4023 |
|
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4024 |
// r0 = result |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4025 |
// r1 = str1 |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4026 |
// r2 = cnt1 |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4027 |
// r3 = str2 |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4028 |
// r4 = cnt2 |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4029 |
// r10 = tmp1 |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4030 |
// r11 = tmp2 |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4031 |
address generate_compare_long_string_different_encoding(bool isLU) { |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4032 |
__ align(CodeEntryAlignment); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4033 |
StubCodeMark mark(this, "StubRoutines", isLU |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4034 |
? "compare_long_string_different_encoding LU" |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4035 |
: "compare_long_string_different_encoding UL"); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4036 |
address entry = __ pc(); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4037 |
Label SMALL_LOOP, TAIL, TAIL_LOAD_16, LOAD_LAST, DIFF1, DIFF2, |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4038 |
DONE, CALCULATE_DIFFERENCE, LARGE_LOOP_PREFETCH, SMALL_LOOP_ENTER, |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4039 |
LARGE_LOOP_PREFETCH_REPEAT1, LARGE_LOOP_PREFETCH_REPEAT2; |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4040 |
Register result = r0, str1 = r1, cnt1 = r2, str2 = r3, cnt2 = r4, |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4041 |
tmp1 = r10, tmp2 = r11, tmp3 = r12, tmp4 = r14; |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4042 |
FloatRegister vtmpZ = v0, vtmp = v1, vtmp3 = v2; |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4043 |
RegSet spilled_regs = RegSet::of(tmp3, tmp4); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4044 |
|
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4045 |
int prefetchLoopExitCondition = MAX(32, SoftwarePrefetchHintDistance/2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4046 |
|
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4047 |
__ eor(vtmpZ, __ T16B, vtmpZ, vtmpZ); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4048 |
// cnt2 == amount of characters left to compare |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4049 |
// Check already loaded first 4 symbols(vtmp and tmp2(LU)/tmp1(UL)) |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4050 |
__ zip1(vtmp, __ T8B, vtmp, vtmpZ); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4051 |
__ add(str1, str1, isLU ? wordSize/2 : wordSize); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4052 |
__ add(str2, str2, isLU ? wordSize : wordSize/2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4053 |
__ fmovd(isLU ? tmp1 : tmp2, vtmp); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4054 |
__ subw(cnt2, cnt2, 8); // Already loaded 4 symbols. Last 4 is special case. |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4055 |
__ add(str1, str1, cnt2, __ LSL, isLU ? 0 : 1); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4056 |
__ eor(rscratch2, tmp1, tmp2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4057 |
__ add(str2, str2, cnt2, __ LSL, isLU ? 1 : 0); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4058 |
__ mov(rscratch1, tmp2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4059 |
__ cbnz(rscratch2, CALCULATE_DIFFERENCE); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4060 |
Register strU = isLU ? str2 : str1, |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4061 |
strL = isLU ? str1 : str2, |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4062 |
tmpU = isLU ? rscratch1 : tmp1, // where to keep U for comparison |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4063 |
tmpL = isLU ? tmp1 : rscratch1; // where to keep L for comparison |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4064 |
__ push(spilled_regs, sp); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4065 |
__ sub(tmp2, strL, cnt2); // strL pointer to load from |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4066 |
__ sub(cnt1, strU, cnt2, __ LSL, 1); // strU pointer to load from |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4067 |
|
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4068 |
__ ldr(tmp3, Address(__ post(cnt1, 8))); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4069 |
|
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4070 |
if (SoftwarePrefetchHintDistance >= 0) { |
51374
7be0084191ed
8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents:
50758
diff
changeset
|
4071 |
__ subs(rscratch2, cnt2, prefetchLoopExitCondition); |
50756
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4072 |
__ br(__ LT, SMALL_LOOP); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4073 |
__ bind(LARGE_LOOP_PREFETCH); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4074 |
__ prfm(Address(tmp2, SoftwarePrefetchHintDistance)); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4075 |
__ mov(tmp4, 2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4076 |
__ prfm(Address(cnt1, SoftwarePrefetchHintDistance)); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4077 |
__ bind(LARGE_LOOP_PREFETCH_REPEAT1); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4078 |
compare_string_16_x_LU(tmpL, tmpU, DIFF1, DIFF2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4079 |
__ subs(tmp4, tmp4, 1); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4080 |
__ br(__ GT, LARGE_LOOP_PREFETCH_REPEAT1); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4081 |
__ prfm(Address(cnt1, SoftwarePrefetchHintDistance)); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4082 |
__ mov(tmp4, 2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4083 |
__ bind(LARGE_LOOP_PREFETCH_REPEAT2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4084 |
compare_string_16_x_LU(tmpL, tmpU, DIFF1, DIFF2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4085 |
__ subs(tmp4, tmp4, 1); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4086 |
__ br(__ GT, LARGE_LOOP_PREFETCH_REPEAT2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4087 |
__ sub(cnt2, cnt2, 64); |
51374
7be0084191ed
8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents:
50758
diff
changeset
|
4088 |
__ subs(rscratch2, cnt2, prefetchLoopExitCondition); |
50756
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4089 |
__ br(__ GE, LARGE_LOOP_PREFETCH); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4090 |
} |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4091 |
__ cbz(cnt2, LOAD_LAST); // no characters left except last load |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4092 |
__ subs(cnt2, cnt2, 16); |
7ad092f40454
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diff
changeset
|
4093 |
__ br(__ LT, TAIL); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4094 |
__ b(SMALL_LOOP_ENTER); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
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diff
changeset
|
4095 |
__ bind(SMALL_LOOP); // smaller loop |
7ad092f40454
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parents:
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diff
changeset
|
4096 |
__ subs(cnt2, cnt2, 16); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4097 |
__ bind(SMALL_LOOP_ENTER); |
7ad092f40454
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parents:
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diff
changeset
|
4098 |
compare_string_16_x_LU(tmpL, tmpU, DIFF1, DIFF2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4099 |
__ br(__ GE, SMALL_LOOP); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4100 |
__ cbz(cnt2, LOAD_LAST); |
7ad092f40454
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parents:
50755
diff
changeset
|
4101 |
__ bind(TAIL); // 1..15 characters left |
51374
7be0084191ed
8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents:
50758
diff
changeset
|
4102 |
__ subs(zr, cnt2, -8); |
50756
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
50755
diff
changeset
|
4103 |
__ br(__ GT, TAIL_LOAD_16); |
7ad092f40454
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parents:
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diff
changeset
|
4104 |
__ ldrd(vtmp, Address(tmp2)); |
7ad092f40454
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parents:
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diff
changeset
|
4105 |
__ zip1(vtmp3, __ T8B, vtmp, vtmpZ); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4106 |
|
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4107 |
__ ldr(tmpU, Address(__ post(cnt1, 8))); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4108 |
__ fmovd(tmpL, vtmp3); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
50755
diff
changeset
|
4109 |
__ eor(rscratch2, tmp3, tmpL); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
50755
diff
changeset
|
4110 |
__ cbnz(rscratch2, DIFF2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
50755
diff
changeset
|
4111 |
__ umov(tmpL, vtmp3, __ D, 1); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
50755
diff
changeset
|
4112 |
__ eor(rscratch2, tmpU, tmpL); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4113 |
__ cbnz(rscratch2, DIFF1); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
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diff
changeset
|
4114 |
__ b(LOAD_LAST); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4115 |
__ bind(TAIL_LOAD_16); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4116 |
__ ldrq(vtmp, Address(tmp2)); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4117 |
__ ldr(tmpU, Address(__ post(cnt1, 8))); |
7ad092f40454
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parents:
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diff
changeset
|
4118 |
__ zip1(vtmp3, __ T16B, vtmp, vtmpZ); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
50755
diff
changeset
|
4119 |
__ zip2(vtmp, __ T16B, vtmp, vtmpZ); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4120 |
__ fmovd(tmpL, vtmp3); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4121 |
__ eor(rscratch2, tmp3, tmpL); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4122 |
__ cbnz(rscratch2, DIFF2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
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diff
changeset
|
4123 |
|
7ad092f40454
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parents:
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diff
changeset
|
4124 |
__ ldr(tmp3, Address(__ post(cnt1, 8))); |
7ad092f40454
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parents:
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diff
changeset
|
4125 |
__ umov(tmpL, vtmp3, __ D, 1); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4126 |
__ eor(rscratch2, tmpU, tmpL); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4127 |
__ cbnz(rscratch2, DIFF1); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
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diff
changeset
|
4128 |
|
7ad092f40454
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parents:
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diff
changeset
|
4129 |
__ ldr(tmpU, Address(__ post(cnt1, 8))); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
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diff
changeset
|
4130 |
__ fmovd(tmpL, vtmp); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4131 |
__ eor(rscratch2, tmp3, tmpL); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4132 |
__ cbnz(rscratch2, DIFF2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
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diff
changeset
|
4133 |
|
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4134 |
__ umov(tmpL, vtmp, __ D, 1); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4135 |
__ eor(rscratch2, tmpU, tmpL); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4136 |
__ cbnz(rscratch2, DIFF1); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4137 |
__ b(LOAD_LAST); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4138 |
__ bind(DIFF2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4139 |
__ mov(tmpU, tmp3); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4140 |
__ bind(DIFF1); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4141 |
__ pop(spilled_regs, sp); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4142 |
__ b(CALCULATE_DIFFERENCE); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4143 |
__ bind(LOAD_LAST); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4144 |
__ pop(spilled_regs, sp); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4145 |
|
7ad092f40454
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parents:
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diff
changeset
|
4146 |
__ ldrs(vtmp, Address(strL)); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
50755
diff
changeset
|
4147 |
__ ldr(tmpU, Address(strU)); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4148 |
__ zip1(vtmp, __ T8B, vtmp, vtmpZ); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4149 |
__ fmovd(tmpL, vtmp); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4150 |
|
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
50755
diff
changeset
|
4151 |
__ eor(rscratch2, tmpU, tmpL); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4152 |
__ cbz(rscratch2, DONE); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4153 |
|
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4154 |
// Find the first different characters in the longwords and |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4155 |
// compute their difference. |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4156 |
__ bind(CALCULATE_DIFFERENCE); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4157 |
__ rev(rscratch2, rscratch2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4158 |
__ clz(rscratch2, rscratch2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4159 |
__ andr(rscratch2, rscratch2, -16); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4160 |
__ lsrv(tmp1, tmp1, rscratch2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4161 |
__ uxthw(tmp1, tmp1); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4162 |
__ lsrv(rscratch1, rscratch1, rscratch2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4163 |
__ uxthw(rscratch1, rscratch1); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4164 |
__ subw(result, tmp1, rscratch1); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4165 |
__ bind(DONE); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4166 |
__ ret(lr); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4167 |
return entry; |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4168 |
} |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4169 |
|
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
50755
diff
changeset
|
4170 |
// r0 = result |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4171 |
// r1 = str1 |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4172 |
// r2 = cnt1 |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4173 |
// r3 = str2 |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4174 |
// r4 = cnt2 |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4175 |
// r10 = tmp1 |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
50755
diff
changeset
|
4176 |
// r11 = tmp2 |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
50755
diff
changeset
|
4177 |
address generate_compare_long_string_same_encoding(bool isLL) { |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4178 |
__ align(CodeEntryAlignment); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4179 |
StubCodeMark mark(this, "StubRoutines", isLL |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4180 |
? "compare_long_string_same_encoding LL" |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4181 |
: "compare_long_string_same_encoding UU"); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4182 |
address entry = __ pc(); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4183 |
Register result = r0, str1 = r1, cnt1 = r2, str2 = r3, cnt2 = r4, |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4184 |
tmp1 = r10, tmp2 = r11; |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4185 |
Label SMALL_LOOP, LARGE_LOOP_PREFETCH, CHECK_LAST, DIFF2, TAIL, |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4186 |
LENGTH_DIFF, DIFF, LAST_CHECK_AND_LENGTH_DIFF, |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4187 |
DIFF_LAST_POSITION, DIFF_LAST_POSITION2; |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4188 |
// exit from large loop when less than 64 bytes left to read or we're about |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4189 |
// to prefetch memory behind array border |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4190 |
int largeLoopExitCondition = MAX(64, SoftwarePrefetchHintDistance)/(isLL ? 1 : 2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4191 |
// cnt1/cnt2 contains amount of characters to compare. cnt1 can be re-used |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4192 |
// update cnt2 counter with already loaded 8 bytes |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4193 |
__ sub(cnt2, cnt2, wordSize/(isLL ? 1 : 2)); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4194 |
// update pointers, because of previous read |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4195 |
__ add(str1, str1, wordSize); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4196 |
__ add(str2, str2, wordSize); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4197 |
if (SoftwarePrefetchHintDistance >= 0) { |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4198 |
__ bind(LARGE_LOOP_PREFETCH); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4199 |
__ prfm(Address(str1, SoftwarePrefetchHintDistance)); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4200 |
__ prfm(Address(str2, SoftwarePrefetchHintDistance)); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4201 |
compare_string_16_bytes_same(DIFF, DIFF2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4202 |
compare_string_16_bytes_same(DIFF, DIFF2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4203 |
__ sub(cnt2, cnt2, isLL ? 64 : 32); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4204 |
compare_string_16_bytes_same(DIFF, DIFF2); |
51374
7be0084191ed
8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents:
50758
diff
changeset
|
4205 |
__ subs(rscratch2, cnt2, largeLoopExitCondition); |
50756
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4206 |
compare_string_16_bytes_same(DIFF, DIFF2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4207 |
__ br(__ GT, LARGE_LOOP_PREFETCH); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4208 |
__ cbz(cnt2, LAST_CHECK_AND_LENGTH_DIFF); // no more chars left? |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4209 |
// less than 16 bytes left? |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4210 |
__ subs(cnt2, cnt2, isLL ? 16 : 8); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4211 |
__ br(__ LT, TAIL); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4212 |
} |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4213 |
__ bind(SMALL_LOOP); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4214 |
compare_string_16_bytes_same(DIFF, DIFF2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4215 |
__ subs(cnt2, cnt2, isLL ? 16 : 8); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4216 |
__ br(__ GE, SMALL_LOOP); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4217 |
__ bind(TAIL); |
7ad092f40454
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diff
changeset
|
4218 |
__ adds(cnt2, cnt2, isLL ? 16 : 8); |
7ad092f40454
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parents:
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diff
changeset
|
4219 |
__ br(__ EQ, LAST_CHECK_AND_LENGTH_DIFF); |
7ad092f40454
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parents:
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diff
changeset
|
4220 |
__ subs(cnt2, cnt2, isLL ? 8 : 4); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
50755
diff
changeset
|
4221 |
__ br(__ LE, CHECK_LAST); |
7ad092f40454
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parents:
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diff
changeset
|
4222 |
__ eor(rscratch2, tmp1, tmp2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
50755
diff
changeset
|
4223 |
__ cbnz(rscratch2, DIFF); |
7ad092f40454
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parents:
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diff
changeset
|
4224 |
__ ldr(tmp1, Address(__ post(str1, 8))); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4225 |
__ ldr(tmp2, Address(__ post(str2, 8))); |
7ad092f40454
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parents:
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diff
changeset
|
4226 |
__ sub(cnt2, cnt2, isLL ? 8 : 4); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
50755
diff
changeset
|
4227 |
__ bind(CHECK_LAST); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4228 |
if (!isLL) { |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4229 |
__ add(cnt2, cnt2, cnt2); // now in bytes |
7ad092f40454
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parents:
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diff
changeset
|
4230 |
} |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4231 |
__ eor(rscratch2, tmp1, tmp2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4232 |
__ cbnz(rscratch2, DIFF); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4233 |
__ ldr(rscratch1, Address(str1, cnt2)); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4234 |
__ ldr(cnt1, Address(str2, cnt2)); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4235 |
__ eor(rscratch2, rscratch1, cnt1); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
50755
diff
changeset
|
4236 |
__ cbz(rscratch2, LENGTH_DIFF); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
50755
diff
changeset
|
4237 |
// Find the first different characters in the longwords and |
7ad092f40454
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parents:
50755
diff
changeset
|
4238 |
// compute their difference. |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4239 |
__ bind(DIFF2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4240 |
__ rev(rscratch2, rscratch2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4241 |
__ clz(rscratch2, rscratch2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4242 |
__ andr(rscratch2, rscratch2, isLL ? -8 : -16); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
50755
diff
changeset
|
4243 |
__ lsrv(rscratch1, rscratch1, rscratch2); |
7ad092f40454
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parents:
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diff
changeset
|
4244 |
if (isLL) { |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4245 |
__ lsrv(cnt1, cnt1, rscratch2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4246 |
__ uxtbw(rscratch1, rscratch1); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4247 |
__ uxtbw(cnt1, cnt1); |
7ad092f40454
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parents:
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diff
changeset
|
4248 |
} else { |
7ad092f40454
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parents:
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diff
changeset
|
4249 |
__ lsrv(cnt1, cnt1, rscratch2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4250 |
__ uxthw(rscratch1, rscratch1); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4251 |
__ uxthw(cnt1, cnt1); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4252 |
} |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4253 |
__ subw(result, rscratch1, cnt1); |
7ad092f40454
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parents:
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diff
changeset
|
4254 |
__ b(LENGTH_DIFF); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4255 |
__ bind(DIFF); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4256 |
__ rev(rscratch2, rscratch2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
50755
diff
changeset
|
4257 |
__ clz(rscratch2, rscratch2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
50755
diff
changeset
|
4258 |
__ andr(rscratch2, rscratch2, isLL ? -8 : -16); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4259 |
__ lsrv(tmp1, tmp1, rscratch2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4260 |
if (isLL) { |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
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diff
changeset
|
4261 |
__ lsrv(tmp2, tmp2, rscratch2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4262 |
__ uxtbw(tmp1, tmp1); |
7ad092f40454
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dpochepk
parents:
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diff
changeset
|
4263 |
__ uxtbw(tmp2, tmp2); |
7ad092f40454
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parents:
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diff
changeset
|
4264 |
} else { |
7ad092f40454
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parents:
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diff
changeset
|
4265 |
__ lsrv(tmp2, tmp2, rscratch2); |
7ad092f40454
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parents:
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diff
changeset
|
4266 |
__ uxthw(tmp1, tmp1); |
7ad092f40454
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parents:
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diff
changeset
|
4267 |
__ uxthw(tmp2, tmp2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4268 |
} |
7ad092f40454
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parents:
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diff
changeset
|
4269 |
__ subw(result, tmp1, tmp2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4270 |
__ b(LENGTH_DIFF); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4271 |
__ bind(LAST_CHECK_AND_LENGTH_DIFF); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4272 |
__ eor(rscratch2, tmp1, tmp2); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4273 |
__ cbnz(rscratch2, DIFF); |
7ad092f40454
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parents:
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diff
changeset
|
4274 |
__ bind(LENGTH_DIFF); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
50755
diff
changeset
|
4275 |
__ ret(lr); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
4276 |
return entry; |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
50755
diff
changeset
|
4277 |
} |
7ad092f40454
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parents:
50755
diff
changeset
|
4278 |
|
7ad092f40454
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parents:
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diff
changeset
|
4279 |
void generate_compare_long_strings() { |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
50755
diff
changeset
|
4280 |
StubRoutines::aarch64::_compare_long_string_LL |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4281 |
= generate_compare_long_string_same_encoding(true); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4282 |
StubRoutines::aarch64::_compare_long_string_UU |
7ad092f40454
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diff
changeset
|
4283 |
= generate_compare_long_string_same_encoding(false); |
7ad092f40454
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diff
changeset
|
4284 |
StubRoutines::aarch64::_compare_long_string_LU |
7ad092f40454
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diff
changeset
|
4285 |
= generate_compare_long_string_different_encoding(true); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
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diff
changeset
|
4286 |
StubRoutines::aarch64::_compare_long_string_UL |
7ad092f40454
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diff
changeset
|
4287 |
= generate_compare_long_string_different_encoding(false); |
7ad092f40454
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parents:
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diff
changeset
|
4288 |
} |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
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parents:
50755
diff
changeset
|
4289 |
|
50757
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
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parents:
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diff
changeset
|
4290 |
// R0 = result |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
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parents:
50756
diff
changeset
|
4291 |
// R1 = str2 |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
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parents:
50756
diff
changeset
|
4292 |
// R2 = cnt1 |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
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parents:
50756
diff
changeset
|
4293 |
// R3 = str1 |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
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parents:
50756
diff
changeset
|
4294 |
// R4 = cnt2 |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
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parents:
50756
diff
changeset
|
4295 |
// This generic linear code use few additional ideas, which makes it faster: |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4296 |
// 1) we can safely keep at least 1st register of pattern(since length >= 8) |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
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parents:
50756
diff
changeset
|
4297 |
// in order to skip initial loading(help in systems with 1 ld pipeline) |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
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parents:
50756
diff
changeset
|
4298 |
// 2) we can use "fast" algorithm of finding single character to search for |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4299 |
// first symbol with less branches(1 branch per each loaded register instead |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4300 |
// of branch for each symbol), so, this is where constants like |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4301 |
// 0x0101...01, 0x00010001...0001, 0x7f7f...7f, 0x7fff7fff...7fff comes from |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4302 |
// 3) after loading and analyzing 1st register of source string, it can be |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4303 |
// used to search for every 1st character entry, saving few loads in |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4304 |
// comparison with "simplier-but-slower" implementation |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4305 |
// 4) in order to avoid lots of push/pop operations, code below is heavily |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4306 |
// re-using/re-initializing/compressing register values, which makes code |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4307 |
// larger and a bit less readable, however, most of extra operations are |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4308 |
// issued during loads or branches, so, penalty is minimal |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4309 |
address generate_string_indexof_linear(bool str1_isL, bool str2_isL) { |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4310 |
const char* stubName = str1_isL |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4311 |
? (str2_isL ? "indexof_linear_ll" : "indexof_linear_ul") |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4312 |
: "indexof_linear_uu"; |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4313 |
__ align(CodeEntryAlignment); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4314 |
StubCodeMark mark(this, "StubRoutines", stubName); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4315 |
address entry = __ pc(); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4316 |
|
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4317 |
int str1_chr_size = str1_isL ? 1 : 2; |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4318 |
int str2_chr_size = str2_isL ? 1 : 2; |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
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diff
changeset
|
4319 |
int str1_chr_shift = str1_isL ? 0 : 1; |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
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diff
changeset
|
4320 |
int str2_chr_shift = str2_isL ? 0 : 1; |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4321 |
bool isL = str1_isL && str2_isL; |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4322 |
// parameters |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4323 |
Register result = r0, str2 = r1, cnt1 = r2, str1 = r3, cnt2 = r4; |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
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diff
changeset
|
4324 |
// temporary registers |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4325 |
Register tmp1 = r20, tmp2 = r21, tmp3 = r22, tmp4 = r23; |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4326 |
RegSet spilled_regs = RegSet::range(tmp1, tmp4); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4327 |
// redefinitions |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4328 |
Register ch1 = rscratch1, ch2 = rscratch2, first = tmp3; |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4329 |
|
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4330 |
__ push(spilled_regs, sp); |
51756 | 4331 |
Label L_LOOP, L_LOOP_PROCEED, L_SMALL, L_HAS_ZERO, |
50757
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4332 |
L_HAS_ZERO_LOOP, L_CMP_LOOP, L_CMP_LOOP_NOMATCH, L_SMALL_PROCEED, |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4333 |
L_SMALL_HAS_ZERO_LOOP, L_SMALL_CMP_LOOP_NOMATCH, L_SMALL_CMP_LOOP, |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4334 |
L_POST_LOOP, L_CMP_LOOP_LAST_CMP, L_HAS_ZERO_LOOP_NOMATCH, |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4335 |
L_SMALL_CMP_LOOP_LAST_CMP, L_SMALL_CMP_LOOP_LAST_CMP2, |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4336 |
L_CMP_LOOP_LAST_CMP2, DONE, NOMATCH; |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4337 |
// Read whole register from str1. It is safe, because length >=8 here |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4338 |
__ ldr(ch1, Address(str1)); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4339 |
// Read whole register from str2. It is safe, because length >=8 here |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4340 |
__ ldr(ch2, Address(str2)); |
54990
cbc557f166f2
8215792: AArch64: String.indexOf generates incorrect result
dpochepk
parents:
54979
diff
changeset
|
4341 |
__ sub(cnt2, cnt2, cnt1); |
50757
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4342 |
__ andr(first, ch1, str1_isL ? 0xFF : 0xFFFF); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4343 |
if (str1_isL != str2_isL) { |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4344 |
__ eor(v0, __ T16B, v0, v0); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4345 |
} |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4346 |
__ mov(tmp1, str2_isL ? 0x0101010101010101 : 0x0001000100010001); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4347 |
__ mul(first, first, tmp1); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4348 |
// check if we have less than 1 register to check |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4349 |
__ subs(cnt2, cnt2, wordSize/str2_chr_size - 1); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4350 |
if (str1_isL != str2_isL) { |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4351 |
__ fmovd(v1, ch1); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4352 |
} |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4353 |
__ br(__ LE, L_SMALL); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4354 |
__ eor(ch2, first, ch2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4355 |
if (str1_isL != str2_isL) { |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4356 |
__ zip1(v1, __ T16B, v1, v0); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4357 |
} |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4358 |
__ sub(tmp2, ch2, tmp1); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4359 |
__ orr(ch2, ch2, str2_isL ? 0x7f7f7f7f7f7f7f7f : 0x7fff7fff7fff7fff); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4360 |
__ bics(tmp2, tmp2, ch2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4361 |
if (str1_isL != str2_isL) { |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4362 |
__ fmovd(ch1, v1); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4363 |
} |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4364 |
__ br(__ NE, L_HAS_ZERO); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4365 |
__ subs(cnt2, cnt2, wordSize/str2_chr_size); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4366 |
__ add(result, result, wordSize/str2_chr_size); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4367 |
__ add(str2, str2, wordSize); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4368 |
__ br(__ LT, L_POST_LOOP); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4369 |
__ BIND(L_LOOP); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4370 |
__ ldr(ch2, Address(str2)); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4371 |
__ eor(ch2, first, ch2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4372 |
__ sub(tmp2, ch2, tmp1); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4373 |
__ orr(ch2, ch2, str2_isL ? 0x7f7f7f7f7f7f7f7f : 0x7fff7fff7fff7fff); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4374 |
__ bics(tmp2, tmp2, ch2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4375 |
__ br(__ NE, L_HAS_ZERO); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4376 |
__ BIND(L_LOOP_PROCEED); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4377 |
__ subs(cnt2, cnt2, wordSize/str2_chr_size); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4378 |
__ add(str2, str2, wordSize); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4379 |
__ add(result, result, wordSize/str2_chr_size); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4380 |
__ br(__ GE, L_LOOP); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4381 |
__ BIND(L_POST_LOOP); |
51374
7be0084191ed
8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents:
50758
diff
changeset
|
4382 |
__ subs(zr, cnt2, -wordSize/str2_chr_size); // no extra characters to check |
50757
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4383 |
__ br(__ LE, NOMATCH); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4384 |
__ ldr(ch2, Address(str2)); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4385 |
__ sub(cnt2, zr, cnt2, __ LSL, LogBitsPerByte + str2_chr_shift); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4386 |
__ eor(ch2, first, ch2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4387 |
__ sub(tmp2, ch2, tmp1); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4388 |
__ orr(ch2, ch2, str2_isL ? 0x7f7f7f7f7f7f7f7f : 0x7fff7fff7fff7fff); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4389 |
__ mov(tmp4, -1); // all bits set |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4390 |
__ b(L_SMALL_PROCEED); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4391 |
__ align(OptoLoopAlignment); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4392 |
__ BIND(L_SMALL); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4393 |
__ sub(cnt2, zr, cnt2, __ LSL, LogBitsPerByte + str2_chr_shift); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4394 |
__ eor(ch2, first, ch2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4395 |
if (str1_isL != str2_isL) { |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4396 |
__ zip1(v1, __ T16B, v1, v0); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4397 |
} |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4398 |
__ sub(tmp2, ch2, tmp1); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4399 |
__ mov(tmp4, -1); // all bits set |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4400 |
__ orr(ch2, ch2, str2_isL ? 0x7f7f7f7f7f7f7f7f : 0x7fff7fff7fff7fff); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4401 |
if (str1_isL != str2_isL) { |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4402 |
__ fmovd(ch1, v1); // move converted 4 symbols |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4403 |
} |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4404 |
__ BIND(L_SMALL_PROCEED); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4405 |
__ lsrv(tmp4, tmp4, cnt2); // mask. zeroes on useless bits. |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4406 |
__ bic(tmp2, tmp2, ch2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4407 |
__ ands(tmp2, tmp2, tmp4); // clear useless bits and check |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4408 |
__ rbit(tmp2, tmp2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4409 |
__ br(__ EQ, NOMATCH); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4410 |
__ BIND(L_SMALL_HAS_ZERO_LOOP); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4411 |
__ clz(tmp4, tmp2); // potentially long. Up to 4 cycles on some cpu's |
51374
7be0084191ed
8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents:
50758
diff
changeset
|
4412 |
__ cmp(cnt1, u1(wordSize/str2_chr_size)); |
50757
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4413 |
__ br(__ LE, L_SMALL_CMP_LOOP_LAST_CMP2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4414 |
if (str2_isL) { // LL |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4415 |
__ add(str2, str2, tmp4, __ LSR, LogBitsPerByte); // address of "index" |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4416 |
__ ldr(ch2, Address(str2)); // read whole register of str2. Safe. |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4417 |
__ lslv(tmp2, tmp2, tmp4); // shift off leading zeroes from match info |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4418 |
__ add(result, result, tmp4, __ LSR, LogBitsPerByte); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4419 |
__ lsl(tmp2, tmp2, 1); // shift off leading "1" from match info |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4420 |
} else { |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4421 |
__ mov(ch2, 0xE); // all bits in byte set except last one |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4422 |
__ andr(ch2, ch2, tmp4, __ LSR, LogBitsPerByte); // byte shift amount |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4423 |
__ ldr(ch2, Address(str2, ch2)); // read whole register of str2. Safe. |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4424 |
__ lslv(tmp2, tmp2, tmp4); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4425 |
__ add(result, result, tmp4, __ LSR, LogBitsPerByte + str2_chr_shift); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4426 |
__ add(str2, str2, tmp4, __ LSR, LogBitsPerByte + str2_chr_shift); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4427 |
__ lsl(tmp2, tmp2, 1); // shift off leading "1" from match info |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4428 |
__ add(str2, str2, tmp4, __ LSR, LogBitsPerByte + str2_chr_shift); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4429 |
} |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4430 |
__ cmp(ch1, ch2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4431 |
__ mov(tmp4, wordSize/str2_chr_size); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4432 |
__ br(__ NE, L_SMALL_CMP_LOOP_NOMATCH); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4433 |
__ BIND(L_SMALL_CMP_LOOP); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4434 |
str1_isL ? __ ldrb(first, Address(str1, tmp4, Address::lsl(str1_chr_shift))) |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4435 |
: __ ldrh(first, Address(str1, tmp4, Address::lsl(str1_chr_shift))); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4436 |
str2_isL ? __ ldrb(ch2, Address(str2, tmp4, Address::lsl(str2_chr_shift))) |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4437 |
: __ ldrh(ch2, Address(str2, tmp4, Address::lsl(str2_chr_shift))); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4438 |
__ add(tmp4, tmp4, 1); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4439 |
__ cmp(tmp4, cnt1); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4440 |
__ br(__ GE, L_SMALL_CMP_LOOP_LAST_CMP); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4441 |
__ cmp(first, ch2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4442 |
__ br(__ EQ, L_SMALL_CMP_LOOP); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4443 |
__ BIND(L_SMALL_CMP_LOOP_NOMATCH); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4444 |
__ cbz(tmp2, NOMATCH); // no more matches. exit |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4445 |
__ clz(tmp4, tmp2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4446 |
__ add(result, result, 1); // advance index |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4447 |
__ add(str2, str2, str2_chr_size); // advance pointer |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4448 |
__ b(L_SMALL_HAS_ZERO_LOOP); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4449 |
__ align(OptoLoopAlignment); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4450 |
__ BIND(L_SMALL_CMP_LOOP_LAST_CMP); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4451 |
__ cmp(first, ch2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4452 |
__ br(__ NE, L_SMALL_CMP_LOOP_NOMATCH); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4453 |
__ b(DONE); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4454 |
__ align(OptoLoopAlignment); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4455 |
__ BIND(L_SMALL_CMP_LOOP_LAST_CMP2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4456 |
if (str2_isL) { // LL |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4457 |
__ add(str2, str2, tmp4, __ LSR, LogBitsPerByte); // address of "index" |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4458 |
__ ldr(ch2, Address(str2)); // read whole register of str2. Safe. |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4459 |
__ lslv(tmp2, tmp2, tmp4); // shift off leading zeroes from match info |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4460 |
__ add(result, result, tmp4, __ LSR, LogBitsPerByte); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4461 |
__ lsl(tmp2, tmp2, 1); // shift off leading "1" from match info |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4462 |
} else { |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4463 |
__ mov(ch2, 0xE); // all bits in byte set except last one |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4464 |
__ andr(ch2, ch2, tmp4, __ LSR, LogBitsPerByte); // byte shift amount |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4465 |
__ ldr(ch2, Address(str2, ch2)); // read whole register of str2. Safe. |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4466 |
__ lslv(tmp2, tmp2, tmp4); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4467 |
__ add(result, result, tmp4, __ LSR, LogBitsPerByte + str2_chr_shift); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4468 |
__ add(str2, str2, tmp4, __ LSR, LogBitsPerByte + str2_chr_shift); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4469 |
__ lsl(tmp2, tmp2, 1); // shift off leading "1" from match info |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4470 |
__ add(str2, str2, tmp4, __ LSR, LogBitsPerByte + str2_chr_shift); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4471 |
} |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4472 |
__ cmp(ch1, ch2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4473 |
__ br(__ NE, L_SMALL_CMP_LOOP_NOMATCH); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4474 |
__ b(DONE); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4475 |
__ align(OptoLoopAlignment); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4476 |
__ BIND(L_HAS_ZERO); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4477 |
__ rbit(tmp2, tmp2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4478 |
__ clz(tmp4, tmp2); // potentially long. Up to 4 cycles on some CPU's |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4479 |
// Now, perform compression of counters(cnt2 and cnt1) into one register. |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4480 |
// It's fine because both counters are 32bit and are not changed in this |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4481 |
// loop. Just restore it on exit. So, cnt1 can be re-used in this loop. |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4482 |
__ orr(cnt2, cnt2, cnt1, __ LSL, BitsPerByte * wordSize / 2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4483 |
__ sub(result, result, 1); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4484 |
__ BIND(L_HAS_ZERO_LOOP); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4485 |
__ mov(cnt1, wordSize/str2_chr_size); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4486 |
__ cmp(cnt1, cnt2, __ LSR, BitsPerByte * wordSize / 2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4487 |
__ br(__ GE, L_CMP_LOOP_LAST_CMP2); // case of 8 bytes only to compare |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4488 |
if (str2_isL) { |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4489 |
__ lsr(ch2, tmp4, LogBitsPerByte + str2_chr_shift); // char index |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4490 |
__ ldr(ch2, Address(str2, ch2)); // read whole register of str2. Safe. |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4491 |
__ lslv(tmp2, tmp2, tmp4); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4492 |
__ add(str2, str2, tmp4, __ LSR, LogBitsPerByte + str2_chr_shift); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4493 |
__ add(tmp4, tmp4, 1); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4494 |
__ add(result, result, tmp4, __ LSR, LogBitsPerByte + str2_chr_shift); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4495 |
__ lsl(tmp2, tmp2, 1); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4496 |
__ mov(tmp4, wordSize/str2_chr_size); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4497 |
} else { |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4498 |
__ mov(ch2, 0xE); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4499 |
__ andr(ch2, ch2, tmp4, __ LSR, LogBitsPerByte); // byte shift amount |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4500 |
__ ldr(ch2, Address(str2, ch2)); // read whole register of str2. Safe. |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4501 |
__ lslv(tmp2, tmp2, tmp4); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4502 |
__ add(tmp4, tmp4, 1); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4503 |
__ add(result, result, tmp4, __ LSR, LogBitsPerByte + str2_chr_shift); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4504 |
__ add(str2, str2, tmp4, __ LSR, LogBitsPerByte); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4505 |
__ lsl(tmp2, tmp2, 1); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4506 |
__ mov(tmp4, wordSize/str2_chr_size); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4507 |
__ sub(str2, str2, str2_chr_size); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4508 |
} |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4509 |
__ cmp(ch1, ch2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4510 |
__ mov(tmp4, wordSize/str2_chr_size); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4511 |
__ br(__ NE, L_CMP_LOOP_NOMATCH); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4512 |
__ BIND(L_CMP_LOOP); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4513 |
str1_isL ? __ ldrb(cnt1, Address(str1, tmp4, Address::lsl(str1_chr_shift))) |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4514 |
: __ ldrh(cnt1, Address(str1, tmp4, Address::lsl(str1_chr_shift))); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4515 |
str2_isL ? __ ldrb(ch2, Address(str2, tmp4, Address::lsl(str2_chr_shift))) |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4516 |
: __ ldrh(ch2, Address(str2, tmp4, Address::lsl(str2_chr_shift))); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4517 |
__ add(tmp4, tmp4, 1); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4518 |
__ cmp(tmp4, cnt2, __ LSR, BitsPerByte * wordSize / 2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4519 |
__ br(__ GE, L_CMP_LOOP_LAST_CMP); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4520 |
__ cmp(cnt1, ch2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4521 |
__ br(__ EQ, L_CMP_LOOP); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4522 |
__ BIND(L_CMP_LOOP_NOMATCH); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4523 |
// here we're not matched |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4524 |
__ cbz(tmp2, L_HAS_ZERO_LOOP_NOMATCH); // no more matches. Proceed to main loop |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4525 |
__ clz(tmp4, tmp2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4526 |
__ add(str2, str2, str2_chr_size); // advance pointer |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4527 |
__ b(L_HAS_ZERO_LOOP); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4528 |
__ align(OptoLoopAlignment); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4529 |
__ BIND(L_CMP_LOOP_LAST_CMP); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4530 |
__ cmp(cnt1, ch2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4531 |
__ br(__ NE, L_CMP_LOOP_NOMATCH); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4532 |
__ b(DONE); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4533 |
__ align(OptoLoopAlignment); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4534 |
__ BIND(L_CMP_LOOP_LAST_CMP2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4535 |
if (str2_isL) { |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4536 |
__ lsr(ch2, tmp4, LogBitsPerByte + str2_chr_shift); // char index |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4537 |
__ ldr(ch2, Address(str2, ch2)); // read whole register of str2. Safe. |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4538 |
__ lslv(tmp2, tmp2, tmp4); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4539 |
__ add(str2, str2, tmp4, __ LSR, LogBitsPerByte + str2_chr_shift); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4540 |
__ add(tmp4, tmp4, 1); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4541 |
__ add(result, result, tmp4, __ LSR, LogBitsPerByte + str2_chr_shift); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4542 |
__ lsl(tmp2, tmp2, 1); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4543 |
} else { |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4544 |
__ mov(ch2, 0xE); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4545 |
__ andr(ch2, ch2, tmp4, __ LSR, LogBitsPerByte); // byte shift amount |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4546 |
__ ldr(ch2, Address(str2, ch2)); // read whole register of str2. Safe. |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4547 |
__ lslv(tmp2, tmp2, tmp4); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4548 |
__ add(tmp4, tmp4, 1); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4549 |
__ add(result, result, tmp4, __ LSR, LogBitsPerByte + str2_chr_shift); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4550 |
__ add(str2, str2, tmp4, __ LSR, LogBitsPerByte); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4551 |
__ lsl(tmp2, tmp2, 1); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4552 |
__ sub(str2, str2, str2_chr_size); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4553 |
} |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4554 |
__ cmp(ch1, ch2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4555 |
__ br(__ NE, L_CMP_LOOP_NOMATCH); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4556 |
__ b(DONE); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4557 |
__ align(OptoLoopAlignment); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4558 |
__ BIND(L_HAS_ZERO_LOOP_NOMATCH); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4559 |
// 1) Restore "result" index. Index was wordSize/str2_chr_size * N until |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4560 |
// L_HAS_ZERO block. Byte octet was analyzed in L_HAS_ZERO_LOOP, |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4561 |
// so, result was increased at max by wordSize/str2_chr_size - 1, so, |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4562 |
// respective high bit wasn't changed. L_LOOP_PROCEED will increase |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4563 |
// result by analyzed characters value, so, we can just reset lower bits |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4564 |
// in result here. Clear 2 lower bits for UU/UL and 3 bits for LL |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4565 |
// 2) restore cnt1 and cnt2 values from "compressed" cnt2 |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4566 |
// 3) advance str2 value to represent next str2 octet. result & 7/3 is |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4567 |
// index of last analyzed substring inside current octet. So, str2 in at |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4568 |
// respective start address. We need to advance it to next octet |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4569 |
__ andr(tmp2, result, wordSize/str2_chr_size - 1); // symbols analyzed |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4570 |
__ lsr(cnt1, cnt2, BitsPerByte * wordSize / 2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4571 |
__ bfm(result, zr, 0, 2 - str2_chr_shift); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4572 |
__ sub(str2, str2, tmp2, __ LSL, str2_chr_shift); // restore str2 |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4573 |
__ movw(cnt2, cnt2); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4574 |
__ b(L_LOOP_PROCEED); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4575 |
__ align(OptoLoopAlignment); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4576 |
__ BIND(NOMATCH); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4577 |
__ mov(result, -1); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4578 |
__ BIND(DONE); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4579 |
__ pop(spilled_regs, sp); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4580 |
__ ret(lr); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4581 |
return entry; |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4582 |
} |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4583 |
|
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4584 |
void generate_string_indexof_stubs() { |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4585 |
StubRoutines::aarch64::_string_indexof_linear_ll = generate_string_indexof_linear(true, true); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4586 |
StubRoutines::aarch64::_string_indexof_linear_uu = generate_string_indexof_linear(false, false); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4587 |
StubRoutines::aarch64::_string_indexof_linear_ul = generate_string_indexof_linear(true, false); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4588 |
} |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
4589 |
|
50758
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4590 |
void inflate_and_store_2_fp_registers(bool generatePrfm, |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4591 |
FloatRegister src1, FloatRegister src2) { |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4592 |
Register dst = r1; |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4593 |
__ zip1(v1, __ T16B, src1, v0); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4594 |
__ zip2(v2, __ T16B, src1, v0); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4595 |
if (generatePrfm) { |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4596 |
__ prfm(Address(dst, SoftwarePrefetchHintDistance), PSTL1STRM); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4597 |
} |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4598 |
__ zip1(v3, __ T16B, src2, v0); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4599 |
__ zip2(v4, __ T16B, src2, v0); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4600 |
__ st1(v1, v2, v3, v4, __ T16B, Address(__ post(dst, 64))); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4601 |
} |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4602 |
|
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4603 |
// R0 = src |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4604 |
// R1 = dst |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4605 |
// R2 = len |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4606 |
// R3 = len >> 3 |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4607 |
// V0 = 0 |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4608 |
// v1 = loaded 8 bytes |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4609 |
address generate_large_byte_array_inflate() { |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4610 |
__ align(CodeEntryAlignment); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4611 |
StubCodeMark mark(this, "StubRoutines", "large_byte_array_inflate"); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4612 |
address entry = __ pc(); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4613 |
Label LOOP, LOOP_START, LOOP_PRFM, LOOP_PRFM_START, DONE; |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4614 |
Register src = r0, dst = r1, len = r2, octetCounter = r3; |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4615 |
const int large_loop_threshold = MAX(64, SoftwarePrefetchHintDistance)/8 + 4; |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4616 |
|
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4617 |
// do one more 8-byte read to have address 16-byte aligned in most cases |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4618 |
// also use single store instruction |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4619 |
__ ldrd(v2, __ post(src, 8)); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4620 |
__ sub(octetCounter, octetCounter, 2); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4621 |
__ zip1(v1, __ T16B, v1, v0); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4622 |
__ zip1(v2, __ T16B, v2, v0); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4623 |
__ st1(v1, v2, __ T16B, __ post(dst, 32)); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4624 |
__ ld1(v3, v4, v5, v6, __ T16B, Address(__ post(src, 64))); |
51374
7be0084191ed
8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents:
50758
diff
changeset
|
4625 |
__ subs(rscratch1, octetCounter, large_loop_threshold); |
50758
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4626 |
__ br(__ LE, LOOP_START); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4627 |
__ b(LOOP_PRFM_START); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4628 |
__ bind(LOOP_PRFM); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4629 |
__ ld1(v3, v4, v5, v6, __ T16B, Address(__ post(src, 64))); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4630 |
__ bind(LOOP_PRFM_START); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4631 |
__ prfm(Address(src, SoftwarePrefetchHintDistance)); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4632 |
__ sub(octetCounter, octetCounter, 8); |
51374
7be0084191ed
8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents:
50758
diff
changeset
|
4633 |
__ subs(rscratch1, octetCounter, large_loop_threshold); |
50758
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4634 |
inflate_and_store_2_fp_registers(true, v3, v4); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4635 |
inflate_and_store_2_fp_registers(true, v5, v6); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4636 |
__ br(__ GT, LOOP_PRFM); |
51374
7be0084191ed
8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents:
50758
diff
changeset
|
4637 |
__ cmp(octetCounter, (u1)8); |
50758
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4638 |
__ br(__ LT, DONE); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4639 |
__ bind(LOOP); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4640 |
__ ld1(v3, v4, v5, v6, __ T16B, Address(__ post(src, 64))); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4641 |
__ bind(LOOP_START); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4642 |
__ sub(octetCounter, octetCounter, 8); |
51374
7be0084191ed
8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents:
50758
diff
changeset
|
4643 |
__ cmp(octetCounter, (u1)8); |
50758
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4644 |
inflate_and_store_2_fp_registers(false, v3, v4); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4645 |
inflate_and_store_2_fp_registers(false, v5, v6); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4646 |
__ br(__ GE, LOOP); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4647 |
__ bind(DONE); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4648 |
__ ret(lr); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4649 |
return entry; |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4650 |
} |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
4651 |
|
31961
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4652 |
/** |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4653 |
* Arguments: |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4654 |
* |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4655 |
* Input: |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4656 |
* c_rarg0 - current state address |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4657 |
* c_rarg1 - H key address |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4658 |
* c_rarg2 - data address |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4659 |
* c_rarg3 - number of blocks |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4660 |
* |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4661 |
* Output: |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4662 |
* Updated state at c_rarg0 |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4663 |
*/ |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4664 |
address generate_ghash_processBlocks() { |
32574 | 4665 |
// Bafflingly, GCM uses little-endian for the byte order, but |
4666 |
// big-endian for the bit order. For example, the polynomial 1 is |
|
4667 |
// represented as the 16-byte string 80 00 00 00 | 12 bytes of 00. |
|
4668 |
// |
|
4669 |
// So, we must either reverse the bytes in each word and do |
|
4670 |
// everything big-endian or reverse the bits in each byte and do |
|
4671 |
// it little-endian. On AArch64 it's more idiomatic to reverse |
|
4672 |
// the bits in each byte (we have an instruction, RBIT, to do |
|
4673 |
// that) and keep the data in little-endian bit order throught the |
|
4674 |
// calculation, bit-reversing the inputs and outputs. |
|
31961
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4675 |
|
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4676 |
StubCodeMark mark(this, "StubRoutines", "ghash_processBlocks"); |
32574 | 4677 |
__ align(wordSize * 2); |
4678 |
address p = __ pc(); |
|
4679 |
__ emit_int64(0x87); // The low-order bits of the field |
|
4680 |
// polynomial (i.e. p = z^7+z^2+z+1) |
|
4681 |
// repeated in the low and high parts of a |
|
4682 |
// 128-bit vector |
|
4683 |
__ emit_int64(0x87); |
|
4684 |
||
4685 |
__ align(CodeEntryAlignment); |
|
31961
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4686 |
address start = __ pc(); |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4687 |
|
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4688 |
Register state = c_rarg0; |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4689 |
Register subkeyH = c_rarg1; |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4690 |
Register data = c_rarg2; |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4691 |
Register blocks = c_rarg3; |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4692 |
|
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4693 |
FloatRegister vzr = v30; |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4694 |
__ eor(vzr, __ T16B, vzr, vzr); // zero register |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4695 |
|
32574 | 4696 |
__ ldrq(v0, Address(state)); |
4697 |
__ ldrq(v1, Address(subkeyH)); |
|
4698 |
||
4699 |
__ rev64(v0, __ T16B, v0); // Bit-reverse words in state and subkeyH |
|
4700 |
__ rbit(v0, __ T16B, v0); |
|
4701 |
__ rev64(v1, __ T16B, v1); |
|
4702 |
__ rbit(v1, __ T16B, v1); |
|
4703 |
||
4704 |
__ ldrq(v26, p); |
|
4705 |
||
4706 |
__ ext(v16, __ T16B, v1, v1, 0x08); // long-swap subkeyH into v1 |
|
4707 |
__ eor(v16, __ T16B, v16, v1); // xor subkeyH into subkeyL (Karatsuba: (A1+A0)) |
|
4708 |
||
4709 |
{ |
|
4710 |
Label L_ghash_loop; |
|
4711 |
__ bind(L_ghash_loop); |
|
4712 |
||
4713 |
__ ldrq(v2, Address(__ post(data, 0x10))); // Load the data, bit |
|
4714 |
// reversing each byte |
|
4715 |
__ rbit(v2, __ T16B, v2); |
|
4716 |
__ eor(v2, __ T16B, v0, v2); // bit-swapped data ^ bit-swapped state |
|
4717 |
||
4718 |
// Multiply state in v2 by subkey in v1 |
|
4719 |
ghash_multiply(/*result_lo*/v5, /*result_hi*/v7, |
|
4720 |
/*a*/v1, /*b*/v2, /*a1_xor_a0*/v16, |
|
4721 |
/*temps*/v6, v20, v18, v21); |
|
4722 |
// Reduce v7:v5 by the field polynomial |
|
4723 |
ghash_reduce(v0, v5, v7, v26, vzr, v20); |
|
4724 |
||
4725 |
__ sub(blocks, blocks, 1); |
|
4726 |
__ cbnz(blocks, L_ghash_loop); |
|
4727 |
} |
|
4728 |
||
4729 |
// The bit-reversed result is at this point in v0 |
|
4730 |
__ rev64(v1, __ T16B, v0); |
|
4731 |
__ rbit(v1, __ T16B, v1); |
|
4732 |
||
31961
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4733 |
__ st1(v1, __ T16B, state); |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4734 |
__ ret(lr); |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4735 |
|
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4736 |
return start; |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4737 |
} |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31955
diff
changeset
|
4738 |
|
29183 | 4739 |
// Continuation point for throwing of implicit exceptions that are |
4740 |
// not handled in the current activation. Fabricates an exception |
|
4741 |
// oop and initiates normal exception dispatching in this |
|
4742 |
// frame. Since we need to preserve callee-saved values (currently |
|
4743 |
// only for C2, but done for C1 as well) we need a callee-saved oop |
|
4744 |
// map and therefore have to make these stubs into RuntimeStubs |
|
4745 |
// rather than BufferBlobs. If the compiler needs all registers to |
|
4746 |
// be preserved between the fault point and the exception handler |
|
4747 |
// then it must assume responsibility for that in |
|
4748 |
// AbstractCompiler::continuation_for_implicit_null_exception or |
|
4749 |
// continuation_for_implicit_division_by_zero_exception. All other |
|
4750 |
// implicit exceptions (e.g., NullPointerException or |
|
4751 |
// AbstractMethodError on entry) are either at call sites or |
|
4752 |
// otherwise assume that stack unwinding will be initiated, so |
|
4753 |
// caller saved registers were assumed volatile in the compiler. |
|
4754 |
||
30225
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
4755 |
#undef __ |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
4756 |
#define __ masm-> |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
4757 |
|
29183 | 4758 |
address generate_throw_exception(const char* name, |
4759 |
address runtime_entry, |
|
4760 |
Register arg1 = noreg, |
|
4761 |
Register arg2 = noreg) { |
|
4762 |
// Information about frame layout at time of blocking runtime call. |
|
4763 |
// Note that we only have to preserve callee-saved registers since |
|
4764 |
// the compilers are responsible for supplying a continuation point |
|
4765 |
// if they expect all registers to be preserved. |
|
4766 |
// n.b. aarch64 asserts that frame::arg_reg_save_area_bytes == 0 |
|
4767 |
enum layout { |
|
4768 |
rfp_off = 0, |
|
4769 |
rfp_off2, |
|
4770 |
return_off, |
|
4771 |
return_off2, |
|
4772 |
framesize // inclusive of return address |
|
4773 |
}; |
|
4774 |
||
4775 |
int insts_size = 512; |
|
4776 |
int locs_size = 64; |
|
4777 |
||
4778 |
CodeBuffer code(name, insts_size, locs_size); |
|
4779 |
OopMapSet* oop_maps = new OopMapSet(); |
|
4780 |
MacroAssembler* masm = new MacroAssembler(&code); |
|
4781 |
||
4782 |
address start = __ pc(); |
|
4783 |
||
4784 |
// This is an inlined and slightly modified version of call_VM |
|
4785 |
// which has the ability to fetch the return PC out of |
|
4786 |
// thread-local storage and also sets up last_Java_sp slightly |
|
4787 |
// differently than the real call_VM |
|
4788 |
||
4789 |
__ enter(); // Save FP and LR before call |
|
4790 |
||
4791 |
assert(is_even(framesize/2), "sp not 16-byte aligned"); |
|
4792 |
||
4793 |
// lr and fp are already in place |
|
4794 |
__ sub(sp, rfp, ((unsigned)framesize-4) << LogBytesPerInt); // prolog |
|
4795 |
||
4796 |
int frame_complete = __ pc() - start; |
|
4797 |
||
4798 |
// Set up last_Java_sp and last_Java_fp |
|
4799 |
address the_pc = __ pc(); |
|
53967 | 4800 |
__ set_last_Java_frame(sp, rfp, the_pc, rscratch1); |
29183 | 4801 |
|
4802 |
// Call runtime |
|
4803 |
if (arg1 != noreg) { |
|
4804 |
assert(arg2 != c_rarg1, "clobbered"); |
|
4805 |
__ mov(c_rarg1, arg1); |
|
4806 |
} |
|
4807 |
if (arg2 != noreg) { |
|
4808 |
__ mov(c_rarg2, arg2); |
|
4809 |
} |
|
4810 |
__ mov(c_rarg0, rthread); |
|
4811 |
BLOCK_COMMENT("call runtime_entry"); |
|
4812 |
__ mov(rscratch1, runtime_entry); |
|
4813 |
__ blrt(rscratch1, 3 /* number_of_arguments */, 0, 1); |
|
4814 |
||
4815 |
// Generate oop map |
|
4816 |
OopMap* map = new OopMap(framesize, 0); |
|
4817 |
||
4818 |
oop_maps->add_gc_map(the_pc - start, map); |
|
4819 |
||
40643 | 4820 |
__ reset_last_Java_frame(true); |
29183 | 4821 |
__ maybe_isb(); |
4822 |
||
4823 |
__ leave(); |
|
4824 |
||
4825 |
// check for pending exceptions |
|
4826 |
#ifdef ASSERT |
|
4827 |
Label L; |
|
4828 |
__ ldr(rscratch1, Address(rthread, Thread::pending_exception_offset())); |
|
4829 |
__ cbnz(rscratch1, L); |
|
4830 |
__ should_not_reach_here(); |
|
4831 |
__ bind(L); |
|
4832 |
#endif // ASSERT |
|
4833 |
__ far_jump(RuntimeAddress(StubRoutines::forward_exception_entry())); |
|
4834 |
||
4835 |
||
4836 |
// codeBlob framesize is in words (not VMRegImpl::slot_size) |
|
4837 |
RuntimeStub* stub = |
|
4838 |
RuntimeStub::new_runtime_stub(name, |
|
4839 |
&code, |
|
4840 |
frame_complete, |
|
4841 |
(framesize >> (LogBytesPerWord - LogBytesPerInt)), |
|
4842 |
oop_maps, false); |
|
4843 |
return stub->entry_point(); |
|
4844 |
} |
|
4845 |
||
31955 | 4846 |
class MontgomeryMultiplyGenerator : public MacroAssembler { |
4847 |
||
4848 |
Register Pa_base, Pb_base, Pn_base, Pm_base, inv, Rlen, Ra, Rb, Rm, Rn, |
|
4849 |
Pa, Pb, Pn, Pm, Rhi_ab, Rlo_ab, Rhi_mn, Rlo_mn, t0, t1, t2, Ri, Rj; |
|
4850 |
||
4851 |
RegSet _toSave; |
|
4852 |
bool _squaring; |
|
4853 |
||
4854 |
public: |
|
4855 |
MontgomeryMultiplyGenerator (Assembler *as, bool squaring) |
|
4856 |
: MacroAssembler(as->code()), _squaring(squaring) { |
|
4857 |
||
4858 |
// Register allocation |
|
4859 |
||
4860 |
Register reg = c_rarg0; |
|
4861 |
Pa_base = reg; // Argument registers |
|
4862 |
if (squaring) |
|
4863 |
Pb_base = Pa_base; |
|
4864 |
else |
|
4865 |
Pb_base = ++reg; |
|
4866 |
Pn_base = ++reg; |
|
4867 |
Rlen= ++reg; |
|
4868 |
inv = ++reg; |
|
4869 |
Pm_base = ++reg; |
|
4870 |
||
4871 |
// Working registers: |
|
4872 |
Ra = ++reg; // The current digit of a, b, n, and m. |
|
4873 |
Rb = ++reg; |
|
4874 |
Rm = ++reg; |
|
4875 |
Rn = ++reg; |
|
4876 |
||
4877 |
Pa = ++reg; // Pointers to the current/next digit of a, b, n, and m. |
|
4878 |
Pb = ++reg; |
|
4879 |
Pm = ++reg; |
|
4880 |
Pn = ++reg; |
|
4881 |
||
4882 |
t0 = ++reg; // Three registers which form a |
|
4883 |
t1 = ++reg; // triple-precision accumuator. |
|
4884 |
t2 = ++reg; |
|
4885 |
||
4886 |
Ri = ++reg; // Inner and outer loop indexes. |
|
4887 |
Rj = ++reg; |
|
4888 |
||
4889 |
Rhi_ab = ++reg; // Product registers: low and high parts |
|
4890 |
Rlo_ab = ++reg; // of a*b and m*n. |
|
4891 |
Rhi_mn = ++reg; |
|
4892 |
Rlo_mn = ++reg; |
|
4893 |
||
4894 |
// r19 and up are callee-saved. |
|
4895 |
_toSave = RegSet::range(r19, reg) + Pm_base; |
|
4896 |
} |
|
4897 |
||
4898 |
private: |
|
4899 |
void save_regs() { |
|
4900 |
push(_toSave, sp); |
|
4901 |
} |
|
4902 |
||
4903 |
void restore_regs() { |
|
4904 |
pop(_toSave, sp); |
|
4905 |
} |
|
4906 |
||
4907 |
template <typename T> |
|
4908 |
void unroll_2(Register count, T block) { |
|
4909 |
Label loop, end, odd; |
|
4910 |
tbnz(count, 0, odd); |
|
4911 |
cbz(count, end); |
|
4912 |
align(16); |
|
4913 |
bind(loop); |
|
4914 |
(this->*block)(); |
|
4915 |
bind(odd); |
|
4916 |
(this->*block)(); |
|
4917 |
subs(count, count, 2); |
|
4918 |
br(Assembler::GT, loop); |
|
4919 |
bind(end); |
|
4920 |
} |
|
4921 |
||
4922 |
template <typename T> |
|
4923 |
void unroll_2(Register count, T block, Register d, Register s, Register tmp) { |
|
4924 |
Label loop, end, odd; |
|
4925 |
tbnz(count, 0, odd); |
|
4926 |
cbz(count, end); |
|
4927 |
align(16); |
|
4928 |
bind(loop); |
|
4929 |
(this->*block)(d, s, tmp); |
|
4930 |
bind(odd); |
|
4931 |
(this->*block)(d, s, tmp); |
|
4932 |
subs(count, count, 2); |
|
4933 |
br(Assembler::GT, loop); |
|
4934 |
bind(end); |
|
4935 |
} |
|
4936 |
||
4937 |
void pre1(RegisterOrConstant i) { |
|
4938 |
block_comment("pre1"); |
|
4939 |
// Pa = Pa_base; |
|
4940 |
// Pb = Pb_base + i; |
|
4941 |
// Pm = Pm_base; |
|
4942 |
// Pn = Pn_base + i; |
|
4943 |
// Ra = *Pa; |
|
4944 |
// Rb = *Pb; |
|
4945 |
// Rm = *Pm; |
|
4946 |
// Rn = *Pn; |
|
4947 |
ldr(Ra, Address(Pa_base)); |
|
4948 |
ldr(Rb, Address(Pb_base, i, Address::uxtw(LogBytesPerWord))); |
|
4949 |
ldr(Rm, Address(Pm_base)); |
|
4950 |
ldr(Rn, Address(Pn_base, i, Address::uxtw(LogBytesPerWord))); |
|
4951 |
lea(Pa, Address(Pa_base)); |
|
4952 |
lea(Pb, Address(Pb_base, i, Address::uxtw(LogBytesPerWord))); |
|
4953 |
lea(Pm, Address(Pm_base)); |
|
4954 |
lea(Pn, Address(Pn_base, i, Address::uxtw(LogBytesPerWord))); |
|
4955 |
||
4956 |
// Zero the m*n result. |
|
4957 |
mov(Rhi_mn, zr); |
|
4958 |
mov(Rlo_mn, zr); |
|
4959 |
} |
|
4960 |
||
4961 |
// The core multiply-accumulate step of a Montgomery |
|
4962 |
// multiplication. The idea is to schedule operations as a |
|
4963 |
// pipeline so that instructions with long latencies (loads and |
|
4964 |
// multiplies) have time to complete before their results are |
|
4965 |
// used. This most benefits in-order implementations of the |
|
4966 |
// architecture but out-of-order ones also benefit. |
|
4967 |
void step() { |
|
4968 |
block_comment("step"); |
|
4969 |
// MACC(Ra, Rb, t0, t1, t2); |
|
4970 |
// Ra = *++Pa; |
|
4971 |
// Rb = *--Pb; |
|
4972 |
umulh(Rhi_ab, Ra, Rb); |
|
4973 |
mul(Rlo_ab, Ra, Rb); |
|
4974 |
ldr(Ra, pre(Pa, wordSize)); |
|
4975 |
ldr(Rb, pre(Pb, -wordSize)); |
|
4976 |
acc(Rhi_mn, Rlo_mn, t0, t1, t2); // The pending m*n from the |
|
4977 |
// previous iteration. |
|
4978 |
// MACC(Rm, Rn, t0, t1, t2); |
|
4979 |
// Rm = *++Pm; |
|
4980 |
// Rn = *--Pn; |
|
4981 |
umulh(Rhi_mn, Rm, Rn); |
|
4982 |
mul(Rlo_mn, Rm, Rn); |
|
4983 |
ldr(Rm, pre(Pm, wordSize)); |
|
4984 |
ldr(Rn, pre(Pn, -wordSize)); |
|
4985 |
acc(Rhi_ab, Rlo_ab, t0, t1, t2); |
|
4986 |
} |
|
4987 |
||
4988 |
void post1() { |
|
4989 |
block_comment("post1"); |
|
4990 |
||
4991 |
// MACC(Ra, Rb, t0, t1, t2); |
|
4992 |
// Ra = *++Pa; |
|
4993 |
// Rb = *--Pb; |
|
4994 |
umulh(Rhi_ab, Ra, Rb); |
|
4995 |
mul(Rlo_ab, Ra, Rb); |
|
4996 |
acc(Rhi_mn, Rlo_mn, t0, t1, t2); // The pending m*n |
|
4997 |
acc(Rhi_ab, Rlo_ab, t0, t1, t2); |
|
4998 |
||
4999 |
// *Pm = Rm = t0 * inv; |
|
5000 |
mul(Rm, t0, inv); |
|
5001 |
str(Rm, Address(Pm)); |
|
5002 |
||
5003 |
// MACC(Rm, Rn, t0, t1, t2); |
|
5004 |
// t0 = t1; t1 = t2; t2 = 0; |
|
5005 |
umulh(Rhi_mn, Rm, Rn); |
|
5006 |
||
5007 |
#ifndef PRODUCT |
|
5008 |
// assert(m[i] * n[0] + t0 == 0, "broken Montgomery multiply"); |
|
5009 |
{ |
|
5010 |
mul(Rlo_mn, Rm, Rn); |
|
5011 |
add(Rlo_mn, t0, Rlo_mn); |
|
5012 |
Label ok; |
|
5013 |
cbz(Rlo_mn, ok); { |
|
5014 |
stop("broken Montgomery multiply"); |
|
5015 |
} bind(ok); |
|
5016 |
} |
|
5017 |
#endif |
|
5018 |
// We have very carefully set things up so that |
|
5019 |
// m[i]*n[0] + t0 == 0 (mod b), so we don't have to calculate |
|
5020 |
// the lower half of Rm * Rn because we know the result already: |
|
5021 |
// it must be -t0. t0 + (-t0) must generate a carry iff |
|
5022 |
// t0 != 0. So, rather than do a mul and an adds we just set |
|
5023 |
// the carry flag iff t0 is nonzero. |
|
5024 |
// |
|
5025 |
// mul(Rlo_mn, Rm, Rn); |
|
5026 |
// adds(zr, t0, Rlo_mn); |
|
5027 |
subs(zr, t0, 1); // Set carry iff t0 is nonzero |
|
5028 |
adcs(t0, t1, Rhi_mn); |
|
5029 |
adc(t1, t2, zr); |
|
5030 |
mov(t2, zr); |
|
5031 |
} |
|
5032 |
||
5033 |
void pre2(RegisterOrConstant i, RegisterOrConstant len) { |
|
5034 |
block_comment("pre2"); |
|
5035 |
// Pa = Pa_base + i-len; |
|
5036 |
// Pb = Pb_base + len; |
|
5037 |
// Pm = Pm_base + i-len; |
|
5038 |
// Pn = Pn_base + len; |
|
5039 |
||
5040 |
if (i.is_register()) { |
|
5041 |
sub(Rj, i.as_register(), len); |
|
5042 |
} else { |
|
5043 |
mov(Rj, i.as_constant()); |
|
5044 |
sub(Rj, Rj, len); |
|
5045 |
} |
|
5046 |
// Rj == i-len |
|
5047 |
||
5048 |
lea(Pa, Address(Pa_base, Rj, Address::uxtw(LogBytesPerWord))); |
|
5049 |
lea(Pb, Address(Pb_base, len, Address::uxtw(LogBytesPerWord))); |
|
5050 |
lea(Pm, Address(Pm_base, Rj, Address::uxtw(LogBytesPerWord))); |
|
5051 |
lea(Pn, Address(Pn_base, len, Address::uxtw(LogBytesPerWord))); |
|
5052 |
||
5053 |
// Ra = *++Pa; |
|
5054 |
// Rb = *--Pb; |
|
5055 |
// Rm = *++Pm; |
|
5056 |
// Rn = *--Pn; |
|
5057 |
ldr(Ra, pre(Pa, wordSize)); |
|
5058 |
ldr(Rb, pre(Pb, -wordSize)); |
|
5059 |
ldr(Rm, pre(Pm, wordSize)); |
|
5060 |
ldr(Rn, pre(Pn, -wordSize)); |
|
5061 |
||
5062 |
mov(Rhi_mn, zr); |
|
5063 |
mov(Rlo_mn, zr); |
|
5064 |
} |
|
5065 |
||
5066 |
void post2(RegisterOrConstant i, RegisterOrConstant len) { |
|
5067 |
block_comment("post2"); |
|
5068 |
if (i.is_constant()) { |
|
5069 |
mov(Rj, i.as_constant()-len.as_constant()); |
|
5070 |
} else { |
|
5071 |
sub(Rj, i.as_register(), len); |
|
5072 |
} |
|
5073 |
||
5074 |
adds(t0, t0, Rlo_mn); // The pending m*n, low part |
|
5075 |
||
5076 |
// As soon as we know the least significant digit of our result, |
|
5077 |
// store it. |
|
5078 |
// Pm_base[i-len] = t0; |
|
5079 |
str(t0, Address(Pm_base, Rj, Address::uxtw(LogBytesPerWord))); |
|
5080 |
||
5081 |
// t0 = t1; t1 = t2; t2 = 0; |
|
5082 |
adcs(t0, t1, Rhi_mn); // The pending m*n, high part |
|
5083 |
adc(t1, t2, zr); |
|
5084 |
mov(t2, zr); |
|
5085 |
} |
|
5086 |
||
5087 |
// A carry in t0 after Montgomery multiplication means that we |
|
5088 |
// should subtract multiples of n from our result in m. We'll |
|
5089 |
// keep doing that until there is no carry. |
|
5090 |
void normalize(RegisterOrConstant len) { |
|
5091 |
block_comment("normalize"); |
|
5092 |
// while (t0) |
|
5093 |
// t0 = sub(Pm_base, Pn_base, t0, len); |
|
5094 |
Label loop, post, again; |
|
5095 |
Register cnt = t1, i = t2; // Re-use registers; we're done with them now |
|
5096 |
cbz(t0, post); { |
|
5097 |
bind(again); { |
|
5098 |
mov(i, zr); |
|
5099 |
mov(cnt, len); |
|
5100 |
ldr(Rm, Address(Pm_base, i, Address::uxtw(LogBytesPerWord))); |
|
5101 |
ldr(Rn, Address(Pn_base, i, Address::uxtw(LogBytesPerWord))); |
|
5102 |
subs(zr, zr, zr); // set carry flag, i.e. no borrow |
|
5103 |
align(16); |
|
5104 |
bind(loop); { |
|
5105 |
sbcs(Rm, Rm, Rn); |
|
5106 |
str(Rm, Address(Pm_base, i, Address::uxtw(LogBytesPerWord))); |
|
5107 |
add(i, i, 1); |
|
5108 |
ldr(Rm, Address(Pm_base, i, Address::uxtw(LogBytesPerWord))); |
|
5109 |
ldr(Rn, Address(Pn_base, i, Address::uxtw(LogBytesPerWord))); |
|
5110 |
sub(cnt, cnt, 1); |
|
5111 |
} cbnz(cnt, loop); |
|
5112 |
sbc(t0, t0, zr); |
|
5113 |
} cbnz(t0, again); |
|
5114 |
} bind(post); |
|
5115 |
} |
|
5116 |
||
5117 |
// Move memory at s to d, reversing words. |
|
5118 |
// Increments d to end of copied memory |
|
5119 |
// Destroys tmp1, tmp2 |
|
5120 |
// Preserves len |
|
5121 |
// Leaves s pointing to the address which was in d at start |
|
5122 |
void reverse(Register d, Register s, Register len, Register tmp1, Register tmp2) { |
|
5123 |
assert(tmp1 < r19 && tmp2 < r19, "register corruption"); |
|
5124 |
||
5125 |
lea(s, Address(s, len, Address::uxtw(LogBytesPerWord))); |
|
5126 |
mov(tmp1, len); |
|
5127 |
unroll_2(tmp1, &MontgomeryMultiplyGenerator::reverse1, d, s, tmp2); |
|
5128 |
sub(s, d, len, ext::uxtw, LogBytesPerWord); |
|
5129 |
} |
|
5130 |
// where |
|
5131 |
void reverse1(Register d, Register s, Register tmp) { |
|
5132 |
ldr(tmp, pre(s, -wordSize)); |
|
5133 |
ror(tmp, tmp, 32); |
|
5134 |
str(tmp, post(d, wordSize)); |
|
5135 |
} |
|
5136 |
||
5137 |
void step_squaring() { |
|
5138 |
// An extra ACC |
|
5139 |
step(); |
|
5140 |
acc(Rhi_ab, Rlo_ab, t0, t1, t2); |
|
5141 |
} |
|
5142 |
||
5143 |
void last_squaring(RegisterOrConstant i) { |
|
5144 |
Label dont; |
|
5145 |
// if ((i & 1) == 0) { |
|
5146 |
tbnz(i.as_register(), 0, dont); { |
|
5147 |
// MACC(Ra, Rb, t0, t1, t2); |
|
5148 |
// Ra = *++Pa; |
|
5149 |
// Rb = *--Pb; |
|
5150 |
umulh(Rhi_ab, Ra, Rb); |
|
5151 |
mul(Rlo_ab, Ra, Rb); |
|
5152 |
acc(Rhi_ab, Rlo_ab, t0, t1, t2); |
|
5153 |
} bind(dont); |
|
5154 |
} |
|
5155 |
||
5156 |
void extra_step_squaring() { |
|
5157 |
acc(Rhi_mn, Rlo_mn, t0, t1, t2); // The pending m*n |
|
5158 |
||
5159 |
// MACC(Rm, Rn, t0, t1, t2); |
|
5160 |
// Rm = *++Pm; |
|
5161 |
// Rn = *--Pn; |
|
5162 |
umulh(Rhi_mn, Rm, Rn); |
|
5163 |
mul(Rlo_mn, Rm, Rn); |
|
5164 |
ldr(Rm, pre(Pm, wordSize)); |
|
5165 |
ldr(Rn, pre(Pn, -wordSize)); |
|
5166 |
} |
|
5167 |
||
5168 |
void post1_squaring() { |
|
5169 |
acc(Rhi_mn, Rlo_mn, t0, t1, t2); // The pending m*n |
|
5170 |
||
5171 |
// *Pm = Rm = t0 * inv; |
|
5172 |
mul(Rm, t0, inv); |
|
5173 |
str(Rm, Address(Pm)); |
|
5174 |
||
5175 |
// MACC(Rm, Rn, t0, t1, t2); |
|
5176 |
// t0 = t1; t1 = t2; t2 = 0; |
|
5177 |
umulh(Rhi_mn, Rm, Rn); |
|
5178 |
||
5179 |
#ifndef PRODUCT |
|
5180 |
// assert(m[i] * n[0] + t0 == 0, "broken Montgomery multiply"); |
|
5181 |
{ |
|
5182 |
mul(Rlo_mn, Rm, Rn); |
|
5183 |
add(Rlo_mn, t0, Rlo_mn); |
|
5184 |
Label ok; |
|
5185 |
cbz(Rlo_mn, ok); { |
|
5186 |
stop("broken Montgomery multiply"); |
|
5187 |
} bind(ok); |
|
5188 |
} |
|
5189 |
#endif |
|
5190 |
// We have very carefully set things up so that |
|
5191 |
// m[i]*n[0] + t0 == 0 (mod b), so we don't have to calculate |
|
5192 |
// the lower half of Rm * Rn because we know the result already: |
|
5193 |
// it must be -t0. t0 + (-t0) must generate a carry iff |
|
5194 |
// t0 != 0. So, rather than do a mul and an adds we just set |
|
5195 |
// the carry flag iff t0 is nonzero. |
|
5196 |
// |
|
5197 |
// mul(Rlo_mn, Rm, Rn); |
|
5198 |
// adds(zr, t0, Rlo_mn); |
|
5199 |
subs(zr, t0, 1); // Set carry iff t0 is nonzero |
|
5200 |
adcs(t0, t1, Rhi_mn); |
|
5201 |
adc(t1, t2, zr); |
|
5202 |
mov(t2, zr); |
|
5203 |
} |
|
5204 |
||
5205 |
void acc(Register Rhi, Register Rlo, |
|
5206 |
Register t0, Register t1, Register t2) { |
|
5207 |
adds(t0, t0, Rlo); |
|
5208 |
adcs(t1, t1, Rhi); |
|
5209 |
adc(t2, t2, zr); |
|
5210 |
} |
|
5211 |
||
5212 |
public: |
|
5213 |
/** |
|
5214 |
* Fast Montgomery multiplication. The derivation of the |
|
5215 |
* algorithm is in A Cryptographic Library for the Motorola |
|
5216 |
* DSP56000, Dusse and Kaliski, Proc. EUROCRYPT 90, pp. 230-237. |
|
5217 |
* |
|
5218 |
* Arguments: |
|
5219 |
* |
|
5220 |
* Inputs for multiplication: |
|
5221 |
* c_rarg0 - int array elements a |
|
5222 |
* c_rarg1 - int array elements b |
|
5223 |
* c_rarg2 - int array elements n (the modulus) |
|
5224 |
* c_rarg3 - int length |
|
5225 |
* c_rarg4 - int inv |
|
5226 |
* c_rarg5 - int array elements m (the result) |
|
5227 |
* |
|
5228 |
* Inputs for squaring: |
|
5229 |
* c_rarg0 - int array elements a |
|
5230 |
* c_rarg1 - int array elements n (the modulus) |
|
5231 |
* c_rarg2 - int length |
|
5232 |
* c_rarg3 - int inv |
|
5233 |
* c_rarg4 - int array elements m (the result) |
|
5234 |
* |
|
5235 |
*/ |
|
5236 |
address generate_multiply() { |
|
5237 |
Label argh, nothing; |
|
5238 |
bind(argh); |
|
5239 |
stop("MontgomeryMultiply total_allocation must be <= 8192"); |
|
5240 |
||
5241 |
align(CodeEntryAlignment); |
|
5242 |
address entry = pc(); |
|
5243 |
||
5244 |
cbzw(Rlen, nothing); |
|
5245 |
||
5246 |
enter(); |
|
5247 |
||
5248 |
// Make room. |
|
5249 |
cmpw(Rlen, 512); |
|
5250 |
br(Assembler::HI, argh); |
|
5251 |
sub(Ra, sp, Rlen, ext::uxtw, exact_log2(4 * sizeof (jint))); |
|
5252 |
andr(sp, Ra, -2 * wordSize); |
|
5253 |
||
5254 |
lsrw(Rlen, Rlen, 1); // length in longwords = len/2 |
|
5255 |
||
5256 |
{ |
|
5257 |
// Copy input args, reversing as we go. We use Ra as a |
|
5258 |
// temporary variable. |
|
5259 |
reverse(Ra, Pa_base, Rlen, t0, t1); |
|
5260 |
if (!_squaring) |
|
5261 |
reverse(Ra, Pb_base, Rlen, t0, t1); |
|
5262 |
reverse(Ra, Pn_base, Rlen, t0, t1); |
|
5263 |
} |
|
5264 |
||
5265 |
// Push all call-saved registers and also Pm_base which we'll need |
|
5266 |
// at the end. |
|
5267 |
save_regs(); |
|
5268 |
||
5269 |
#ifndef PRODUCT |
|
5270 |
// assert(inv * n[0] == -1UL, "broken inverse in Montgomery multiply"); |
|
5271 |
{ |
|
5272 |
ldr(Rn, Address(Pn_base, 0)); |
|
5273 |
mul(Rlo_mn, Rn, inv); |
|
51374
7be0084191ed
8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents:
50758
diff
changeset
|
5274 |
subs(zr, Rlo_mn, -1); |
31955 | 5275 |
Label ok; |
5276 |
br(EQ, ok); { |
|
5277 |
stop("broken inverse in Montgomery multiply"); |
|
5278 |
} bind(ok); |
|
5279 |
} |
|
5280 |
#endif |
|
5281 |
||
5282 |
mov(Pm_base, Ra); |
|
5283 |
||
5284 |
mov(t0, zr); |
|
5285 |
mov(t1, zr); |
|
5286 |
mov(t2, zr); |
|
5287 |
||
5288 |
block_comment("for (int i = 0; i < len; i++) {"); |
|
5289 |
mov(Ri, zr); { |
|
5290 |
Label loop, end; |
|
5291 |
cmpw(Ri, Rlen); |
|
5292 |
br(Assembler::GE, end); |
|
5293 |
||
5294 |
bind(loop); |
|
5295 |
pre1(Ri); |
|
5296 |
||
5297 |
block_comment(" for (j = i; j; j--) {"); { |
|
5298 |
movw(Rj, Ri); |
|
5299 |
unroll_2(Rj, &MontgomeryMultiplyGenerator::step); |
|
5300 |
} block_comment(" } // j"); |
|
5301 |
||
5302 |
post1(); |
|
5303 |
addw(Ri, Ri, 1); |
|
5304 |
cmpw(Ri, Rlen); |
|
5305 |
br(Assembler::LT, loop); |
|
5306 |
bind(end); |
|
5307 |
block_comment("} // i"); |
|
5308 |
} |
|
5309 |
||
5310 |
block_comment("for (int i = len; i < 2*len; i++) {"); |
|
5311 |
mov(Ri, Rlen); { |
|
5312 |
Label loop, end; |
|
5313 |
cmpw(Ri, Rlen, Assembler::LSL, 1); |
|
5314 |
br(Assembler::GE, end); |
|
5315 |
||
5316 |
bind(loop); |
|
5317 |
pre2(Ri, Rlen); |
|
5318 |
||
5319 |
block_comment(" for (j = len*2-i-1; j; j--) {"); { |
|
5320 |
lslw(Rj, Rlen, 1); |
|
5321 |
subw(Rj, Rj, Ri); |
|
5322 |
subw(Rj, Rj, 1); |
|
5323 |
unroll_2(Rj, &MontgomeryMultiplyGenerator::step); |
|
5324 |
} block_comment(" } // j"); |
|
5325 |
||
5326 |
post2(Ri, Rlen); |
|
5327 |
addw(Ri, Ri, 1); |
|
5328 |
cmpw(Ri, Rlen, Assembler::LSL, 1); |
|
5329 |
br(Assembler::LT, loop); |
|
5330 |
bind(end); |
|
5331 |
} |
|
5332 |
block_comment("} // i"); |
|
5333 |
||
5334 |
normalize(Rlen); |
|
5335 |
||
5336 |
mov(Ra, Pm_base); // Save Pm_base in Ra |
|
5337 |
restore_regs(); // Restore caller's Pm_base |
|
5338 |
||
5339 |
// Copy our result into caller's Pm_base |
|
5340 |
reverse(Pm_base, Ra, Rlen, t0, t1); |
|
5341 |
||
5342 |
leave(); |
|
5343 |
bind(nothing); |
|
5344 |
ret(lr); |
|
5345 |
||
5346 |
return entry; |
|
5347 |
} |
|
5348 |
// In C, approximately: |
|
5349 |
||
5350 |
// void |
|
5351 |
// montgomery_multiply(unsigned long Pa_base[], unsigned long Pb_base[], |
|
5352 |
// unsigned long Pn_base[], unsigned long Pm_base[], |
|
5353 |
// unsigned long inv, int len) { |
|
5354 |
// unsigned long t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator |
|
5355 |
// unsigned long *Pa, *Pb, *Pn, *Pm; |
|
5356 |
// unsigned long Ra, Rb, Rn, Rm; |
|
5357 |
||
5358 |
// int i; |
|
5359 |
||
5360 |
// assert(inv * Pn_base[0] == -1UL, "broken inverse in Montgomery multiply"); |
|
5361 |
||
5362 |
// for (i = 0; i < len; i++) { |
|
5363 |
// int j; |
|
5364 |
||
5365 |
// Pa = Pa_base; |
|
5366 |
// Pb = Pb_base + i; |
|
5367 |
// Pm = Pm_base; |
|
5368 |
// Pn = Pn_base + i; |
|
5369 |
||
5370 |
// Ra = *Pa; |
|
5371 |
// Rb = *Pb; |
|
5372 |
// Rm = *Pm; |
|
5373 |
// Rn = *Pn; |
|
5374 |
||
5375 |
// int iters = i; |
|
5376 |
// for (j = 0; iters--; j++) { |
|
5377 |
// assert(Ra == Pa_base[j] && Rb == Pb_base[i-j], "must be"); |
|
5378 |
// MACC(Ra, Rb, t0, t1, t2); |
|
5379 |
// Ra = *++Pa; |
|
5380 |
// Rb = *--Pb; |
|
5381 |
// assert(Rm == Pm_base[j] && Rn == Pn_base[i-j], "must be"); |
|
5382 |
// MACC(Rm, Rn, t0, t1, t2); |
|
5383 |
// Rm = *++Pm; |
|
5384 |
// Rn = *--Pn; |
|
5385 |
// } |
|
5386 |
||
5387 |
// assert(Ra == Pa_base[i] && Rb == Pb_base[0], "must be"); |
|
5388 |
// MACC(Ra, Rb, t0, t1, t2); |
|
5389 |
// *Pm = Rm = t0 * inv; |
|
5390 |
// assert(Rm == Pm_base[i] && Rn == Pn_base[0], "must be"); |
|
5391 |
// MACC(Rm, Rn, t0, t1, t2); |
|
5392 |
||
5393 |
// assert(t0 == 0, "broken Montgomery multiply"); |
|
5394 |
||
5395 |
// t0 = t1; t1 = t2; t2 = 0; |
|
5396 |
// } |
|
5397 |
||
5398 |
// for (i = len; i < 2*len; i++) { |
|
5399 |
// int j; |
|
5400 |
||
5401 |
// Pa = Pa_base + i-len; |
|
5402 |
// Pb = Pb_base + len; |
|
5403 |
// Pm = Pm_base + i-len; |
|
5404 |
// Pn = Pn_base + len; |
|
5405 |
||
5406 |
// Ra = *++Pa; |
|
5407 |
// Rb = *--Pb; |
|
5408 |
// Rm = *++Pm; |
|
5409 |
// Rn = *--Pn; |
|
5410 |
||
5411 |
// int iters = len*2-i-1; |
|
5412 |
// for (j = i-len+1; iters--; j++) { |
|
5413 |
// assert(Ra == Pa_base[j] && Rb == Pb_base[i-j], "must be"); |
|
5414 |
// MACC(Ra, Rb, t0, t1, t2); |
|
5415 |
// Ra = *++Pa; |
|
5416 |
// Rb = *--Pb; |
|
5417 |
// assert(Rm == Pm_base[j] && Rn == Pn_base[i-j], "must be"); |
|
5418 |
// MACC(Rm, Rn, t0, t1, t2); |
|
5419 |
// Rm = *++Pm; |
|
5420 |
// Rn = *--Pn; |
|
5421 |
// } |
|
5422 |
||
5423 |
// Pm_base[i-len] = t0; |
|
5424 |
// t0 = t1; t1 = t2; t2 = 0; |
|
5425 |
// } |
|
5426 |
||
5427 |
// while (t0) |
|
5428 |
// t0 = sub(Pm_base, Pn_base, t0, len); |
|
5429 |
// } |
|
5430 |
||
5431 |
/** |
|
5432 |
* Fast Montgomery squaring. This uses asymptotically 25% fewer |
|
5433 |
* multiplies than Montgomery multiplication so it should be up to |
|
5434 |
* 25% faster. However, its loop control is more complex and it |
|
5435 |
* may actually run slower on some machines. |
|
5436 |
* |
|
5437 |
* Arguments: |
|
5438 |
* |
|
5439 |
* Inputs: |
|
5440 |
* c_rarg0 - int array elements a |
|
5441 |
* c_rarg1 - int array elements n (the modulus) |
|
5442 |
* c_rarg2 - int length |
|
5443 |
* c_rarg3 - int inv |
|
5444 |
* c_rarg4 - int array elements m (the result) |
|
5445 |
* |
|
5446 |
*/ |
|
5447 |
address generate_square() { |
|
5448 |
Label argh; |
|
5449 |
bind(argh); |
|
5450 |
stop("MontgomeryMultiply total_allocation must be <= 8192"); |
|
5451 |
||
5452 |
align(CodeEntryAlignment); |
|
5453 |
address entry = pc(); |
|
5454 |
||
5455 |
enter(); |
|
5456 |
||
5457 |
// Make room. |
|
5458 |
cmpw(Rlen, 512); |
|
5459 |
br(Assembler::HI, argh); |
|
5460 |
sub(Ra, sp, Rlen, ext::uxtw, exact_log2(4 * sizeof (jint))); |
|
5461 |
andr(sp, Ra, -2 * wordSize); |
|
5462 |
||
5463 |
lsrw(Rlen, Rlen, 1); // length in longwords = len/2 |
|
5464 |
||
5465 |
{ |
|
5466 |
// Copy input args, reversing as we go. We use Ra as a |
|
5467 |
// temporary variable. |
|
5468 |
reverse(Ra, Pa_base, Rlen, t0, t1); |
|
5469 |
reverse(Ra, Pn_base, Rlen, t0, t1); |
|
5470 |
} |
|
5471 |
||
5472 |
// Push all call-saved registers and also Pm_base which we'll need |
|
5473 |
// at the end. |
|
5474 |
save_regs(); |
|
5475 |
||
5476 |
mov(Pm_base, Ra); |
|
5477 |
||
5478 |
mov(t0, zr); |
|
5479 |
mov(t1, zr); |
|
5480 |
mov(t2, zr); |
|
5481 |
||
5482 |
block_comment("for (int i = 0; i < len; i++) {"); |
|
5483 |
mov(Ri, zr); { |
|
5484 |
Label loop, end; |
|
5485 |
bind(loop); |
|
5486 |
cmp(Ri, Rlen); |
|
5487 |
br(Assembler::GE, end); |
|
5488 |
||
5489 |
pre1(Ri); |
|
5490 |
||
5491 |
block_comment("for (j = (i+1)/2; j; j--) {"); { |
|
5492 |
add(Rj, Ri, 1); |
|
5493 |
lsr(Rj, Rj, 1); |
|
5494 |
unroll_2(Rj, &MontgomeryMultiplyGenerator::step_squaring); |
|
5495 |
} block_comment(" } // j"); |
|
5496 |
||
5497 |
last_squaring(Ri); |
|
5498 |
||
5499 |
block_comment(" for (j = i/2; j; j--) {"); { |
|
5500 |
lsr(Rj, Ri, 1); |
|
5501 |
unroll_2(Rj, &MontgomeryMultiplyGenerator::extra_step_squaring); |
|
5502 |
} block_comment(" } // j"); |
|
5503 |
||
5504 |
post1_squaring(); |
|
5505 |
add(Ri, Ri, 1); |
|
5506 |
cmp(Ri, Rlen); |
|
5507 |
br(Assembler::LT, loop); |
|
5508 |
||
5509 |
bind(end); |
|
5510 |
block_comment("} // i"); |
|
5511 |
} |
|
5512 |
||
5513 |
block_comment("for (int i = len; i < 2*len; i++) {"); |
|
5514 |
mov(Ri, Rlen); { |
|
5515 |
Label loop, end; |
|
5516 |
bind(loop); |
|
5517 |
cmp(Ri, Rlen, Assembler::LSL, 1); |
|
5518 |
br(Assembler::GE, end); |
|
5519 |
||
5520 |
pre2(Ri, Rlen); |
|
5521 |
||
5522 |
block_comment(" for (j = (2*len-i-1)/2; j; j--) {"); { |
|
5523 |
lsl(Rj, Rlen, 1); |
|
5524 |
sub(Rj, Rj, Ri); |
|
5525 |
sub(Rj, Rj, 1); |
|
5526 |
lsr(Rj, Rj, 1); |
|
5527 |
unroll_2(Rj, &MontgomeryMultiplyGenerator::step_squaring); |
|
5528 |
} block_comment(" } // j"); |
|
5529 |
||
5530 |
last_squaring(Ri); |
|
5531 |
||
5532 |
block_comment(" for (j = (2*len-i)/2; j; j--) {"); { |
|
5533 |
lsl(Rj, Rlen, 1); |
|
5534 |
sub(Rj, Rj, Ri); |
|
5535 |
lsr(Rj, Rj, 1); |
|
5536 |
unroll_2(Rj, &MontgomeryMultiplyGenerator::extra_step_squaring); |
|
5537 |
} block_comment(" } // j"); |
|
5538 |
||
5539 |
post2(Ri, Rlen); |
|
5540 |
add(Ri, Ri, 1); |
|
5541 |
cmp(Ri, Rlen, Assembler::LSL, 1); |
|
5542 |
||
5543 |
br(Assembler::LT, loop); |
|
5544 |
bind(end); |
|
5545 |
block_comment("} // i"); |
|
5546 |
} |
|
5547 |
||
5548 |
normalize(Rlen); |
|
5549 |
||
5550 |
mov(Ra, Pm_base); // Save Pm_base in Ra |
|
5551 |
restore_regs(); // Restore caller's Pm_base |
|
5552 |
||
5553 |
// Copy our result into caller's Pm_base |
|
5554 |
reverse(Pm_base, Ra, Rlen, t0, t1); |
|
5555 |
||
5556 |
leave(); |
|
5557 |
ret(lr); |
|
5558 |
||
5559 |
return entry; |
|
5560 |
} |
|
5561 |
// In C, approximately: |
|
5562 |
||
5563 |
// void |
|
5564 |
// montgomery_square(unsigned long Pa_base[], unsigned long Pn_base[], |
|
5565 |
// unsigned long Pm_base[], unsigned long inv, int len) { |
|
5566 |
// unsigned long t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator |
|
5567 |
// unsigned long *Pa, *Pb, *Pn, *Pm; |
|
5568 |
// unsigned long Ra, Rb, Rn, Rm; |
|
5569 |
||
5570 |
// int i; |
|
5571 |
||
5572 |
// assert(inv * Pn_base[0] == -1UL, "broken inverse in Montgomery multiply"); |
|
5573 |
||
5574 |
// for (i = 0; i < len; i++) { |
|
5575 |
// int j; |
|
5576 |
||
5577 |
// Pa = Pa_base; |
|
5578 |
// Pb = Pa_base + i; |
|
5579 |
// Pm = Pm_base; |
|
5580 |
// Pn = Pn_base + i; |
|
5581 |
||
5582 |
// Ra = *Pa; |
|
5583 |
// Rb = *Pb; |
|
5584 |
// Rm = *Pm; |
|
5585 |
// Rn = *Pn; |
|
5586 |
||
5587 |
// int iters = (i+1)/2; |
|
5588 |
// for (j = 0; iters--; j++) { |
|
5589 |
// assert(Ra == Pa_base[j] && Rb == Pa_base[i-j], "must be"); |
|
5590 |
// MACC2(Ra, Rb, t0, t1, t2); |
|
5591 |
// Ra = *++Pa; |
|
5592 |
// Rb = *--Pb; |
|
5593 |
// assert(Rm == Pm_base[j] && Rn == Pn_base[i-j], "must be"); |
|
5594 |
// MACC(Rm, Rn, t0, t1, t2); |
|
5595 |
// Rm = *++Pm; |
|
5596 |
// Rn = *--Pn; |
|
5597 |
// } |
|
5598 |
// if ((i & 1) == 0) { |
|
5599 |
// assert(Ra == Pa_base[j], "must be"); |
|
5600 |
// MACC(Ra, Ra, t0, t1, t2); |
|
5601 |
// } |
|
5602 |
// iters = i/2; |
|
5603 |
// assert(iters == i-j, "must be"); |
|
5604 |
// for (; iters--; j++) { |
|
5605 |
// assert(Rm == Pm_base[j] && Rn == Pn_base[i-j], "must be"); |
|
5606 |
// MACC(Rm, Rn, t0, t1, t2); |
|
5607 |
// Rm = *++Pm; |
|
5608 |
// Rn = *--Pn; |
|
5609 |
// } |
|
5610 |
||
5611 |
// *Pm = Rm = t0 * inv; |
|
5612 |
// assert(Rm == Pm_base[i] && Rn == Pn_base[0], "must be"); |
|
5613 |
// MACC(Rm, Rn, t0, t1, t2); |
|
5614 |
||
5615 |
// assert(t0 == 0, "broken Montgomery multiply"); |
|
5616 |
||
5617 |
// t0 = t1; t1 = t2; t2 = 0; |
|
5618 |
// } |
|
5619 |
||
5620 |
// for (i = len; i < 2*len; i++) { |
|
5621 |
// int start = i-len+1; |
|
5622 |
// int end = start + (len - start)/2; |
|
5623 |
// int j; |
|
5624 |
||
5625 |
// Pa = Pa_base + i-len; |
|
5626 |
// Pb = Pa_base + len; |
|
5627 |
// Pm = Pm_base + i-len; |
|
5628 |
// Pn = Pn_base + len; |
|
5629 |
||
5630 |
// Ra = *++Pa; |
|
5631 |
// Rb = *--Pb; |
|
5632 |
// Rm = *++Pm; |
|
5633 |
// Rn = *--Pn; |
|
5634 |
||
5635 |
// int iters = (2*len-i-1)/2; |
|
5636 |
// assert(iters == end-start, "must be"); |
|
5637 |
// for (j = start; iters--; j++) { |
|
5638 |
// assert(Ra == Pa_base[j] && Rb == Pa_base[i-j], "must be"); |
|
5639 |
// MACC2(Ra, Rb, t0, t1, t2); |
|
5640 |
// Ra = *++Pa; |
|
5641 |
// Rb = *--Pb; |
|
5642 |
// assert(Rm == Pm_base[j] && Rn == Pn_base[i-j], "must be"); |
|
5643 |
// MACC(Rm, Rn, t0, t1, t2); |
|
5644 |
// Rm = *++Pm; |
|
5645 |
// Rn = *--Pn; |
|
5646 |
// } |
|
5647 |
// if ((i & 1) == 0) { |
|
5648 |
// assert(Ra == Pa_base[j], "must be"); |
|
5649 |
// MACC(Ra, Ra, t0, t1, t2); |
|
5650 |
// } |
|
5651 |
// iters = (2*len-i)/2; |
|
5652 |
// assert(iters == len-j, "must be"); |
|
5653 |
// for (; iters--; j++) { |
|
5654 |
// assert(Rm == Pm_base[j] && Rn == Pn_base[i-j], "must be"); |
|
5655 |
// MACC(Rm, Rn, t0, t1, t2); |
|
5656 |
// Rm = *++Pm; |
|
5657 |
// Rn = *--Pn; |
|
5658 |
// } |
|
5659 |
// Pm_base[i-len] = t0; |
|
5660 |
// t0 = t1; t1 = t2; t2 = 0; |
|
5661 |
// } |
|
5662 |
||
5663 |
// while (t0) |
|
5664 |
// t0 = sub(Pm_base, Pn_base, t0, len); |
|
5665 |
// } |
|
5666 |
}; |
|
5667 |
||
46814 | 5668 |
|
29183 | 5669 |
// Initialization |
5670 |
void generate_initial() { |
|
5671 |
// Generate initial stubs and initializes the entry points |
|
5672 |
||
5673 |
// entry points that exist in all platforms Note: This is code |
|
5674 |
// that could be shared among different platforms - however the |
|
5675 |
// benefit seems to be smaller than the disadvantage of having a |
|
5676 |
// much more complicated generator structure. See also comment in |
|
5677 |
// stubRoutines.hpp. |
|
5678 |
||
5679 |
StubRoutines::_forward_exception_entry = generate_forward_exception(); |
|
5680 |
||
5681 |
StubRoutines::_call_stub_entry = |
|
5682 |
generate_call_stub(StubRoutines::_call_stub_return_address); |
|
5683 |
||
5684 |
// is referenced by megamorphic call |
|
5685 |
StubRoutines::_catch_exception_entry = generate_catch_exception(); |
|
5686 |
||
5687 |
// Build this early so it's available for the interpreter. |
|
5688 |
StubRoutines::_throw_StackOverflowError_entry = |
|
5689 |
generate_throw_exception("StackOverflowError throw_exception", |
|
5690 |
CAST_FROM_FN_PTR(address, |
|
43439
5e03c9ba74f3
8172144: AArch64: Implement "JEP 270: Reserved Stack Areas for Critical Sections"
aph
parents:
42577
diff
changeset
|
5691 |
SharedRuntime::throw_StackOverflowError)); |
5e03c9ba74f3
8172144: AArch64: Implement "JEP 270: Reserved Stack Areas for Critical Sections"
aph
parents:
42577
diff
changeset
|
5692 |
StubRoutines::_throw_delayed_StackOverflowError_entry = |
5e03c9ba74f3
8172144: AArch64: Implement "JEP 270: Reserved Stack Areas for Critical Sections"
aph
parents:
42577
diff
changeset
|
5693 |
generate_throw_exception("delayed StackOverflowError throw_exception", |
5e03c9ba74f3
8172144: AArch64: Implement "JEP 270: Reserved Stack Areas for Critical Sections"
aph
parents:
42577
diff
changeset
|
5694 |
CAST_FROM_FN_PTR(address, |
5e03c9ba74f3
8172144: AArch64: Implement "JEP 270: Reserved Stack Areas for Critical Sections"
aph
parents:
42577
diff
changeset
|
5695 |
SharedRuntime::throw_delayed_StackOverflowError)); |
29183 | 5696 |
if (UseCRC32Intrinsics) { |
5697 |
// set table address before stub generation which use it |
|
5698 |
StubRoutines::_crc_table_adr = (address)StubRoutines::aarch64::_crc_table; |
|
5699 |
StubRoutines::_updateBytesCRC32 = generate_updateBytesCRC32(); |
|
5700 |
} |
|
47767
107622f2695c
8189745: AARCH64: Use CRC32C intrinsic code in interpreter and C1
dchuyko
parents:
47571
diff
changeset
|
5701 |
|
107622f2695c
8189745: AARCH64: Use CRC32C intrinsic code in interpreter and C1
dchuyko
parents:
47571
diff
changeset
|
5702 |
if (UseCRC32CIntrinsics) { |
107622f2695c
8189745: AARCH64: Use CRC32C intrinsic code in interpreter and C1
dchuyko
parents:
47571
diff
changeset
|
5703 |
StubRoutines::_updateBytesCRC32C = generate_updateBytesCRC32C(); |
107622f2695c
8189745: AARCH64: Use CRC32C intrinsic code in interpreter and C1
dchuyko
parents:
47571
diff
changeset
|
5704 |
} |
50753 | 5705 |
|
52927
226c451bd954
8215133: AARCH64: disable Math.log intrinsic publishing
dpochepk
parents:
51756
diff
changeset
|
5706 |
// Disabled until JDK-8210858 is fixed |
226c451bd954
8215133: AARCH64: disable Math.log intrinsic publishing
dpochepk
parents:
51756
diff
changeset
|
5707 |
// if (vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dlog)) { |
226c451bd954
8215133: AARCH64: disable Math.log intrinsic publishing
dpochepk
parents:
51756
diff
changeset
|
5708 |
// StubRoutines::_dlog = generate_dlog(); |
226c451bd954
8215133: AARCH64: disable Math.log intrinsic publishing
dpochepk
parents:
51756
diff
changeset
|
5709 |
// } |
50755
680d04ae76e9
8204289: AARCH64: enable math intrinsics usage in interpreter and C1
dpochepk
parents:
50754
diff
changeset
|
5710 |
|
680d04ae76e9
8204289: AARCH64: enable math intrinsics usage in interpreter and C1
dpochepk
parents:
50754
diff
changeset
|
5711 |
if (vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dsin)) { |
680d04ae76e9
8204289: AARCH64: enable math intrinsics usage in interpreter and C1
dpochepk
parents:
50754
diff
changeset
|
5712 |
StubRoutines::_dsin = generate_dsin_dcos(/* isCos = */ false); |
680d04ae76e9
8204289: AARCH64: enable math intrinsics usage in interpreter and C1
dpochepk
parents:
50754
diff
changeset
|
5713 |
} |
680d04ae76e9
8204289: AARCH64: enable math intrinsics usage in interpreter and C1
dpochepk
parents:
50754
diff
changeset
|
5714 |
|
680d04ae76e9
8204289: AARCH64: enable math intrinsics usage in interpreter and C1
dpochepk
parents:
50754
diff
changeset
|
5715 |
if (vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dcos)) { |
680d04ae76e9
8204289: AARCH64: enable math intrinsics usage in interpreter and C1
dpochepk
parents:
50754
diff
changeset
|
5716 |
StubRoutines::_dcos = generate_dsin_dcos(/* isCos = */ true); |
680d04ae76e9
8204289: AARCH64: enable math intrinsics usage in interpreter and C1
dpochepk
parents:
50754
diff
changeset
|
5717 |
} |
29183 | 5718 |
} |
5719 |
||
5720 |
void generate_all() { |
|
5721 |
// support for verify_oop (must happen after universe_init) |
|
5722 |
StubRoutines::_verify_oop_subroutine_entry = generate_verify_oop(); |
|
5723 |
StubRoutines::_throw_AbstractMethodError_entry = |
|
5724 |
generate_throw_exception("AbstractMethodError throw_exception", |
|
5725 |
CAST_FROM_FN_PTR(address, |
|
5726 |
SharedRuntime:: |
|
5727 |
throw_AbstractMethodError)); |
|
5728 |
||
5729 |
StubRoutines::_throw_IncompatibleClassChangeError_entry = |
|
5730 |
generate_throw_exception("IncompatibleClassChangeError throw_exception", |
|
5731 |
CAST_FROM_FN_PTR(address, |
|
5732 |
SharedRuntime:: |
|
5733 |
throw_IncompatibleClassChangeError)); |
|
5734 |
||
5735 |
StubRoutines::_throw_NullPointerException_at_call_entry = |
|
5736 |
generate_throw_exception("NullPointerException at call throw_exception", |
|
5737 |
CAST_FROM_FN_PTR(address, |
|
5738 |
SharedRuntime:: |
|
5739 |
throw_NullPointerException_at_call)); |
|
5740 |
||
5741 |
// arraycopy stubs used by compilers |
|
5742 |
generate_arraycopy_stubs(); |
|
5743 |
||
46814 | 5744 |
// has negatives stub for large arrays. |
5745 |
StubRoutines::aarch64::_has_negatives = generate_has_negatives(StubRoutines::aarch64::_has_negatives_long); |
|
5746 |
||
49724
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
5747 |
// array equals stub for large arrays. |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
5748 |
if (!UseSimpleArrayEquals) { |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
5749 |
StubRoutines::aarch64::_large_array_equals = generate_large_array_equals(); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
5750 |
} |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49484
diff
changeset
|
5751 |
|
50756
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
5752 |
generate_compare_long_strings(); |
7ad092f40454
8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents:
50755
diff
changeset
|
5753 |
|
50757
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
5754 |
generate_string_indexof_stubs(); |
866c9aa29ee4
8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents:
50756
diff
changeset
|
5755 |
|
50758
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
5756 |
// byte_array_inflate stub for large arrays. |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
5757 |
StubRoutines::aarch64::_large_byte_array_inflate = generate_large_byte_array_inflate(); |
afca3c78ea0f
8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents:
50757
diff
changeset
|
5758 |
|
51619
dca697c71e5d
8207247: AARCH64: Enable Minimal and Client VM builds
avoitylov
parents:
51374
diff
changeset
|
5759 |
#ifdef COMPILER2 |
30225
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
5760 |
if (UseMultiplyToLenIntrinsic) { |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
5761 |
StubRoutines::_multiplyToLen = generate_multiplyToLen(); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
5762 |
} |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29695
diff
changeset
|
5763 |
|
47571
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
5764 |
if (UseSquareToLenIntrinsic) { |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
5765 |
StubRoutines::_squareToLen = generate_squareToLen(); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
5766 |
} |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
5767 |
|
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
5768 |
if (UseMulAddIntrinsic) { |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
5769 |
StubRoutines::_mulAdd = generate_mulAdd(); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
5770 |
} |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
5771 |
|
31955 | 5772 |
if (UseMontgomeryMultiplyIntrinsic) { |
5773 |
StubCodeMark mark(this, "StubRoutines", "montgomeryMultiply"); |
|
5774 |
MontgomeryMultiplyGenerator g(_masm, /*squaring*/false); |
|
5775 |
StubRoutines::_montgomeryMultiply = g.generate_multiply(); |
|
5776 |
} |
|
5777 |
||
5778 |
if (UseMontgomerySquareIntrinsic) { |
|
5779 |
StubCodeMark mark(this, "StubRoutines", "montgomerySquare"); |
|
5780 |
MontgomeryMultiplyGenerator g(_masm, /*squaring*/true); |
|
5781 |
// We use generate_multiply() rather than generate_square() |
|
5782 |
// because it's faster for the sizes of modulus we care about. |
|
5783 |
StubRoutines::_montgomerySquare = g.generate_multiply(); |
|
5784 |
} |
|
51619
dca697c71e5d
8207247: AARCH64: Enable Minimal and Client VM builds
avoitylov
parents:
51374
diff
changeset
|
5785 |
#endif // COMPILER2 |
31955 | 5786 |
|
29183 | 5787 |
#ifndef BUILTIN_SIM |
31961
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|
5788 |
// generate GHASH intrinsics code |
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5789 |
if (UseGHASHIntrinsics) { |
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|
5790 |
StubRoutines::_ghash_processBlocks = generate_ghash_processBlocks(); |
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5791 |
} |
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5792 |
|
29183 | 5793 |
if (UseAESIntrinsics) { |
5794 |
StubRoutines::_aescrypt_encryptBlock = generate_aescrypt_encryptBlock(); |
|
5795 |
StubRoutines::_aescrypt_decryptBlock = generate_aescrypt_decryptBlock(); |
|
5796 |
StubRoutines::_cipherBlockChaining_encryptAESCrypt = generate_cipherBlockChaining_encryptAESCrypt(); |
|
5797 |
StubRoutines::_cipherBlockChaining_decryptAESCrypt = generate_cipherBlockChaining_decryptAESCrypt(); |
|
5798 |
} |
|
5799 |
||
5800 |
if (UseSHA1Intrinsics) { |
|
5801 |
StubRoutines::_sha1_implCompress = generate_sha1_implCompress(false, "sha1_implCompress"); |
|
5802 |
StubRoutines::_sha1_implCompressMB = generate_sha1_implCompress(true, "sha1_implCompressMB"); |
|
5803 |
} |
|
5804 |
if (UseSHA256Intrinsics) { |
|
5805 |
StubRoutines::_sha256_implCompress = generate_sha256_implCompress(false, "sha256_implCompress"); |
|
5806 |
StubRoutines::_sha256_implCompressMB = generate_sha256_implCompress(true, "sha256_implCompressMB"); |
|
5807 |
} |
|
5808 |
||
33176
54393049bf1e
8139043: aarch64: add support for adler32 intrinsic
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diff
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|
5809 |
// generate Adler32 intrinsics code |
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changeset
|
5810 |
if (UseAdler32Intrinsics) { |
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|
5811 |
StubRoutines::_updateBytesAdler32 = generate_updateBytesAdler32(); |
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|
5812 |
} |
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|
5813 |
|
29183 | 5814 |
// Safefetch stubs. |
5815 |
generate_safefetch("SafeFetch32", sizeof(int), &StubRoutines::_safefetch32_entry, |
|
5816 |
&StubRoutines::_safefetch32_fault_pc, |
|
5817 |
&StubRoutines::_safefetch32_continuation_pc); |
|
5818 |
generate_safefetch("SafeFetchN", sizeof(intptr_t), &StubRoutines::_safefetchN_entry, |
|
5819 |
&StubRoutines::_safefetchN_fault_pc, |
|
5820 |
&StubRoutines::_safefetchN_continuation_pc); |
|
5821 |
#endif |
|
45054 | 5822 |
StubRoutines::aarch64::set_completed(); |
29183 | 5823 |
} |
5824 |
||
5825 |
public: |
|
5826 |
StubGenerator(CodeBuffer* code, bool all) : StubCodeGenerator(code) { |
|
5827 |
if (all) { |
|
5828 |
generate_all(); |
|
5829 |
} else { |
|
5830 |
generate_initial(); |
|
5831 |
} |
|
5832 |
} |
|
5833 |
}; // end class declaration |
|
5834 |
||
5835 |
void StubGenerator_generate(CodeBuffer* code, bool all) { |
|
5836 |
StubGenerator g(code, all); |
|
5837 |
} |