hotspot/src/share/vm/opto/matcher.cpp
author cvarming
Mon, 20 Jun 2016 08:11:22 -0400
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child 41323 ddd5600d4762
permissions -rw-r--r--
8159720: Failure of C2 compilation with tiered prevents some C1 compilations. Summary: If C2 fails to compile a method with tiered compilation, then it should mark the method as not compileable on the C2 tier only. Reviewed-by: twisti, thartmann
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/*
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 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#include "precompiled.hpp"
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#include "memory/allocation.inline.hpp"
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#include "memory/resourceArea.hpp"
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#include "opto/ad.hpp"
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#include "opto/addnode.hpp"
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#include "opto/callnode.hpp"
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#include "opto/idealGraphPrinter.hpp"
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#include "opto/matcher.hpp"
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#include "opto/memnode.hpp"
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#include "opto/movenode.hpp"
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#include "opto/opcodes.hpp"
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#include "opto/regmask.hpp"
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#include "opto/rootnode.hpp"
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#include "opto/runtime.hpp"
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#include "opto/type.hpp"
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#include "opto/vectornode.hpp"
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#include "runtime/os.hpp"
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#include "runtime/sharedRuntime.hpp"
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OptoReg::Name OptoReg::c_frame_pointer;
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const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
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RegMask Matcher::mreg2regmask[_last_Mach_Reg];
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RegMask Matcher::STACK_ONLY_mask;
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RegMask Matcher::c_frame_ptr_mask;
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const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
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const uint Matcher::_end_rematerialize   = _END_REMATERIALIZE;
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//---------------------------Matcher-------------------------------------------
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Matcher::Matcher()
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: PhaseTransform( Phase::Ins_Select ),
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#ifdef ASSERT
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  _old2new_map(C->comp_arena()),
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  _new2old_map(C->comp_arena()),
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#endif
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  _shared_nodes(C->comp_arena()),
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  _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
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  _swallowed(swallowed),
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  _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
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  _end_inst_chain_rule(_END_INST_CHAIN_RULE),
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  _must_clone(must_clone),
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  _register_save_policy(register_save_policy),
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  _c_reg_save_policy(c_reg_save_policy),
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  _register_save_type(register_save_type),
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  _ruleName(ruleName),
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  _allocation_started(false),
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  _states_arena(Chunk::medium_size),
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  _visited(&_states_arena),
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  _shared(&_states_arena),
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  _dontcare(&_states_arena) {
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  C->set_matcher(this);
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  idealreg2spillmask  [Op_RegI] = NULL;
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  idealreg2spillmask  [Op_RegN] = NULL;
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  idealreg2spillmask  [Op_RegL] = NULL;
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  idealreg2spillmask  [Op_RegF] = NULL;
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  idealreg2spillmask  [Op_RegD] = NULL;
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  idealreg2spillmask  [Op_RegP] = NULL;
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  idealreg2spillmask  [Op_VecS] = NULL;
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  idealreg2spillmask  [Op_VecD] = NULL;
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  idealreg2spillmask  [Op_VecX] = NULL;
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  idealreg2spillmask  [Op_VecY] = NULL;
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  idealreg2spillmask  [Op_VecZ] = NULL;
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  idealreg2debugmask  [Op_RegI] = NULL;
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  idealreg2debugmask  [Op_RegN] = NULL;
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  idealreg2debugmask  [Op_RegL] = NULL;
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  idealreg2debugmask  [Op_RegF] = NULL;
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  idealreg2debugmask  [Op_RegD] = NULL;
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  idealreg2debugmask  [Op_RegP] = NULL;
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  idealreg2debugmask  [Op_VecS] = NULL;
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  idealreg2debugmask  [Op_VecD] = NULL;
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  idealreg2debugmask  [Op_VecX] = NULL;
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  idealreg2debugmask  [Op_VecY] = NULL;
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  idealreg2debugmask  [Op_VecZ] = NULL;
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  idealreg2mhdebugmask[Op_RegI] = NULL;
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  idealreg2mhdebugmask[Op_RegN] = NULL;
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  idealreg2mhdebugmask[Op_RegL] = NULL;
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  idealreg2mhdebugmask[Op_RegF] = NULL;
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  idealreg2mhdebugmask[Op_RegD] = NULL;
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  idealreg2mhdebugmask[Op_RegP] = NULL;
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  idealreg2mhdebugmask[Op_VecS] = NULL;
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  idealreg2mhdebugmask[Op_VecD] = NULL;
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  idealreg2mhdebugmask[Op_VecX] = NULL;
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  idealreg2mhdebugmask[Op_VecY] = NULL;
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  idealreg2mhdebugmask[Op_VecZ] = NULL;
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  debug_only(_mem_node = NULL;)   // Ideal memory node consumed by mach node
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}
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//------------------------------warp_incoming_stk_arg------------------------
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// This warps a VMReg into an OptoReg::Name
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OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
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  OptoReg::Name warped;
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  if( reg->is_stack() ) {  // Stack slot argument?
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    warped = OptoReg::add(_old_SP, reg->reg2stack() );
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    warped = OptoReg::add(warped, C->out_preserve_stack_slots());
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    if( warped >= _in_arg_limit )
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      _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
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    if (!RegMask::can_represent_arg(warped)) {
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      // the compiler cannot represent this method's calling sequence
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      C->record_method_not_compilable("unsupported incoming calling sequence");
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      return OptoReg::Bad;
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    }
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    return warped;
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  }
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  return OptoReg::as_OptoReg(reg);
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}
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//---------------------------compute_old_SP------------------------------------
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OptoReg::Name Compile::compute_old_SP() {
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  int fixed    = fixed_slots();
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  int preserve = in_preserve_stack_slots();
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  return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots()));
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}
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#ifdef ASSERT
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void Matcher::verify_new_nodes_only(Node* xroot) {
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  // Make sure that the new graph only references new nodes
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  ResourceMark rm;
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  Unique_Node_List worklist;
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  VectorSet visited(Thread::current()->resource_area());
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  worklist.push(xroot);
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  while (worklist.size() > 0) {
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    Node* n = worklist.pop();
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    visited <<= n->_idx;
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    assert(C->node_arena()->contains(n), "dead node");
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    for (uint j = 0; j < n->req(); j++) {
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      Node* in = n->in(j);
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      if (in != NULL) {
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        assert(C->node_arena()->contains(in), "dead node");
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        if (!visited.test(in->_idx)) {
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          worklist.push(in);
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        }
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      }
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    }
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  }
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}
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#endif
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//---------------------------match---------------------------------------------
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void Matcher::match( ) {
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  if( MaxLabelRootDepth < 100 ) { // Too small?
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    assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
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    MaxLabelRootDepth = 100;
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  }
1
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  // One-time initialization of some register masks.
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  init_spill_mask( C->root()->in(1) );
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  _return_addr_mask = return_addr();
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#ifdef _LP64
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  // Pointers take 2 slots in 64-bit land
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  _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
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#endif
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  // Map a Java-signature return type into return register-value
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  // machine registers for 0, 1 and 2 returned values.
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  const TypeTuple *range = C->tf()->range();
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  if( range->cnt() > TypeFunc::Parms ) { // If not a void function
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    // Get ideal-register return type
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    int ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
1
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    // Get machine return register
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    uint sop = C->start()->Opcode();
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    OptoRegPair regs = return_value(ireg, false);
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    // And mask for same
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    _return_value_mask = RegMask(regs.first());
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    if( OptoReg::is_valid(regs.second()) )
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      _return_value_mask.Insert(regs.second());
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  }
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  // ---------------
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  // Frame Layout
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  // Need the method signature to determine the incoming argument types,
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  // because the types determine which registers the incoming arguments are
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  // in, and this affects the matched code.
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  const TypeTuple *domain = C->tf()->domain();
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  uint             argcnt = domain->cnt() - TypeFunc::Parms;
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  BasicType *sig_bt        = NEW_RESOURCE_ARRAY( BasicType, argcnt );
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  VMRegPair *vm_parm_regs  = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
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  _parm_regs               = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
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  _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
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  uint i;
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  for( i = 0; i<argcnt; i++ ) {
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    sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
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  }
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  // Pass array of ideal registers and length to USER code (from the AD file)
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  // that will convert this to an array of register numbers.
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  const StartNode *start = C->start();
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  start->calling_convention( sig_bt, vm_parm_regs, argcnt );
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#ifdef ASSERT
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  // Sanity check users' calling convention.  Real handy while trying to
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  // get the initial port correct.
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  { for (uint i = 0; i<argcnt; i++) {
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      if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
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        assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
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        _parm_regs[i].set_bad();
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        continue;
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      }
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      VMReg parm_reg = vm_parm_regs[i].first();
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      assert(parm_reg->is_valid(), "invalid arg?");
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      if (parm_reg->is_reg()) {
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        OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
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        assert(can_be_java_arg(opto_parm_reg) ||
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               C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
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               opto_parm_reg == inline_cache_reg(),
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               "parameters in register must be preserved by runtime stubs");
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      }
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      for (uint j = 0; j < i; j++) {
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        assert(parm_reg != vm_parm_regs[j].first(),
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               "calling conv. must produce distinct regs");
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      }
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    }
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  }
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#endif
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  // Do some initial frame layout.
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  // Compute the old incoming SP (may be called FP) as
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  //   OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
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  _old_SP = C->compute_old_SP();
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  assert( is_even(_old_SP), "must be even" );
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  // Compute highest incoming stack argument as
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  //   _old_SP + out_preserve_stack_slots + incoming argument size.
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  _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
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  assert( is_even(_in_arg_limit), "out_preserve must be even" );
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  for( i = 0; i < argcnt; i++ ) {
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    // Permit args to have no register
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    _calling_convention_mask[i].Clear();
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    if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
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      continue;
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    }
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    // calling_convention returns stack arguments as a count of
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    // slots beyond OptoReg::stack0()/VMRegImpl::stack0.  We need to convert this to
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    // the allocators point of view, taking into account all the
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    // preserve area, locks & pad2.
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    OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
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    if( OptoReg::is_valid(reg1))
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      _calling_convention_mask[i].Insert(reg1);
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    OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
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    if( OptoReg::is_valid(reg2))
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      _calling_convention_mask[i].Insert(reg2);
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    // Saved biased stack-slot register number
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    _parm_regs[i].set_pair(reg2, reg1);
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  }
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  // Finally, make sure the incoming arguments take up an even number of
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  // words, in case the arguments or locals need to contain doubleword stack
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  // slots.  The rest of the system assumes that stack slot pairs (in
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  // particular, in the spill area) which look aligned will in fact be
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  // aligned relative to the stack pointer in the target machine.  Double
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  // stack slots will always be allocated aligned.
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  _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong));
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  // Compute highest outgoing stack argument as
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  //   _new_SP + out_preserve_stack_slots + max(outgoing argument size).
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  _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
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  assert( is_even(_out_arg_limit), "out_preserve must be even" );
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  if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
1
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    // the compiler cannot represent this method's calling sequence
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    C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
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  }
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  if (C->failing())  return;  // bailed out on incoming arg failure
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  // ---------------
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  // Collect roots of matcher trees.  Every node for which
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  // _shared[_idx] is cleared is guaranteed to not be shared, and thus
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  // can be a valid interior of some tree.
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  find_shared( C->root() );
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  find_shared( C->top() );
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  C->print_method(PHASE_BEFORE_MATCHING);
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  // Create new ideal node ConP #NULL even if it does exist in old space
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  // to avoid false sharing if the corresponding mach node is not used.
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  // The corresponding mach node is only used in rare cases for derived
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  // pointers.
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  Node* new_ideal_null = ConNode::make(TypePtr::NULL_PTR);
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1
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  // Swap out to old-space; emptying new-space
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  Arena *old = C->node_arena()->move_contents(C->old_arena());
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  // Save debug and profile information for nodes in old space:
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  _old_node_note_array = C->node_note_array();
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  if (_old_node_note_array != NULL) {
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    C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
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                           (C->comp_arena(), _old_node_note_array->length(),
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                            0, NULL));
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  }
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  // Pre-size the new_node table to avoid the need for range checks.
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  grow_new_node_array(C->unique());
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  // Reset node counter so MachNodes start with _idx at 0
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  int live_nodes = C->live_nodes();
1
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  C->set_unique(0);
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  C->reset_dead_node_list();
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  // Recursively match trees from old space into new space.
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  // Correct leaves of new-space Nodes; they point to old-space.
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  _visited.Clear();             // Clear visit bits for xform call
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  C->set_cached_top_node(xform( C->top(), live_nodes ));
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  if (!C->failing()) {
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    Node* xroot =        xform( C->root(), 1 );
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    if (xroot == NULL) {
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      Matcher::soft_match_failure();  // recursive matching process failed
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      C->record_method_not_compilable("instruction match failed");
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    } else {
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      // During matching shared constants were attached to C->root()
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      // because xroot wasn't available yet, so transfer the uses to
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      // the xroot.
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   347
      for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   348
        Node* n = C->root()->fast_out(j);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   349
        if (C->node_arena()->contains(n)) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   350
          assert(n->in(0) == C->root(), "should be control user");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   351
          n->set_req(0, xroot);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   352
          --j;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   353
          --jmax;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   354
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   355
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   356
2573
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2348
diff changeset
   357
      // Generate new mach node for ConP #NULL
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2348
diff changeset
   358
      assert(new_ideal_null != NULL, "sanity");
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2348
diff changeset
   359
      _mach_null = match_tree(new_ideal_null);
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2348
diff changeset
   360
      // Don't set control, it will confuse GCM since there are no uses.
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2348
diff changeset
   361
      // The control will be set when this node is used first time
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2348
diff changeset
   362
      // in find_base_for_derived().
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2348
diff changeset
   363
      assert(_mach_null != NULL, "");
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2348
diff changeset
   364
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   365
      C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
2573
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2348
diff changeset
   366
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   367
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   368
      verify_new_nodes_only(xroot);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   369
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   370
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   371
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   372
  if (C->top() == NULL || C->root() == NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   373
    C->record_method_not_compilable("graph lost"); // %%% cannot happen?
489c9b5090e2 Initial load
duke
parents:
diff changeset
   374
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   375
  if (C->failing()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   376
    // delete old;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   377
    old->destruct_contents();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   378
    return;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   379
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   380
  assert( C->top(), "" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   381
  assert( C->root(), "" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   382
  validate_null_checks();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   383
489c9b5090e2 Initial load
duke
parents:
diff changeset
   384
  // Now smoke old-space
489c9b5090e2 Initial load
duke
parents:
diff changeset
   385
  NOT_DEBUG( old->destruct_contents() );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   386
489c9b5090e2 Initial load
duke
parents:
diff changeset
   387
  // ------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   388
  // Set up save-on-entry registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
   389
  Fixup_Save_On_Entry( );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   390
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   391
489c9b5090e2 Initial load
duke
parents:
diff changeset
   392
489c9b5090e2 Initial load
duke
parents:
diff changeset
   393
//------------------------------Fixup_Save_On_Entry----------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   394
// The stated purpose of this routine is to take care of save-on-entry
489c9b5090e2 Initial load
duke
parents:
diff changeset
   395
// registers.  However, the overall goal of the Match phase is to convert into
489c9b5090e2 Initial load
duke
parents:
diff changeset
   396
// machine-specific instructions which have RegMasks to guide allocation.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   397
// So what this procedure really does is put a valid RegMask on each input
489c9b5090e2 Initial load
duke
parents:
diff changeset
   398
// to the machine-specific variations of all Return, TailCall and Halt
489c9b5090e2 Initial load
duke
parents:
diff changeset
   399
// instructions.  It also adds edgs to define the save-on-entry values (and of
489c9b5090e2 Initial load
duke
parents:
diff changeset
   400
// course gives them a mask).
489c9b5090e2 Initial load
duke
parents:
diff changeset
   401
489c9b5090e2 Initial load
duke
parents:
diff changeset
   402
static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   403
  RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   404
  // Do all the pre-defined register masks
489c9b5090e2 Initial load
duke
parents:
diff changeset
   405
  rms[TypeFunc::Control  ] = RegMask::Empty;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   406
  rms[TypeFunc::I_O      ] = RegMask::Empty;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   407
  rms[TypeFunc::Memory   ] = RegMask::Empty;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   408
  rms[TypeFunc::ReturnAdr] = ret_adr;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   409
  rms[TypeFunc::FramePtr ] = fp;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   410
  return rms;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   411
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   412
489c9b5090e2 Initial load
duke
parents:
diff changeset
   413
//---------------------------init_first_stack_mask-----------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   414
// Create the initial stack mask used by values spilling to the stack.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   415
// Disallow any debug info in outgoing argument areas by setting the
489c9b5090e2 Initial load
duke
parents:
diff changeset
   416
// initial mask accordingly.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   417
void Matcher::init_first_stack_mask() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   418
489c9b5090e2 Initial load
duke
parents:
diff changeset
   419
  // Allocate storage for spill masks as masks for the appropriate load type.
30624
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30300
diff changeset
   420
  RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+5));
4566
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   421
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   422
  idealreg2spillmask  [Op_RegN] = &rms[0];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   423
  idealreg2spillmask  [Op_RegI] = &rms[1];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   424
  idealreg2spillmask  [Op_RegL] = &rms[2];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   425
  idealreg2spillmask  [Op_RegF] = &rms[3];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   426
  idealreg2spillmask  [Op_RegD] = &rms[4];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   427
  idealreg2spillmask  [Op_RegP] = &rms[5];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   428
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   429
  idealreg2debugmask  [Op_RegN] = &rms[6];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   430
  idealreg2debugmask  [Op_RegI] = &rms[7];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   431
  idealreg2debugmask  [Op_RegL] = &rms[8];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   432
  idealreg2debugmask  [Op_RegF] = &rms[9];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   433
  idealreg2debugmask  [Op_RegD] = &rms[10];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   434
  idealreg2debugmask  [Op_RegP] = &rms[11];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   435
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   436
  idealreg2mhdebugmask[Op_RegN] = &rms[12];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   437
  idealreg2mhdebugmask[Op_RegI] = &rms[13];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   438
  idealreg2mhdebugmask[Op_RegL] = &rms[14];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   439
  idealreg2mhdebugmask[Op_RegF] = &rms[15];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   440
  idealreg2mhdebugmask[Op_RegD] = &rms[16];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   441
  idealreg2mhdebugmask[Op_RegP] = &rms[17];
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   442
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   443
  idealreg2spillmask  [Op_VecS] = &rms[18];
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   444
  idealreg2spillmask  [Op_VecD] = &rms[19];
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   445
  idealreg2spillmask  [Op_VecX] = &rms[20];
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   446
  idealreg2spillmask  [Op_VecY] = &rms[21];
30624
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30300
diff changeset
   447
  idealreg2spillmask  [Op_VecZ] = &rms[22];
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   448
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   449
  OptoReg::Name i;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   450
489c9b5090e2 Initial load
duke
parents:
diff changeset
   451
  // At first, start with the empty mask
489c9b5090e2 Initial load
duke
parents:
diff changeset
   452
  C->FIRST_STACK_mask().Clear();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   453
489c9b5090e2 Initial load
duke
parents:
diff changeset
   454
  // Add in the incoming argument area
21574
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   455
  OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   456
  for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   457
    C->FIRST_STACK_mask().Insert(i);
21574
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   458
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   459
  // Add in all bits past the outgoing argument area
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   460
  guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   461
            "must be able to represent all call arguments in reg mask");
21574
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   462
  OptoReg::Name init = _out_arg_limit;
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   463
  for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   464
    C->FIRST_STACK_mask().Insert(i);
21574
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   465
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   466
  // Finally, set the "infinite stack" bit.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   467
  C->FIRST_STACK_mask().set_AllStack();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   468
489c9b5090e2 Initial load
duke
parents:
diff changeset
   469
  // Make spill masks.  Registers for their class, plus FIRST_STACK_mask.
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   470
  RegMask aligned_stack_mask = C->FIRST_STACK_mask();
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   471
  // Keep spill masks aligned.
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   472
  aligned_stack_mask.clear_to_pairs();
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   473
  assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   474
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   475
  *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
   476
#ifdef _LP64
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
   477
  *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
   478
   idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   479
   idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   480
#else
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   481
   idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
   482
#endif
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   483
  *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   484
   idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
489c9b5090e2 Initial load
duke
parents:
diff changeset
   485
  *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   486
   idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   487
  *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   488
   idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
489c9b5090e2 Initial load
duke
parents:
diff changeset
   489
  *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   490
   idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   491
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   492
  if (Matcher::vector_size_supported(T_BYTE,4)) {
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   493
    *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   494
     idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   495
  }
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   496
  if (Matcher::vector_size_supported(T_FLOAT,2)) {
21574
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   497
    // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   498
    // RA guarantees such alignment since it is needed for Double and Long values.
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   499
    *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   500
     idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   501
  }
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   502
  if (Matcher::vector_size_supported(T_FLOAT,4)) {
21574
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   503
    // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   504
    //
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   505
    // RA can use input arguments stack slots for spills but until RA
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   506
    // we don't know frame size and offset of input arg stack slots.
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   507
    //
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   508
    // Exclude last input arg stack slots to avoid spilling vectors there
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   509
    // otherwise vector spills could stomp over stack slots in caller frame.
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   510
    OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   511
    for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   512
      aligned_stack_mask.Remove(in);
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   513
      in = OptoReg::add(in, -1);
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   514
    }
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   515
     aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   516
     assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   517
    *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   518
     idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   519
  }
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   520
  if (Matcher::vector_size_supported(T_FLOAT,8)) {
21574
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   521
    // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   522
    OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   523
    for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   524
      aligned_stack_mask.Remove(in);
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   525
      in = OptoReg::add(in, -1);
d47713227456 8024830: SEGV in org.apache.lucene.codecs.compressing.CompressingTermVectorsReader.get
kvn
parents: 20289
diff changeset
   526
    }
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   527
     aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   528
     assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   529
    *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   530
     idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   531
  }
30624
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30300
diff changeset
   532
  if (Matcher::vector_size_supported(T_FLOAT,16)) {
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30300
diff changeset
   533
    // For VecZ we need enough alignment and 64 bytes (16 slots) for spills.
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30300
diff changeset
   534
    OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30300
diff changeset
   535
    for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) {
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30300
diff changeset
   536
      aligned_stack_mask.Remove(in);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30300
diff changeset
   537
      in = OptoReg::add(in, -1);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30300
diff changeset
   538
    }
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30300
diff changeset
   539
     aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30300
diff changeset
   540
     assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30300
diff changeset
   541
    *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ];
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30300
diff changeset
   542
     idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30300
diff changeset
   543
  }
6272
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5702
diff changeset
   544
   if (UseFPUForSpilling) {
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5702
diff changeset
   545
     // This mask logic assumes that the spill operations are
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5702
diff changeset
   546
     // symmetric and that the registers involved are the same size.
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5702
diff changeset
   547
     // On sparc for instance we may have to use 64 bit moves will
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5702
diff changeset
   548
     // kill 2 registers when used with F0-F31.
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5702
diff changeset
   549
     idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5702
diff changeset
   550
     idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5702
diff changeset
   551
#ifdef _LP64
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5702
diff changeset
   552
     idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5702
diff changeset
   553
     idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5702
diff changeset
   554
     idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5702
diff changeset
   555
     idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5702
diff changeset
   556
#else
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5702
diff changeset
   557
     idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
10518
71e6d7ccdc8d 7086394: c2/arm: enable UseFPUForSpilling
roland
parents: 10514
diff changeset
   558
#ifdef ARM
71e6d7ccdc8d 7086394: c2/arm: enable UseFPUForSpilling
roland
parents: 10514
diff changeset
   559
     // ARM has support for moving 64bit values between a pair of
71e6d7ccdc8d 7086394: c2/arm: enable UseFPUForSpilling
roland
parents: 10514
diff changeset
   560
     // integer registers and a double register
71e6d7ccdc8d 7086394: c2/arm: enable UseFPUForSpilling
roland
parents: 10514
diff changeset
   561
     idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
71e6d7ccdc8d 7086394: c2/arm: enable UseFPUForSpilling
roland
parents: 10514
diff changeset
   562
     idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
71e6d7ccdc8d 7086394: c2/arm: enable UseFPUForSpilling
roland
parents: 10514
diff changeset
   563
#endif
6272
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5702
diff changeset
   564
#endif
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5702
diff changeset
   565
   }
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5702
diff changeset
   566
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   567
  // Make up debug masks.  Any spill slot plus callee-save registers.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   568
  // Caller-save registers are assumed to be trashable by the various
489c9b5090e2 Initial load
duke
parents:
diff changeset
   569
  // inline-cache fixup routines.
4566
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   570
  *idealreg2debugmask  [Op_RegN]= *idealreg2spillmask[Op_RegN];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   571
  *idealreg2debugmask  [Op_RegI]= *idealreg2spillmask[Op_RegI];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   572
  *idealreg2debugmask  [Op_RegL]= *idealreg2spillmask[Op_RegL];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   573
  *idealreg2debugmask  [Op_RegF]= *idealreg2spillmask[Op_RegF];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   574
  *idealreg2debugmask  [Op_RegD]= *idealreg2spillmask[Op_RegD];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   575
  *idealreg2debugmask  [Op_RegP]= *idealreg2spillmask[Op_RegP];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   576
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   577
  *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   578
  *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   579
  *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   580
  *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   581
  *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   582
  *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   583
489c9b5090e2 Initial load
duke
parents:
diff changeset
   584
  // Prevent stub compilations from attempting to reference
489c9b5090e2 Initial load
duke
parents:
diff changeset
   585
  // callee-saved registers from debug info
489c9b5090e2 Initial load
duke
parents:
diff changeset
   586
  bool exclude_soe = !Compile::current()->is_method_compilation();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   587
489c9b5090e2 Initial load
duke
parents:
diff changeset
   588
  for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   589
    // registers the caller has to save do not work
489c9b5090e2 Initial load
duke
parents:
diff changeset
   590
    if( _register_save_policy[i] == 'C' ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
   591
        _register_save_policy[i] == 'A' ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
   592
        (_register_save_policy[i] == 'E' && exclude_soe) ) {
4566
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   593
      idealreg2debugmask  [Op_RegN]->Remove(i);
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   594
      idealreg2debugmask  [Op_RegI]->Remove(i); // Exclude save-on-call
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   595
      idealreg2debugmask  [Op_RegL]->Remove(i); // registers from debug
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   596
      idealreg2debugmask  [Op_RegF]->Remove(i); // masks
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   597
      idealreg2debugmask  [Op_RegD]->Remove(i);
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   598
      idealreg2debugmask  [Op_RegP]->Remove(i);
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   599
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   600
      idealreg2mhdebugmask[Op_RegN]->Remove(i);
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   601
      idealreg2mhdebugmask[Op_RegI]->Remove(i);
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   602
      idealreg2mhdebugmask[Op_RegL]->Remove(i);
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   603
      idealreg2mhdebugmask[Op_RegF]->Remove(i);
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   604
      idealreg2mhdebugmask[Op_RegD]->Remove(i);
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   605
      idealreg2mhdebugmask[Op_RegP]->Remove(i);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   606
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   607
  }
4566
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   608
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   609
  // Subtract the register we use to save the SP for MethodHandle
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   610
  // invokes to from the debug mask.
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   611
  const RegMask save_mask = method_handle_invoke_SP_save_mask();
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   612
  idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   613
  idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   614
  idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   615
  idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   616
  idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
   617
  idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   618
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   619
489c9b5090e2 Initial load
duke
parents:
diff changeset
   620
//---------------------------is_save_on_entry----------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   621
bool Matcher::is_save_on_entry( int reg ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   622
  return
489c9b5090e2 Initial load
duke
parents:
diff changeset
   623
    _register_save_policy[reg] == 'E' ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
   624
    _register_save_policy[reg] == 'A' || // Save-on-entry register?
489c9b5090e2 Initial load
duke
parents:
diff changeset
   625
    // Also save argument registers in the trampolining stubs
489c9b5090e2 Initial load
duke
parents:
diff changeset
   626
    (C->save_argument_registers() && is_spillable_arg(reg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   627
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   628
489c9b5090e2 Initial load
duke
parents:
diff changeset
   629
//---------------------------Fixup_Save_On_Entry-------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   630
void Matcher::Fixup_Save_On_Entry( ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   631
  init_first_stack_mask();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   632
489c9b5090e2 Initial load
duke
parents:
diff changeset
   633
  Node *root = C->root();       // Short name for root
489c9b5090e2 Initial load
duke
parents:
diff changeset
   634
  // Count number of save-on-entry registers.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   635
  uint soe_cnt = number_of_saved_registers();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   636
  uint i;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   637
489c9b5090e2 Initial load
duke
parents:
diff changeset
   638
  // Find the procedure Start Node
489c9b5090e2 Initial load
duke
parents:
diff changeset
   639
  StartNode *start = C->start();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   640
  assert( start, "Expect a start node" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   641
489c9b5090e2 Initial load
duke
parents:
diff changeset
   642
  // Save argument registers in the trampolining stubs
489c9b5090e2 Initial load
duke
parents:
diff changeset
   643
  if( C->save_argument_registers() )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   644
    for( i = 0; i < _last_Mach_Reg; i++ )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   645
      if( is_spillable_arg(i) )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   646
        soe_cnt++;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   647
489c9b5090e2 Initial load
duke
parents:
diff changeset
   648
  // Input RegMask array shared by all Returns.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   649
  // The type for doubles and longs has a count of 2, but
489c9b5090e2 Initial load
duke
parents:
diff changeset
   650
  // there is only 1 returned value
489c9b5090e2 Initial load
duke
parents:
diff changeset
   651
  uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   652
  RegMask *ret_rms  = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   653
  // Returns have 0 or 1 returned values depending on call signature.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   654
  // Return register is specified by return_value in the AD file.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   655
  if (ret_edge_cnt > TypeFunc::Parms)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   656
    ret_rms[TypeFunc::Parms+0] = _return_value_mask;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   657
489c9b5090e2 Initial load
duke
parents:
diff changeset
   658
  // Input RegMask array shared by all Rethrows.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   659
  uint reth_edge_cnt = TypeFunc::Parms+1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   660
  RegMask *reth_rms  = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   661
  // Rethrow takes exception oop only, but in the argument 0 slot.
38658
34f9c45625d8 8140594: Various minor code improvements (compiler)
goetz
parents: 38286
diff changeset
   662
  OptoReg::Name reg = find_receiver(false);
34f9c45625d8 8140594: Various minor code improvements (compiler)
goetz
parents: 38286
diff changeset
   663
  if (reg >= 0) {
34f9c45625d8 8140594: Various minor code improvements (compiler)
goetz
parents: 38286
diff changeset
   664
    reth_rms[TypeFunc::Parms] = mreg2regmask[reg];
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   665
#ifdef _LP64
38658
34f9c45625d8 8140594: Various minor code improvements (compiler)
goetz
parents: 38286
diff changeset
   666
    // Need two slots for ptrs in 64-bit land
34f9c45625d8 8140594: Various minor code improvements (compiler)
goetz
parents: 38286
diff changeset
   667
    reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(reg), 1));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   668
#endif
38658
34f9c45625d8 8140594: Various minor code improvements (compiler)
goetz
parents: 38286
diff changeset
   669
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   670
489c9b5090e2 Initial load
duke
parents:
diff changeset
   671
  // Input RegMask array shared by all TailCalls
489c9b5090e2 Initial load
duke
parents:
diff changeset
   672
  uint tail_call_edge_cnt = TypeFunc::Parms+2;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   673
  RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   674
489c9b5090e2 Initial load
duke
parents:
diff changeset
   675
  // Input RegMask array shared by all TailJumps
489c9b5090e2 Initial load
duke
parents:
diff changeset
   676
  uint tail_jump_edge_cnt = TypeFunc::Parms+2;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   677
  RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   678
489c9b5090e2 Initial load
duke
parents:
diff changeset
   679
  // TailCalls have 2 returned values (target & moop), whose masks come
489c9b5090e2 Initial load
duke
parents:
diff changeset
   680
  // from the usual MachNode/MachOper mechanism.  Find a sample
489c9b5090e2 Initial load
duke
parents:
diff changeset
   681
  // TailCall to extract these masks and put the correct masks into
489c9b5090e2 Initial load
duke
parents:
diff changeset
   682
  // the tail_call_rms array.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   683
  for( i=1; i < root->req(); i++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   684
    MachReturnNode *m = root->in(i)->as_MachReturn();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   685
    if( m->ideal_Opcode() == Op_TailCall ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   686
      tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   687
      tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   688
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   689
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   690
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   691
489c9b5090e2 Initial load
duke
parents:
diff changeset
   692
  // TailJumps have 2 returned values (target & ex_oop), whose masks come
489c9b5090e2 Initial load
duke
parents:
diff changeset
   693
  // from the usual MachNode/MachOper mechanism.  Find a sample
489c9b5090e2 Initial load
duke
parents:
diff changeset
   694
  // TailJump to extract these masks and put the correct masks into
489c9b5090e2 Initial load
duke
parents:
diff changeset
   695
  // the tail_jump_rms array.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   696
  for( i=1; i < root->req(); i++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   697
    MachReturnNode *m = root->in(i)->as_MachReturn();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   698
    if( m->ideal_Opcode() == Op_TailJump ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   699
      tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   700
      tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   701
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   702
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   703
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   704
489c9b5090e2 Initial load
duke
parents:
diff changeset
   705
  // Input RegMask array shared by all Halts
489c9b5090e2 Initial load
duke
parents:
diff changeset
   706
  uint halt_edge_cnt = TypeFunc::Parms;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   707
  RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   708
489c9b5090e2 Initial load
duke
parents:
diff changeset
   709
  // Capture the return input masks into each exit flavor
489c9b5090e2 Initial load
duke
parents:
diff changeset
   710
  for( i=1; i < root->req(); i++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   711
    MachReturnNode *exit = root->in(i)->as_MachReturn();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   712
    switch( exit->ideal_Opcode() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   713
      case Op_Return   : exit->_in_rms = ret_rms;  break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   714
      case Op_Rethrow  : exit->_in_rms = reth_rms; break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   715
      case Op_TailCall : exit->_in_rms = tail_call_rms; break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   716
      case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   717
      case Op_Halt     : exit->_in_rms = halt_rms; break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   718
      default          : ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   719
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   720
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   721
489c9b5090e2 Initial load
duke
parents:
diff changeset
   722
  // Next unused projection number from Start.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   723
  int proj_cnt = C->tf()->domain()->cnt();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   724
489c9b5090e2 Initial load
duke
parents:
diff changeset
   725
  // Do all the save-on-entry registers.  Make projections from Start for
489c9b5090e2 Initial load
duke
parents:
diff changeset
   726
  // them, and give them a use at the exit points.  To the allocator, they
489c9b5090e2 Initial load
duke
parents:
diff changeset
   727
  // look like incoming register arguments.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   728
  for( i = 0; i < _last_Mach_Reg; i++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   729
    if( is_save_on_entry(i) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   730
489c9b5090e2 Initial load
duke
parents:
diff changeset
   731
      // Add the save-on-entry to the mask array
489c9b5090e2 Initial load
duke
parents:
diff changeset
   732
      ret_rms      [      ret_edge_cnt] = mreg2regmask[i];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   733
      reth_rms     [     reth_edge_cnt] = mreg2regmask[i];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   734
      tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   735
      tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   736
      // Halts need the SOE registers, but only in the stack as debug info.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   737
      // A just-prior uncommon-trap or deoptimization will use the SOE regs.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   738
      halt_rms     [     halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   739
489c9b5090e2 Initial load
duke
parents:
diff changeset
   740
      Node *mproj;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   741
489c9b5090e2 Initial load
duke
parents:
diff changeset
   742
      // Is this a RegF low half of a RegD?  Double up 2 adjacent RegF's
489c9b5090e2 Initial load
duke
parents:
diff changeset
   743
      // into a single RegD.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   744
      if( (i&1) == 0 &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   745
          _register_save_type[i  ] == Op_RegF &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   746
          _register_save_type[i+1] == Op_RegF &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   747
          is_save_on_entry(i+1) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   748
        // Add other bit for double
489c9b5090e2 Initial load
duke
parents:
diff changeset
   749
        ret_rms      [      ret_edge_cnt].Insert(OptoReg::Name(i+1));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   750
        reth_rms     [     reth_edge_cnt].Insert(OptoReg::Name(i+1));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   751
        tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   752
        tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   753
        halt_rms     [     halt_edge_cnt].Insert(OptoReg::Name(i+1));
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24424
diff changeset
   754
        mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   755
        proj_cnt += 2;          // Skip 2 for doubles
489c9b5090e2 Initial load
duke
parents:
diff changeset
   756
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   757
      else if( (i&1) == 1 &&    // Else check for high half of double
489c9b5090e2 Initial load
duke
parents:
diff changeset
   758
               _register_save_type[i-1] == Op_RegF &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   759
               _register_save_type[i  ] == Op_RegF &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   760
               is_save_on_entry(i-1) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   761
        ret_rms      [      ret_edge_cnt] = RegMask::Empty;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   762
        reth_rms     [     reth_edge_cnt] = RegMask::Empty;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   763
        tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   764
        tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   765
        halt_rms     [     halt_edge_cnt] = RegMask::Empty;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   766
        mproj = C->top();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   767
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   768
      // Is this a RegI low half of a RegL?  Double up 2 adjacent RegI's
489c9b5090e2 Initial load
duke
parents:
diff changeset
   769
      // into a single RegL.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   770
      else if( (i&1) == 0 &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   771
          _register_save_type[i  ] == Op_RegI &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   772
          _register_save_type[i+1] == Op_RegI &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   773
        is_save_on_entry(i+1) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   774
        // Add other bit for long
489c9b5090e2 Initial load
duke
parents:
diff changeset
   775
        ret_rms      [      ret_edge_cnt].Insert(OptoReg::Name(i+1));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   776
        reth_rms     [     reth_edge_cnt].Insert(OptoReg::Name(i+1));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   777
        tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   778
        tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   779
        halt_rms     [     halt_edge_cnt].Insert(OptoReg::Name(i+1));
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24424
diff changeset
   780
        mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   781
        proj_cnt += 2;          // Skip 2 for longs
489c9b5090e2 Initial load
duke
parents:
diff changeset
   782
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   783
      else if( (i&1) == 1 &&    // Else check for high half of long
489c9b5090e2 Initial load
duke
parents:
diff changeset
   784
               _register_save_type[i-1] == Op_RegI &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   785
               _register_save_type[i  ] == Op_RegI &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   786
               is_save_on_entry(i-1) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   787
        ret_rms      [      ret_edge_cnt] = RegMask::Empty;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   788
        reth_rms     [     reth_edge_cnt] = RegMask::Empty;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   789
        tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   790
        tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   791
        halt_rms     [     halt_edge_cnt] = RegMask::Empty;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   792
        mproj = C->top();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   793
      } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   794
        // Make a projection for it off the Start
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24424
diff changeset
   795
        mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   796
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   797
489c9b5090e2 Initial load
duke
parents:
diff changeset
   798
      ret_edge_cnt ++;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   799
      reth_edge_cnt ++;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   800
      tail_call_edge_cnt ++;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   801
      tail_jump_edge_cnt ++;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   802
      halt_edge_cnt ++;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   803
489c9b5090e2 Initial load
duke
parents:
diff changeset
   804
      // Add a use of the SOE register to all exit paths
489c9b5090e2 Initial load
duke
parents:
diff changeset
   805
      for( uint j=1; j < root->req(); j++ )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   806
        root->in(j)->add_req(mproj);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   807
    } // End of if a save-on-entry register
489c9b5090e2 Initial load
duke
parents:
diff changeset
   808
  } // End of for all machine registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
   809
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   810
489c9b5090e2 Initial load
duke
parents:
diff changeset
   811
//------------------------------init_spill_mask--------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   812
void Matcher::init_spill_mask( Node *ret ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   813
  if( idealreg2regmask[Op_RegI] ) return; // One time only init
489c9b5090e2 Initial load
duke
parents:
diff changeset
   814
489c9b5090e2 Initial load
duke
parents:
diff changeset
   815
  OptoReg::c_frame_pointer = c_frame_pointer();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   816
  c_frame_ptr_mask = c_frame_pointer();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   817
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
   818
  // pointers are twice as big
489c9b5090e2 Initial load
duke
parents:
diff changeset
   819
  c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   820
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   821
489c9b5090e2 Initial load
duke
parents:
diff changeset
   822
  // Start at OptoReg::stack0()
489c9b5090e2 Initial load
duke
parents:
diff changeset
   823
  STACK_ONLY_mask.Clear();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   824
  OptoReg::Name init = OptoReg::stack2reg(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   825
  // STACK_ONLY_mask is all stack bits
489c9b5090e2 Initial load
duke
parents:
diff changeset
   826
  OptoReg::Name i;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   827
  for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
489c9b5090e2 Initial load
duke
parents:
diff changeset
   828
    STACK_ONLY_mask.Insert(i);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   829
  // Also set the "infinite stack" bit.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   830
  STACK_ONLY_mask.set_AllStack();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   831
489c9b5090e2 Initial load
duke
parents:
diff changeset
   832
  // Copy the register names over into the shared world
489c9b5090e2 Initial load
duke
parents:
diff changeset
   833
  for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   834
    // SharedInfo::regName[i] = regName[i];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   835
    // Handy RegMasks per machine register
489c9b5090e2 Initial load
duke
parents:
diff changeset
   836
    mreg2regmask[i].Insert(i);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   837
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   838
489c9b5090e2 Initial load
duke
parents:
diff changeset
   839
  // Grab the Frame Pointer
489c9b5090e2 Initial load
duke
parents:
diff changeset
   840
  Node *fp  = ret->in(TypeFunc::FramePtr);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   841
  Node *mem = ret->in(TypeFunc::Memory);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   842
  const TypePtr* atp = TypePtr::BOTTOM;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   843
  // Share frame pointer while making spill ops
489c9b5090e2 Initial load
duke
parents:
diff changeset
   844
  set_shared(fp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   845
489c9b5090e2 Initial load
duke
parents:
diff changeset
   846
  // Compute generic short-offset Loads
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
   847
#ifdef _LP64
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24424
diff changeset
   848
  MachNode *spillCP = match_tree(new LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
   849
#endif
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24424
diff changeset
   850
  MachNode *spillI  = match_tree(new LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered));
31035
0f0743952c41 8077504: Unsafe load can loose control dependency and cause crash
roland
parents: 30624
diff changeset
   851
  MachNode *spillL  = match_tree(new LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered, LoadNode::DependsOnlyOnTest, false));
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24424
diff changeset
   852
  MachNode *spillF  = match_tree(new LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered));
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24424
diff changeset
   853
  MachNode *spillD  = match_tree(new LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered));
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24424
diff changeset
   854
  MachNode *spillP  = match_tree(new LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   855
  assert(spillI != NULL && spillL != NULL && spillF != NULL &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   856
         spillD != NULL && spillP != NULL, "");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   857
  // Get the ADLC notion of the right regmask, for each basic type.
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
   858
#ifdef _LP64
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
   859
  idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
   860
#endif
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   861
  idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   862
  idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   863
  idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   864
  idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   865
  idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   866
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   867
  // Vector regmasks.
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   868
  if (Matcher::vector_size_supported(T_BYTE,4)) {
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   869
    TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24424
diff changeset
   870
    MachNode *spillVectS = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   871
    idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   872
  }
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   873
  if (Matcher::vector_size_supported(T_FLOAT,2)) {
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24424
diff changeset
   874
    MachNode *spillVectD = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   875
    idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   876
  }
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   877
  if (Matcher::vector_size_supported(T_FLOAT,4)) {
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24424
diff changeset
   878
    MachNode *spillVectX = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX));
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   879
    idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask();
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   880
  }
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   881
  if (Matcher::vector_size_supported(T_FLOAT,8)) {
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24424
diff changeset
   882
    MachNode *spillVectY = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY));
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   883
    idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask();
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
   884
  }
30624
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30300
diff changeset
   885
  if (Matcher::vector_size_supported(T_FLOAT,16)) {
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30300
diff changeset
   886
    MachNode *spillVectZ = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTZ));
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30300
diff changeset
   887
    idealreg2regmask[Op_VecZ] = &spillVectZ->out_RegMask();
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30300
diff changeset
   888
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   889
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   890
489c9b5090e2 Initial load
duke
parents:
diff changeset
   891
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   892
static void match_alias_type(Compile* C, Node* n, Node* m) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   893
  if (!VerifyAliases)  return;  // do not go looking for trouble by default
489c9b5090e2 Initial load
duke
parents:
diff changeset
   894
  const TypePtr* nat = n->adr_type();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   895
  const TypePtr* mat = m->adr_type();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   896
  int nidx = C->get_alias_index(nat);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   897
  int midx = C->get_alias_index(mat);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   898
  // Detune the assert for cases like (AndI 0xFF (LoadB p)).
489c9b5090e2 Initial load
duke
parents:
diff changeset
   899
  if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   900
    for (uint i = 1; i < n->req(); i++) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   901
      Node* n1 = n->in(i);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   902
      const TypePtr* n1at = n1->adr_type();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   903
      if (n1at != NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   904
        nat = n1at;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   905
        nidx = C->get_alias_index(n1at);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   906
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   907
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   908
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   909
  // %%% Kludgery.  Instead, fix ideal adr_type methods for all these cases:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   910
  if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   911
    switch (n->Opcode()) {
10267
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10262
diff changeset
   912
    case Op_PrefetchAllocation:
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   913
      nidx = Compile::AliasIdxRaw;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   914
      nat = TypeRawPtr::BOTTOM;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   915
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   916
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   917
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   918
  if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   919
    switch (n->Opcode()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   920
    case Op_ClearArray:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   921
      midx = Compile::AliasIdxRaw;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   922
      mat = TypeRawPtr::BOTTOM;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   923
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   924
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   925
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   926
  if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   927
    switch (n->Opcode()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   928
    case Op_Return:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   929
    case Op_Rethrow:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   930
    case Op_Halt:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   931
    case Op_TailCall:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   932
    case Op_TailJump:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   933
      nidx = Compile::AliasIdxBot;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   934
      nat = TypePtr::BOTTOM;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   935
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   936
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   937
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   938
  if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   939
    switch (n->Opcode()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   940
    case Op_StrComp:
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
   941
    case Op_StrEquals:
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
   942
    case Op_StrIndexOf:
33628
09241459a8b8 8141132: JEP 254: Compact Strings
thartmann
parents: 33469
diff changeset
   943
    case Op_StrIndexOfChar:
595
a2be4c89de81 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 594
diff changeset
   944
    case Op_AryEq:
33628
09241459a8b8 8141132: JEP 254: Compact Strings
thartmann
parents: 33469
diff changeset
   945
    case Op_HasNegatives:
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   946
    case Op_MemBarVolatile:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   947
    case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
33628
09241459a8b8 8141132: JEP 254: Compact Strings
thartmann
parents: 33469
diff changeset
   948
    case Op_StrInflatedCopy:
09241459a8b8 8141132: JEP 254: Compact Strings
thartmann
parents: 33469
diff changeset
   949
    case Op_StrCompressedCopy:
38017
55047d16f141 8147844: new method j.l.Runtime.onSpinWait() and the corresponding x86 hotspot instrinsic
ikrylov
parents: 36336
diff changeset
   950
    case Op_OnSpinWait:
15242
695bb216be99 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents: 14623
diff changeset
   951
    case Op_EncodeISOArray:
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   952
      nidx = Compile::AliasIdxTop;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   953
      nat = NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   954
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   955
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   956
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   957
  if (nidx != midx) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   958
    if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   959
      tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   960
      n->dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   961
      m->dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   962
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   963
    assert(C->subsume_loads() && C->must_alias(nat, midx),
489c9b5090e2 Initial load
duke
parents:
diff changeset
   964
           "must not lose alias info when matching");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   965
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   966
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   967
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   968
489c9b5090e2 Initial load
duke
parents:
diff changeset
   969
//------------------------------xform------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   970
// Given a Node in old-space, Match him (Label/Reduce) to produce a machine
489c9b5090e2 Initial load
duke
parents:
diff changeset
   971
// Node in new-space.  Given a new-space Node, recursively walk his children.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   972
Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   973
Node *Matcher::xform( Node *n, int max_stack ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   974
  // Use one stack to keep both: child's node/state and parent's node/index
33158
f4e6c593ba73 8137160: Use Compile::live_nodes instead of Compile::unique() in appropriate places -- followup
zmajo
parents: 33082
diff changeset
   975
  MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   976
  mstack.push(n, Visit, NULL, -1);  // set NULL as parent to indicate root
489c9b5090e2 Initial load
duke
parents:
diff changeset
   977
489c9b5090e2 Initial load
duke
parents:
diff changeset
   978
  while (mstack.is_nonempty()) {
18099
45973b036c3e 8014959: assert(Compile::current()->live_nodes() < (uint)MaxNodeLimit) failed: Live Node limit exceeded limit
drchase
parents: 17875
diff changeset
   979
    C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
45973b036c3e 8014959: assert(Compile::current()->live_nodes() < (uint)MaxNodeLimit) failed: Live Node limit exceeded limit
drchase
parents: 17875
diff changeset
   980
    if (C->failing()) return NULL;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   981
    n = mstack.node();          // Leave node on stack
489c9b5090e2 Initial load
duke
parents:
diff changeset
   982
    Node_State nstate = mstack.state();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   983
    if (nstate == Visit) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   984
      mstack.set_state(Post_Visit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   985
      Node *oldn = n;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   986
      // Old-space or new-space check
489c9b5090e2 Initial load
duke
parents:
diff changeset
   987
      if (!C->node_arena()->contains(n)) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   988
        // Old space!
489c9b5090e2 Initial load
duke
parents:
diff changeset
   989
        Node* m;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   990
        if (has_new_node(n)) {  // Not yet Label/Reduced
489c9b5090e2 Initial load
duke
parents:
diff changeset
   991
          m = new_node(n);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   992
        } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   993
          if (!is_dontcare(n)) { // Matcher can match this guy
489c9b5090e2 Initial load
duke
parents:
diff changeset
   994
            // Calls match special.  They match alone with no children.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   995
            // Their children, the incoming arguments, match normally.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   996
            m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   997
            if (C->failing())  return NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   998
            if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   999
          } else {                  // Nothing the matcher cares about
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1000
            if( n->is_Proj() && n->in(0)->is_Multi()) {       // Projections?
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1001
              // Convert to machine-dependent projection
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1002
              m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
768
d0bebc7eefc2 6718676: putback for 6604014 is incomplete
never
parents: 767
diff changeset
  1003
#ifdef ASSERT
d0bebc7eefc2 6718676: putback for 6604014 is incomplete
never
parents: 767
diff changeset
  1004
              _new2old_map.map(m->_idx, n);
d0bebc7eefc2 6718676: putback for 6604014 is incomplete
never
parents: 767
diff changeset
  1005
#endif
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1006
              if (m->in(0) != NULL) // m might be top
1400
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  1007
                collect_null_checks(m, n);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1008
            } else {                // Else just a regular 'ol guy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1009
              m = n->clone();       // So just clone into new-space
768
d0bebc7eefc2 6718676: putback for 6604014 is incomplete
never
parents: 767
diff changeset
  1010
#ifdef ASSERT
d0bebc7eefc2 6718676: putback for 6604014 is incomplete
never
parents: 767
diff changeset
  1011
              _new2old_map.map(m->_idx, n);
d0bebc7eefc2 6718676: putback for 6604014 is incomplete
never
parents: 767
diff changeset
  1012
#endif
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1013
              // Def-Use edges will be added incrementally as Uses
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1014
              // of this node are matched.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1015
              assert(m->outcnt() == 0, "no Uses of this clone yet");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1016
            }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1017
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1018
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1019
          set_new_node(n, m);       // Map old to new
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1020
          if (_old_node_note_array != NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1021
            Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1022
                                                  n->_idx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1023
            C->set_node_notes_at(m->_idx, nn);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1024
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1025
          debug_only(match_alias_type(C, n, m));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1026
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1027
        n = m;    // n is now a new-space node
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1028
        mstack.set_node(n);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1029
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1030
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1031
      // New space!
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1032
      if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1033
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1034
      int i;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1035
      // Put precedence edges on stack first (match them last).
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1036
      for (i = oldn->req(); (uint)i < oldn->len(); i++) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1037
        Node *m = oldn->in(i);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1038
        if (m == NULL) break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1039
        // set -1 to call add_prec() instead of set_req() during Step1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1040
        mstack.push(m, Visit, n, -1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1041
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1042
30300
4b12a5b40064 8069191: moving predicate out of loops may cause array accesses to bypass null check
roland
parents: 29083
diff changeset
  1043
      // Handle precedence edges for interior nodes
4b12a5b40064 8069191: moving predicate out of loops may cause array accesses to bypass null check
roland
parents: 29083
diff changeset
  1044
      for (i = n->len()-1; (uint)i >= n->req(); i--) {
4b12a5b40064 8069191: moving predicate out of loops may cause array accesses to bypass null check
roland
parents: 29083
diff changeset
  1045
        Node *m = n->in(i);
4b12a5b40064 8069191: moving predicate out of loops may cause array accesses to bypass null check
roland
parents: 29083
diff changeset
  1046
        if (m == NULL || C->node_arena()->contains(m)) continue;
4b12a5b40064 8069191: moving predicate out of loops may cause array accesses to bypass null check
roland
parents: 29083
diff changeset
  1047
        n->rm_prec(i);
4b12a5b40064 8069191: moving predicate out of loops may cause array accesses to bypass null check
roland
parents: 29083
diff changeset
  1048
        // set -1 to call add_prec() instead of set_req() during Step1
4b12a5b40064 8069191: moving predicate out of loops may cause array accesses to bypass null check
roland
parents: 29083
diff changeset
  1049
        mstack.push(m, Visit, n, -1);
4b12a5b40064 8069191: moving predicate out of loops may cause array accesses to bypass null check
roland
parents: 29083
diff changeset
  1050
      }
4b12a5b40064 8069191: moving predicate out of loops may cause array accesses to bypass null check
roland
parents: 29083
diff changeset
  1051
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1052
      // For constant debug info, I'd rather have unmatched constants.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1053
      int cnt = n->req();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1054
      JVMState* jvms = n->jvms();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1055
      int debug_cnt = jvms ? jvms->debug_start() : cnt;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1056
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1057
      // Now do only debug info.  Clone constants rather than matching.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1058
      // Constants are represented directly in the debug info without
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1059
      // the need for executable machine instructions.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1060
      // Monitor boxes are also represented directly.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1061
      for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1062
        Node *m = n->in(i);          // Get input
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1063
        int op = m->Opcode();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1064
        assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
13969
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13895
diff changeset
  1065
        if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1066
            op == Op_ConF || op == Op_ConD || op == Op_ConL
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1067
            // || op == Op_BoxLock  // %%%% enable this and remove (+++) in chaitin.cpp
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1068
            ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1069
          m = m->clone();
768
d0bebc7eefc2 6718676: putback for 6604014 is incomplete
never
parents: 767
diff changeset
  1070
#ifdef ASSERT
d0bebc7eefc2 6718676: putback for 6604014 is incomplete
never
parents: 767
diff changeset
  1071
          _new2old_map.map(m->_idx, n);
d0bebc7eefc2 6718676: putback for 6604014 is incomplete
never
parents: 767
diff changeset
  1072
#endif
2131
98f9cef66a34 6810672: Comment typos
twisti
parents: 2112
diff changeset
  1073
          mstack.push(m, Post_Visit, n, i); // Don't need to visit
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1074
          mstack.push(m->in(0), Visit, m, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1075
        } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1076
          mstack.push(m, Visit, n, i);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1077
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1078
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1079
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1080
      // And now walk his children, and convert his inputs to new-space.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1081
      for( ; i >= 0; --i ) { // For all normal inputs do
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1082
        Node *m = n->in(i);  // Get input
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1083
        if(m != NULL)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1084
          mstack.push(m, Visit, n, i);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1085
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1086
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1087
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1088
    else if (nstate == Post_Visit) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1089
      // Set xformed input
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1090
      Node *p = mstack.parent();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1091
      if (p != NULL) { // root doesn't have parent
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1092
        int i = (int)mstack.index();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1093
        if (i >= 0)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1094
          p->set_req(i, n); // required input
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1095
        else if (i == -1)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1096
          p->add_prec(n);   // precedence input
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1097
        else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1098
          ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1099
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1100
      mstack.pop(); // remove processed node from stack
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1101
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1102
    else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1103
      ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1104
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1105
  } // while (mstack.is_nonempty())
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1106
  return n; // Return new-space Node
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1107
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1108
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1109
//------------------------------warp_outgoing_stk_arg------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1110
OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1111
  // Convert outgoing argument location to a pre-biased stack offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1112
  if (reg->is_stack()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1113
    OptoReg::Name warped = reg->reg2stack();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1114
    // Adjust the stack slot offset to be the register number used
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1115
    // by the allocator.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1116
    warped = OptoReg::add(begin_out_arg_area, warped);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1117
    // Keep track of the largest numbered stack slot used for an arg.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1118
    // Largest used slot per call-site indicates the amount of stack
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1119
    // that is killed by the call.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1120
    if( warped >= out_arg_limit_per_call )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1121
      out_arg_limit_per_call = OptoReg::add(warped,1);
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
  1122
    if (!RegMask::can_represent_arg(warped)) {
39431
cb1b2538c4b2 8159720: Failure of C2 compilation with tiered prevents some C1 compilations.
cvarming
parents: 39419
diff changeset
  1123
      C->record_method_not_compilable("unsupported calling sequence");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1124
      return OptoReg::Bad;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1125
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1126
    return warped;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1127
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1128
  return OptoReg::as_OptoReg(reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1129
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1130
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1131
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1132
//------------------------------match_sfpt-------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1133
// Helper function to match call instructions.  Calls match special.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1134
// They match alone with no children.  Their children, the incoming
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1135
// arguments, match normally.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1136
MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1137
  MachSafePointNode *msfpt = NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1138
  MachCallNode      *mcall = NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1139
  uint               cnt;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1140
  // Split out case for SafePoint vs Call
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1141
  CallNode *call;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1142
  const TypeTuple *domain;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1143
  ciMethod*        method = NULL;
4566
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
  1144
  bool             is_method_handle_invoke = false;  // for special kill effects
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1145
  if( sfpt->is_Call() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1146
    call = sfpt->as_Call();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1147
    domain = call->tf()->domain();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1148
    cnt = domain->cnt();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1149
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1150
    // Match just the call, nothing else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1151
    MachNode *m = match_tree(call);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1152
    if (C->failing())  return NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1153
    if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1154
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1155
    // Copy data from the Ideal SafePoint to the machine version
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1156
    mcall = m->as_MachCall();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1157
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1158
    mcall->set_tf(         call->tf());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1159
    mcall->set_entry_point(call->entry_point());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1160
    mcall->set_cnt(        call->cnt());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1161
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1162
    if( mcall->is_MachCallJava() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1163
      MachCallJavaNode *mcall_java  = mcall->as_MachCallJava();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1164
      const CallJavaNode *call_java =  call->as_CallJava();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1165
      method = call_java->method();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1166
      mcall_java->_method = method;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1167
      mcall_java->_bci = call_java->_bci;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1168
      mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
4566
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
  1169
      is_method_handle_invoke = call_java->is_method_handle_invoke();
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4431
diff changeset
  1170
      mcall_java->_method_handle_invoke = is_method_handle_invoke;
35086
bbf32241d851 8072008: Emit direct call instead of linkTo* for recursive indy/MH.invoke* calls
vlivanov
parents: 34174
diff changeset
  1171
      mcall_java->_override_symbolic_info = call_java->override_symbolic_info();
10514
e229a19078cf 7071307: MethodHandle bimorphic inlining should consider the frequency
never
parents: 10267
diff changeset
  1172
      if (is_method_handle_invoke) {
e229a19078cf 7071307: MethodHandle bimorphic inlining should consider the frequency
never
parents: 10267
diff changeset
  1173
        C->set_has_method_handle_invokes(true);
e229a19078cf 7071307: MethodHandle bimorphic inlining should consider the frequency
never
parents: 10267
diff changeset
  1174
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1175
      if( mcall_java->is_MachCallStaticJava() )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1176
        mcall_java->as_MachCallStaticJava()->_name =
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1177
         call_java->as_CallStaticJava()->_name;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1178
      if( mcall_java->is_MachCallDynamicJava() )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1179
        mcall_java->as_MachCallDynamicJava()->_vtable_index =
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1180
         call_java->as_CallDynamicJava()->_vtable_index;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1181
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1182
    else if( mcall->is_MachCallRuntime() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1183
      mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1184
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1185
    msfpt = mcall;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1186
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1187
  // This is a non-call safepoint
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1188
  else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1189
    call = NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1190
    domain = NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1191
    MachNode *mn = match_tree(sfpt);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1192
    if (C->failing())  return NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1193
    msfpt = mn->as_MachSafePoint();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1194
    cnt = TypeFunc::Parms;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1195
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1196
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1197
  // Advertise the correct memory effects (for anti-dependence computation).
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1198
  msfpt->set_adr_type(sfpt->adr_type());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1199
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1200
  // Allocate a private array of RegMasks.  These RegMasks are not shared.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1201
  msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1202
  // Empty them all.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1203
  memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1204
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1205
  // Do all the pre-defined non-Empty register masks
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1206
  msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1207
  msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1208
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1209
  // Place first outgoing argument can possibly be put.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1210
  OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1211
  assert( is_even(begin_out_arg_area), "" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1212
  // Compute max outgoing register number per call site.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1213
  OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1214
  // Calls to C may hammer extra stack slots above and beyond any arguments.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1215
  // These are usually backing store for register arguments for varargs.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1216
  if( call != NULL && call->is_CallRuntime() )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1217
    out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1218
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1219
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1220
  // Do the normal argument list (parameters) register masks
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1221
  int argcnt = cnt - TypeFunc::Parms;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1222
  if( argcnt > 0 ) {          // Skip it all if we have no args
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1223
    BasicType *sig_bt  = NEW_RESOURCE_ARRAY( BasicType, argcnt );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1224
    VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1225
    int i;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1226
    for( i = 0; i < argcnt; i++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1227
      sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1228
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1229
    // V-call to pick proper calling convention
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1230
    call->calling_convention( sig_bt, parm_regs, argcnt );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1231
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1232
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1233
    // Sanity check users' calling convention.  Really handy during
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1234
    // the initial porting effort.  Fairly expensive otherwise.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1235
    { for (int i = 0; i<argcnt; i++) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1236
      if( !parm_regs[i].first()->is_valid() &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1237
          !parm_regs[i].second()->is_valid() ) continue;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1238
      VMReg reg1 = parm_regs[i].first();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1239
      VMReg reg2 = parm_regs[i].second();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1240
      for (int j = 0; j < i; j++) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1241
        if( !parm_regs[j].first()->is_valid() &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1242
            !parm_regs[j].second()->is_valid() ) continue;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1243
        VMReg reg3 = parm_regs[j].first();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1244
        VMReg reg4 = parm_regs[j].second();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1245
        if( !reg1->is_valid() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1246
          assert( !reg2->is_valid(), "valid halvsies" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1247
        } else if( !reg3->is_valid() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1248
          assert( !reg4->is_valid(), "valid halvsies" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1249
        } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1250
          assert( reg1 != reg2, "calling conv. must produce distinct regs");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1251
          assert( reg1 != reg3, "calling conv. must produce distinct regs");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1252
          assert( reg1 != reg4, "calling conv. must produce distinct regs");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1253
          assert( reg2 != reg3, "calling conv. must produce distinct regs");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1254
          assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1255
          assert( reg3 != reg4, "calling conv. must produce distinct regs");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1256
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1257
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1258
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1259
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1260
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1261
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1262
    // Visit each argument.  Compute its outgoing register mask.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1263
    // Return results now can have 2 bits returned.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1264
    // Compute max over all outgoing arguments both per call-site
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1265
    // and over the entire method.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1266
    for( i = 0; i < argcnt; i++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1267
      // Address of incoming argument mask to fill in
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1268
      RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1269
      if( !parm_regs[i].first()->is_valid() &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1270
          !parm_regs[i].second()->is_valid() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1271
        continue;               // Avoid Halves
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1272
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1273
      // Grab first register, adjust stack slots and insert in mask.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1274
      OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1275
      if (OptoReg::is_valid(reg1))
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1276
        rm->Insert( reg1 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1277
      // Grab second register (if any), adjust stack slots and insert in mask.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1278
      OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1279
      if (OptoReg::is_valid(reg2))
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1280
        rm->Insert( reg2 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1281
    } // End of for all arguments
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1282
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1283
    // Compute number of stack slots needed to restore stack in case of
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1284
    // Pascal-style argument popping.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1285
    mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1286
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1287
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1288
  // Compute the max stack slot killed by any call.  These will not be
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1289
  // available for debug info, and will be used to adjust FIRST_STACK_mask
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1290
  // after all call sites have been visited.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1291
  if( _out_arg_limit < out_arg_limit_per_call)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1292
    _out_arg_limit = out_arg_limit_per_call;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1293
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1294
  if (mcall) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1295
    // Kill the outgoing argument area, including any non-argument holes and
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1296
    // any legacy C-killed slots.  Use Fat-Projections to do the killing.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1297
    // Since the max-per-method covers the max-per-call-site and debug info
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1298
    // is excluded on the max-per-method basis, debug info cannot land in
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1299
    // this killed area.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1300
    uint r_cnt = mcall->tf()->range()->cnt();
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24424
diff changeset
  1301
    MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11429
diff changeset
  1302
    if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
39431
cb1b2538c4b2 8159720: Failure of C2 compilation with tiered prevents some C1 compilations.
cvarming
parents: 39419
diff changeset
  1303
      C->record_method_not_compilable("unsupported outgoing calling sequence");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1304
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1305
      for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1306
        proj->_rout.Insert(OptoReg::Name(i));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1307
    }
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 18956
diff changeset
  1308
    if (proj->_rout.is_NotEmpty()) {
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 18956
diff changeset
  1309
      push_projection(proj);
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 18956
diff changeset
  1310
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1311
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1312
  // Transfer the safepoint information from the call to the mcall
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1313
  // Move the JVMState list
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1314
  msfpt->set_jvms(sfpt->jvms());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1315
  for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1316
    jvms->set_map(sfpt);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1317
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1318
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1319
  // Debug inputs begin just after the last incoming parameter
22865
3b8857d7b3cc 8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents: 22856
diff changeset
  1320
  assert((mcall == NULL) || (mcall->jvms() == NULL) ||
3b8857d7b3cc 8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents: 22856
diff changeset
  1321
         (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1322
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1323
  // Move the OopMap
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1324
  msfpt->_oop_map = sfpt->_oop_map;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1325
22865
3b8857d7b3cc 8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents: 22856
diff changeset
  1326
  // Add additional edges.
3b8857d7b3cc 8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents: 22856
diff changeset
  1327
  if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) {
3b8857d7b3cc 8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents: 22856
diff changeset
  1328
    // For these calls we can not add MachConstantBase in expand(), as the
3b8857d7b3cc 8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents: 22856
diff changeset
  1329
    // ins are not complete then.
3b8857d7b3cc 8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents: 22856
diff changeset
  1330
    msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
3b8857d7b3cc 8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents: 22856
diff changeset
  1331
    if (msfpt->jvms() &&
3b8857d7b3cc 8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents: 22856
diff changeset
  1332
        msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
3b8857d7b3cc 8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents: 22856
diff changeset
  1333
      // We added an edge before jvms, so we must adapt the position of the ins.
3b8857d7b3cc 8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents: 22856
diff changeset
  1334
      msfpt->jvms()->adapt_position(+1);
3b8857d7b3cc 8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents: 22856
diff changeset
  1335
    }
3b8857d7b3cc 8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents: 22856
diff changeset
  1336
  }
3b8857d7b3cc 8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
goetz
parents: 22856
diff changeset
  1337
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1338
  // Registers killed by the call are set in the local scheduling pass
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1339
  // of Global Code Motion.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1340
  return msfpt;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1341
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1342
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1343
//---------------------------match_tree----------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1344
// Match a Ideal Node DAG - turn it into a tree; Label & Reduce.  Used as part
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1345
// of the whole-sale conversion from Ideal to Mach Nodes.  Also used for
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1346
// making GotoNodes while building the CFG and in init_spill_mask() to identify
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1347
// a Load's result RegMask for memoization in idealreg2regmask[]
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1348
MachNode *Matcher::match_tree( const Node *n ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1349
  assert( n->Opcode() != Op_Phi, "cannot match" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1350
  assert( !n->is_block_start(), "cannot match" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1351
  // Set the mark for all locally allocated State objects.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1352
  // When this call returns, the _states_arena arena will be reset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1353
  // freeing all State objects.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1354
  ResourceMark rm( &_states_arena );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1355
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1356
  LabelRootDepth = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1357
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1358
  // StoreNodes require their Memory input to match any LoadNodes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1359
  Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
762
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1360
#ifdef ASSERT
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1361
  Node* save_mem_node = _mem_node;
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1362
  _mem_node = n->is_Store() ? (Node*)n : NULL;
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1363
#endif
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1364
  // State object for root node of match tree
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1365
  // Allocate it on _states_arena - stack allocation can cause stack overflow.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1366
  State *s = new (&_states_arena) State;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1367
  s->_kids[0] = NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1368
  s->_kids[1] = NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1369
  s->_leaf = (Node*)n;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1370
  // Label the input tree, allocating labels from top-level arena
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1371
  Label_Root( n, s, n->in(0), mem );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1372
  if (C->failing())  return NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1373
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1374
  // The minimum cost match for the whole tree is found at the root State
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1375
  uint mincost = max_juint;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1376
  uint cost = max_juint;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1377
  uint i;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1378
  for( i = 0; i < NUM_OPERANDS; i++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1379
    if( s->valid(i) &&                // valid entry and
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1380
        s->_cost[i] < cost &&         // low cost and
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1381
        s->_rule[i] >= NUM_OPERANDS ) // not an operand
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1382
      cost = s->_cost[mincost=i];
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1383
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1384
  if (mincost == max_juint) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1385
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1386
    tty->print("No matching rule for:");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1387
    s->dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1388
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1389
    Matcher::soft_match_failure();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1390
    return NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1391
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1392
  // Reduce input tree based upon the state labels to machine Nodes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1393
  MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1394
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1395
  _old2new_map.map(n->_idx, m);
768
d0bebc7eefc2 6718676: putback for 6604014 is incomplete
never
parents: 767
diff changeset
  1396
  _new2old_map.map(m->_idx, (Node*)n);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1397
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1398
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1399
  // Add any Matcher-ignored edges
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1400
  uint cnt = n->req();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1401
  uint start = 1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1402
  if( mem != (Node*)1 ) start = MemNode::Memory+1;
594
9f4474e5dbaf 6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents: 590
diff changeset
  1403
  if( n->is_AddP() ) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1404
    assert( mem == (Node*)1, "" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1405
    start = AddPNode::Base+1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1406
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1407
  for( i = start; i < cnt; i++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1408
    if( !n->match_edge(i) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1409
      if( i < m->req() )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1410
        m->ins_req( i, n->in(i) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1411
      else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1412
        m->add_req( n->in(i) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1413
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1414
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1415
762
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1416
  debug_only( _mem_node = save_mem_node; )
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1417
  return m;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1418
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1419
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1420
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1421
//------------------------------match_into_reg---------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1422
// Choose to either match this Node in a register or part of the current
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1423
// match tree.  Return true for requiring a register and false for matching
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1424
// as part of the current match tree.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1425
static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1426
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1427
  const Type *t = m->bottom_type();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1428
11429
e894217a5d94 7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents: 10988
diff changeset
  1429
  if (t->singleton()) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1430
    // Never force constants into registers.  Allow them to match as
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1431
    // constants or registers.  Copies of the same value will share
594
9f4474e5dbaf 6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents: 590
diff changeset
  1432
    // the same register.  See find_shared_node.
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1433
    return false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1434
  } else {                      // Not a constant
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1435
    // Stop recursion if they have different Controls.
11429
e894217a5d94 7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents: 10988
diff changeset
  1436
    Node* m_control = m->in(0);
e894217a5d94 7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents: 10988
diff changeset
  1437
    // Control of load's memory can post-dominates load's control.
e894217a5d94 7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents: 10988
diff changeset
  1438
    // So use it since load can't float above its memory.
e894217a5d94 7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents: 10988
diff changeset
  1439
    Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL;
e894217a5d94 7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents: 10988
diff changeset
  1440
    if (control && m_control && control != m_control && control != mem_control) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1441
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1442
      // Actually, we can live with the most conservative control we
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1443
      // find, if it post-dominates the others.  This allows us to
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1444
      // pick up load/op/store trees where the load can float a little
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1445
      // above the store.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1446
      Node *x = control;
11429
e894217a5d94 7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents: 10988
diff changeset
  1447
      const uint max_scan = 6;  // Arbitrary scan cutoff
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1448
      uint j;
11429
e894217a5d94 7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents: 10988
diff changeset
  1449
      for (j=0; j<max_scan; j++) {
e894217a5d94 7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents: 10988
diff changeset
  1450
        if (x->is_Region())     // Bail out at merge points
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1451
          return true;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1452
        x = x->in(0);
11429
e894217a5d94 7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents: 10988
diff changeset
  1453
        if (x == m_control)     // Does 'control' post-dominate
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1454
          break;                // m->in(0)?  If so, we can use it
11429
e894217a5d94 7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents: 10988
diff changeset
  1455
        if (x == mem_control)   // Does 'control' post-dominate
e894217a5d94 7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents: 10988
diff changeset
  1456
          break;                // mem_control?  If so, we can use it
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1457
      }
11429
e894217a5d94 7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents: 10988
diff changeset
  1458
      if (j == max_scan)        // No post-domination before scan end?
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1459
        return true;            // Then break the match tree up
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1460
    }
13969
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13895
diff changeset
  1461
    if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13895
diff changeset
  1462
        (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
  1463
      // These are commonly used in address expressions and can
594
9f4474e5dbaf 6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents: 590
diff changeset
  1464
      // efficiently fold into them on X64 in some cases.
9f4474e5dbaf 6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents: 590
diff changeset
  1465
      return false;
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
  1466
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1467
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1468
2131
98f9cef66a34 6810672: Comment typos
twisti
parents: 2112
diff changeset
  1469
  // Not forceable cloning.  If shared, put it into a register.
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1470
  return shared;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1471
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1472
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1473
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1474
//------------------------------Instruction Selection--------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1475
// Label method walks a "tree" of nodes, using the ADLC generated DFA to match
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1476
// ideal nodes to machine instructions.  Trees are delimited by shared Nodes,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1477
// things the Matcher does not match (e.g., Memory), and things with different
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1478
// Controls (hence forced into different blocks).  We pass in the Control
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1479
// selected for this entire State tree.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1480
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1481
// The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1482
// Store and the Load must have identical Memories (as well as identical
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1483
// pointers).  Since the Matcher does not have anything for Memory (and
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1484
// does not handle DAGs), I have to match the Memory input myself.  If the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1485
// Tree root is a Store, I require all Loads to have the identical memory.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1486
Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1487
  // Since Label_Root is a recursive function, its possible that we might run
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1488
  // out of stack space.  See bugs 6272980 & 6227033 for more info.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1489
  LabelRootDepth++;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1490
  if (LabelRootDepth > MaxLabelRootDepth) {
39431
cb1b2538c4b2 8159720: Failure of C2 compilation with tiered prevents some C1 compilations.
cvarming
parents: 39419
diff changeset
  1491
    C->record_method_not_compilable("Out of stack space, increase MaxLabelRootDepth");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1492
    return NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1493
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1494
  uint care = 0;                // Edges matcher cares about
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1495
  uint cnt = n->req();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1496
  uint i = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1497
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1498
  // Examine children for memory state
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1499
  // Can only subsume a child into your match-tree if that child's memory state
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1500
  // is not modified along the path to another input.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1501
  // It is unsafe even if the other inputs are separate roots.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1502
  Node *input_mem = NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1503
  for( i = 1; i < cnt; i++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1504
    if( !n->match_edge(i) ) continue;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1505
    Node *m = n->in(i);         // Get ith input
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1506
    assert( m, "expect non-null children" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1507
    if( m->is_Load() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1508
      if( input_mem == NULL ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1509
        input_mem = m->in(MemNode::Memory);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1510
      } else if( input_mem != m->in(MemNode::Memory) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1511
        input_mem = NodeSentinel;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1512
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1513
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1514
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1515
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1516
  for( i = 1; i < cnt; i++ ){// For my children
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1517
    if( !n->match_edge(i) ) continue;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1518
    Node *m = n->in(i);         // Get ith input
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1519
    // Allocate states out of a private arena
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1520
    State *s = new (&_states_arena) State;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1521
    svec->_kids[care++] = s;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1522
    assert( care <= 2, "binary only for now" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1523
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1524
    // Recursively label the State tree.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1525
    s->_kids[0] = NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1526
    s->_kids[1] = NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1527
    s->_leaf = m;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1528
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1529
    // Check for leaves of the State Tree; things that cannot be a part of
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1530
    // the current tree.  If it finds any, that value is matched as a
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1531
    // register operand.  If not, then the normal matching is used.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1532
    if( match_into_reg(n, m, control, i, is_shared(m)) ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1533
        //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1534
        // Stop recursion if this is LoadNode and the root of this tree is a
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1535
        // StoreNode and the load & store have different memories.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1536
        ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1537
        // Can NOT include the match of a subtree when its memory state
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1538
        // is used by any of the other subtrees
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1539
        (input_mem == NodeSentinel) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1540
      // Print when we exclude matching due to different memory states at input-loads
34174
4db2fb26dc49 8140424: don't prefix developer and notproduct flag variables with CONST_ in product builds
twisti
parents: 33628
diff changeset
  1541
      if (PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
4db2fb26dc49 8140424: don't prefix developer and notproduct flag variables with CONST_ in product builds
twisti
parents: 33628
diff changeset
  1542
        && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem)) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1543
        tty->print_cr("invalid input_mem");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1544
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1545
      // Switch to a register-only opcode; this value must be in a register
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1546
      // and cannot be subsumed as part of a larger instruction.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1547
      s->DFA( m->ideal_reg(), m );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1548
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1549
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1550
      // If match tree has no control and we do, adopt it for entire tree
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1551
      if( control == NULL && m->in(0) != NULL && m->req() > 1 )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1552
        control = m->in(0);         // Pick up control
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1553
      // Else match as a normal part of the match tree.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1554
      control = Label_Root(m,s,control,mem);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1555
      if (C->failing()) return NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1556
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1557
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1558
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1559
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1560
  // Call DFA to match this node, and return
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1561
  svec->DFA( n->Opcode(), n );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1562
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1563
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1564
  uint x;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1565
  for( x = 0; x < _LAST_MACH_OPER; x++ )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1566
    if( svec->valid(x) )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1567
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1568
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1569
  if (x >= _LAST_MACH_OPER) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1570
    n->dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1571
    svec->dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1572
    assert( false, "bad AD file" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1573
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1574
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1575
  return control;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1576
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1577
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1578
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1579
// Con nodes reduced using the same rule can share their MachNode
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1580
// which reduces the number of copies of a constant in the final
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1581
// program.  The register allocator is free to split uses later to
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1582
// split live ranges.
594
9f4474e5dbaf 6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents: 590
diff changeset
  1583
MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
13969
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13895
diff changeset
  1584
  if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1585
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1586
  // See if this Con has already been reduced using this rule.
594
9f4474e5dbaf 6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents: 590
diff changeset
  1587
  if (_shared_nodes.Size() <= leaf->_idx) return NULL;
9f4474e5dbaf 6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents: 590
diff changeset
  1588
  MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1589
  if (last != NULL && rule == last->rule()) {
594
9f4474e5dbaf 6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents: 590
diff changeset
  1590
    // Don't expect control change for DecodeN
13969
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13895
diff changeset
  1591
    if (leaf->is_DecodeNarrowPtr())
594
9f4474e5dbaf 6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents: 590
diff changeset
  1592
      return last;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1593
    // Get the new space root.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1594
    Node* xroot = new_node(C->root());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1595
    if (xroot == NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1596
      // This shouldn't happen give the order of matching.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1597
      return NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1598
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1599
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1600
    // Shared constants need to have their control be root so they
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1601
    // can be scheduled properly.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1602
    Node* control = last->in(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1603
    if (control != xroot) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1604
      if (control == NULL || control == C->root()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1605
        last->set_req(0, xroot);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1606
      } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1607
        assert(false, "unexpected control");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1608
        return NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1609
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1610
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1611
    return last;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1612
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1613
  return NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1614
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1615
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1616
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1617
//------------------------------ReduceInst-------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1618
// Reduce a State tree (with given Control) into a tree of MachNodes.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1619
// This routine (and it's cohort ReduceOper) convert Ideal Nodes into
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1620
// complicated machine Nodes.  Each MachNode covers some tree of Ideal Nodes.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1621
// Each MachNode has a number of complicated MachOper operands; each
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1622
// MachOper also covers a further tree of Ideal Nodes.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1623
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1624
// The root of the Ideal match tree is always an instruction, so we enter
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1625
// the recursion here.  After building the MachNode, we need to recurse
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1626
// the tree checking for these cases:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1627
// (1) Child is an instruction -
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1628
//     Build the instruction (recursively), add it as an edge.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1629
//     Build a simple operand (register) to hold the result of the instruction.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1630
// (2) Child is an interior part of an instruction -
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1631
//     Skip over it (do nothing)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1632
// (3) Child is the start of a operand -
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1633
//     Build the operand, place it inside the instruction
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1634
//     Call ReduceOper.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1635
MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1636
  assert( rule >= NUM_OPERANDS, "called with operand rule" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1637
594
9f4474e5dbaf 6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents: 590
diff changeset
  1638
  MachNode* shared_node = find_shared_node(s->_leaf, rule);
9f4474e5dbaf 6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents: 590
diff changeset
  1639
  if (shared_node != NULL) {
9f4474e5dbaf 6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents: 590
diff changeset
  1640
    return shared_node;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1641
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1642
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1643
  // Build the object to represent this state & prepare for recursive calls
25930
eae8b7490d2c 8054033: Remove unused references to Compile*
thartmann
parents: 25715
diff changeset
  1644
  MachNode *mach = s->MachNodeGenerator(rule);
eae8b7490d2c 8054033: Remove unused references to Compile*
thartmann
parents: 25715
diff changeset
  1645
  mach->_opnds[0] = s->MachOperGenerator(_reduceOp[rule]);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1646
  assert( mach->_opnds[0] != NULL, "Missing result operand" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1647
  Node *leaf = s->_leaf;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1648
  // Check for instruction or instruction chain rule
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1649
  if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1071
f331132bffdc 6732698: crash with dead code from compressed oops in gcm
never
parents: 781
diff changeset
  1650
    assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
f331132bffdc 6732698: crash with dead code from compressed oops in gcm
never
parents: 781
diff changeset
  1651
           "duplicating node that's already been matched");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1652
    // Instruction
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1653
    mach->add_req( leaf->in(0) ); // Set initial control
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1654
    // Reduce interior of complex instruction
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1655
    ReduceInst_Interior( s, rule, mem, mach, 1 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1656
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1657
    // Instruction chain rules are data-dependent on their inputs
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1658
    mach->add_req(0);             // Set initial control to none
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1659
    ReduceInst_Chain_Rule( s, rule, mem, mach );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1660
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1661
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1662
  // If a Memory was used, insert a Memory edge
762
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1663
  if( mem != (Node*)1 ) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1664
    mach->ins_req(MemNode::Memory,mem);
762
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1665
#ifdef ASSERT
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1666
    // Verify adr type after matching memory operation
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1667
    const MachOper* oper = mach->memory_operand();
3268
f034e0c86895 6851742: (EA) allocation elimination doesn't work with UseG1GC
kvn
parents: 3176
diff changeset
  1668
    if (oper != NULL && oper != (MachOper*)-1) {
762
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1669
      // It has a unique memory operand.  Find corresponding ideal mem node.
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1670
      Node* m = NULL;
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1671
      if (leaf->is_Mem()) {
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1672
        m = leaf;
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1673
      } else {
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1674
        m = _mem_node;
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1675
        assert(m != NULL && m->is_Mem(), "expecting memory node");
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1676
      }
1400
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  1677
      const Type* mach_at = mach->adr_type();
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  1678
      // DecodeN node consumed by an address may have different type
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  1679
      // then its input. Don't compare types for such case.
2254
f13dda645a4b 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 2131
diff changeset
  1680
      if (m->adr_type() != mach_at &&
13969
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13895
diff changeset
  1681
          (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
2254
f13dda645a4b 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 2131
diff changeset
  1682
           m->in(MemNode::Address)->is_AddP() &&
13969
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13895
diff changeset
  1683
           m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr() ||
2254
f13dda645a4b 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 2131
diff changeset
  1684
           m->in(MemNode::Address)->is_AddP() &&
f13dda645a4b 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 2131
diff changeset
  1685
           m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
13969
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13895
diff changeset
  1686
           m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr())) {
1400
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  1687
        mach_at = m->adr_type();
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  1688
      }
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  1689
      if (m->adr_type() != mach_at) {
762
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1690
        m->dump();
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1691
        tty->print_cr("mach:");
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1692
        mach->dump(1);
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1693
      }
1400
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  1694
      assert(m->adr_type() == mach_at, "matcher should not change adr type");
762
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1695
    }
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1696
#endif
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1697
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1698
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1699
  // If the _leaf is an AddP, insert the base edge
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 18956
diff changeset
  1700
  if (leaf->is_AddP()) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1701
    mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 18956
diff changeset
  1702
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1703
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 18956
diff changeset
  1704
  uint number_of_projections_prior = number_of_projections();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1705
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1706
  // Perform any 1-to-many expansions required
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 18956
diff changeset
  1707
  MachNode *ex = mach->Expand(s, _projection_list, mem);
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 18956
diff changeset
  1708
  if (ex != mach) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1709
    assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1710
    if( ex->in(1)->is_Con() )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1711
      ex->in(1)->set_req(0, C->root());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1712
    // Remove old node from the graph
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1713
    for( uint i=0; i<mach->req(); i++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1714
      mach->set_req(i,NULL);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1715
    }
768
d0bebc7eefc2 6718676: putback for 6604014 is incomplete
never
parents: 767
diff changeset
  1716
#ifdef ASSERT
d0bebc7eefc2 6718676: putback for 6604014 is incomplete
never
parents: 767
diff changeset
  1717
    _new2old_map.map(ex->_idx, s->_leaf);
d0bebc7eefc2 6718676: putback for 6604014 is incomplete
never
parents: 767
diff changeset
  1718
#endif
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1719
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1720
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1721
  // PhaseChaitin::fixup_spills will sometimes generate spill code
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1722
  // via the matcher.  By the time, nodes have been wired into the CFG,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1723
  // and any further nodes generated by expand rules will be left hanging
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1724
  // in space, and will not get emitted as output code.  Catch this.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1725
  // Also, catch any new register allocation constraints ("projections")
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1726
  // generated belatedly during spill code generation.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1727
  if (_allocation_started) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1728
    guarantee(ex == mach, "no expand rules during spill generation");
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 18956
diff changeset
  1729
    guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1730
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1731
13969
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13895
diff changeset
  1732
  if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1733
    // Record the con for sharing
594
9f4474e5dbaf 6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents: 590
diff changeset
  1734
    _shared_nodes.map(leaf->_idx, ex);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1735
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1736
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1737
  return ex;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1738
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1739
30300
4b12a5b40064 8069191: moving predicate out of loops may cause array accesses to bypass null check
roland
parents: 29083
diff changeset
  1740
void Matcher::handle_precedence_edges(Node* n, MachNode *mach) {
4b12a5b40064 8069191: moving predicate out of loops may cause array accesses to bypass null check
roland
parents: 29083
diff changeset
  1741
  for (uint i = n->req(); i < n->len(); i++) {
4b12a5b40064 8069191: moving predicate out of loops may cause array accesses to bypass null check
roland
parents: 29083
diff changeset
  1742
    if (n->in(i) != NULL) {
4b12a5b40064 8069191: moving predicate out of loops may cause array accesses to bypass null check
roland
parents: 29083
diff changeset
  1743
      mach->add_prec(n->in(i));
4b12a5b40064 8069191: moving predicate out of loops may cause array accesses to bypass null check
roland
parents: 29083
diff changeset
  1744
    }
4b12a5b40064 8069191: moving predicate out of loops may cause array accesses to bypass null check
roland
parents: 29083
diff changeset
  1745
  }
4b12a5b40064 8069191: moving predicate out of loops may cause array accesses to bypass null check
roland
parents: 29083
diff changeset
  1746
}
4b12a5b40064 8069191: moving predicate out of loops may cause array accesses to bypass null check
roland
parents: 29083
diff changeset
  1747
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1748
void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1749
  // 'op' is what I am expecting to receive
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1750
  int op = _leftOp[rule];
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1751
  // Operand type to catch childs result
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1752
  // This is what my child will give me.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1753
  int opnd_class_instance = s->_rule[op];
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1754
  // Choose between operand class or not.
2131
98f9cef66a34 6810672: Comment typos
twisti
parents: 2112
diff changeset
  1755
  // This is what I will receive.
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1756
  int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1757
  // New rule for child.  Chase operand classes to get the actual rule.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1758
  int newrule = s->_rule[catch_op];
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1759
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1760
  if( newrule < NUM_OPERANDS ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1761
    // Chain from operand or operand class, may be output of shared node
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1762
    assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1763
            "Bad AD file: Instruction chain rule must chain from operand");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1764
    // Insert operand into array of operands for this instruction
25930
eae8b7490d2c 8054033: Remove unused references to Compile*
thartmann
parents: 25715
diff changeset
  1765
    mach->_opnds[1] = s->MachOperGenerator(opnd_class_instance);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1766
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1767
    ReduceOper( s, newrule, mem, mach );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1768
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1769
    // Chain from the result of an instruction
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1770
    assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
25930
eae8b7490d2c 8054033: Remove unused references to Compile*
thartmann
parents: 25715
diff changeset
  1771
    mach->_opnds[1] = s->MachOperGenerator(_reduceOp[catch_op]);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1772
    Node *mem1 = (Node*)1;
762
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1773
    debug_only(Node *save_mem_node = _mem_node;)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1774
    mach->add_req( ReduceInst(s, newrule, mem1) );
762
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1775
    debug_only(_mem_node = save_mem_node;)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1776
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1777
  return;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1778
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1779
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1780
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1781
uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
30300
4b12a5b40064 8069191: moving predicate out of loops may cause array accesses to bypass null check
roland
parents: 29083
diff changeset
  1782
  handle_precedence_edges(s->_leaf, mach);
4b12a5b40064 8069191: moving predicate out of loops may cause array accesses to bypass null check
roland
parents: 29083
diff changeset
  1783
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1784
  if( s->_leaf->is_Load() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1785
    Node *mem2 = s->_leaf->in(MemNode::Memory);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1786
    assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
762
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1787
    debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1788
    mem = mem2;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1789
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1790
  if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1791
    if( mach->in(0) == NULL )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1792
      mach->set_req(0, s->_leaf->in(0));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1793
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1794
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1795
  // Now recursively walk the state tree & add operand list.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1796
  for( uint i=0; i<2; i++ ) {   // binary tree
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1797
    State *newstate = s->_kids[i];
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1798
    if( newstate == NULL ) break;      // Might only have 1 child
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1799
    // 'op' is what I am expecting to receive
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1800
    int op;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1801
    if( i == 0 ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1802
      op = _leftOp[rule];
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1803
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1804
      op = _rightOp[rule];
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1805
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1806
    // Operand type to catch childs result
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1807
    // This is what my child will give me.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1808
    int opnd_class_instance = newstate->_rule[op];
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1809
    // Choose between operand class or not.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1810
    // This is what I will receive.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1811
    int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1812
    // New rule for child.  Chase operand classes to get the actual rule.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1813
    int newrule = newstate->_rule[catch_op];
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1814
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1815
    if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1816
      // Operand/operandClass
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1817
      // Insert operand into array of operands for this instruction
25930
eae8b7490d2c 8054033: Remove unused references to Compile*
thartmann
parents: 25715
diff changeset
  1818
      mach->_opnds[num_opnds++] = newstate->MachOperGenerator(opnd_class_instance);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1819
      ReduceOper( newstate, newrule, mem, mach );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1820
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1821
    } else {                    // Child is internal operand or new instruction
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1822
      if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1823
        // internal operand --> call ReduceInst_Interior
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1824
        // Interior of complex instruction.  Do nothing but recurse.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1825
        num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1826
      } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1827
        // instruction --> call build operand(  ) to catch result
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1828
        //             --> ReduceInst( newrule )
25930
eae8b7490d2c 8054033: Remove unused references to Compile*
thartmann
parents: 25715
diff changeset
  1829
        mach->_opnds[num_opnds++] = s->MachOperGenerator(_reduceOp[catch_op]);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1830
        Node *mem1 = (Node*)1;
762
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1831
        debug_only(Node *save_mem_node = _mem_node;)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1832
        mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
762
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1833
        debug_only(_mem_node = save_mem_node;)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1834
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1835
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1836
    assert( mach->_opnds[num_opnds-1], "" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1837
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1838
  return num_opnds;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1839
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1840
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1841
// This routine walks the interior of possible complex operands.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1842
// At each point we check our children in the match tree:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1843
// (1) No children -
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1844
//     We are a leaf; add _leaf field as an input to the MachNode
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1845
// (2) Child is an internal operand -
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1846
//     Skip over it ( do nothing )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1847
// (3) Child is an instruction -
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1848
//     Call ReduceInst recursively and
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1849
//     and instruction as an input to the MachNode
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1850
void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1851
  assert( rule < _LAST_MACH_OPER, "called with operand rule" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1852
  State *kid = s->_kids[0];
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1853
  assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1854
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1855
  // Leaf?  And not subsumed?
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1856
  if( kid == NULL && !_swallowed[rule] ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1857
    mach->add_req( s->_leaf );  // Add leaf pointer
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1858
    return;                     // Bail out
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1859
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1860
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1861
  if( s->_leaf->is_Load() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1862
    assert( mem == (Node*)1, "multiple Memories being matched at once?" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1863
    mem = s->_leaf->in(MemNode::Memory);
762
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1864
    debug_only(_mem_node = s->_leaf;)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1865
  }
30300
4b12a5b40064 8069191: moving predicate out of loops may cause array accesses to bypass null check
roland
parents: 29083
diff changeset
  1866
4b12a5b40064 8069191: moving predicate out of loops may cause array accesses to bypass null check
roland
parents: 29083
diff changeset
  1867
  handle_precedence_edges(s->_leaf, mach);
4b12a5b40064 8069191: moving predicate out of loops may cause array accesses to bypass null check
roland
parents: 29083
diff changeset
  1868
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1869
  if( s->_leaf->in(0) && s->_leaf->req() > 1) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1870
    if( !mach->in(0) )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1871
      mach->set_req(0,s->_leaf->in(0));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1872
    else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1873
      assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1874
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1875
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1876
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1877
  for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) {   // binary tree
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1878
    int newrule;
18025
b7bcf7497f93 8005849: JEP 167: Event-Based JVM Tracing
sla
parents: 17875
diff changeset
  1879
    if( i == 0)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1880
      newrule = kid->_rule[_leftOp[rule]];
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1881
    else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1882
      newrule = kid->_rule[_rightOp[rule]];
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1883
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1884
    if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1885
      // Internal operand; recurse but do nothing else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1886
      ReduceOper( kid, newrule, mem, mach );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1887
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1888
    } else {                    // Child is a new instruction
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1889
      // Reduce the instruction, and add a direct pointer from this
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1890
      // machine instruction to the newly reduced one.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1891
      Node *mem1 = (Node*)1;
762
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1892
      debug_only(Node *save_mem_node = _mem_node;)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1893
      mach->add_req( ReduceInst( kid, newrule, mem1 ) );
762
1b26adb5fea1 6715633: when matching a memory node the adr_type should not change
kvn
parents: 595
diff changeset
  1894
      debug_only(_mem_node = save_mem_node;)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1895
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1896
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1897
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1898
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1899
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1900
// -------------------------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1901
// Java-Java calling convention
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1902
// (what you use when Java calls Java)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1903
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1904
//------------------------------find_receiver----------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1905
// For a given signature, return the OptoReg for parameter 0.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1906
OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1907
  VMRegPair regs;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1908
  BasicType sig_bt = T_OBJECT;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1909
  calling_convention(&sig_bt, &regs, 1, is_outgoing);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1910
  // Return argument 0 register.  In the LP64 build pointers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1911
  // take 2 registers, but the VM wants only the 'main' name.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1912
  return OptoReg::as_OptoReg(regs.first());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1913
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1914
23220
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1915
// This function identifies sub-graphs in which a 'load' node is
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1916
// input to two different nodes, and such that it can be matched
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1917
// with BMI instructions like blsi, blsr, etc.
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1918
// Example : for b = -a[i] & a[i] can be matched to blsi r32, m32.
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1919
// The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL*
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1920
// refers to the same node.
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1921
#ifdef X86
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1922
// Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop)
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1923
// This is a temporary solution until we make DAGs expressible in ADL.
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1924
template<typename ConType>
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1925
class FusedPatternMatcher {
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1926
  Node* _op1_node;
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1927
  Node* _mop_node;
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1928
  int _con_op;
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1929
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1930
  static int match_next(Node* n, int next_op, int next_op_idx) {
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1931
    if (n->in(1) == NULL || n->in(2) == NULL) {
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1932
      return -1;
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1933
    }
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1934
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1935
    if (next_op_idx == -1) { // n is commutative, try rotations
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1936
      if (n->in(1)->Opcode() == next_op) {
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1937
        return 1;
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1938
      } else if (n->in(2)->Opcode() == next_op) {
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1939
        return 2;
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1940
      }
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1941
    } else {
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1942
      assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index");
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1943
      if (n->in(next_op_idx)->Opcode() == next_op) {
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1944
        return next_op_idx;
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1945
      }
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1946
    }
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1947
    return -1;
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1948
  }
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1949
public:
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1950
  FusedPatternMatcher(Node* op1_node, Node *mop_node, int con_op) :
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1951
    _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { }
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1952
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1953
  bool match(int op1, int op1_op2_idx,  // op1 and the index of the op1->op2 edge, -1 if op1 is commutative
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1954
             int op2, int op2_con_idx,  // op2 and the index of the op2->con edge, -1 if op2 is commutative
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1955
             typename ConType::NativeType con_value) {
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1956
    if (_op1_node->Opcode() != op1) {
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1957
      return false;
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1958
    }
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1959
    if (_mop_node->outcnt() > 2) {
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1960
      return false;
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1961
    }
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1962
    op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx);
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1963
    if (op1_op2_idx == -1) {
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1964
      return false;
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1965
    }
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1966
    // Memory operation must be the other edge
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1967
    int op1_mop_idx = (op1_op2_idx & 1) + 1;
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1968
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1969
    // Check that the mop node is really what we want
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1970
    if (_op1_node->in(op1_mop_idx) == _mop_node) {
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1971
      Node *op2_node = _op1_node->in(op1_op2_idx);
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1972
      if (op2_node->outcnt() > 1) {
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1973
        return false;
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1974
      }
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1975
      assert(op2_node->Opcode() == op2, "Should be");
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1976
      op2_con_idx = match_next(op2_node, _con_op, op2_con_idx);
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1977
      if (op2_con_idx == -1) {
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1978
        return false;
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1979
      }
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1980
      // Memory operation must be the other edge
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1981
      int op2_mop_idx = (op2_con_idx & 1) + 1;
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1982
      // Check that the memory operation is the same node
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1983
      if (op2_node->in(op2_mop_idx) == _mop_node) {
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1984
        // Now check the constant
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1985
        const Type* con_type = op2_node->in(op2_con_idx)->bottom_type();
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1986
        if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) {
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1987
          return true;
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1988
        }
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1989
      }
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1990
    }
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1991
    return false;
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1992
  }
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1993
};
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1994
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1995
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1996
bool Matcher::is_bmi_pattern(Node *n, Node *m) {
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1997
  if (n != NULL && m != NULL) {
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1998
    if (m->Opcode() == Op_LoadI) {
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  1999
      FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI);
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  2000
      return bmii.match(Op_AndI, -1, Op_SubI,  1,  0)  ||
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  2001
             bmii.match(Op_AndI, -1, Op_AddI, -1, -1)  ||
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  2002
             bmii.match(Op_XorI, -1, Op_AddI, -1, -1);
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  2003
    } else if (m->Opcode() == Op_LoadL) {
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  2004
      FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL);
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  2005
      return bmil.match(Op_AndL, -1, Op_SubL,  1,  0) ||
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  2006
             bmil.match(Op_AndL, -1, Op_AddL, -1, -1) ||
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  2007
             bmil.match(Op_XorL, -1, Op_AddL, -1, -1);
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  2008
    }
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  2009
  }
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  2010
  return false;
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  2011
}
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  2012
#endif // X86
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  2013
38286
0ddb6f84e138 8154826: AArch64: take advantage better of base + shifted offset addressing mode
roland
parents: 38033
diff changeset
  2014
bool Matcher::clone_base_plus_offset_address(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
0ddb6f84e138 8154826: AArch64: take advantage better of base + shifted offset addressing mode
roland
parents: 38033
diff changeset
  2015
  Node *off = m->in(AddPNode::Offset);
0ddb6f84e138 8154826: AArch64: take advantage better of base + shifted offset addressing mode
roland
parents: 38033
diff changeset
  2016
  if (off->is_Con()) {
0ddb6f84e138 8154826: AArch64: take advantage better of base + shifted offset addressing mode
roland
parents: 38033
diff changeset
  2017
    address_visited.test_set(m->_idx); // Flag as address_visited
0ddb6f84e138 8154826: AArch64: take advantage better of base + shifted offset addressing mode
roland
parents: 38033
diff changeset
  2018
    mstack.push(m->in(AddPNode::Address), Pre_Visit);
0ddb6f84e138 8154826: AArch64: take advantage better of base + shifted offset addressing mode
roland
parents: 38033
diff changeset
  2019
    // Clone X+offset as it also folds into most addressing expressions
0ddb6f84e138 8154826: AArch64: take advantage better of base + shifted offset addressing mode
roland
parents: 38033
diff changeset
  2020
    mstack.push(off, Visit);
0ddb6f84e138 8154826: AArch64: take advantage better of base + shifted offset addressing mode
roland
parents: 38033
diff changeset
  2021
    mstack.push(m->in(AddPNode::Base), Pre_Visit);
33082
c3e302e8e429 8136820: Generate better code for some Unsafe addressing patterns
roland
parents: 32202
diff changeset
  2022
    return true;
c3e302e8e429 8136820: Generate better code for some Unsafe addressing patterns
roland
parents: 32202
diff changeset
  2023
  }
c3e302e8e429 8136820: Generate better code for some Unsafe addressing patterns
roland
parents: 32202
diff changeset
  2024
  return false;
c3e302e8e429 8136820: Generate better code for some Unsafe addressing patterns
roland
parents: 32202
diff changeset
  2025
}
c3e302e8e429 8136820: Generate better code for some Unsafe addressing patterns
roland
parents: 32202
diff changeset
  2026
38286
0ddb6f84e138 8154826: AArch64: take advantage better of base + shifted offset addressing mode
roland
parents: 38033
diff changeset
  2027
// A method-klass-holder may be passed in the inline_cache_reg
0ddb6f84e138 8154826: AArch64: take advantage better of base + shifted offset addressing mode
roland
parents: 38033
diff changeset
  2028
// and then expanded into the inline_cache_reg and a method_oop register
0ddb6f84e138 8154826: AArch64: take advantage better of base + shifted offset addressing mode
roland
parents: 38033
diff changeset
  2029
//   defined in ad_<arch>.cpp
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2030
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2031
//------------------------------find_shared------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2032
// Set bits if Node is shared or otherwise a root
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2033
void Matcher::find_shared( Node *n ) {
33158
f4e6c593ba73 8137160: Use Compile::live_nodes instead of Compile::unique() in appropriate places -- followup
zmajo
parents: 33082
diff changeset
  2034
  // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc
32202
7e7ad8b06f5b 8011858: Use Compile::live_nodes() instead of Compile::unique() in appropriate places
kvn
parents: 31035
diff changeset
  2035
  MStack mstack(C->live_nodes() * 2);
2112
df46c83588fe 6791572: assert("duplicating node that's already been matched")
kvn
parents: 2022
diff changeset
  2036
  // Mark nodes as address_visited if they are inputs to an address expression
df46c83588fe 6791572: assert("duplicating node that's already been matched")
kvn
parents: 2022
diff changeset
  2037
  VectorSet address_visited(Thread::current()->resource_area());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2038
  mstack.push(n, Visit);     // Don't need to pre-visit root node
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2039
  while (mstack.is_nonempty()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2040
    n = mstack.node();       // Leave node on stack
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2041
    Node_State nstate = mstack.state();
2112
df46c83588fe 6791572: assert("duplicating node that's already been matched")
kvn
parents: 2022
diff changeset
  2042
    uint nop = n->Opcode();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2043
    if (nstate == Pre_Visit) {
2112
df46c83588fe 6791572: assert("duplicating node that's already been matched")
kvn
parents: 2022
diff changeset
  2044
      if (address_visited.test(n->_idx)) { // Visited in address already?
df46c83588fe 6791572: assert("duplicating node that's already been matched")
kvn
parents: 2022
diff changeset
  2045
        // Flag as visited and shared now.
df46c83588fe 6791572: assert("duplicating node that's already been matched")
kvn
parents: 2022
diff changeset
  2046
        set_visited(n);
df46c83588fe 6791572: assert("duplicating node that's already been matched")
kvn
parents: 2022
diff changeset
  2047
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2048
      if (is_visited(n)) {   // Visited already?
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2049
        // Node is shared and has no reason to clone.  Flag it as shared.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2050
        // This causes it to match into a register for the sharing.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2051
        set_shared(n);       // Flag as shared and
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2052
        mstack.pop();        // remove node from stack
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2053
        continue;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2054
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2055
      nstate = Visit; // Not already visited; so visit now
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2056
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2057
    if (nstate == Visit) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2058
      mstack.set_state(Post_Visit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2059
      set_visited(n);   // Flag as visited now
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2060
      bool mem_op = false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2061
2112
df46c83588fe 6791572: assert("duplicating node that's already been matched")
kvn
parents: 2022
diff changeset
  2062
      switch( nop ) {  // Handle some opcodes special
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2063
      case Op_Phi:             // Treat Phis as shared roots
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2064
      case Op_Parm:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2065
      case Op_Proj:            // All handled specially during matching
236
9a04268c8eea 6671807: (Escape Analysis) Add new ideal node to represent the state of a scalarized object at a safepoint
kvn
parents: 1
diff changeset
  2066
      case Op_SafePointScalarObject:
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2067
        set_shared(n);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2068
        set_dontcare(n);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2069
        break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2070
      case Op_If:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2071
      case Op_CountedLoopEnd:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2072
        mstack.set_state(Alt_Post_Visit); // Alternative way
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2073
        // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)).  Helps
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2074
        // with matching cmp/branch in 1 instruction.  The Matcher needs the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2075
        // Bool and CmpX side-by-side, because it can only get at constants
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2076
        // that are at the leaves of Match trees, and the Bool's condition acts
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2077
        // as a constant here.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2078
        mstack.push(n->in(1), Visit);         // Clone the Bool
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2079
        mstack.push(n->in(0), Pre_Visit);     // Visit control input
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2080
        continue; // while (mstack.is_nonempty())
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2081
      case Op_ConvI2D:         // These forms efficiently match with a prior
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2082
      case Op_ConvI2F:         //   Load but not a following Store
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2083
        if( n->in(1)->is_Load() &&        // Prior load
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2084
            n->outcnt() == 1 &&           // Not already shared
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2085
            n->unique_out()->is_Store() ) // Following store
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2086
          set_shared(n);       // Force it to be a root
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2087
        break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2088
      case Op_ReverseBytesI:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2089
      case Op_ReverseBytesL:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2090
        if( n->in(1)->is_Load() &&        // Prior load
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2091
            n->outcnt() == 1 )            // Not already shared
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2092
          set_shared(n);                  // Force it to be a root
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2093
        break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2094
      case Op_BoxLock:         // Cant match until we get stack-regs in ADLC
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2095
      case Op_IfFalse:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2096
      case Op_IfTrue:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2097
      case Op_MachProj:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2098
      case Op_MergeMem:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2099
      case Op_Catch:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2100
      case Op_CatchProj:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2101
      case Op_CProj:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2102
      case Op_JumpProj:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2103
      case Op_JProj:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2104
      case Op_NeverBranch:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2105
        set_dontcare(n);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2106
        break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2107
      case Op_Jump:
10988
a3b2bd43ef4f 7107042: assert(no_dead_loop) failed: dead loop detected
kvn
parents: 10518
diff changeset
  2108
        mstack.push(n->in(1), Pre_Visit);     // Switch Value (could be shared)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2109
        mstack.push(n->in(0), Pre_Visit);     // Visit Control input
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2110
        continue;                             // while (mstack.is_nonempty())
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2111
      case Op_StrComp:
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  2112
      case Op_StrEquals:
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  2113
      case Op_StrIndexOf:
33628
09241459a8b8 8141132: JEP 254: Compact Strings
thartmann
parents: 33469
diff changeset
  2114
      case Op_StrIndexOfChar:
595
a2be4c89de81 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 594
diff changeset
  2115
      case Op_AryEq:
33628
09241459a8b8 8141132: JEP 254: Compact Strings
thartmann
parents: 33469
diff changeset
  2116
      case Op_HasNegatives:
09241459a8b8 8141132: JEP 254: Compact Strings
thartmann
parents: 33469
diff changeset
  2117
      case Op_StrInflatedCopy:
09241459a8b8 8141132: JEP 254: Compact Strings
thartmann
parents: 33469
diff changeset
  2118
      case Op_StrCompressedCopy:
15242
695bb216be99 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents: 14623
diff changeset
  2119
      case Op_EncodeISOArray:
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2120
        set_shared(n); // Force result into register (it will be anyways)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2121
        break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2122
      case Op_ConP: {  // Convert pointers above the centerline to NUL
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2123
        TypeNode *tn = n->as_Type(); // Constants derive from type nodes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2124
        const TypePtr* tp = tn->type()->is_ptr();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2125
        if (tp->_ptr == TypePtr::AnyNull) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2126
          tn->set_type(TypePtr::NULL_PTR);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2127
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2128
        break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2129
      }
589
a44a1e70a3e4 6695810: null oop passed to encode_heap_oop_not_null
kvn
parents: 360
diff changeset
  2130
      case Op_ConN: {  // Convert narrow pointers above the centerline to NUL
a44a1e70a3e4 6695810: null oop passed to encode_heap_oop_not_null
kvn
parents: 360
diff changeset
  2131
        TypeNode *tn = n->as_Type(); // Constants derive from type nodes
767
64fb1fd7186d 6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents: 762
diff changeset
  2132
        const TypePtr* tp = tn->type()->make_ptr();
64fb1fd7186d 6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents: 762
diff changeset
  2133
        if (tp && tp->_ptr == TypePtr::AnyNull) {
589
a44a1e70a3e4 6695810: null oop passed to encode_heap_oop_not_null
kvn
parents: 360
diff changeset
  2134
          tn->set_type(TypeNarrowOop::NULL_PTR);
a44a1e70a3e4 6695810: null oop passed to encode_heap_oop_not_null
kvn
parents: 360
diff changeset
  2135
        }
a44a1e70a3e4 6695810: null oop passed to encode_heap_oop_not_null
kvn
parents: 360
diff changeset
  2136
        break;
a44a1e70a3e4 6695810: null oop passed to encode_heap_oop_not_null
kvn
parents: 360
diff changeset
  2137
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2138
      case Op_Binary:         // These are introduced in the Post_Visit state.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2139
        ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2140
        break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2141
      case Op_ClearArray:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2142
      case Op_SafePoint:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2143
        mem_op = true;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2144
        break;
4431
98ff8f025c55 6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents: 3905
diff changeset
  2145
      default:
98ff8f025c55 6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents: 3905
diff changeset
  2146
        if( n->is_Store() ) {
98ff8f025c55 6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents: 3905
diff changeset
  2147
          // Do match stores, despite no ideal reg
98ff8f025c55 6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents: 3905
diff changeset
  2148
          mem_op = true;
98ff8f025c55 6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents: 3905
diff changeset
  2149
          break;
98ff8f025c55 6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents: 3905
diff changeset
  2150
        }
98ff8f025c55 6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents: 3905
diff changeset
  2151
        if( n->is_Mem() ) { // Loads and LoadStores
98ff8f025c55 6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents: 3905
diff changeset
  2152
          mem_op = true;
98ff8f025c55 6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents: 3905
diff changeset
  2153
          // Loads must be root of match tree due to prior load conflict
98ff8f025c55 6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents: 3905
diff changeset
  2154
          if( C->subsume_loads() == false )
98ff8f025c55 6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents: 3905
diff changeset
  2155
            set_shared(n);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2156
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2157
        // Fall into default case
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2158
        if( !n->ideal_reg() )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2159
          set_dontcare(n);  // Unmatchable Nodes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2160
      } // end_switch
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2161
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2162
      for(int i = n->req() - 1; i >= 0; --i) { // For my children
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2163
        Node *m = n->in(i); // Get ith input
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2164
        if (m == NULL) continue;  // Ignore NULLs
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2165
        uint mop = m->Opcode();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2166
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2167
        // Must clone all producers of flags, or we will not match correctly.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2168
        // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2169
        // then it will match into an ideal Op_RegFlags.  Alas, the fp-flags
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2170
        // are also there, so we may match a float-branch to int-flags and
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2171
        // expect the allocator to haul the flags from the int-side to the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2172
        // fp-side.  No can do.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2173
        if( _must_clone[mop] ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2174
          mstack.push(m, Visit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2175
          continue; // for(int i = ...)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2176
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2177
13969
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13895
diff changeset
  2178
        if( mop == Op_AddP && m->in(AddPNode::Base)->is_DecodeNarrowPtr()) {
4431
98ff8f025c55 6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents: 3905
diff changeset
  2179
          // Bases used in addresses must be shared but since
98ff8f025c55 6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents: 3905
diff changeset
  2180
          // they are shared through a DecodeN they may appear
98ff8f025c55 6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents: 3905
diff changeset
  2181
          // to have a single use so force sharing here.
98ff8f025c55 6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents: 3905
diff changeset
  2182
          set_shared(m->in(AddPNode::Base)->in(1));
98ff8f025c55 6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents: 3905
diff changeset
  2183
        }
98ff8f025c55 6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents: 3905
diff changeset
  2184
23220
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  2185
        // if 'n' and 'm' are part of a graph for BMI instruction, clone this node.
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  2186
#ifdef X86
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  2187
        if (UseBMI1Instructions && is_bmi_pattern(n, m)) {
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  2188
          mstack.push(m, Visit);
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  2189
          continue;
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  2190
        }
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  2191
#endif
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 22911
diff changeset
  2192
4431
98ff8f025c55 6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents: 3905
diff changeset
  2193
        // Clone addressing expressions as they are "free" in memory access instructions
33082
c3e302e8e429 8136820: Generate better code for some Unsafe addressing patterns
roland
parents: 32202
diff changeset
  2194
        if (mem_op && i == MemNode::Address && mop == Op_AddP &&
c3e302e8e429 8136820: Generate better code for some Unsafe addressing patterns
roland
parents: 32202
diff changeset
  2195
            // When there are other uses besides address expressions
c3e302e8e429 8136820: Generate better code for some Unsafe addressing patterns
roland
parents: 32202
diff changeset
  2196
            // put it on stack and mark as shared.
c3e302e8e429 8136820: Generate better code for some Unsafe addressing patterns
roland
parents: 32202
diff changeset
  2197
            !is_visited(m)) {
2112
df46c83588fe 6791572: assert("duplicating node that's already been matched")
kvn
parents: 2022
diff changeset
  2198
          // Some inputs for address expression are not put on stack
df46c83588fe 6791572: assert("duplicating node that's already been matched")
kvn
parents: 2022
diff changeset
  2199
          // to avoid marking them as shared and forcing them into register
df46c83588fe 6791572: assert("duplicating node that's already been matched")
kvn
parents: 2022
diff changeset
  2200
          // if they are used only in address expressions.
df46c83588fe 6791572: assert("duplicating node that's already been matched")
kvn
parents: 2022
diff changeset
  2201
          // But they should be marked as shared if there are other uses
df46c83588fe 6791572: assert("duplicating node that's already been matched")
kvn
parents: 2022
diff changeset
  2202
          // besides address expressions.
df46c83588fe 6791572: assert("duplicating node that's already been matched")
kvn
parents: 2022
diff changeset
  2203
38286
0ddb6f84e138 8154826: AArch64: take advantage better of base + shifted offset addressing mode
roland
parents: 38033
diff changeset
  2204
          if (clone_address_expressions(m->as_AddP(), mstack, address_visited)) {
0ddb6f84e138 8154826: AArch64: take advantage better of base + shifted offset addressing mode
roland
parents: 38033
diff changeset
  2205
            continue;
0ddb6f84e138 8154826: AArch64: take advantage better of base + shifted offset addressing mode
roland
parents: 38033
diff changeset
  2206
          }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2207
        }   // if( mem_op &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2208
        mstack.push(m, Pre_Visit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2209
      }     // for(int i = ...)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2210
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2211
    else if (nstate == Alt_Post_Visit) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2212
      mstack.pop(); // Remove node from stack
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2213
      // We cannot remove the Cmp input from the Bool here, as the Bool may be
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2214
      // shared and all users of the Bool need to move the Cmp in parallel.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2215
      // This leaves both the Bool and the If pointing at the Cmp.  To
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2216
      // prevent the Matcher from trying to Match the Cmp along both paths
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2217
      // BoolNode::match_edge always returns a zero.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2218
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2219
      // We reorder the Op_If in a pre-order manner, so we can visit without
2131
98f9cef66a34 6810672: Comment typos
twisti
parents: 2112
diff changeset
  2220
      // accidentally sharing the Cmp (the Bool and the If make 2 users).
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2221
      n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2222
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2223
    else if (nstate == Post_Visit) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2224
      mstack.pop(); // Remove node from stack
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2225
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2226
      // Now hack a few special opcodes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2227
      switch( n->Opcode() ) {       // Handle some opcodes special
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2228
      case Op_StorePConditional:
1500
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1400
diff changeset
  2229
      case Op_StoreIConditional:
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2230
      case Op_StoreLConditional:
39419
cc993a4ab581 8157726: VarHandles/Unsafe should support sub-word atomic ops
shade
parents: 38658
diff changeset
  2231
      case Op_CompareAndExchangeB:
cc993a4ab581 8157726: VarHandles/Unsafe should support sub-word atomic ops
shade
parents: 38658
diff changeset
  2232
      case Op_CompareAndExchangeS:
36316
7a83de7aabca 8148146: Integrate new internal Unsafe entry points, and basic intrinsic support for VarHandles
shade
parents: 35086
diff changeset
  2233
      case Op_CompareAndExchangeI:
7a83de7aabca 8148146: Integrate new internal Unsafe entry points, and basic intrinsic support for VarHandles
shade
parents: 35086
diff changeset
  2234
      case Op_CompareAndExchangeL:
7a83de7aabca 8148146: Integrate new internal Unsafe entry points, and basic intrinsic support for VarHandles
shade
parents: 35086
diff changeset
  2235
      case Op_CompareAndExchangeP:
7a83de7aabca 8148146: Integrate new internal Unsafe entry points, and basic intrinsic support for VarHandles
shade
parents: 35086
diff changeset
  2236
      case Op_CompareAndExchangeN:
39419
cc993a4ab581 8157726: VarHandles/Unsafe should support sub-word atomic ops
shade
parents: 38658
diff changeset
  2237
      case Op_WeakCompareAndSwapB:
cc993a4ab581 8157726: VarHandles/Unsafe should support sub-word atomic ops
shade
parents: 38658
diff changeset
  2238
      case Op_WeakCompareAndSwapS:
36316
7a83de7aabca 8148146: Integrate new internal Unsafe entry points, and basic intrinsic support for VarHandles
shade
parents: 35086
diff changeset
  2239
      case Op_WeakCompareAndSwapI:
7a83de7aabca 8148146: Integrate new internal Unsafe entry points, and basic intrinsic support for VarHandles
shade
parents: 35086
diff changeset
  2240
      case Op_WeakCompareAndSwapL:
7a83de7aabca 8148146: Integrate new internal Unsafe entry points, and basic intrinsic support for VarHandles
shade
parents: 35086
diff changeset
  2241
      case Op_WeakCompareAndSwapP:
7a83de7aabca 8148146: Integrate new internal Unsafe entry points, and basic intrinsic support for VarHandles
shade
parents: 35086
diff changeset
  2242
      case Op_WeakCompareAndSwapN:
39419
cc993a4ab581 8157726: VarHandles/Unsafe should support sub-word atomic ops
shade
parents: 38658
diff changeset
  2243
      case Op_CompareAndSwapB:
cc993a4ab581 8157726: VarHandles/Unsafe should support sub-word atomic ops
shade
parents: 38658
diff changeset
  2244
      case Op_CompareAndSwapS:
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2245
      case Op_CompareAndSwapI:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2246
      case Op_CompareAndSwapL:
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
  2247
      case Op_CompareAndSwapP:
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
  2248
      case Op_CompareAndSwapN: {   // Convert trinary to binary-tree
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2249
        Node *newval = n->in(MemNode::ValueIn );
13886
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  2250
        Node *oldval  = n->in(LoadStoreConditionalNode::ExpectedIn);
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24424
diff changeset
  2251
        Node *pair = new BinaryNode( oldval, newval );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2252
        n->set_req(MemNode::ValueIn,pair);
13886
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  2253
        n->del_req(LoadStoreConditionalNode::ExpectedIn);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2254
        break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2255
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2256
      case Op_CMoveD:              // Convert trinary to binary-tree
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2257
      case Op_CMoveF:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2258
      case Op_CMoveI:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2259
      case Op_CMoveL:
590
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  2260
      case Op_CMoveN:
33469
30f4811eded0 8139340: SuperWord enhancement to support vector conditional move (CMovVD) on Intel AVX cpu
iveresov
parents: 33158
diff changeset
  2261
      case Op_CMoveP:
30f4811eded0 8139340: SuperWord enhancement to support vector conditional move (CMovVD) on Intel AVX cpu
iveresov
parents: 33158
diff changeset
  2262
      case Op_CMoveVD:  {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2263
        // Restructure into a binary tree for Matching.  It's possible that
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2264
        // we could move this code up next to the graph reshaping for IfNodes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2265
        // or vice-versa, but I do not want to debug this for Ladybird.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2266
        // 10/2/2000 CNC.
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24424
diff changeset
  2267
        Node *pair1 = new BinaryNode(n->in(1),n->in(1)->in(1));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2268
        n->set_req(1,pair1);
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24424
diff changeset
  2269
        Node *pair2 = new BinaryNode(n->in(2),n->in(3));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2270
        n->set_req(2,pair2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2271
        n->del_req(3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2272
        break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2273
      }
9446
748a37b25d10 5091921: Sign flip issues in loop optimizer
kvn
parents: 8921
diff changeset
  2274
      case Op_LoopLimit: {
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24424
diff changeset
  2275
        Node *pair1 = new BinaryNode(n->in(1),n->in(2));
9446
748a37b25d10 5091921: Sign flip issues in loop optimizer
kvn
parents: 8921
diff changeset
  2276
        n->set_req(1,pair1);
748a37b25d10 5091921: Sign flip issues in loop optimizer
kvn
parents: 8921
diff changeset
  2277
        n->set_req(2,n->in(3));
748a37b25d10 5091921: Sign flip issues in loop optimizer
kvn
parents: 8921
diff changeset
  2278
        n->del_req(3);
748a37b25d10 5091921: Sign flip issues in loop optimizer
kvn
parents: 8921
diff changeset
  2279
        break;
748a37b25d10 5091921: Sign flip issues in loop optimizer
kvn
parents: 8921
diff changeset
  2280
      }
33628
09241459a8b8 8141132: JEP 254: Compact Strings
thartmann
parents: 33469
diff changeset
  2281
      case Op_StrEquals:
09241459a8b8 8141132: JEP 254: Compact Strings
thartmann
parents: 33469
diff changeset
  2282
      case Op_StrIndexOfChar: {
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24424
diff changeset
  2283
        Node *pair1 = new BinaryNode(n->in(2),n->in(3));
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3268
diff changeset
  2284
        n->set_req(2,pair1);
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3268
diff changeset
  2285
        n->set_req(3,n->in(4));
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3268
diff changeset
  2286
        n->del_req(4);
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3268
diff changeset
  2287
        break;
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3268
diff changeset
  2288
      }
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3268
diff changeset
  2289
      case Op_StrComp:
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3268
diff changeset
  2290
      case Op_StrIndexOf: {
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24424
diff changeset
  2291
        Node *pair1 = new BinaryNode(n->in(2),n->in(3));
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3268
diff changeset
  2292
        n->set_req(2,pair1);
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24424
diff changeset
  2293
        Node *pair2 = new BinaryNode(n->in(4),n->in(5));
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3268
diff changeset
  2294
        n->set_req(3,pair2);
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3268
diff changeset
  2295
        n->del_req(5);
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3268
diff changeset
  2296
        n->del_req(4);
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3268
diff changeset
  2297
        break;
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3268
diff changeset
  2298
      }
33628
09241459a8b8 8141132: JEP 254: Compact Strings
thartmann
parents: 33469
diff changeset
  2299
      case Op_StrCompressedCopy:
09241459a8b8 8141132: JEP 254: Compact Strings
thartmann
parents: 33469
diff changeset
  2300
      case Op_StrInflatedCopy:
15242
695bb216be99 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents: 14623
diff changeset
  2301
      case Op_EncodeISOArray: {
695bb216be99 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents: 14623
diff changeset
  2302
        // Restructure into a binary tree for Matching.
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24424
diff changeset
  2303
        Node* pair = new BinaryNode(n->in(3), n->in(4));
15242
695bb216be99 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents: 14623
diff changeset
  2304
        n->set_req(3, pair);
695bb216be99 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents: 14623
diff changeset
  2305
        n->del_req(4);
695bb216be99 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents: 14623
diff changeset
  2306
        break;
695bb216be99 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents: 14623
diff changeset
  2307
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2308
      default:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2309
        break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2310
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2311
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2312
    else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2313
      ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2314
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2315
  } // end of while (mstack.is_nonempty())
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2316
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2317
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2318
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2319
// machine-independent root to machine-dependent root
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2320
void Matcher::dump_old2new_map() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2321
  _old2new_map.dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2322
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2323
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2324
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2325
//---------------------------collect_null_checks-------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2326
// Find null checks in the ideal graph; write a machine-specific node for
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2327
// it.  Used by later implicit-null-check handling.  Actually collects
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2328
// either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2329
// value being tested.
1400
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2330
void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2331
  Node *iff = proj->in(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2332
  if( iff->Opcode() == Op_If ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2333
    // During matching If's have Bool & Cmp side-by-side
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2334
    BoolNode *b = iff->in(1)->as_Bool();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2335
    Node *cmp = iff->in(2);
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
  2336
    int opc = cmp->Opcode();
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
  2337
    if (opc != Op_CmpP && opc != Op_CmpN) return;
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
  2338
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
  2339
    const Type* ct = cmp->in(2)->bottom_type();
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
  2340
    if (ct == TypePtr::NULL_PTR ||
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
  2341
        (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2342
1400
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2343
      bool push_it = false;
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
  2344
      if( proj->Opcode() == Op_IfTrue ) {
36336
7006dd73b206 8150720: Cleanup code around PrintOptoStatistics
redestad
parents: 36316
diff changeset
  2345
#ifndef PRODUCT
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
  2346
        extern int all_null_checks_found;
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
  2347
        all_null_checks_found++;
36336
7006dd73b206 8150720: Cleanup code around PrintOptoStatistics
redestad
parents: 36316
diff changeset
  2348
#endif
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
  2349
        if( b->_test._test == BoolTest::ne ) {
1400
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2350
          push_it = true;
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
  2351
        }
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
  2352
      } else {
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
  2353
        assert( proj->Opcode() == Op_IfFalse, "" );
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
  2354
        if( b->_test._test == BoolTest::eq ) {
1400
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2355
          push_it = true;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2356
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2357
      }
1400
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2358
      if( push_it ) {
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2359
        _null_check_tests.push(proj);
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2360
        Node* val = cmp->in(1);
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2361
#ifdef _LP64
5698
091095915ee6 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 4751
diff changeset
  2362
        if (val->bottom_type()->isa_narrowoop() &&
091095915ee6 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 4751
diff changeset
  2363
            !Matcher::narrow_oop_use_complex_address()) {
1400
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2364
          //
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2365
          // Look for DecodeN node which should be pinned to orig_proj.
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2366
          // On platforms (Sparc) which can not handle 2 adds
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2367
          // in addressing mode we have to keep a DecodeN node and
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2368
          // use it to do implicit NULL check in address.
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2369
          //
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2370
          // DecodeN node was pinned to non-null path (orig_proj) during
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2371
          // CastPP transformation in final_graph_reshaping_impl().
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2372
          //
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2373
          uint cnt = orig_proj->outcnt();
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2374
          for (uint i = 0; i < orig_proj->outcnt(); i++) {
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2375
            Node* d = orig_proj->raw_out(i);
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2376
            if (d->is_DecodeN() && d->in(1) == val) {
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2377
              val = d;
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2378
              val->set_req(0, NULL); // Unpin now.
5698
091095915ee6 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 4751
diff changeset
  2379
              // Mark this as special case to distinguish from
091095915ee6 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 4751
diff changeset
  2380
              // a regular case: CmpP(DecodeN, NULL).
091095915ee6 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 4751
diff changeset
  2381
              val = (Node*)(((intptr_t)val) | 1);
1400
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2382
              break;
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2383
            }
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2384
          }
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2385
        }
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2386
#endif
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2387
        _null_check_tests.push(val);
afd034bb8c2e 6747051: Improve code and implicit null check generation for compressed oops
kvn
parents: 1399
diff changeset
  2388
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2389
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2390
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2391
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2392
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2393
//---------------------------validate_null_checks------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2394
// Its possible that the value being NULL checked is not the root of a match
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2395
// tree.  If so, I cannot use the value in an implicit null check.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2396
void Matcher::validate_null_checks( ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2397
  uint cnt = _null_check_tests.size();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2398
  for( uint i=0; i < cnt; i+=2 ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2399
    Node *test = _null_check_tests[i];
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2400
    Node *val = _null_check_tests[i+1];
5698
091095915ee6 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 4751
diff changeset
  2401
    bool is_decoden = ((intptr_t)val) & 1;
091095915ee6 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 4751
diff changeset
  2402
    val = (Node*)(((intptr_t)val) & ~1);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2403
    if (has_new_node(val)) {
5698
091095915ee6 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 4751
diff changeset
  2404
      Node* new_val = new_node(val);
091095915ee6 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 4751
diff changeset
  2405
      if (is_decoden) {
13969
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13895
diff changeset
  2406
        assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity");
5698
091095915ee6 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 4751
diff changeset
  2407
        // Note: new_val may have a control edge if
091095915ee6 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 4751
diff changeset
  2408
        // the original ideal node DecodeN was matched before
091095915ee6 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 4751
diff changeset
  2409
        // it was unpinned in Matcher::collect_null_checks().
091095915ee6 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 4751
diff changeset
  2410
        // Unpin the mach node and mark it.
091095915ee6 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 4751
diff changeset
  2411
        new_val->set_req(0, NULL);
091095915ee6 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 4751
diff changeset
  2412
        new_val = (Node*)(((intptr_t)new_val) | 1);
091095915ee6 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 4751
diff changeset
  2413
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2414
      // Is a match-tree root, so replace with the matched value
5698
091095915ee6 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 4751
diff changeset
  2415
      _null_check_tests.map(i+1, new_val);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2416
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2417
      // Yank from candidate list
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2418
      _null_check_tests.map(i+1,_null_check_tests[--cnt]);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2419
      _null_check_tests.map(i,_null_check_tests[--cnt]);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2420
      _null_check_tests.pop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2421
      _null_check_tests.pop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2422
      i-=2;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2423
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2424
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2425
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2426
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2427
// Used by the DFA in dfa_xxx.cpp.  Check for a following barrier or
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2428
// atomic instruction acting as a store_load barrier without any
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2429
// intervening volatile load, and thus we don't need a barrier here.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2430
// We retain the Node to act as a compiler ordering barrier.
18956
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2431
bool Matcher::post_store_load_barrier(const Node* vmb) {
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2432
  Compile* C = Compile::current();
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2433
  assert(vmb->is_MemBar(), "");
22855
d637fd28a6c3 8028515: PPPC64 (part 113.2): opto: Introduce LoadFence/StoreFence.
goetz
parents: 22851
diff changeset
  2434
  assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, "");
18956
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2435
  const MemBarNode* membar = vmb->as_MemBar();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2436
18956
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2437
  // Get the Ideal Proj node, ctrl, that can be used to iterate forward
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2438
  Node* ctrl = NULL;
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2439
  for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2440
    Node* p = membar->fast_out(i);
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2441
    assert(p->is_Proj(), "only projections here");
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2442
    if ((p->as_Proj()->_con == TypeFunc::Control) &&
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2443
        !C->node_arena()->contains(p)) { // Unmatched old-space only
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2444
      ctrl = p;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2445
      break;
18956
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2446
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2447
  }
18956
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2448
  assert((ctrl != NULL), "missing control projection");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2449
18956
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2450
  for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2451
    Node *x = ctrl->fast_out(j);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2452
    int xop = x->Opcode();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2453
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2454
    // We don't need current barrier if we see another or a lock
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2455
    // before seeing volatile load.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2456
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2457
    // Op_Fastunlock previously appeared in the Op_* list below.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2458
    // With the advent of 1-0 lock operations we're no longer guaranteed
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2459
    // that a monitor exit operation contains a serializing instruction.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2460
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2461
    if (xop == Op_MemBarVolatile ||
39419
cc993a4ab581 8157726: VarHandles/Unsafe should support sub-word atomic ops
shade
parents: 38658
diff changeset
  2462
        xop == Op_CompareAndExchangeB ||
cc993a4ab581 8157726: VarHandles/Unsafe should support sub-word atomic ops
shade
parents: 38658
diff changeset
  2463
        xop == Op_CompareAndExchangeS ||
36316
7a83de7aabca 8148146: Integrate new internal Unsafe entry points, and basic intrinsic support for VarHandles
shade
parents: 35086
diff changeset
  2464
        xop == Op_CompareAndExchangeI ||
7a83de7aabca 8148146: Integrate new internal Unsafe entry points, and basic intrinsic support for VarHandles
shade
parents: 35086
diff changeset
  2465
        xop == Op_CompareAndExchangeL ||
7a83de7aabca 8148146: Integrate new internal Unsafe entry points, and basic intrinsic support for VarHandles
shade
parents: 35086
diff changeset
  2466
        xop == Op_CompareAndExchangeP ||
7a83de7aabca 8148146: Integrate new internal Unsafe entry points, and basic intrinsic support for VarHandles
shade
parents: 35086
diff changeset
  2467
        xop == Op_CompareAndExchangeN ||
39419
cc993a4ab581 8157726: VarHandles/Unsafe should support sub-word atomic ops
shade
parents: 38658
diff changeset
  2468
        xop == Op_WeakCompareAndSwapB ||
cc993a4ab581 8157726: VarHandles/Unsafe should support sub-word atomic ops
shade
parents: 38658
diff changeset
  2469
        xop == Op_WeakCompareAndSwapS ||
36316
7a83de7aabca 8148146: Integrate new internal Unsafe entry points, and basic intrinsic support for VarHandles
shade
parents: 35086
diff changeset
  2470
        xop == Op_WeakCompareAndSwapL ||
7a83de7aabca 8148146: Integrate new internal Unsafe entry points, and basic intrinsic support for VarHandles
shade
parents: 35086
diff changeset
  2471
        xop == Op_WeakCompareAndSwapP ||
7a83de7aabca 8148146: Integrate new internal Unsafe entry points, and basic intrinsic support for VarHandles
shade
parents: 35086
diff changeset
  2472
        xop == Op_WeakCompareAndSwapN ||
7a83de7aabca 8148146: Integrate new internal Unsafe entry points, and basic intrinsic support for VarHandles
shade
parents: 35086
diff changeset
  2473
        xop == Op_WeakCompareAndSwapI ||
39419
cc993a4ab581 8157726: VarHandles/Unsafe should support sub-word atomic ops
shade
parents: 38658
diff changeset
  2474
        xop == Op_CompareAndSwapB ||
cc993a4ab581 8157726: VarHandles/Unsafe should support sub-word atomic ops
shade
parents: 38658
diff changeset
  2475
        xop == Op_CompareAndSwapS ||
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2476
        xop == Op_CompareAndSwapL ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2477
        xop == Op_CompareAndSwapP ||
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 236
diff changeset
  2478
        xop == Op_CompareAndSwapN ||
18956
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2479
        xop == Op_CompareAndSwapI) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2480
      return true;
18956
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2481
    }
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2482
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2483
    // Op_FastLock previously appeared in the Op_* list above.
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2484
    // With biased locking we're no longer guaranteed that a monitor
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2485
    // enter operation contains a serializing instruction.
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2486
    if ((xop == Op_FastLock) && !UseBiasedLocking) {
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2487
      return true;
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2488
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2489
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2490
    if (x->is_MemBar()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2491
      // We must retain this membar if there is an upcoming volatile
18956
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2492
      // load, which will be followed by acquire membar.
22855
d637fd28a6c3 8028515: PPPC64 (part 113.2): opto: Introduce LoadFence/StoreFence.
goetz
parents: 22851
diff changeset
  2493
      if (xop == Op_MemBarAcquire || xop == Op_LoadFence) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2494
        return false;
18956
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2495
      } else {
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2496
        // For other kinds of barriers, check by pretending we
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2497
        // are them, and seeing if we can be removed.
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2498
        return post_store_load_barrier(x->as_MemBar());
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2499
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2500
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2501
18956
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2502
    // probably not necessary to check for these
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2503
    if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
f8fc5dd18a1d 8007898: Incorrect optimization of Memory Barriers in Matcher::post_store_load_barrier()
kvn
parents: 18103
diff changeset
  2504
      return false;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2505
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2506
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2507
  return false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2508
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2509
22856
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2510
// Check whether node n is a branch to an uncommon trap that we could
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2511
// optimize as test with very high branch costs in case of going to
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2512
// the uncommon trap. The code must be able to be recompiled to use
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2513
// a cheaper test.
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2514
bool Matcher::branches_to_uncommon_trap(const Node *n) {
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2515
  // Don't do it for natives, adapters, or runtime stubs
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2516
  Compile *C = Compile::current();
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2517
  if (!C->is_method_compilation()) return false;
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2518
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2519
  assert(n->is_If(), "You should only call this on if nodes.");
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2520
  IfNode *ifn = n->as_If();
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2521
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2522
  Node *ifFalse = NULL;
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2523
  for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) {
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2524
    if (ifn->fast_out(i)->is_IfFalse()) {
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2525
      ifFalse = ifn->fast_out(i);
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2526
      break;
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2527
    }
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2528
  }
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2529
  assert(ifFalse, "An If should have an ifFalse. Graph is broken.");
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2530
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2531
  Node *reg = ifFalse;
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2532
  int cnt = 4; // We must protect against cycles.  Limit to 4 iterations.
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2533
               // Alternatively use visited set?  Seems too expensive.
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2534
  while (reg != NULL && cnt > 0) {
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2535
    CallNode *call = NULL;
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2536
    RegionNode *nxt_reg = NULL;
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2537
    for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) {
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2538
      Node *o = reg->fast_out(i);
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2539
      if (o->is_Call()) {
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2540
        call = o->as_Call();
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2541
      }
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2542
      if (o->is_Region()) {
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2543
        nxt_reg = o->as_Region();
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2544
      }
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2545
    }
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2546
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2547
    if (call &&
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2548
        call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) {
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2549
      const Type* trtype = call->in(TypeFunc::Parms)->bottom_type();
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2550
      if (trtype->isa_int() && trtype->is_int()->is_con()) {
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2551
        jint tr_con = trtype->is_int()->get_con();
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2552
        Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2553
        Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2554
        assert((int)reason < (int)BitsPerInt, "recode bit map");
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2555
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2556
        if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason)
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2557
            && action != Deoptimization::Action_none) {
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2558
          // This uncommon trap is sure to recompile, eventually.
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2559
          // When that happens, C->too_many_traps will prevent
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2560
          // this transformation from happening again.
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2561
          return true;
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2562
        }
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2563
      }
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2564
    }
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2565
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2566
    reg = nxt_reg;
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2567
    cnt--;
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2568
  }
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2569
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2570
  return false;
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2571
}
03ad2cf18166 8029015: PPC64 (part 216): opto: trap based null and range checks
goetz
parents: 22855
diff changeset
  2572
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2573
//=============================================================================
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2574
//---------------------------State---------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2575
State::State(void) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2576
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2577
  _id = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2578
  _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2579
  _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2580
  //memset(_cost, -1, sizeof(_cost));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2581
  //memset(_rule, -1, sizeof(_rule));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2582
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2583
  memset(_valid, 0, sizeof(_valid));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2584
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2585
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2586
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2587
State::~State() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2588
  _id = 99;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2589
  _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2590
  _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2591
  memset(_cost, -3, sizeof(_cost));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2592
  memset(_rule, -3, sizeof(_rule));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2593
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2594
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2595
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2596
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2597
//---------------------------dump----------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2598
void State::dump() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2599
  tty->print("\n");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2600
  dump(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2601
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2602
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2603
void State::dump(int depth) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2604
  for( int j = 0; j < depth; j++ )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2605
    tty->print("   ");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2606
  tty->print("--N: ");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2607
  _leaf->dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2608
  uint i;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2609
  for( i = 0; i < _LAST_MACH_OPER; i++ )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2610
    // Check for valid entry
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2611
    if( valid(i) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2612
      for( int j = 0; j < depth; j++ )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2613
        tty->print("   ");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2614
        assert(_cost[i] != max_juint, "cost must be a valid value");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2615
        assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2616
        tty->print_cr("%s  %d  %s",
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2617
                      ruleName[i], _cost[i], ruleName[_rule[i]] );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2618
      }
24424
2658d7834c6e 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 23528
diff changeset
  2619
  tty->cr();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2620
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2621
  for( i=0; i<2; i++ )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2622
    if( _kids[i] )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2623
      _kids[i]->dump(depth+1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2624
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2625
#endif