author | twisti |
Wed, 17 Mar 2010 10:22:41 +0100 | |
changeset 5052 | c6c9ff8ad36a |
parent 1 | 489c9b5090e2 |
child 5687 | b862d1f189bd |
child 5547 | f4b087cbb361 |
permissions | -rw-r--r-- |
1 | 1 |
/* |
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c6c9ff8ad36a
6934966: JSR 292 add C1 logic for saved SP over MethodHandle calls
twisti
parents:
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changeset
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* Copyright 1999-2010 Sun Microsystems, Inc. All Rights Reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
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* CA 95054 USA or visit www.sun.com if you need additional information or |
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* have any questions. |
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* |
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*/ |
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public: |
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enum { |
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nof_reg_args = 6, // registers o0-o5 are available for parameter passing |
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first_available_sp_in_frame = frame::memory_parameter_word_sp_offset * BytesPerWord, |
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frame_pad_in_bytes = 0 |
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}; |
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static const int pd_c_runtime_reserved_arg_size; |
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static LIR_Opr G0_opr; |
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static LIR_Opr G1_opr; |
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static LIR_Opr G2_opr; |
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static LIR_Opr G3_opr; |
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static LIR_Opr G4_opr; |
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static LIR_Opr G5_opr; |
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static LIR_Opr G6_opr; |
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static LIR_Opr G7_opr; |
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static LIR_Opr O0_opr; |
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static LIR_Opr O1_opr; |
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static LIR_Opr O2_opr; |
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static LIR_Opr O3_opr; |
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static LIR_Opr O4_opr; |
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static LIR_Opr O5_opr; |
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static LIR_Opr O6_opr; |
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static LIR_Opr O7_opr; |
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static LIR_Opr L0_opr; |
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static LIR_Opr L1_opr; |
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static LIR_Opr L2_opr; |
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static LIR_Opr L3_opr; |
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static LIR_Opr L4_opr; |
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static LIR_Opr L5_opr; |
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static LIR_Opr L6_opr; |
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static LIR_Opr L7_opr; |
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static LIR_Opr I0_opr; |
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static LIR_Opr I1_opr; |
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static LIR_Opr I2_opr; |
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static LIR_Opr I3_opr; |
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static LIR_Opr I4_opr; |
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static LIR_Opr I5_opr; |
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static LIR_Opr I6_opr; |
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static LIR_Opr I7_opr; |
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static LIR_Opr SP_opr; |
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static LIR_Opr FP_opr; |
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static LIR_Opr G0_oop_opr; |
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static LIR_Opr G1_oop_opr; |
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static LIR_Opr G2_oop_opr; |
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static LIR_Opr G3_oop_opr; |
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static LIR_Opr G4_oop_opr; |
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static LIR_Opr G5_oop_opr; |
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static LIR_Opr G6_oop_opr; |
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static LIR_Opr G7_oop_opr; |
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static LIR_Opr O0_oop_opr; |
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static LIR_Opr O1_oop_opr; |
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static LIR_Opr O2_oop_opr; |
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static LIR_Opr O3_oop_opr; |
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static LIR_Opr O4_oop_opr; |
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static LIR_Opr O5_oop_opr; |
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static LIR_Opr O6_oop_opr; |
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static LIR_Opr O7_oop_opr; |
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static LIR_Opr L0_oop_opr; |
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static LIR_Opr L1_oop_opr; |
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static LIR_Opr L2_oop_opr; |
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static LIR_Opr L3_oop_opr; |
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static LIR_Opr L4_oop_opr; |
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static LIR_Opr L5_oop_opr; |
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static LIR_Opr L6_oop_opr; |
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static LIR_Opr L7_oop_opr; |
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static LIR_Opr I0_oop_opr; |
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static LIR_Opr I1_oop_opr; |
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static LIR_Opr I2_oop_opr; |
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static LIR_Opr I3_oop_opr; |
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static LIR_Opr I4_oop_opr; |
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static LIR_Opr I5_oop_opr; |
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static LIR_Opr I6_oop_opr; |
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static LIR_Opr I7_oop_opr; |
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static LIR_Opr in_long_opr; |
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static LIR_Opr out_long_opr; |
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static LIR_Opr F0_opr; |
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static LIR_Opr F0_double_opr; |
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static LIR_Opr Oexception_opr; |
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static LIR_Opr Oissuing_pc_opr; |
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private: |
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static FloatRegister _fpu_regs [nof_fpu_regs]; |
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public: |
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#ifdef _LP64 |
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static LIR_Opr as_long_opr(Register r) { |
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return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r)); |
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} |
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static LIR_Opr as_pointer_opr(Register r) { |
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return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r)); |
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} |
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#else |
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static LIR_Opr as_long_opr(Register r) { |
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return LIR_OprFact::double_cpu(cpu_reg2rnr(r->successor()), cpu_reg2rnr(r)); |
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} |
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static LIR_Opr as_pointer_opr(Register r) { |
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return as_opr(r); |
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} |
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#endif |
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static LIR_Opr as_float_opr(FloatRegister r) { |
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return LIR_OprFact::single_fpu(r->encoding()); |
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} |
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static LIR_Opr as_double_opr(FloatRegister r) { |
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return LIR_OprFact::double_fpu(r->successor()->encoding(), r->encoding()); |
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} |
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static FloatRegister nr2floatreg (int rnr); |
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static VMReg fpu_regname (int n); |
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static bool is_caller_save_register (LIR_Opr reg); |
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static bool is_caller_save_register (Register r); |
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5052
c6c9ff8ad36a
6934966: JSR 292 add C1 logic for saved SP over MethodHandle calls
twisti
parents:
1
diff
changeset
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c6c9ff8ad36a
6934966: JSR 292 add C1 logic for saved SP over MethodHandle calls
twisti
parents:
1
diff
changeset
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// JSR 292 |
c6c9ff8ad36a
6934966: JSR 292 add C1 logic for saved SP over MethodHandle calls
twisti
parents:
1
diff
changeset
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static LIR_Opr& method_handle_invoke_SP_save_opr() { return L7_opr; } |