hotspot/src/share/vm/opto/ifg.cpp
author adlertz
Fri, 11 Oct 2013 13:10:22 +0200
changeset 20704 b689a120e974
parent 19717 7819ffdaf0ff
child 22234 da823d78ad65
permissions -rw-r--r--
8011415: CTW on Sparc: assert(lrg.lo_degree()) failed: Summary: Increased the LRG AllStack mask size since the previous size was not big enough when compiling huge methods (60k+ nodes) Reviewed-by: kvn, roland, twisti
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/*
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 * Copyright (c) 1998, 2012, Oracle and/or its affiliates. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#include "precompiled.hpp"
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#include "compiler/oopMap.hpp"
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#include "memory/allocation.inline.hpp"
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#include "opto/addnode.hpp"
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#include "opto/block.hpp"
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#include "opto/callnode.hpp"
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#include "opto/cfgnode.hpp"
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#include "opto/chaitin.hpp"
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#include "opto/coalesce.hpp"
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#include "opto/connode.hpp"
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#include "opto/indexSet.hpp"
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#include "opto/machnode.hpp"
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#include "opto/memnode.hpp"
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#include "opto/opcodes.hpp"
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PhaseIFG::PhaseIFG( Arena *arena ) : Phase(Interference_Graph), _arena(arena) {
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}
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void PhaseIFG::init( uint maxlrg ) {
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  _maxlrg = maxlrg;
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  _yanked = new (_arena) VectorSet(_arena);
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  _is_square = false;
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  // Make uninitialized adjacency lists
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  _adjs = (IndexSet*)_arena->Amalloc(sizeof(IndexSet)*maxlrg);
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  // Also make empty live range structures
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  _lrgs = (LRG *)_arena->Amalloc( maxlrg * sizeof(LRG) );
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  memset(_lrgs,0,sizeof(LRG)*maxlrg);
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  // Init all to empty
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  for( uint i = 0; i < maxlrg; i++ ) {
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    _adjs[i].initialize(maxlrg);
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    _lrgs[i].Set_All();
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  }
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}
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// Add edge between vertices a & b.  These are sorted (triangular matrix),
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// then the smaller number is inserted in the larger numbered array.
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int PhaseIFG::add_edge( uint a, uint b ) {
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  lrgs(a).invalid_degree();
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  lrgs(b).invalid_degree();
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  // Sort a and b, so that a is bigger
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  assert( !_is_square, "only on triangular" );
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  if( a < b ) { uint tmp = a; a = b; b = tmp; }
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  return _adjs[a].insert( b );
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}
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// Add an edge between 'a' and everything in the vector.
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void PhaseIFG::add_vector( uint a, IndexSet *vec ) {
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  // IFG is triangular, so do the inserts where 'a' < 'b'.
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  assert( !_is_square, "only on triangular" );
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  IndexSet *adjs_a = &_adjs[a];
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  if( !vec->count() ) return;
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  IndexSetIterator elements(vec);
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  uint neighbor;
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  while ((neighbor = elements.next()) != 0) {
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    add_edge( a, neighbor );
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  }
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}
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// Is there an edge between a and b?
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int PhaseIFG::test_edge( uint a, uint b ) const {
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  // Sort a and b, so that a is larger
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  assert( !_is_square, "only on triangular" );
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  if( a < b ) { uint tmp = a; a = b; b = tmp; }
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  return _adjs[a].member(b);
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}
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// Convert triangular matrix to square matrix
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void PhaseIFG::SquareUp() {
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  assert( !_is_square, "only on triangular" );
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  // Simple transpose
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  for( uint i = 0; i < _maxlrg; i++ ) {
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    IndexSetIterator elements(&_adjs[i]);
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    uint datum;
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    while ((datum = elements.next()) != 0) {
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      _adjs[datum].insert( i );
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    }
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  }
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  _is_square = true;
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}
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// Compute effective degree in bulk
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void PhaseIFG::Compute_Effective_Degree() {
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  assert( _is_square, "only on square" );
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  for( uint i = 0; i < _maxlrg; i++ )
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    lrgs(i).set_degree(effective_degree(i));
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}
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int PhaseIFG::test_edge_sq( uint a, uint b ) const {
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  assert( _is_square, "only on square" );
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  // Swap, so that 'a' has the lesser count.  Then binary search is on
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  // the smaller of a's list and b's list.
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  if( neighbor_cnt(a) > neighbor_cnt(b) ) { uint tmp = a; a = b; b = tmp; }
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  //return _adjs[a].unordered_member(b);
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  return _adjs[a].member(b);
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}
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// Union edges of B into A
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void PhaseIFG::Union( uint a, uint b ) {
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  assert( _is_square, "only on square" );
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  IndexSet *A = &_adjs[a];
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  IndexSetIterator b_elements(&_adjs[b]);
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  uint datum;
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  while ((datum = b_elements.next()) != 0) {
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    if(A->insert(datum)) {
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      _adjs[datum].insert(a);
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      lrgs(a).invalid_degree();
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      lrgs(datum).invalid_degree();
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    }
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  }
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}
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// Yank a Node and all connected edges from the IFG.  Return a
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// list of neighbors (edges) yanked.
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IndexSet *PhaseIFG::remove_node( uint a ) {
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  assert( _is_square, "only on square" );
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  assert( !_yanked->test(a), "" );
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  _yanked->set(a);
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  // I remove the LRG from all neighbors.
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  IndexSetIterator elements(&_adjs[a]);
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  LRG &lrg_a = lrgs(a);
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  uint datum;
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  while ((datum = elements.next()) != 0) {
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    _adjs[datum].remove(a);
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    lrgs(datum).inc_degree( -lrg_a.compute_degree(lrgs(datum)) );
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  }
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  return neighbors(a);
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}
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// Re-insert a yanked Node.
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void PhaseIFG::re_insert( uint a ) {
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  assert( _is_square, "only on square" );
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  assert( _yanked->test(a), "" );
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  (*_yanked) >>= a;
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  IndexSetIterator elements(&_adjs[a]);
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  uint datum;
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  while ((datum = elements.next()) != 0) {
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    _adjs[datum].insert(a);
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    lrgs(datum).invalid_degree();
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  }
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}
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// Compute the degree between 2 live ranges.  If both live ranges are
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// aligned-adjacent powers-of-2 then we use the MAX size.  If either is
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// mis-aligned (or for Fat-Projections, not-adjacent) then we have to
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// MULTIPLY the sizes.  Inspect Brigg's thesis on register pairs to see why
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// this is so.
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int LRG::compute_degree( LRG &l ) const {
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  int tmp;
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  int num_regs = _num_regs;
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  int nregs = l.num_regs();
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  tmp =  (_fat_proj || l._fat_proj)     // either is a fat-proj?
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    ? (num_regs * nregs)                // then use product
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    : MAX2(num_regs,nregs);             // else use max
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  return tmp;
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}
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// Compute effective degree for this live range.  If both live ranges are
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// aligned-adjacent powers-of-2 then we use the MAX size.  If either is
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// mis-aligned (or for Fat-Projections, not-adjacent) then we have to
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// MULTIPLY the sizes.  Inspect Brigg's thesis on register pairs to see why
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// this is so.
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int PhaseIFG::effective_degree( uint lidx ) const {
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  int eff = 0;
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  int num_regs = lrgs(lidx).num_regs();
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  int fat_proj = lrgs(lidx)._fat_proj;
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  IndexSet *s = neighbors(lidx);
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  IndexSetIterator elements(s);
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  uint nidx;
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  while((nidx = elements.next()) != 0) {
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    LRG &lrgn = lrgs(nidx);
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    int nregs = lrgn.num_regs();
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    eff += (fat_proj || lrgn._fat_proj) // either is a fat-proj?
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      ? (num_regs * nregs)              // then use product
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      : MAX2(num_regs,nregs);           // else use max
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  }
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  return eff;
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}
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#ifndef PRODUCT
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void PhaseIFG::dump() const {
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  tty->print_cr("-- Interference Graph --%s--",
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                _is_square ? "square" : "triangular" );
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  if( _is_square ) {
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    for( uint i = 0; i < _maxlrg; i++ ) {
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      tty->print( (*_yanked)[i] ? "XX " : "  ");
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      tty->print("L%d: { ",i);
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      IndexSetIterator elements(&_adjs[i]);
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      uint datum;
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      while ((datum = elements.next()) != 0) {
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        tty->print("L%d ", datum);
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      }
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      tty->print_cr("}");
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    }
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    return;
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  }
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  // Triangular
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  for( uint i = 0; i < _maxlrg; i++ ) {
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    uint j;
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    tty->print( (*_yanked)[i] ? "XX " : "  ");
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    tty->print("L%d: { ",i);
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    for( j = _maxlrg; j > i; j-- )
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      if( test_edge(j - 1,i) ) {
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        tty->print("L%d ",j - 1);
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      }
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    tty->print("| ");
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    IndexSetIterator elements(&_adjs[i]);
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    uint datum;
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    while ((datum = elements.next()) != 0) {
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      tty->print("L%d ", datum);
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    }
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    tty->print("}\n");
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  }
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  tty->print("\n");
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}
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void PhaseIFG::stats() const {
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  ResourceMark rm;
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  int *h_cnt = NEW_RESOURCE_ARRAY(int,_maxlrg*2);
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  memset( h_cnt, 0, sizeof(int)*_maxlrg*2 );
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  uint i;
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  for( i = 0; i < _maxlrg; i++ ) {
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    h_cnt[neighbor_cnt(i)]++;
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  }
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  tty->print_cr("--Histogram of counts--");
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  for( i = 0; i < _maxlrg*2; i++ )
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    if( h_cnt[i] )
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      tty->print("%d/%d ",i,h_cnt[i]);
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  tty->print_cr("");
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}
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void PhaseIFG::verify( const PhaseChaitin *pc ) const {
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  // IFG is square, sorted and no need for Find
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  for( uint i = 0; i < _maxlrg; i++ ) {
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    assert(!((*_yanked)[i]) || !neighbor_cnt(i), "Is removed completely" );
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    IndexSet *set = &_adjs[i];
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    IndexSetIterator elements(set);
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    uint idx;
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    uint last = 0;
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    while ((idx = elements.next()) != 0) {
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      assert(idx != i, "Must have empty diagonal");
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      assert(pc->_lrg_map.find_const(idx) == idx, "Must not need Find");
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      assert(_adjs[idx].member(i), "IFG not square");
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      assert(!(*_yanked)[idx], "No yanked neighbors");
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      assert(last < idx, "not sorted increasing");
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      last = idx;
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    }
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    assert(!lrgs(i)._degree_valid || effective_degree(i) == lrgs(i).degree(), "degree is valid but wrong");
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  }
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}
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#endif
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// Interfere this register with everything currently live.  Use the RegMasks
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// to trim the set of possible interferences. Return a count of register-only
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// interferences as an estimate of register pressure.
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void PhaseChaitin::interfere_with_live( uint r, IndexSet *liveout ) {
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  uint retval = 0;
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  // Interfere with everything live.
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  const RegMask &rm = lrgs(r).mask();
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  // Check for interference by checking overlap of regmasks.
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  // Only interfere if acceptable register masks overlap.
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  IndexSetIterator elements(liveout);
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  uint l;
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  while( (l = elements.next()) != 0 )
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    if( rm.overlap( lrgs(l).mask() ) )
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      _ifg->add_edge( r, l );
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}
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// Actually build the interference graph.  Uses virtual registers only, no
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// physical register masks.  This allows me to be very aggressive when
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// coalescing copies.  Some of this aggressiveness will have to be undone
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// later, but I'd rather get all the copies I can now (since unremoved copies
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// at this point can end up in bad places).  Copies I re-insert later I have
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// more opportunity to insert them in low-frequency locations.
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void PhaseChaitin::build_ifg_virtual( ) {
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  // For all blocks (in any order) do...
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  for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
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    Block* block = _cfg.get_block(i);
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    IndexSet* liveout = _live->live(block);
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    // The IFG is built by a single reverse pass over each basic block.
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    // Starting with the known live-out set, we remove things that get
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    // defined and add things that become live (essentially executing one
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    // pass of a standard LIVE analysis). Just before a Node defines a value
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    // (and removes it from the live-ness set) that value is certainly live.
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    // The defined value interferes with everything currently live.  The
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    // value is then removed from the live-ness set and it's inputs are
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    // added to the live-ness set.
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    for (uint j = block->end_idx() + 1; j > 1; j--) {
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      Node* n = block->get_node(j - 1);
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      // Get value being defined
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      uint r = _lrg_map.live_range_id(n);
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      // Some special values do not allocate
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      if (r) {
1
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        // Remove from live-out set
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        liveout->remove(r);
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        // Copies do not define a new value and so do not interfere.
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        // Remove the copies source from the liveout set before interfering.
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        uint idx = n->is_Copy();
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        if (idx) {
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          liveout->remove(_lrg_map.live_range_id(n->in(idx)));
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        }
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        // Interfere with everything live
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        interfere_with_live(r, liveout);
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      }
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      // Make all inputs live
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      if (!n->is_Phi()) {      // Phi function uses come from prior block
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        for(uint k = 1; k < n->req(); k++) {
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          liveout->insert(_lrg_map.live_range_id(n->in(k)));
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        }
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      }
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      // 2-address instructions always have the defined value live
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      // on entry to the instruction, even though it is being defined
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      // by the instruction.  We pretend a virtual copy sits just prior
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      // to the instruction and kills the src-def'd register.
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      // In other words, for 2-address instructions the defined value
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      // interferes with all inputs.
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      uint idx;
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      if( n->is_Mach() && (idx = n->as_Mach()->two_adr()) ) {
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        const MachNode *mach = n->as_Mach();
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        // Sometimes my 2-address ADDs are commuted in a bad way.
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        // We generally want the USE-DEF register to refer to the
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        // loop-varying quantity, to avoid a copy.
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   363
        uint op = mach->ideal_Opcode();
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        // Check that mach->num_opnds() == 3 to ensure instruction is
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        // not subsuming constants, effectively excludes addI_cin_imm
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        // Can NOT swap for instructions like addI_cin_imm since it
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        // is adding zero to yhi + carry and the second ideal-input
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        // points to the result of adding low-halves.
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        // Checking req() and num_opnds() does NOT distinguish addI_cout from addI_cout_imm
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        if( (op == Op_AddI && mach->req() == 3 && mach->num_opnds() == 3) &&
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            n->in(1)->bottom_type()->base() == Type::Int &&
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            // See if the ADD is involved in a tight data loop the wrong way
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            n->in(2)->is_Phi() &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   374
            n->in(2)->in(2) == n ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   375
          Node *tmp = n->in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   376
          n->set_req( 1, n->in(2) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   377
          n->set_req( 2, tmp );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   378
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   379
        // Defined value interferes with all inputs
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 16618
diff changeset
   380
        uint lidx = _lrg_map.live_range_id(n->in(idx));
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 16618
diff changeset
   381
        for (uint k = 1; k < n->req(); k++) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 16618
diff changeset
   382
          uint kidx = _lrg_map.live_range_id(n->in(k));
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 16618
diff changeset
   383
          if (kidx != lidx) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 16618
diff changeset
   384
            _ifg->add_edge(r, kidx);
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 16618
diff changeset
   385
          }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   386
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   387
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   388
    } // End of forall instructions in block
489c9b5090e2 Initial load
duke
parents:
diff changeset
   389
  } // End of forall blocks
489c9b5090e2 Initial load
duke
parents:
diff changeset
   390
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   391
489c9b5090e2 Initial load
duke
parents:
diff changeset
   392
uint PhaseChaitin::count_int_pressure( IndexSet *liveout ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   393
  IndexSetIterator elements(liveout);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   394
  uint lidx;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   395
  uint cnt = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   396
  while ((lidx = elements.next()) != 0) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   397
    if( lrgs(lidx).mask().is_UP() &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   398
        lrgs(lidx).mask_size() &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   399
        !lrgs(lidx)._is_float &&
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 7397
diff changeset
   400
        !lrgs(lidx)._is_vector &&
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   401
        lrgs(lidx).mask().overlap(*Matcher::idealreg2regmask[Op_RegI]) )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   402
      cnt += lrgs(lidx).reg_pressure();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   403
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   404
  return cnt;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   405
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   406
489c9b5090e2 Initial load
duke
parents:
diff changeset
   407
uint PhaseChaitin::count_float_pressure( IndexSet *liveout ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   408
  IndexSetIterator elements(liveout);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   409
  uint lidx;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   410
  uint cnt = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   411
  while ((lidx = elements.next()) != 0) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   412
    if( lrgs(lidx).mask().is_UP() &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   413
        lrgs(lidx).mask_size() &&
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 7397
diff changeset
   414
        (lrgs(lidx)._is_float || lrgs(lidx)._is_vector))
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   415
      cnt += lrgs(lidx).reg_pressure();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   416
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   417
  return cnt;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   418
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   419
489c9b5090e2 Initial load
duke
parents:
diff changeset
   420
// Adjust register pressure down by 1.  Capture last hi-to-low transition,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   421
static void lower_pressure( LRG *lrg, uint where, Block *b, uint *pressure, uint *hrp_index ) {
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 7397
diff changeset
   422
  if (lrg->mask().is_UP() && lrg->mask_size()) {
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 7397
diff changeset
   423
    if (lrg->_is_float || lrg->_is_vector) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   424
      pressure[1] -= lrg->reg_pressure();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   425
      if( pressure[1] == (uint)FLOATPRESSURE ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   426
        hrp_index[1] = where;
16618
0d73b54bf055 8010281: Remove code that is never executed
neliasso
parents: 14623
diff changeset
   427
        if( pressure[1] > b->_freg_pressure )
0d73b54bf055 8010281: Remove code that is never executed
neliasso
parents: 14623
diff changeset
   428
          b->_freg_pressure = pressure[1]+1;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   429
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   430
    } else if( lrg->mask().overlap(*Matcher::idealreg2regmask[Op_RegI]) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   431
      pressure[0] -= lrg->reg_pressure();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   432
      if( pressure[0] == (uint)INTPRESSURE   ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   433
        hrp_index[0] = where;
16618
0d73b54bf055 8010281: Remove code that is never executed
neliasso
parents: 14623
diff changeset
   434
        if( pressure[0] > b->_reg_pressure )
0d73b54bf055 8010281: Remove code that is never executed
neliasso
parents: 14623
diff changeset
   435
          b->_reg_pressure = pressure[0]+1;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   436
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   437
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   438
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   439
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   440
489c9b5090e2 Initial load
duke
parents:
diff changeset
   441
// Build the interference graph using physical registers when available.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   442
// That is, if 2 live ranges are simultaneously alive but in their acceptable
489c9b5090e2 Initial load
duke
parents:
diff changeset
   443
// register sets do not overlap, then they do not interfere.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   444
uint PhaseChaitin::build_ifg_physical( ResourceArea *a ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   445
  NOT_PRODUCT( Compile::TracePhase t3("buildIFG", &_t_buildIFGphysical, TimeCompiler); )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   446
489c9b5090e2 Initial load
duke
parents:
diff changeset
   447
  uint must_spill = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   448
489c9b5090e2 Initial load
duke
parents:
diff changeset
   449
  // For all blocks (in any order) do...
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   450
  for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   451
    Block* block = _cfg.get_block(i);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   452
    // Clone (rather than smash in place) the liveout info, so it is alive
489c9b5090e2 Initial load
duke
parents:
diff changeset
   453
    // for the "collect_gc_info" phase later.
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   454
    IndexSet liveout(_live->live(block));
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   455
    uint last_inst = block->end_idx();
2030
39d55e4534b4 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents: 1412
diff changeset
   456
    // Compute first nonphi node index
39d55e4534b4 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents: 1412
diff changeset
   457
    uint first_inst;
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   458
    for (first_inst = 1; first_inst < last_inst; first_inst++) {
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19330
diff changeset
   459
      if (!block->get_node(first_inst)->is_Phi()) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   460
        break;
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   461
      }
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   462
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   463
2030
39d55e4534b4 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents: 1412
diff changeset
   464
    // Spills could be inserted before CreateEx node which should be
39d55e4534b4 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents: 1412
diff changeset
   465
    // first instruction in block after Phis. Move CreateEx up.
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   466
    for (uint insidx = first_inst; insidx < last_inst; insidx++) {
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19330
diff changeset
   467
      Node *ex = block->get_node(insidx);
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   468
      if (ex->is_SpillCopy()) {
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   469
        continue;
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   470
      }
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   471
      if (insidx > first_inst && ex->is_Mach() && ex->as_Mach()->ideal_Opcode() == Op_CreateEx) {
2030
39d55e4534b4 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents: 1412
diff changeset
   472
        // If the CreateEx isn't above all the MachSpillCopies
39d55e4534b4 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents: 1412
diff changeset
   473
        // then move it to the top.
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19330
diff changeset
   474
        block->remove_node(insidx);
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19330
diff changeset
   475
        block->insert_node(ex, first_inst);
2030
39d55e4534b4 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents: 1412
diff changeset
   476
      }
39d55e4534b4 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents: 1412
diff changeset
   477
      // Stop once a CreateEx or any other node is found
39d55e4534b4 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents: 1412
diff changeset
   478
      break;
39d55e4534b4 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents: 1412
diff changeset
   479
    }
39d55e4534b4 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents: 1412
diff changeset
   480
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   481
    // Reset block's register pressure values for each ifg construction
489c9b5090e2 Initial load
duke
parents:
diff changeset
   482
    uint pressure[2], hrp_index[2];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   483
    pressure[0] = pressure[1] = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   484
    hrp_index[0] = hrp_index[1] = last_inst+1;
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   485
    block->_reg_pressure = block->_freg_pressure = 0;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   486
    // Liveout things are presumed live for the whole block.  We accumulate
489c9b5090e2 Initial load
duke
parents:
diff changeset
   487
    // 'area' accordingly.  If they get killed in the block, we'll subtract
489c9b5090e2 Initial load
duke
parents:
diff changeset
   488
    // the unused part of the block from the area.
2030
39d55e4534b4 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents: 1412
diff changeset
   489
    int inst_count = last_inst - first_inst;
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   490
    double cost = (inst_count <= 0) ? 0.0 : block->_freq * double(inst_count);
1401
e5fdc8521d1f 6750588: assert(lrg._area >= 0,"negative spill area") running NSK stmp0101 test
rasbold
parents: 1057
diff changeset
   491
    assert(!(cost < 0.0), "negative spill cost" );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   492
    IndexSetIterator elements(&liveout);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   493
    uint lidx;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   494
    while ((lidx = elements.next()) != 0) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   495
      LRG &lrg = lrgs(lidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   496
      lrg._area += cost;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   497
      // Compute initial register pressure
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 7397
diff changeset
   498
      if (lrg.mask().is_UP() && lrg.mask_size()) {
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 7397
diff changeset
   499
        if (lrg._is_float || lrg._is_vector) {   // Count float pressure
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   500
          pressure[1] += lrg.reg_pressure();
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   501
          if (pressure[1] > block->_freg_pressure) {
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   502
            block->_freg_pressure = pressure[1];
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   503
          }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   504
          // Count int pressure, but do not count the SP, flags
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   505
        } else if(lrgs(lidx).mask().overlap(*Matcher::idealreg2regmask[Op_RegI])) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   506
          pressure[0] += lrg.reg_pressure();
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   507
          if (pressure[0] > block->_reg_pressure) {
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   508
            block->_reg_pressure = pressure[0];
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   509
          }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   510
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   511
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   512
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   513
    assert( pressure[0] == count_int_pressure  (&liveout), "" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   514
    assert( pressure[1] == count_float_pressure(&liveout), "" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   515
489c9b5090e2 Initial load
duke
parents:
diff changeset
   516
    // The IFG is built by a single reverse pass over each basic block.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   517
    // Starting with the known live-out set, we remove things that get
489c9b5090e2 Initial load
duke
parents:
diff changeset
   518
    // defined and add things that become live (essentially executing one
489c9b5090e2 Initial load
duke
parents:
diff changeset
   519
    // pass of a standard LIVE analysis).  Just before a Node defines a value
489c9b5090e2 Initial load
duke
parents:
diff changeset
   520
    // (and removes it from the live-ness set) that value is certainly live.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   521
    // The defined value interferes with everything currently live.  The
489c9b5090e2 Initial load
duke
parents:
diff changeset
   522
    // value is then removed from the live-ness set and it's inputs are added
489c9b5090e2 Initial load
duke
parents:
diff changeset
   523
    // to the live-ness set.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   524
    uint j;
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   525
    for (j = last_inst + 1; j > 1; j--) {
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19330
diff changeset
   526
      Node* n = block->get_node(j - 1);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   527
489c9b5090e2 Initial load
duke
parents:
diff changeset
   528
      // Get value being defined
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 16618
diff changeset
   529
      uint r = _lrg_map.live_range_id(n);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   530
489c9b5090e2 Initial load
duke
parents:
diff changeset
   531
      // Some special values do not allocate
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 16618
diff changeset
   532
      if(r) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   533
        // A DEF normally costs block frequency; rematerialized values are
489c9b5090e2 Initial load
duke
parents:
diff changeset
   534
        // removed from the DEF sight, so LOWER costs here.
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   535
        lrgs(r)._cost += n->rematerialize() ? 0 : block->_freq;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   536
489c9b5090e2 Initial load
duke
parents:
diff changeset
   537
        // If it is not live, then this instruction is dead.  Probably caused
489c9b5090e2 Initial load
duke
parents:
diff changeset
   538
        // by spilling and rematerialization.  Who cares why, yank this baby.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   539
        if( !liveout.member(r) && n->Opcode() != Op_SafePoint ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   540
          Node *def = n->in(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   541
          if( !n->is_Proj() ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
   542
              // Could also be a flags-projection of a dead ADD or such.
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 16618
diff changeset
   543
              (_lrg_map.live_range_id(def) && !liveout.member(_lrg_map.live_range_id(def)))) {
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19330
diff changeset
   544
            block->remove_node(j - 1);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 16618
diff changeset
   545
            if (lrgs(r)._def == n) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 16618
diff changeset
   546
              lrgs(r)._def = 0;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 16618
diff changeset
   547
            }
14623
70c4c1be0a14 7092905: C2: Keep track of the number of dead nodes
bharadwaj
parents: 13104
diff changeset
   548
            n->disconnect_inputs(NULL, C);
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 17013
diff changeset
   549
            _cfg.unmap_node_from_block(n);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   550
            n->replace_by(C->top());
489c9b5090e2 Initial load
duke
parents:
diff changeset
   551
            // Since yanking a Node from block, high pressure moves up one
489c9b5090e2 Initial load
duke
parents:
diff changeset
   552
            hrp_index[0]--;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   553
            hrp_index[1]--;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   554
            continue;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   555
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   556
489c9b5090e2 Initial load
duke
parents:
diff changeset
   557
          // Fat-projections kill many registers which cannot be used to
489c9b5090e2 Initial load
duke
parents:
diff changeset
   558
          // hold live ranges.
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 16618
diff changeset
   559
          if (lrgs(r)._fat_proj) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   560
            // Count the int-only registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
   561
            RegMask itmp = lrgs(r).mask();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   562
            itmp.AND(*Matcher::idealreg2regmask[Op_RegI]);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   563
            int iregs = itmp.Size();
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   564
            if (pressure[0]+iregs > block->_reg_pressure) {
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   565
              block->_reg_pressure = pressure[0] + iregs;
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   566
            }
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   567
            if (pressure[0] <= (uint)INTPRESSURE && pressure[0] + iregs > (uint)INTPRESSURE) {
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   568
              hrp_index[0] = j - 1;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   569
            }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   570
            // Count the float-only registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
   571
            RegMask ftmp = lrgs(r).mask();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   572
            ftmp.AND(*Matcher::idealreg2regmask[Op_RegD]);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   573
            int fregs = ftmp.Size();
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   574
            if (pressure[1] + fregs > block->_freg_pressure) {
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   575
              block->_freg_pressure = pressure[1] + fregs;
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   576
            }
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   577
            if(pressure[1] <= (uint)FLOATPRESSURE && pressure[1]+fregs > (uint)FLOATPRESSURE) {
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   578
              hrp_index[1] = j - 1;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   579
            }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   580
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   581
489c9b5090e2 Initial load
duke
parents:
diff changeset
   582
        } else {                // Else it is live
489c9b5090e2 Initial load
duke
parents:
diff changeset
   583
          // A DEF also ends 'area' partway through the block.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   584
          lrgs(r)._area -= cost;
1401
e5fdc8521d1f 6750588: assert(lrg._area >= 0,"negative spill area") running NSK stmp0101 test
rasbold
parents: 1057
diff changeset
   585
          assert(!(lrgs(r)._area < 0.0), "negative spill area" );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   586
489c9b5090e2 Initial load
duke
parents:
diff changeset
   587
          // Insure high score for immediate-use spill copies so they get a color
489c9b5090e2 Initial load
duke
parents:
diff changeset
   588
          if( n->is_SpillCopy()
1057
44220ef9a775 6732194: Data corruption dependent on -server/-client/-Xbatch
never
parents: 1
diff changeset
   589
              && lrgs(r).is_singledef()        // MultiDef live range can still split
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   590
              && n->outcnt() == 1              // and use must be in this block
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   591
              && _cfg.get_block_for_node(n->unique_out()) == block) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   592
            // All single-use MachSpillCopy(s) that immediately precede their
489c9b5090e2 Initial load
duke
parents:
diff changeset
   593
            // use must color early.  If a longer live range steals their
489c9b5090e2 Initial load
duke
parents:
diff changeset
   594
            // color, the spill copy will split and may push another spill copy
489c9b5090e2 Initial load
duke
parents:
diff changeset
   595
            // further away resulting in an infinite spill-split-retry cycle.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   596
            // Assigning a zero area results in a high score() and a good
489c9b5090e2 Initial load
duke
parents:
diff changeset
   597
            // location in the simplify list.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   598
            //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   599
489c9b5090e2 Initial load
duke
parents:
diff changeset
   600
            Node *single_use = n->unique_out();
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   601
            assert(block->find_node(single_use) >= j, "Use must be later in block");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   602
            // Use can be earlier in block if it is a Phi, but then I should be a MultiDef
489c9b5090e2 Initial load
duke
parents:
diff changeset
   603
489c9b5090e2 Initial load
duke
parents:
diff changeset
   604
            // Find first non SpillCopy 'm' that follows the current instruction
489c9b5090e2 Initial load
duke
parents:
diff changeset
   605
            // (j - 1) is index for current instruction 'n'
489c9b5090e2 Initial load
duke
parents:
diff changeset
   606
            Node *m = n;
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   607
            for (uint i = j; i <= last_inst && m->is_SpillCopy(); ++i) {
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19330
diff changeset
   608
              m = block->get_node(i);
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   609
            }
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   610
            if (m == single_use) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   611
              lrgs(r)._area = 0.0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   612
            }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   613
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   614
489c9b5090e2 Initial load
duke
parents:
diff changeset
   615
          // Remove from live-out set
489c9b5090e2 Initial load
duke
parents:
diff changeset
   616
          if( liveout.remove(r) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   617
            // Adjust register pressure.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   618
            // Capture last hi-to-lo pressure transition
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   619
            lower_pressure(&lrgs(r), j - 1, block, pressure, hrp_index);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   620
            assert( pressure[0] == count_int_pressure  (&liveout), "" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   621
            assert( pressure[1] == count_float_pressure(&liveout), "" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   622
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   623
489c9b5090e2 Initial load
duke
parents:
diff changeset
   624
          // Copies do not define a new value and so do not interfere.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   625
          // Remove the copies source from the liveout set before interfering.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   626
          uint idx = n->is_Copy();
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 16618
diff changeset
   627
          if (idx) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 16618
diff changeset
   628
            uint x = _lrg_map.live_range_id(n->in(idx));
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 16618
diff changeset
   629
            if (liveout.remove(x)) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   630
              lrgs(x)._area -= cost;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   631
              // Adjust register pressure.
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   632
              lower_pressure(&lrgs(x), j - 1, block, pressure, hrp_index);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   633
              assert( pressure[0] == count_int_pressure  (&liveout), "" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   634
              assert( pressure[1] == count_float_pressure(&liveout), "" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   635
            }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   636
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   637
        } // End of if live or not
489c9b5090e2 Initial load
duke
parents:
diff changeset
   638
489c9b5090e2 Initial load
duke
parents:
diff changeset
   639
        // Interfere with everything live.  If the defined value must
489c9b5090e2 Initial load
duke
parents:
diff changeset
   640
        // go in a particular register, just remove that register from
489c9b5090e2 Initial load
duke
parents:
diff changeset
   641
        // all conflicting parties and avoid the interference.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   642
489c9b5090e2 Initial load
duke
parents:
diff changeset
   643
        // Make exclusions for rematerializable defs.  Since rematerializable
489c9b5090e2 Initial load
duke
parents:
diff changeset
   644
        // DEFs are not bound but the live range is, some uses must be bound.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   645
        // If we spill live range 'r', it can rematerialize at each use site
489c9b5090e2 Initial load
duke
parents:
diff changeset
   646
        // according to its bindings.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   647
        const RegMask &rmask = lrgs(r).mask();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   648
        if( lrgs(r).is_bound() && !(n->rematerialize()) && rmask.is_NotEmpty() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   649
          // Check for common case
489c9b5090e2 Initial load
duke
parents:
diff changeset
   650
          int r_size = lrgs(r).num_regs();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   651
          OptoReg::Name r_reg = (r_size == 1) ? rmask.find_first_elem() : OptoReg::Physical;
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 7397
diff changeset
   652
          // Smear odd bits
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   653
          IndexSetIterator elements(&liveout);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   654
          uint l;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   655
          while ((l = elements.next()) != 0) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   656
            LRG &lrg = lrgs(l);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   657
            // If 'l' must spill already, do not further hack his bits.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   658
            // He'll get some interferences and be forced to spill later.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   659
            if( lrg._must_spill ) continue;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   660
            // Remove bound register(s) from 'l's choices
489c9b5090e2 Initial load
duke
parents:
diff changeset
   661
            RegMask old = lrg.mask();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   662
            uint old_size = lrg.mask_size();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   663
            // Remove the bits from LRG 'r' from LRG 'l' so 'l' no
489c9b5090e2 Initial load
duke
parents:
diff changeset
   664
            // longer interferes with 'r'.  If 'l' requires aligned
489c9b5090e2 Initial load
duke
parents:
diff changeset
   665
            // adjacent pairs, subtract out bit pairs.
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 7397
diff changeset
   666
            assert(!lrg._is_vector || !lrg._fat_proj, "sanity");
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 7397
diff changeset
   667
            if (lrg.num_regs() > 1 && !lrg._fat_proj) {
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 7397
diff changeset
   668
              RegMask r2mask = rmask;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 7397
diff changeset
   669
              // Leave only aligned set of bits.
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 7397
diff changeset
   670
              r2mask.smear_to_sets(lrg.num_regs());
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 7397
diff changeset
   671
              // It includes vector case.
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   672
              lrg.SUBTRACT( r2mask );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   673
              lrg.compute_set_mask_size();
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 7397
diff changeset
   674
            } else if( r_size != 1 ) { // fat proj
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   675
              lrg.SUBTRACT( rmask );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   676
              lrg.compute_set_mask_size();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   677
            } else {            // Common case: size 1 bound removal
489c9b5090e2 Initial load
duke
parents:
diff changeset
   678
              if( lrg.mask().Member(r_reg) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   679
                lrg.Remove(r_reg);
20704
b689a120e974 8011415: CTW on Sparc: assert(lrg.lo_degree()) failed:
adlertz
parents: 19717
diff changeset
   680
                lrg.set_mask_size(lrg.mask().is_AllStack() ? LRG::AllStack_size : old_size - 1);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   681
              }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   682
            }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   683
            // If 'l' goes completely dry, it must spill.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   684
            if( lrg.not_free() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   685
              // Give 'l' some kind of reasonable mask, so he picks up
489c9b5090e2 Initial load
duke
parents:
diff changeset
   686
              // interferences (and will spill later).
489c9b5090e2 Initial load
duke
parents:
diff changeset
   687
              lrg.set_mask( old );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   688
              lrg.set_mask_size(old_size);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   689
              must_spill++;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   690
              lrg._must_spill = 1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   691
              lrg.set_reg(OptoReg::Name(LRG::SPILL_REG));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   692
            }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   693
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   694
        } // End of if bound
489c9b5090e2 Initial load
duke
parents:
diff changeset
   695
489c9b5090e2 Initial load
duke
parents:
diff changeset
   696
        // Now interference with everything that is live and has
489c9b5090e2 Initial load
duke
parents:
diff changeset
   697
        // compatible register sets.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   698
        interfere_with_live(r,&liveout);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   699
489c9b5090e2 Initial load
duke
parents:
diff changeset
   700
      } // End of if normal register-allocated value
489c9b5090e2 Initial load
duke
parents:
diff changeset
   701
1401
e5fdc8521d1f 6750588: assert(lrg._area >= 0,"negative spill area") running NSK stmp0101 test
rasbold
parents: 1057
diff changeset
   702
      // Area remaining in the block
e5fdc8521d1f 6750588: assert(lrg._area >= 0,"negative spill area") running NSK stmp0101 test
rasbold
parents: 1057
diff changeset
   703
      inst_count--;
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   704
      cost = (inst_count <= 0) ? 0.0 : block->_freq * double(inst_count);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   705
489c9b5090e2 Initial load
duke
parents:
diff changeset
   706
      // Make all inputs live
489c9b5090e2 Initial load
duke
parents:
diff changeset
   707
      if( !n->is_Phi() ) {      // Phi function uses come from prior block
489c9b5090e2 Initial load
duke
parents:
diff changeset
   708
        JVMState* jvms = n->jvms();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   709
        uint debug_start = jvms ? jvms->debug_start() : 999999;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   710
        // Start loop at 1 (skip control edge) for most Nodes.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   711
        // SCMemProj's might be the sole use of a StoreLConditional.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   712
        // While StoreLConditionals set memory (the SCMemProj use)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   713
        // they also def flags; if that flag def is unused the
489c9b5090e2 Initial load
duke
parents:
diff changeset
   714
        // allocator sees a flag-setting instruction with no use of
489c9b5090e2 Initial load
duke
parents:
diff changeset
   715
        // the flags and assumes it's dead.  This keeps the (useless)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   716
        // flag-setting behavior alive while also keeping the (useful)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   717
        // memory update effect.
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 16618
diff changeset
   718
        for (uint k = ((n->Opcode() == Op_SCMemProj) ? 0:1); k < n->req(); k++) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   719
          Node *def = n->in(k);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 16618
diff changeset
   720
          uint x = _lrg_map.live_range_id(def);
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 16618
diff changeset
   721
          if (!x) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 16618
diff changeset
   722
            continue;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 16618
diff changeset
   723
          }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   724
          LRG &lrg = lrgs(x);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   725
          // No use-side cost for spilling debug info
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 16618
diff changeset
   726
          if (k < debug_start) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   727
            // A USE costs twice block frequency (once for the Load, once
489c9b5090e2 Initial load
duke
parents:
diff changeset
   728
            // for a Load-delay).  Rematerialized uses only cost once.
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   729
            lrg._cost += (def->rematerialize() ? block->_freq : (block->_freq + block->_freq));
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 16618
diff changeset
   730
          }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   731
          // It is live now
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 16618
diff changeset
   732
          if (liveout.insert(x)) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   733
            // Newly live things assumed live from here to top of block
489c9b5090e2 Initial load
duke
parents:
diff changeset
   734
            lrg._area += cost;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   735
            // Adjust register pressure
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 7397
diff changeset
   736
            if (lrg.mask().is_UP() && lrg.mask_size()) {
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 7397
diff changeset
   737
              if (lrg._is_float || lrg._is_vector) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   738
                pressure[1] += lrg.reg_pressure();
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   739
                if (pressure[1] > block->_freg_pressure)  {
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   740
                  block->_freg_pressure = pressure[1];
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   741
                }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   742
              } else if( lrg.mask().overlap(*Matcher::idealreg2regmask[Op_RegI]) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   743
                pressure[0] += lrg.reg_pressure();
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   744
                if (pressure[0] > block->_reg_pressure) {
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   745
                  block->_reg_pressure = pressure[0];
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   746
                }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   747
              }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   748
            }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   749
            assert( pressure[0] == count_int_pressure  (&liveout), "" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   750
            assert( pressure[1] == count_float_pressure(&liveout), "" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   751
          }
1401
e5fdc8521d1f 6750588: assert(lrg._area >= 0,"negative spill area") running NSK stmp0101 test
rasbold
parents: 1057
diff changeset
   752
          assert(!(lrg._area < 0.0), "negative spill area" );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   753
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   754
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   755
    } // End of reverse pass over all instructions in block
489c9b5090e2 Initial load
duke
parents:
diff changeset
   756
489c9b5090e2 Initial load
duke
parents:
diff changeset
   757
    // If we run off the top of the block with high pressure and
489c9b5090e2 Initial load
duke
parents:
diff changeset
   758
    // never see a hi-to-low pressure transition, just record that
489c9b5090e2 Initial load
duke
parents:
diff changeset
   759
    // the whole block is high pressure.
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   760
    if (pressure[0] > (uint)INTPRESSURE) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   761
      hrp_index[0] = 0;
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   762
      if (pressure[0] > block->_reg_pressure) {
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   763
        block->_reg_pressure = pressure[0];
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   764
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   765
    }
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   766
    if (pressure[1] > (uint)FLOATPRESSURE) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   767
      hrp_index[1] = 0;
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   768
      if (pressure[1] > block->_freg_pressure) {
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   769
        block->_freg_pressure = pressure[1];
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   770
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   771
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   772
489c9b5090e2 Initial load
duke
parents:
diff changeset
   773
    // Compute high pressure indice; avoid landing in the middle of projnodes
489c9b5090e2 Initial load
duke
parents:
diff changeset
   774
    j = hrp_index[0];
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19330
diff changeset
   775
    if (j < block->number_of_nodes() && j < block->end_idx() + 1) {
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19330
diff changeset
   776
      Node* cur = block->get_node(j);
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   777
      while (cur->is_Proj() || (cur->is_MachNullCheck()) || cur->is_Catch()) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   778
        j--;
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19330
diff changeset
   779
        cur = block->get_node(j);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   780
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   781
    }
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   782
    block->_ihrp_index = j;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   783
    j = hrp_index[1];
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19330
diff changeset
   784
    if (j < block->number_of_nodes() && j < block->end_idx() + 1) {
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19330
diff changeset
   785
      Node* cur = block->get_node(j);
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   786
      while (cur->is_Proj() || (cur->is_MachNullCheck()) || cur->is_Catch()) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   787
        j--;
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19330
diff changeset
   788
        cur = block->get_node(j);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   789
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   790
    }
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   791
    block->_fhrp_index = j;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   792
489c9b5090e2 Initial load
duke
parents:
diff changeset
   793
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   794
    // Gather Register Pressure Statistics
489c9b5090e2 Initial load
duke
parents:
diff changeset
   795
    if( PrintOptoStatistics ) {
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   796
      if (block->_reg_pressure > (uint)INTPRESSURE || block->_freg_pressure > (uint)FLOATPRESSURE) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   797
        _high_pressure++;
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   798
      } else {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   799
        _low_pressure++;
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   800
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   801
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   802
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   803
  } // End of for all blocks
489c9b5090e2 Initial load
duke
parents:
diff changeset
   804
489c9b5090e2 Initial load
duke
parents:
diff changeset
   805
  return must_spill;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   806
}