author | kvn |
Wed, 01 May 2019 12:31:29 -0700 | |
changeset 54669 | ad45b3802d4e |
parent 47562 | f789ccebcfe4 |
permissions | -rw-r--r-- |
43972 | 1 |
/* |
54669
ad45b3802d4e
8220623: [JVMCI] Update JVMCI to support JVMCI based Compiler compiled into shared library
kvn
parents:
47562
diff
changeset
|
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* Copyright (c) 2013, 2019, Oracle and/or its affiliates. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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*/ |
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package jdk.vm.ci.sparc; |
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import static java.nio.ByteOrder.BIG_ENDIAN; |
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import static jdk.vm.ci.code.MemoryBarriers.LOAD_LOAD; |
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import static jdk.vm.ci.code.MemoryBarriers.LOAD_STORE; |
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import static jdk.vm.ci.code.MemoryBarriers.STORE_STORE; |
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import java.util.Set; |
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import jdk.vm.ci.code.Architecture; |
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import jdk.vm.ci.code.Register; |
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import jdk.vm.ci.code.Register.RegisterCategory; |
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import jdk.vm.ci.code.RegisterArray; |
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import jdk.vm.ci.meta.JavaKind; |
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import jdk.vm.ci.meta.PlatformKind; |
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/** |
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* Represents the SPARC architecture. |
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*/ |
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public class SPARC extends Architecture { |
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public static final RegisterCategory CPU = new RegisterCategory("CPU"); |
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public static final RegisterCategory FPUs = new RegisterCategory("FPUs"); |
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public static final RegisterCategory FPUd = new RegisterCategory("FPUd"); |
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public static final RegisterCategory FPUq = new RegisterCategory("FPUq"); |
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// General purpose registers |
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public static final Register g0 = new Register(0, 0, "g0", CPU); |
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public static final Register g1 = new Register(1, 1, "g1", CPU); |
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public static final Register g2 = new Register(2, 2, "g2", CPU); |
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public static final Register g3 = new Register(3, 3, "g3", CPU); |
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public static final Register g4 = new Register(4, 4, "g4", CPU); |
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public static final Register g5 = new Register(5, 5, "g5", CPU); |
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public static final Register g6 = new Register(6, 6, "g6", CPU); |
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public static final Register g7 = new Register(7, 7, "g7", CPU); |
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public static final Register o0 = new Register(8, 8, "o0", CPU); |
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public static final Register o1 = new Register(9, 9, "o1", CPU); |
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public static final Register o2 = new Register(10, 10, "o2", CPU); |
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public static final Register o3 = new Register(11, 11, "o3", CPU); |
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public static final Register o4 = new Register(12, 12, "o4", CPU); |
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public static final Register o5 = new Register(13, 13, "o5", CPU); |
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public static final Register o6 = new Register(14, 14, "o6", CPU); |
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public static final Register o7 = new Register(15, 15, "o7", CPU); |
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public static final Register l0 = new Register(16, 16, "l0", CPU); |
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public static final Register l1 = new Register(17, 17, "l1", CPU); |
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public static final Register l2 = new Register(18, 18, "l2", CPU); |
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public static final Register l3 = new Register(19, 19, "l3", CPU); |
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public static final Register l4 = new Register(20, 20, "l4", CPU); |
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public static final Register l5 = new Register(21, 21, "l5", CPU); |
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public static final Register l6 = new Register(22, 22, "l6", CPU); |
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public static final Register l7 = new Register(23, 23, "l7", CPU); |
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public static final Register i0 = new Register(24, 24, "i0", CPU); |
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public static final Register i1 = new Register(25, 25, "i1", CPU); |
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public static final Register i2 = new Register(26, 26, "i2", CPU); |
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public static final Register i3 = new Register(27, 27, "i3", CPU); |
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public static final Register i4 = new Register(28, 28, "i4", CPU); |
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public static final Register i5 = new Register(29, 29, "i5", CPU); |
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public static final Register i6 = new Register(30, 30, "i6", CPU); |
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public static final Register i7 = new Register(31, 31, "i7", CPU); |
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public static final Register sp = o6; |
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public static final Register fp = i6; |
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// Floating point registers |
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public static final Register f0 = new Register(32, 0, "f0", FPUs); |
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public static final Register f1 = new Register(33, 1, "f1", FPUs); |
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public static final Register f2 = new Register(34, 2, "f2", FPUs); |
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public static final Register f3 = new Register(35, 3, "f3", FPUs); |
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public static final Register f4 = new Register(36, 4, "f4", FPUs); |
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public static final Register f5 = new Register(37, 5, "f5", FPUs); |
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public static final Register f6 = new Register(38, 6, "f6", FPUs); |
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public static final Register f7 = new Register(39, 7, "f7", FPUs); |
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public static final Register f8 = new Register(40, 8, "f8", FPUs); |
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public static final Register f9 = new Register(41, 9, "f9", FPUs); |
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public static final Register f10 = new Register(42, 10, "f10", FPUs); |
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public static final Register f11 = new Register(43, 11, "f11", FPUs); |
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public static final Register f12 = new Register(44, 12, "f12", FPUs); |
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public static final Register f13 = new Register(45, 13, "f13", FPUs); |
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public static final Register f14 = new Register(46, 14, "f14", FPUs); |
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public static final Register f15 = new Register(47, 15, "f15", FPUs); |
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public static final Register f16 = new Register(48, 16, "f16", FPUs); |
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public static final Register f17 = new Register(49, 17, "f17", FPUs); |
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public static final Register f18 = new Register(50, 18, "f18", FPUs); |
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public static final Register f19 = new Register(51, 19, "f19", FPUs); |
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public static final Register f20 = new Register(52, 20, "f20", FPUs); |
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public static final Register f21 = new Register(53, 21, "f21", FPUs); |
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public static final Register f22 = new Register(54, 22, "f22", FPUs); |
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public static final Register f23 = new Register(55, 23, "f23", FPUs); |
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public static final Register f24 = new Register(56, 24, "f24", FPUs); |
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public static final Register f25 = new Register(57, 25, "f25", FPUs); |
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public static final Register f26 = new Register(58, 26, "f26", FPUs); |
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public static final Register f27 = new Register(59, 27, "f27", FPUs); |
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public static final Register f28 = new Register(60, 28, "f28", FPUs); |
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public static final Register f29 = new Register(61, 29, "f29", FPUs); |
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public static final Register f30 = new Register(62, 30, "f30", FPUs); |
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public static final Register f31 = new Register(63, 31, "f31", FPUs); |
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// Double precision registers |
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public static final Register d0 = new Register(64, getDoubleEncoding(0), "d0", FPUd); |
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public static final Register d2 = new Register(65, getDoubleEncoding(2), "d2", FPUd); |
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public static final Register d4 = new Register(66, getDoubleEncoding(4), "d4", FPUd); |
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public static final Register d6 = new Register(67, getDoubleEncoding(6), "d6", FPUd); |
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public static final Register d8 = new Register(68, getDoubleEncoding(8), "d8", FPUd); |
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public static final Register d10 = new Register(69, getDoubleEncoding(10), "d10", FPUd); |
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public static final Register d12 = new Register(70, getDoubleEncoding(12), "d12", FPUd); |
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public static final Register d14 = new Register(71, getDoubleEncoding(14), "d14", FPUd); |
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public static final Register d16 = new Register(72, getDoubleEncoding(16), "d16", FPUd); |
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public static final Register d18 = new Register(73, getDoubleEncoding(18), "d18", FPUd); |
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public static final Register d20 = new Register(74, getDoubleEncoding(20), "d20", FPUd); |
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public static final Register d22 = new Register(75, getDoubleEncoding(22), "d22", FPUd); |
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public static final Register d24 = new Register(76, getDoubleEncoding(24), "d24", FPUd); |
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public static final Register d26 = new Register(77, getDoubleEncoding(26), "d26", FPUd); |
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public static final Register d28 = new Register(78, getDoubleEncoding(28), "d28", FPUd); |
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public static final Register d30 = new Register(79, getDoubleEncoding(28), "d28", FPUd); |
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public static final Register d32 = new Register(80, getDoubleEncoding(32), "d32", FPUd); |
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public static final Register d34 = new Register(81, getDoubleEncoding(34), "d34", FPUd); |
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public static final Register d36 = new Register(82, getDoubleEncoding(36), "d36", FPUd); |
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public static final Register d38 = new Register(83, getDoubleEncoding(38), "d38", FPUd); |
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public static final Register d40 = new Register(84, getDoubleEncoding(40), "d40", FPUd); |
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public static final Register d42 = new Register(85, getDoubleEncoding(42), "d42", FPUd); |
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public static final Register d44 = new Register(86, getDoubleEncoding(44), "d44", FPUd); |
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public static final Register d46 = new Register(87, getDoubleEncoding(46), "d46", FPUd); |
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public static final Register d48 = new Register(88, getDoubleEncoding(48), "d48", FPUd); |
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public static final Register d50 = new Register(89, getDoubleEncoding(50), "d50", FPUd); |
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public static final Register d52 = new Register(90, getDoubleEncoding(52), "d52", FPUd); |
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public static final Register d54 = new Register(91, getDoubleEncoding(54), "d54", FPUd); |
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public static final Register d56 = new Register(92, getDoubleEncoding(56), "d56", FPUd); |
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public static final Register d58 = new Register(93, getDoubleEncoding(58), "d58", FPUd); |
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public static final Register d60 = new Register(94, getDoubleEncoding(60), "d60", FPUd); |
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public static final Register d62 = new Register(95, getDoubleEncoding(62), "d62", FPUd); |
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// Quad precision registers |
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public static final Register q0 = new Register(96, getQuadncoding(0), "q0", FPUq); |
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public static final Register q4 = new Register(97, getQuadncoding(4), "q4", FPUq); |
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public static final Register q8 = new Register(98, getQuadncoding(8), "q8", FPUq); |
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public static final Register q12 = new Register(99, getQuadncoding(12), "q12", FPUq); |
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public static final Register q16 = new Register(100, getQuadncoding(16), "q16", FPUq); |
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public static final Register q20 = new Register(101, getQuadncoding(20), "q20", FPUq); |
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public static final Register q24 = new Register(102, getQuadncoding(24), "q24", FPUq); |
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public static final Register q28 = new Register(103, getQuadncoding(28), "q28", FPUq); |
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public static final Register q32 = new Register(104, getQuadncoding(32), "q32", FPUq); |
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public static final Register q36 = new Register(105, getQuadncoding(36), "q36", FPUq); |
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public static final Register q40 = new Register(106, getQuadncoding(40), "q40", FPUq); |
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public static final Register q44 = new Register(107, getQuadncoding(44), "q44", FPUq); |
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public static final Register q48 = new Register(108, getQuadncoding(48), "q48", FPUq); |
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public static final Register q52 = new Register(109, getQuadncoding(52), "q52", FPUq); |
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public static final Register q56 = new Register(110, getQuadncoding(56), "q56", FPUq); |
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public static final Register q60 = new Register(111, getQuadncoding(60), "q60", FPUq); |
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// @formatter:off |
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public static final RegisterArray cpuRegisters = new RegisterArray( |
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g0, g1, g2, g3, g4, g5, g6, g7, |
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o0, o1, o2, o3, o4, o5, o6, o7, |
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l0, l1, l2, l3, l4, l5, l6, l7, |
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i0, i1, i2, i3, i4, i5, i6, i7 |
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); |
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public static final RegisterArray fpusRegisters = new RegisterArray( |
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f0, f1, f2, f3, f4, f5, f6, f7, |
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f8, f9, f10, f11, f12, f13, f14, f15, |
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f16, f17, f18, f19, f20, f21, f22, f23, |
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f24, f25, f26, f27, f28, f29, f30, f31 |
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); |
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public static final RegisterArray fpudRegisters = new RegisterArray( |
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d0, d2, d4, d6, d8, d10, d12, d14, |
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d16, d18, d20, d22, d24, d26, d28, d30, |
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d32, d34, d36, d38, d40, d42, d44, d46, |
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d48, d50, d52, d54, d56, d58, d60, d62 |
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); |
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public static final RegisterArray fpuqRegisters = new RegisterArray( |
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q0, q4, q8, q12, |
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q16, q20, q24, q28, |
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q32, q36, q40, q44, |
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q48, q52, q56, q60 |
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); |
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public static final RegisterArray allRegisters = new RegisterArray( |
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g0, g1, g2, g3, g4, g5, g6, g7, |
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o0, o1, o2, o3, o4, o5, o6, o7, |
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l0, l1, l2, l3, l4, l5, l6, l7, |
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i0, i1, i2, i3, i4, i5, i6, i7, |
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f0, f1, f2, f3, f4, f5, f6, f7, |
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f8, f9, f10, f11, f12, f13, f14, f15, |
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f16, f17, f18, f19, f20, f21, f22, f23, |
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f24, f25, f26, f27, f28, f29, f30, f31, |
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d0, d2, d4, d6, d8, d10, d12, d14, |
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d16, d18, d20, d22, d24, d26, d28, d30, |
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d32, d34, d36, d38, d40, d42, d44, d46, |
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d48, d50, d52, d54, d56, d58, d60, d62, |
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q0, q4, q8, q12, |
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q16, q20, q24, q28, |
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q32, q36, q40, q44, |
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q48, q52, q56, q60 |
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); |
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// @formatter:on |
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/** |
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* Stack bias for stack and frame pointer loads. |
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*/ |
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public static final int STACK_BIAS = 0x7ff; |
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/** |
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* Size to keep free for flushing the register-window to stack. |
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*/ |
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public static final int REGISTER_SAFE_AREA_SIZE = 128; |
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public final Set<CPUFeature> features; |
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public SPARC(Set<CPUFeature> features) { |
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super("SPARC", SPARCKind.XWORD, BIG_ENDIAN, false, allRegisters, LOAD_LOAD | LOAD_STORE | STORE_STORE, 1, 8); |
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this.features = features; |
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} |
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@Override |
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public RegisterArray getAvailableValueRegisters() { |
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return allRegisters; |
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} |
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@Override |
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public boolean canStoreValue(RegisterCategory category, PlatformKind kind) { |
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SPARCKind sparcKind = (SPARCKind) kind; |
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switch (sparcKind) { |
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case BYTE: |
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case HWORD: |
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case WORD: |
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case XWORD: |
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return CPU.equals(category); |
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case SINGLE: |
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case V32_BYTE: |
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case V32_HWORD: |
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return FPUs.equals(category); |
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case DOUBLE: |
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case V64_BYTE: |
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case V64_HWORD: |
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case V64_WORD: |
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case V64_SINGLE: |
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return FPUd.equals(category); |
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case QUAD: |
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return FPUq.equals(category); |
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default: |
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return false; |
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} |
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} |
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282 |
@Override |
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public PlatformKind getLargestStorableKind(RegisterCategory category) { |
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if (category.equals(CPU)) { |
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return SPARCKind.XWORD; |
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} else if (category.equals(FPUd)) { |
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return SPARCKind.DOUBLE; |
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} else if (category.equals(FPUs)) { |
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return SPARCKind.SINGLE; |
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} else if (category.equals(FPUq)) { |
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return SPARCKind.QUAD; |
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} else { |
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throw new IllegalArgumentException("Unknown register category: " + category); |
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294 |
} |
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295 |
} |
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296 |
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297 |
@Override |
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298 |
public PlatformKind getPlatformKind(JavaKind javaKind) { |
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299 |
switch (javaKind) { |
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case Boolean: |
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case Byte: |
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return SPARCKind.BYTE; |
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case Short: |
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304 |
case Char: |
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305 |
return SPARCKind.HWORD; |
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306 |
case Int: |
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307 |
return SPARCKind.WORD; |
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case Long: |
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case Object: |
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return SPARCKind.XWORD; |
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311 |
case Float: |
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312 |
return SPARCKind.SINGLE; |
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case Double: |
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314 |
return SPARCKind.DOUBLE; |
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315 |
default: |
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54669
ad45b3802d4e
8220623: [JVMCI] Update JVMCI to support JVMCI based Compiler compiled into shared library
kvn
parents:
47562
diff
changeset
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316 |
return null; |
43972 | 317 |
} |
318 |
} |
|
319 |
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320 |
private static int getDoubleEncoding(int reg) { |
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321 |
assert reg < 64 && ((reg & 1) == 0); |
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322 |
return (reg & 0x1e) | ((reg & 0x20) >> 5); |
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323 |
} |
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324 |
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325 |
private static int getQuadncoding(int reg) { |
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326 |
assert reg < 64 && ((reg & 1) == 0); |
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327 |
return (reg & 0x1c) | ((reg & 0x20) >> 5); |
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328 |
} |
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329 |
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330 |
public Set<CPUFeature> getFeatures() { |
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331 |
return features; |
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332 |
} |
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333 |
||
334 |
public boolean hasFeature(CPUFeature feature) { |
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return features.contains(feature); |
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336 |
} |
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337 |
||
338 |
public enum CPUFeature { |
|
46592
6e357e2c8143
8172231: SPARC ISA/CPU feature detection is broken/insufficient (on Solaris)
neliasso
parents:
43972
diff
changeset
|
339 |
// ISA determined properties: |
6e357e2c8143
8172231: SPARC ISA/CPU feature detection is broken/insufficient (on Solaris)
neliasso
parents:
43972
diff
changeset
|
340 |
ADI, |
6e357e2c8143
8172231: SPARC ISA/CPU feature detection is broken/insufficient (on Solaris)
neliasso
parents:
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341 |
AES, |
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|
342 |
BLK_INIT, |
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|
343 |
CAMELLIA, |
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344 |
CBCOND, |
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345 |
CRC32C, |
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346 |
DES, |
47562
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|
347 |
DICTUNP, |
46592
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348 |
FMAF, |
47562
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|
349 |
FPCMPSHL, |
46592
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350 |
HPC, |
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351 |
IMA, |
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352 |
KASUMI, |
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353 |
MD5, |
47562
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|
354 |
MME, |
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355 |
MONT, |
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356 |
MPMUL, |
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|
357 |
MWAIT, |
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|
358 |
PAUSE, |
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359 |
PAUSE_NSEC, |
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360 |
POPC, |
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|
361 |
RLE, |
46592
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362 |
SHA1, |
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|
363 |
SHA256, |
47562
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|
364 |
SHA3, |
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|
365 |
SHA512, |
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|
366 |
SPARC5, |
47562
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|
367 |
SPARC5B, |
f789ccebcfe4
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|
368 |
SPARC6, |
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369 |
V9, |
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|
370 |
VAMASK, |
43972 | 371 |
VIS1, |
372 |
VIS2, |
|
373 |
VIS3, |
|
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374 |
VIS3B, |
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|
375 |
VIS3C, |
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376 |
XMONT, |
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|
377 |
XMPMUL, |
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|
378 |
// Synthesised CPU properties: |
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379 |
BLK_ZEROING, |
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|
380 |
FAST_BIS, |
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|
381 |
FAST_CMOVE, |
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|
382 |
FAST_IDIV, |
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383 |
FAST_IND_BR, |
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|
384 |
FAST_LD, |
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385 |
FAST_RDPC |
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} |
387 |
} |