hotspot/src/cpu/sparc/vm/nativeInst_sparc.hpp
author morris
Fri, 07 Jun 2013 16:46:37 -0700
changeset 18097 acd70736bd60
parent 14631 526804361522
child 22234 da823d78ad65
permissions -rw-r--r--
8008407: remove SPARC V8 support Summary: Removed most of the SPARC V8 instructions Reviewed-by: kvn, twisti
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/*
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 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#ifndef CPU_SPARC_VM_NATIVEINST_SPARC_HPP
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#define CPU_SPARC_VM_NATIVEINST_SPARC_HPP
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#include "asm/macroAssembler.hpp"
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#include "memory/allocation.hpp"
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#include "runtime/icache.hpp"
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#include "runtime/os.hpp"
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#include "utilities/top.hpp"
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// We have interface for the following instructions:
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// - NativeInstruction
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// - - NativeCall
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// - - NativeFarCall
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// - - NativeMovConstReg
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// - - NativeMovConstRegPatching
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// - - NativeMovRegMem
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// - - NativeMovRegMemPatching
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// - - NativeJump
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// - - NativeGeneralJump
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// - - NativeIllegalInstruction
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// The base class for different kinds of native instruction abstractions.
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// Provides the primitive operations to manipulate code relative to this.
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class NativeInstruction VALUE_OBJ_CLASS_SPEC {
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  friend class Relocation;
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 public:
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  enum Sparc_specific_constants {
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    nop_instruction_size        =    4
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  };
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  bool is_dtrace_trap();
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  bool is_nop()                        { return long_at(0) == nop_instruction(); }
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  bool is_call()                       { return is_op(long_at(0), Assembler::call_op); }
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  bool is_sethi()                      { return (is_op2(long_at(0), Assembler::sethi_op2)
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                                          && inv_rd(long_at(0)) != G0); }
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  bool sets_cc() {
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    // conservative (returns true for some instructions that do not set the
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    // the condition code, such as, "save".
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    // Does not return true for the deprecated tagged instructions, such as, TADDcc
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    int x = long_at(0);
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    return (is_op(x, Assembler::arith_op) &&
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            (inv_op3(x) & Assembler::cc_bit_op3) == Assembler::cc_bit_op3);
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  }
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  bool is_illegal();
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  bool is_zombie() {
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    int x = long_at(0);
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    return is_op3(x,
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                  Assembler::ldsw_op3,
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                  Assembler::ldst_op)
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        && Assembler::inv_rs1(x) == G0
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        && Assembler::inv_rd(x) == O7;
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  }
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  bool is_ic_miss_trap();       // Inline-cache uses a trap to detect a miss
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  bool is_return() {
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    // is it the output of MacroAssembler::ret or MacroAssembler::retl?
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    int x = long_at(0);
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    const int pc_return_offset = 8; // see frame_sparc.hpp
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    return is_op3(x, Assembler::jmpl_op3, Assembler::arith_op)
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        && (inv_rs1(x) == I7 || inv_rs1(x) == O7)
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        && inv_immed(x) && inv_simm(x, 13) == pc_return_offset
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        && inv_rd(x) == G0;
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  }
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  bool is_int_jump() {
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    // is it the output of MacroAssembler::b?
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    int x = long_at(0);
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    return is_op2(x, Assembler::bp_op2) || is_op2(x, Assembler::br_op2);
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  }
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  bool is_float_jump() {
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    // is it the output of MacroAssembler::fb?
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    int x = long_at(0);
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    return is_op2(x, Assembler::fbp_op2) || is_op2(x, Assembler::fb_op2);
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  }
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  bool is_jump() {
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    return is_int_jump() || is_float_jump();
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  }
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  bool is_cond_jump() {
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    int x = long_at(0);
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    return (is_int_jump() && Assembler::inv_cond(x) != Assembler::always) ||
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           (is_float_jump() && Assembler::inv_cond(x) != Assembler::f_always);
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  }
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  bool is_stack_bang() {
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    int x = long_at(0);
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    return is_op3(x, Assembler::stw_op3, Assembler::ldst_op) &&
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      (inv_rd(x) == G0) && (inv_rs1(x) == SP) && (inv_rs2(x) == G3_scratch);
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  }
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  bool is_prefetch() {
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    int x = long_at(0);
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    return is_op3(x, Assembler::prefetch_op3, Assembler::ldst_op);
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  }
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  bool is_membar() {
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    int x = long_at(0);
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    return is_op3(x, Assembler::membar_op3, Assembler::arith_op) &&
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      (inv_rd(x) == G0) && (inv_rs1(x) == O7);
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  }
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  bool is_safepoint_poll() {
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    int x = long_at(0);
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#ifdef _LP64
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    return is_op3(x, Assembler::ldx_op3,  Assembler::ldst_op) &&
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#else
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    return is_op3(x, Assembler::lduw_op3, Assembler::ldst_op) &&
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#endif
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      (inv_rd(x) == G0) && (inv_immed(x) ? Assembler::inv_simm13(x) == 0 : inv_rs2(x) == G0);
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  }
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  bool is_zero_test(Register &reg);
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  bool is_load_store_with_small_offset(Register reg);
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 public:
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#ifdef ASSERT
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  static int rdpc_instruction()        { return Assembler::op(Assembler::arith_op ) | Assembler::op3(Assembler::rdreg_op3) | Assembler::u_field(5, 18, 14) | Assembler::rd(O7); }
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#else
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  // Temporary fix: in optimized mode, u_field is a macro for efficiency reasons (see Assembler::u_field) - needs to be fixed
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  static int rdpc_instruction()        { return Assembler::op(Assembler::arith_op ) | Assembler::op3(Assembler::rdreg_op3) |            u_field(5, 18, 14) | Assembler::rd(O7); }
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#endif
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  static int nop_instruction()         { return Assembler::op(Assembler::branch_op) | Assembler::op2(Assembler::sethi_op2); }
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  static int illegal_instruction();    // the output of __ breakpoint_trap()
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  static int call_instruction(address destination, address pc) { return Assembler::op(Assembler::call_op) | Assembler::wdisp((intptr_t)destination, (intptr_t)pc, 30); }
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  static int branch_instruction(Assembler::op2s op2val, Assembler::Condition c, bool a) {
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    return Assembler::op(Assembler::branch_op) | Assembler::op2(op2val) | Assembler::annul(a) | Assembler::cond(c);
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  }
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  static int op3_instruction(Assembler::ops opval, Register rd, Assembler::op3s op3val, Register rs1, int simm13a) {
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    return Assembler::op(opval) | Assembler::rd(rd) | Assembler::op3(op3val) | Assembler::rs1(rs1) | Assembler::immed(true) | Assembler::simm(simm13a, 13);
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  }
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  static int sethi_instruction(Register rd, int imm22a) {
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    return Assembler::op(Assembler::branch_op) | Assembler::rd(rd) | Assembler::op2(Assembler::sethi_op2) | Assembler::hi22(imm22a);
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  }
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 protected:
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  address  addr_at(int offset) const    { return address(this) + offset; }
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  int      long_at(int offset) const    { return *(int*)addr_at(offset); }
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  void set_long_at(int offset, int i);      /* deals with I-cache */
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  void set_jlong_at(int offset, jlong i);   /* deals with I-cache */
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  void set_addr_at(int offset, address x);  /* deals with I-cache */
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  address instruction_address() const       { return addr_at(0); }
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  address next_instruction_address() const  { return addr_at(BytesPerInstWord); }
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  static bool is_op( int x, Assembler::ops opval)  {
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    return Assembler::inv_op(x) == opval;
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  }
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  static bool is_op2(int x, Assembler::op2s op2val) {
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    return Assembler::inv_op(x) == Assembler::branch_op && Assembler::inv_op2(x) == op2val;
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  }
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  static bool is_op3(int x, Assembler::op3s op3val, Assembler::ops opval) {
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    return Assembler::inv_op(x) == opval && Assembler::inv_op3(x) == op3val;
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  }
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  // utilities to help subclasses decode:
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  static Register inv_rd(  int x ) { return Assembler::inv_rd( x); }
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  static Register inv_rs1( int x ) { return Assembler::inv_rs1(x); }
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  static Register inv_rs2( int x ) { return Assembler::inv_rs2(x); }
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  static bool inv_immed( int x ) { return Assembler::inv_immed(x); }
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  static bool inv_annul( int x ) { return (Assembler::annul(true) & x) != 0; }
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  static int  inv_cond(  int x ) { return Assembler::inv_cond(x); }
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  static int inv_op(  int x ) { return Assembler::inv_op( x); }
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  static int inv_op2( int x ) { return Assembler::inv_op2(x); }
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  static int inv_op3( int x ) { return Assembler::inv_op3(x); }
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  static int inv_simm(    int x, int nbits ) { return Assembler::inv_simm(x, nbits); }
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  static intptr_t inv_wdisp(   int x, int nbits ) { return Assembler::inv_wdisp(  x, 0, nbits); }
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  static intptr_t inv_wdisp16( int x )            { return Assembler::inv_wdisp16(x, 0); }
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  static int branch_destination_offset(int x) { return MacroAssembler::branch_destination(x, 0); }
1
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  static int patch_branch_destination_offset(int dest_offset, int x) {
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    return MacroAssembler::patched_branch(dest_offset, x, 0);
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  }
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  // utility for checking if x is either of 2 small constants
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  static bool is_either(int x, int k1, int k2) {
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    // return x == k1 || x == k2;
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    return (1 << x) & (1 << k1 | 1 << k2);
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  }
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  // utility for checking overflow of signed instruction fields
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  static bool fits_in_simm(int x, int nbits) {
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    // cf. Assembler::assert_signed_range()
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    // return -(1 << nbits-1) <= x  &&  x < ( 1 << nbits-1),
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    return (unsigned)(x + (1 << nbits-1)) < (unsigned)(1 << nbits);
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  }
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  // set a signed immediate field
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  static int set_simm(int insn, int imm, int nbits) {
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    return (insn &~ Assembler::simm(-1, nbits)) | Assembler::simm(imm, nbits);
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  }
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  // set a wdisp field (disp should be the difference of two addresses)
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  static int set_wdisp(int insn, intptr_t disp, int nbits) {
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    return (insn &~ Assembler::wdisp((intptr_t)-4, (intptr_t)0, nbits)) | Assembler::wdisp(disp, 0, nbits);
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  }
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  static int set_wdisp16(int insn, intptr_t disp) {
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    return (insn &~ Assembler::wdisp16((intptr_t)-4, 0)) | Assembler::wdisp16(disp, 0);
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  }
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  // get a simm13 field from an arithmetic or memory instruction
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  static int get_simm13(int insn) {
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    assert(is_either(Assembler::inv_op(insn),
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                     Assembler::arith_op, Assembler::ldst_op) &&
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            (insn & Assembler::immed(true)), "must have a simm13 field");
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    return Assembler::inv_simm(insn, 13);
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  }
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  // set the simm13 field of an arithmetic or memory instruction
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  static bool set_simm13(int insn, int imm) {
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    get_simm13(insn);           // tickle the assertion check
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    return set_simm(insn, imm, 13);
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  }
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  // combine the fields of a sethi stream (7 instructions ) and an add, jmp or ld/st
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  static intptr_t data64( address pc, int arith_insn ) {
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    assert(is_op2(*(unsigned int *)pc, Assembler::sethi_op2), "must be sethi");
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    intptr_t hi = (intptr_t)gethi( (unsigned int *)pc );
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    intptr_t lo = (intptr_t)get_simm13(arith_insn);
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    assert((unsigned)lo < (1 << 10), "offset field of set_metadata must be 10 bits");
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    return hi | lo;
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  }
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  // Regenerate the instruction sequence that performs the 64 bit
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  // sethi.  This only does the sethi.  The disp field (bottom 10 bits)
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  // must be handled separately.
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  static void set_data64_sethi(address instaddr, intptr_t x);
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  static void verify_data64_sethi(address instaddr, intptr_t x);
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  // combine the fields of a sethi/simm13 pair (simm13 = or, add, jmpl, ld/st)
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  static int data32(int sethi_insn, int arith_insn) {
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    assert(is_op2(sethi_insn, Assembler::sethi_op2), "must be sethi");
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    int hi = Assembler::inv_hi22(sethi_insn);
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    int lo = get_simm13(arith_insn);
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    assert((unsigned)lo < (1 << 10), "offset field of set_metadata must be 10 bits");
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    return hi | lo;
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  }
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  static int set_data32_sethi(int sethi_insn, int imm) {
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    // note that Assembler::hi22 clips the low 10 bits for us
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    assert(is_op2(sethi_insn, Assembler::sethi_op2), "must be sethi");
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    return (sethi_insn &~ Assembler::hi22(-1)) | Assembler::hi22(imm);
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  }
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  static int set_data32_simm13(int arith_insn, int imm) {
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    get_simm13(arith_insn);             // tickle the assertion check
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    int imm10 = Assembler::low10(imm);
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    return (arith_insn &~ Assembler::simm(-1, 13)) | Assembler::simm(imm10, 13);
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  }
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  static int low10(int imm) {
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    return Assembler::low10(imm);
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  }
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  // Perform the inverse of the LP64 Macroassembler::sethi
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  // routine.  Extracts the 54 bits of address from the instruction
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  // stream. This routine must agree with the sethi routine in
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  // assembler_inline_sparc.hpp
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  static address gethi( unsigned int *pc ) {
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    int i = 0;
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    uintptr_t adr;
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    // We first start out with the real sethi instruction
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    assert(is_op2(*pc, Assembler::sethi_op2), "in gethi - must be sethi");
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    adr = (unsigned int)Assembler::inv_hi22( *(pc++) );
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    i++;
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    while ( i < 7 ) {
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       // We're done if we hit a nop
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       if ( (int)*pc == nop_instruction() ) break;
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       assert ( Assembler::inv_op(*pc) == Assembler::arith_op, "in gethi - must be arith_op" );
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   297
       switch  ( Assembler::inv_op3(*pc) ) {
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         case Assembler::xor_op3:
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           adr ^= (intptr_t)get_simm13( *pc );
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           return ( (address)adr );
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           break;
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         case Assembler::sll_op3:
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   303
           adr <<= ( *pc & 0x3f );
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           break;
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         case Assembler::or_op3:
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   306
           adr |= (intptr_t)get_simm13( *pc );
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           break;
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   308
         default:
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           assert ( 0, "in gethi - Should not reach here" );
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           break;
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       }
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       pc++;
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       i++;
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    }
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    return ( (address)adr );
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  }
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 public:
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  void  verify();
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  void  print();
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   321
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  // unit test stuff
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  static void test() {}                 // override for testing
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   324
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  inline friend NativeInstruction* nativeInstruction_at(address address);
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};
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   327
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inline NativeInstruction* nativeInstruction_at(address address) {
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    NativeInstruction* inst = (NativeInstruction*)address;
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#ifdef ASSERT
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      inst->verify();
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#endif
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    return inst;
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}
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   335
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   336
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//-----------------------------------------------------------------------------
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// The NativeCall is an abstraction for accessing/manipulating native call imm32 instructions.
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// (used to manipulate inline caches, primitive & dll calls, etc.)
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inline NativeCall* nativeCall_at(address instr);
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inline NativeCall* nativeCall_overwriting_at(address instr,
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                                             address destination);
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inline NativeCall* nativeCall_before(address return_address);
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class NativeCall: public NativeInstruction {
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 public:
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  enum Sparc_specific_constants {
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    instruction_size                   = 8,
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    return_address_offset              = 8,
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    call_displacement_width            = 30,
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    displacement_offset                = 0,
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    instruction_offset                 = 0
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  };
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  address instruction_address() const       { return addr_at(0); }
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  address next_instruction_address() const  { return addr_at(instruction_size); }
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  address return_address() const            { return addr_at(return_address_offset); }
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   358
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  address destination() const               { return inv_wdisp(long_at(0), call_displacement_width) + instruction_address(); }
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   360
  address displacement_address() const      { return addr_at(displacement_offset); }
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   361
  void  set_destination(address dest)       { set_long_at(0, set_wdisp(long_at(0), dest - instruction_address(), call_displacement_width)); }
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parents:
diff changeset
   362
  void  set_destination_mt_safe(address dest);
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parents:
diff changeset
   363
489c9b5090e2 Initial load
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parents:
diff changeset
   364
  void  verify_alignment() {} // do nothing on sparc
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parents:
diff changeset
   365
  void  verify();
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diff changeset
   366
  void  print();
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parents:
diff changeset
   367
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parents:
diff changeset
   368
  // unit test stuff
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parents:
diff changeset
   369
  static void  test();
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parents:
diff changeset
   370
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parents:
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   371
  // Creation
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parents:
diff changeset
   372
  friend inline NativeCall* nativeCall_at(address instr);
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parents:
diff changeset
   373
  friend NativeCall* nativeCall_overwriting_at(address instr, address destination = NULL) {
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parents:
diff changeset
   374
    // insert a "blank" call:
489c9b5090e2 Initial load
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parents:
diff changeset
   375
    NativeCall* call = (NativeCall*)instr;
489c9b5090e2 Initial load
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parents:
diff changeset
   376
    call->set_long_at(0 * BytesPerInstWord, call_instruction(destination, instr));
489c9b5090e2 Initial load
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parents:
diff changeset
   377
    call->set_long_at(1 * BytesPerInstWord, nop_instruction());
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parents:
diff changeset
   378
    assert(call->addr_at(2 * BytesPerInstWord) - instr == instruction_size, "instruction size");
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parents:
diff changeset
   379
    // check its structure now:
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parents:
diff changeset
   380
    assert(nativeCall_at(instr)->destination() == destination, "correct call destination");
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parents:
diff changeset
   381
    return call;
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parents:
diff changeset
   382
  }
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parents:
diff changeset
   383
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parents:
diff changeset
   384
  friend inline NativeCall* nativeCall_before(address return_address) {
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parents:
diff changeset
   385
    NativeCall* call = (NativeCall*)(return_address - return_address_offset);
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parents:
diff changeset
   386
    #ifdef ASSERT
489c9b5090e2 Initial load
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parents:
diff changeset
   387
      call->verify();
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parents:
diff changeset
   388
    #endif
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parents:
diff changeset
   389
    return call;
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parents:
diff changeset
   390
  }
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parents:
diff changeset
   391
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parents:
diff changeset
   392
  static bool is_call_at(address instr) {
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parents:
diff changeset
   393
    return nativeInstruction_at(instr)->is_call();
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parents:
diff changeset
   394
  }
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parents:
diff changeset
   395
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parents:
diff changeset
   396
  static bool is_call_before(address instr) {
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parents:
diff changeset
   397
    return nativeInstruction_at(instr - return_address_offset)->is_call();
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parents:
diff changeset
   398
  }
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parents:
diff changeset
   399
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parents:
diff changeset
   400
  static bool is_call_to(address instr, address target) {
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parents:
diff changeset
   401
    return nativeInstruction_at(instr)->is_call() &&
489c9b5090e2 Initial load
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parents:
diff changeset
   402
      nativeCall_at(instr)->destination() == target;
489c9b5090e2 Initial load
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parents:
diff changeset
   403
  }
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parents:
diff changeset
   404
489c9b5090e2 Initial load
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parents:
diff changeset
   405
  // MT-safe patching of a call instruction.
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parents:
diff changeset
   406
  static void insert(address code_pos, address entry) {
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parents:
diff changeset
   407
    (void)nativeCall_overwriting_at(code_pos, entry);
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parents:
diff changeset
   408
  }
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parents:
diff changeset
   409
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parents:
diff changeset
   410
  static void replace_mt_safe(address instr_addr, address code_buffer);
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parents:
diff changeset
   411
};
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parents:
diff changeset
   412
inline NativeCall* nativeCall_at(address instr) {
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parents:
diff changeset
   413
  NativeCall* call = (NativeCall*)instr;
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parents:
diff changeset
   414
#ifdef ASSERT
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parents:
diff changeset
   415
  call->verify();
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parents:
diff changeset
   416
#endif
489c9b5090e2 Initial load
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parents:
diff changeset
   417
  return call;
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parents:
diff changeset
   418
}
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parents:
diff changeset
   419
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parents:
diff changeset
   420
// The NativeFarCall is an abstraction for accessing/manipulating native call-anywhere
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parents:
diff changeset
   421
// instructions in the sparcv9 vm.  Used to call native methods which may be loaded
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parents:
diff changeset
   422
// anywhere in the address space, possibly out of reach of a call instruction.
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parents:
diff changeset
   423
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parents:
diff changeset
   424
#ifndef _LP64
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parents:
diff changeset
   425
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parents:
diff changeset
   426
// On 32-bit systems, a far call is the same as a near one.
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parents:
diff changeset
   427
class NativeFarCall;
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parents:
diff changeset
   428
inline NativeFarCall* nativeFarCall_at(address instr);
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parents:
diff changeset
   429
class NativeFarCall : public NativeCall {
489c9b5090e2 Initial load
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parents:
diff changeset
   430
public:
489c9b5090e2 Initial load
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parents:
diff changeset
   431
  friend inline NativeFarCall* nativeFarCall_at(address instr) { return (NativeFarCall*)nativeCall_at(instr); }
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parents:
diff changeset
   432
  friend NativeFarCall* nativeFarCall_overwriting_at(address instr, address destination = NULL)
489c9b5090e2 Initial load
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parents:
diff changeset
   433
                                                        { return (NativeFarCall*)nativeCall_overwriting_at(instr, destination); }
489c9b5090e2 Initial load
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parents:
diff changeset
   434
  friend NativeFarCall* nativeFarCall_before(address return_address)
489c9b5090e2 Initial load
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parents:
diff changeset
   435
                                                        { return (NativeFarCall*)nativeCall_before(return_address); }
489c9b5090e2 Initial load
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parents:
diff changeset
   436
};
489c9b5090e2 Initial load
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parents:
diff changeset
   437
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parents:
diff changeset
   438
#else
489c9b5090e2 Initial load
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parents:
diff changeset
   439
489c9b5090e2 Initial load
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parents:
diff changeset
   440
// The format of this extended-range call is:
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parents:
diff changeset
   441
//      jumpl_to addr, lreg
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parents:
diff changeset
   442
//      == sethi %hi54(addr), O7 ;  jumpl O7, %lo10(addr), O7 ;  <delay>
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parents:
diff changeset
   443
// That is, it is essentially the same as a NativeJump.
489c9b5090e2 Initial load
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parents:
diff changeset
   444
class NativeFarCall;
489c9b5090e2 Initial load
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parents:
diff changeset
   445
inline NativeFarCall* nativeFarCall_overwriting_at(address instr, address destination);
489c9b5090e2 Initial load
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parents:
diff changeset
   446
inline NativeFarCall* nativeFarCall_at(address instr);
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duke
parents:
diff changeset
   447
class NativeFarCall: public NativeInstruction {
489c9b5090e2 Initial load
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parents:
diff changeset
   448
 public:
489c9b5090e2 Initial load
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parents:
diff changeset
   449
  enum Sparc_specific_constants {
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parents:
diff changeset
   450
    // instruction_size includes the delay slot instruction.
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parents:
diff changeset
   451
    instruction_size                   = 9 * BytesPerInstWord,
489c9b5090e2 Initial load
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parents:
diff changeset
   452
    return_address_offset              = 9 * BytesPerInstWord,
489c9b5090e2 Initial load
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parents:
diff changeset
   453
    jmpl_offset                        = 7 * BytesPerInstWord,
489c9b5090e2 Initial load
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parents:
diff changeset
   454
    displacement_offset                = 0,
489c9b5090e2 Initial load
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parents:
diff changeset
   455
    instruction_offset                 = 0
489c9b5090e2 Initial load
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parents:
diff changeset
   456
  };
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parents:
diff changeset
   457
  address instruction_address() const       { return addr_at(0); }
489c9b5090e2 Initial load
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parents:
diff changeset
   458
  address next_instruction_address() const  { return addr_at(instruction_size); }
489c9b5090e2 Initial load
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parents:
diff changeset
   459
  address return_address() const            { return addr_at(return_address_offset); }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   460
489c9b5090e2 Initial load
duke
parents:
diff changeset
   461
  address destination() const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   462
    return (address) data64(addr_at(0), long_at(jmpl_offset));
489c9b5090e2 Initial load
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parents:
diff changeset
   463
  }
489c9b5090e2 Initial load
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parents:
diff changeset
   464
  address displacement_address() const      { return addr_at(displacement_offset); }
489c9b5090e2 Initial load
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parents:
diff changeset
   465
  void set_destination(address dest);
489c9b5090e2 Initial load
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parents:
diff changeset
   466
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parents:
diff changeset
   467
  bool destination_is_compiled_verified_entry_point();
489c9b5090e2 Initial load
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parents:
diff changeset
   468
489c9b5090e2 Initial load
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parents:
diff changeset
   469
  void  verify();
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parents:
diff changeset
   470
  void  print();
489c9b5090e2 Initial load
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parents:
diff changeset
   471
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parents:
diff changeset
   472
  // unit test stuff
489c9b5090e2 Initial load
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parents:
diff changeset
   473
  static void  test();
489c9b5090e2 Initial load
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parents:
diff changeset
   474
489c9b5090e2 Initial load
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parents:
diff changeset
   475
  // Creation
489c9b5090e2 Initial load
duke
parents:
diff changeset
   476
  friend inline NativeFarCall* nativeFarCall_at(address instr) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   477
    NativeFarCall* call = (NativeFarCall*)instr;
489c9b5090e2 Initial load
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parents:
diff changeset
   478
    #ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   479
      call->verify();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   480
    #endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   481
    return call;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   482
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   483
489c9b5090e2 Initial load
duke
parents:
diff changeset
   484
  friend inline NativeFarCall* nativeFarCall_overwriting_at(address instr, address destination = NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   485
    Unimplemented();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   486
    NativeFarCall* call = (NativeFarCall*)instr;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   487
    return call;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   488
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   489
489c9b5090e2 Initial load
duke
parents:
diff changeset
   490
  friend NativeFarCall* nativeFarCall_before(address return_address) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   491
    NativeFarCall* call = (NativeFarCall*)(return_address - return_address_offset);
489c9b5090e2 Initial load
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parents:
diff changeset
   492
    #ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   493
      call->verify();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   494
    #endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   495
    return call;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   496
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   497
489c9b5090e2 Initial load
duke
parents:
diff changeset
   498
  static bool is_call_at(address instr);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   499
489c9b5090e2 Initial load
duke
parents:
diff changeset
   500
  // MT-safe patching of a call instruction.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   501
  static void insert(address code_pos, address entry) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   502
    (void)nativeFarCall_overwriting_at(code_pos, entry);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   503
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   504
  static void replace_mt_safe(address instr_addr, address code_buffer);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   505
};
489c9b5090e2 Initial load
duke
parents:
diff changeset
   506
489c9b5090e2 Initial load
duke
parents:
diff changeset
   507
#endif // _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
   508
13728
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 8921
diff changeset
   509
// An interface for accessing/manipulating native set_metadata imm, reg instructions.
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   510
// (used to manipulate inlined data references, etc.)
13728
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 8921
diff changeset
   511
//      set_metadata imm, reg
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   512
//      == sethi %hi22(imm), reg ;  add reg, %lo10(imm), reg
489c9b5090e2 Initial load
duke
parents:
diff changeset
   513
class NativeMovConstReg;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   514
inline NativeMovConstReg* nativeMovConstReg_at(address address);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   515
class NativeMovConstReg: public NativeInstruction {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   516
 public:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   517
  enum Sparc_specific_constants {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   518
    sethi_offset           = 0,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   519
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
   520
    add_offset             = 7 * BytesPerInstWord,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   521
    instruction_size       = 8 * BytesPerInstWord
489c9b5090e2 Initial load
duke
parents:
diff changeset
   522
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   523
    add_offset             = 4,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   524
    instruction_size       = 8
489c9b5090e2 Initial load
duke
parents:
diff changeset
   525
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   526
  };
489c9b5090e2 Initial load
duke
parents:
diff changeset
   527
489c9b5090e2 Initial load
duke
parents:
diff changeset
   528
  address instruction_address() const       { return addr_at(0); }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   529
  address next_instruction_address() const  { return addr_at(instruction_size); }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   530
489c9b5090e2 Initial load
duke
parents:
diff changeset
   531
  // (The [set_]data accessor respects oop_type relocs also.)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   532
  intptr_t data() const;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   533
  void set_data(intptr_t x);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   534
489c9b5090e2 Initial load
duke
parents:
diff changeset
   535
  // report the destination register
489c9b5090e2 Initial load
duke
parents:
diff changeset
   536
  Register destination() { return inv_rd(long_at(sethi_offset)); }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   537
489c9b5090e2 Initial load
duke
parents:
diff changeset
   538
  void  verify();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   539
  void  print();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   540
489c9b5090e2 Initial load
duke
parents:
diff changeset
   541
  // unit test stuff
489c9b5090e2 Initial load
duke
parents:
diff changeset
   542
  static void test();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   543
489c9b5090e2 Initial load
duke
parents:
diff changeset
   544
  // Creation
489c9b5090e2 Initial load
duke
parents:
diff changeset
   545
  friend inline NativeMovConstReg* nativeMovConstReg_at(address address) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   546
    NativeMovConstReg* test = (NativeMovConstReg*)address;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   547
    #ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   548
      test->verify();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   549
    #endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   550
    return test;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   551
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   552
489c9b5090e2 Initial load
duke
parents:
diff changeset
   553
489c9b5090e2 Initial load
duke
parents:
diff changeset
   554
  friend NativeMovConstReg* nativeMovConstReg_before(address address) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   555
    NativeMovConstReg* test = (NativeMovConstReg*)(address - instruction_size);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   556
    #ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   557
      test->verify();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   558
    #endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   559
    return test;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   560
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   561
489c9b5090e2 Initial load
duke
parents:
diff changeset
   562
};
489c9b5090e2 Initial load
duke
parents:
diff changeset
   563
489c9b5090e2 Initial load
duke
parents:
diff changeset
   564
13728
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 8921
diff changeset
   565
// An interface for accessing/manipulating native set_metadata imm, reg instructions.
1
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parents:
diff changeset
   566
// (used to manipulate inlined data references, etc.)
13728
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 8921
diff changeset
   567
//      set_metadata imm, reg
1
489c9b5090e2 Initial load
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parents:
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   568
//      == sethi %hi22(imm), reg; nop; add reg, %lo10(imm), reg
489c9b5090e2 Initial load
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parents:
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   569
//
489c9b5090e2 Initial load
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parents:
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   570
// Note that it is identical to NativeMovConstReg with the exception of a nop between the
489c9b5090e2 Initial load
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parents:
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   571
// sethi and the add.  The nop is required to be in the delay slot of the call instruction
489c9b5090e2 Initial load
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parents:
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   572
// which overwrites the sethi during patching.
489c9b5090e2 Initial load
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   573
class NativeMovConstRegPatching;
489c9b5090e2 Initial load
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   574
inline NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address);class NativeMovConstRegPatching: public NativeInstruction {
489c9b5090e2 Initial load
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   575
 public:
489c9b5090e2 Initial load
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   576
  enum Sparc_specific_constants {
489c9b5090e2 Initial load
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   577
    sethi_offset           = 0,
489c9b5090e2 Initial load
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parents:
diff changeset
   578
#ifdef _LP64
489c9b5090e2 Initial load
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   579
    nop_offset             = 7 * BytesPerInstWord,
489c9b5090e2 Initial load
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parents:
diff changeset
   580
#else
489c9b5090e2 Initial load
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parents:
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   581
    nop_offset             = sethi_offset + BytesPerInstWord,
489c9b5090e2 Initial load
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parents:
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   582
#endif
489c9b5090e2 Initial load
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parents:
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   583
    add_offset             = nop_offset   + BytesPerInstWord,
489c9b5090e2 Initial load
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parents:
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   584
    instruction_size       = add_offset   + BytesPerInstWord
489c9b5090e2 Initial load
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   585
  };
489c9b5090e2 Initial load
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parents:
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   586
489c9b5090e2 Initial load
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   587
  address instruction_address() const       { return addr_at(0); }
489c9b5090e2 Initial load
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   588
  address next_instruction_address() const  { return addr_at(instruction_size); }
489c9b5090e2 Initial load
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   589
489c9b5090e2 Initial load
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   590
  // (The [set_]data accessor respects oop_type relocs also.)
489c9b5090e2 Initial load
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   591
  int data() const;
489c9b5090e2 Initial load
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   592
  void  set_data(int x);
489c9b5090e2 Initial load
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   593
489c9b5090e2 Initial load
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parents:
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   594
  // report the destination register
489c9b5090e2 Initial load
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   595
  Register destination() { return inv_rd(long_at(sethi_offset)); }
489c9b5090e2 Initial load
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   596
489c9b5090e2 Initial load
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   597
  void  verify();
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   598
  void  print();
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   599
489c9b5090e2 Initial load
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parents:
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   600
  // unit test stuff
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parents:
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   601
  static void test();
489c9b5090e2 Initial load
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   602
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parents:
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   603
  // Creation
489c9b5090e2 Initial load
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   604
  friend inline NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) {
489c9b5090e2 Initial load
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   605
    NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)address;
489c9b5090e2 Initial load
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   606
    #ifdef ASSERT
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   607
      test->verify();
489c9b5090e2 Initial load
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   608
    #endif
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   609
    return test;
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   610
  }
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   611
489c9b5090e2 Initial load
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   612
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   613
  friend NativeMovConstRegPatching* nativeMovConstRegPatching_before(address address) {
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   614
    NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_size);
489c9b5090e2 Initial load
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   615
    #ifdef ASSERT
489c9b5090e2 Initial load
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   616
      test->verify();
489c9b5090e2 Initial load
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   617
    #endif
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   618
    return test;
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   619
  }
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   620
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   621
};
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   622
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   623
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   624
// An interface for accessing/manipulating native memory ops
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   625
//      ld* [reg + offset], reg
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   626
//      st* reg, [reg + offset]
489c9b5090e2 Initial load
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   627
//      sethi %hi(imm), reg; add reg, %lo(imm), reg; ld* [reg1 + reg], reg2
489c9b5090e2 Initial load
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parents:
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   628
//      sethi %hi(imm), reg; add reg, %lo(imm), reg; st* reg2, [reg1 + reg]
489c9b5090e2 Initial load
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parents:
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   629
// Ops covered: {lds,ldu,st}{w,b,h}, {ld,st}{d,x}
489c9b5090e2 Initial load
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   630
//
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   631
class NativeMovRegMem;
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   632
inline NativeMovRegMem* nativeMovRegMem_at (address address);
489c9b5090e2 Initial load
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   633
class NativeMovRegMem: public NativeInstruction {
489c9b5090e2 Initial load
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   634
 public:
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   635
  enum Sparc_specific_constants {
489c9b5090e2 Initial load
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parents:
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   636
    op3_mask_ld = 1 << Assembler::lduw_op3 |
489c9b5090e2 Initial load
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parents:
diff changeset
   637
                  1 << Assembler::ldub_op3 |
489c9b5090e2 Initial load
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parents:
diff changeset
   638
                  1 << Assembler::lduh_op3 |
489c9b5090e2 Initial load
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parents:
diff changeset
   639
                  1 << Assembler::ldd_op3 |
489c9b5090e2 Initial load
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parents:
diff changeset
   640
                  1 << Assembler::ldsw_op3 |
489c9b5090e2 Initial load
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parents:
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   641
                  1 << Assembler::ldsb_op3 |
489c9b5090e2 Initial load
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parents:
diff changeset
   642
                  1 << Assembler::ldsh_op3 |
489c9b5090e2 Initial load
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parents:
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   643
                  1 << Assembler::ldx_op3,
489c9b5090e2 Initial load
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parents:
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   644
    op3_mask_st = 1 << Assembler::stw_op3 |
489c9b5090e2 Initial load
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parents:
diff changeset
   645
                  1 << Assembler::stb_op3 |
489c9b5090e2 Initial load
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parents:
diff changeset
   646
                  1 << Assembler::sth_op3 |
489c9b5090e2 Initial load
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parents:
diff changeset
   647
                  1 << Assembler::std_op3 |
489c9b5090e2 Initial load
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parents:
diff changeset
   648
                  1 << Assembler::stx_op3,
489c9b5090e2 Initial load
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parents:
diff changeset
   649
    op3_ldst_int_limit = Assembler::ldf_op3,
489c9b5090e2 Initial load
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parents:
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   650
    op3_mask_ldf = 1 << (Assembler::ldf_op3  - op3_ldst_int_limit) |
489c9b5090e2 Initial load
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parents:
diff changeset
   651
                   1 << (Assembler::lddf_op3 - op3_ldst_int_limit),
489c9b5090e2 Initial load
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parents:
diff changeset
   652
    op3_mask_stf = 1 << (Assembler::stf_op3  - op3_ldst_int_limit) |
489c9b5090e2 Initial load
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parents:
diff changeset
   653
                   1 << (Assembler::stdf_op3 - op3_ldst_int_limit),
489c9b5090e2 Initial load
duke
parents:
diff changeset
   654
489c9b5090e2 Initial load
duke
parents:
diff changeset
   655
    offset_width    = 13,
489c9b5090e2 Initial load
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parents:
diff changeset
   656
    sethi_offset    = 0,
489c9b5090e2 Initial load
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parents:
diff changeset
   657
#ifdef _LP64
489c9b5090e2 Initial load
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parents:
diff changeset
   658
    add_offset      = 7 * BytesPerInstWord,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   659
#else
489c9b5090e2 Initial load
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parents:
diff changeset
   660
    add_offset      = 4,
489c9b5090e2 Initial load
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parents:
diff changeset
   661
#endif
489c9b5090e2 Initial load
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parents:
diff changeset
   662
    ldst_offset     = add_offset + BytesPerInstWord
489c9b5090e2 Initial load
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parents:
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   663
  };
489c9b5090e2 Initial load
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parents:
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   664
  bool is_immediate() const {
489c9b5090e2 Initial load
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parents:
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   665
    // check if instruction is ld* [reg + offset], reg or st* reg, [reg + offset]
489c9b5090e2 Initial load
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parents:
diff changeset
   666
    int i0 = long_at(0);
489c9b5090e2 Initial load
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parents:
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   667
    return (is_op(i0, Assembler::ldst_op));
489c9b5090e2 Initial load
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parents:
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   668
  }
489c9b5090e2 Initial load
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parents:
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   669
489c9b5090e2 Initial load
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parents:
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   670
  address instruction_address() const           { return addr_at(0); }
489c9b5090e2 Initial load
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parents:
diff changeset
   671
  address next_instruction_address() const      {
489c9b5090e2 Initial load
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parents:
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   672
#ifdef _LP64
489c9b5090e2 Initial load
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parents:
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   673
    return addr_at(is_immediate() ? 4 : (7 * BytesPerInstWord));
489c9b5090e2 Initial load
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parents:
diff changeset
   674
#else
489c9b5090e2 Initial load
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parents:
diff changeset
   675
    return addr_at(is_immediate() ? 4 : 12);
489c9b5090e2 Initial load
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parents:
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   676
#endif
489c9b5090e2 Initial load
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parents:
diff changeset
   677
  }
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parents:
diff changeset
   678
  intptr_t   offset() const                             {
489c9b5090e2 Initial load
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parents:
diff changeset
   679
     return is_immediate()? inv_simm(long_at(0), offset_width) :
489c9b5090e2 Initial load
duke
parents:
diff changeset
   680
                            nativeMovConstReg_at(addr_at(0))->data();
489c9b5090e2 Initial load
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parents:
diff changeset
   681
  }
489c9b5090e2 Initial load
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parents:
diff changeset
   682
  void  set_offset(intptr_t x) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   683
    if (is_immediate()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   684
      guarantee(fits_in_simm(x, offset_width), "data block offset overflow");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   685
      set_long_at(0, set_simm(long_at(0), x, offset_width));
489c9b5090e2 Initial load
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parents:
diff changeset
   686
    } else
489c9b5090e2 Initial load
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parents:
diff changeset
   687
      nativeMovConstReg_at(addr_at(0))->set_data(x);
489c9b5090e2 Initial load
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parents:
diff changeset
   688
  }
489c9b5090e2 Initial load
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parents:
diff changeset
   689
489c9b5090e2 Initial load
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parents:
diff changeset
   690
  void  add_offset_in_bytes(intptr_t radd_offset)     {
489c9b5090e2 Initial load
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parents:
diff changeset
   691
      set_offset (offset() + radd_offset);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   692
  }
489c9b5090e2 Initial load
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parents:
diff changeset
   693
489c9b5090e2 Initial load
duke
parents:
diff changeset
   694
  void  copy_instruction_to(address new_instruction_address);
489c9b5090e2 Initial load
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parents:
diff changeset
   695
489c9b5090e2 Initial load
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parents:
diff changeset
   696
  void verify();
489c9b5090e2 Initial load
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parents:
diff changeset
   697
  void print ();
489c9b5090e2 Initial load
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parents:
diff changeset
   698
489c9b5090e2 Initial load
duke
parents:
diff changeset
   699
  // unit test stuff
489c9b5090e2 Initial load
duke
parents:
diff changeset
   700
  static void test();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   701
489c9b5090e2 Initial load
duke
parents:
diff changeset
   702
 private:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   703
  friend inline NativeMovRegMem* nativeMovRegMem_at (address address) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   704
    NativeMovRegMem* test = (NativeMovRegMem*)address;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   705
    #ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   706
      test->verify();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   707
    #endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   708
    return test;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   709
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   710
};
489c9b5090e2 Initial load
duke
parents:
diff changeset
   711
489c9b5090e2 Initial load
duke
parents:
diff changeset
   712
489c9b5090e2 Initial load
duke
parents:
diff changeset
   713
// An interface for accessing/manipulating native memory ops
489c9b5090e2 Initial load
duke
parents:
diff changeset
   714
//      ld* [reg + offset], reg
489c9b5090e2 Initial load
duke
parents:
diff changeset
   715
//      st* reg, [reg + offset]
489c9b5090e2 Initial load
duke
parents:
diff changeset
   716
//      sethi %hi(imm), reg; nop; add reg, %lo(imm), reg; ld* [reg1 + reg], reg2
489c9b5090e2 Initial load
duke
parents:
diff changeset
   717
//      sethi %hi(imm), reg; nop; add reg, %lo(imm), reg; st* reg2, [reg1 + reg]
489c9b5090e2 Initial load
duke
parents:
diff changeset
   718
// Ops covered: {lds,ldu,st}{w,b,h}, {ld,st}{d,x}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   719
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   720
// Note that it is identical to NativeMovRegMem with the exception of a nop between the
489c9b5090e2 Initial load
duke
parents:
diff changeset
   721
// sethi and the add.  The nop is required to be in the delay slot of the call instruction
489c9b5090e2 Initial load
duke
parents:
diff changeset
   722
// which overwrites the sethi during patching.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   723
class NativeMovRegMemPatching;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   724
inline NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   725
class NativeMovRegMemPatching: public NativeInstruction {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   726
 public:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   727
  enum Sparc_specific_constants {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   728
    op3_mask_ld = 1 << Assembler::lduw_op3 |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   729
                  1 << Assembler::ldub_op3 |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   730
                  1 << Assembler::lduh_op3 |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   731
                  1 << Assembler::ldd_op3 |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   732
                  1 << Assembler::ldsw_op3 |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   733
                  1 << Assembler::ldsb_op3 |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   734
                  1 << Assembler::ldsh_op3 |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   735
                  1 << Assembler::ldx_op3,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   736
    op3_mask_st = 1 << Assembler::stw_op3 |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   737
                  1 << Assembler::stb_op3 |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   738
                  1 << Assembler::sth_op3 |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   739
                  1 << Assembler::std_op3 |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   740
                  1 << Assembler::stx_op3,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   741
    op3_ldst_int_limit = Assembler::ldf_op3,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   742
    op3_mask_ldf = 1 << (Assembler::ldf_op3  - op3_ldst_int_limit) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   743
                   1 << (Assembler::lddf_op3 - op3_ldst_int_limit),
489c9b5090e2 Initial load
duke
parents:
diff changeset
   744
    op3_mask_stf = 1 << (Assembler::stf_op3  - op3_ldst_int_limit) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   745
                   1 << (Assembler::stdf_op3 - op3_ldst_int_limit),
489c9b5090e2 Initial load
duke
parents:
diff changeset
   746
489c9b5090e2 Initial load
duke
parents:
diff changeset
   747
    offset_width    = 13,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   748
    sethi_offset    = 0,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   749
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
   750
    nop_offset      = 7 * BytesPerInstWord,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   751
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   752
    nop_offset      = 4,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   753
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   754
    add_offset      = nop_offset + BytesPerInstWord,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   755
    ldst_offset     = add_offset + BytesPerInstWord
489c9b5090e2 Initial load
duke
parents:
diff changeset
   756
  };
489c9b5090e2 Initial load
duke
parents:
diff changeset
   757
  bool is_immediate() const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   758
    // check if instruction is ld* [reg + offset], reg or st* reg, [reg + offset]
489c9b5090e2 Initial load
duke
parents:
diff changeset
   759
    int i0 = long_at(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   760
    return (is_op(i0, Assembler::ldst_op));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   761
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   762
489c9b5090e2 Initial load
duke
parents:
diff changeset
   763
  address instruction_address() const           { return addr_at(0); }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   764
  address next_instruction_address() const      {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   765
    return addr_at(is_immediate()? 4 : 16);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   766
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   767
  int   offset() const                          {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   768
     return is_immediate()? inv_simm(long_at(0), offset_width) :
489c9b5090e2 Initial load
duke
parents:
diff changeset
   769
                            nativeMovConstRegPatching_at(addr_at(0))->data();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   770
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   771
  void  set_offset(int x) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   772
    if (is_immediate()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   773
      guarantee(fits_in_simm(x, offset_width), "data block offset overflow");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   774
      set_long_at(0, set_simm(long_at(0), x, offset_width));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   775
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   776
    else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   777
      nativeMovConstRegPatching_at(addr_at(0))->set_data(x);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   778
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   779
489c9b5090e2 Initial load
duke
parents:
diff changeset
   780
  void  add_offset_in_bytes(intptr_t radd_offset)     {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   781
      set_offset (offset() + radd_offset);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   782
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   783
489c9b5090e2 Initial load
duke
parents:
diff changeset
   784
  void  copy_instruction_to(address new_instruction_address);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   785
489c9b5090e2 Initial load
duke
parents:
diff changeset
   786
  void verify();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   787
  void print ();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   788
489c9b5090e2 Initial load
duke
parents:
diff changeset
   789
  // unit test stuff
489c9b5090e2 Initial load
duke
parents:
diff changeset
   790
  static void test();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   791
489c9b5090e2 Initial load
duke
parents:
diff changeset
   792
 private:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   793
  friend inline NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   794
    NativeMovRegMemPatching* test = (NativeMovRegMemPatching*)address;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   795
    #ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   796
      test->verify();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   797
    #endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   798
    return test;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   799
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   800
};
489c9b5090e2 Initial load
duke
parents:
diff changeset
   801
489c9b5090e2 Initial load
duke
parents:
diff changeset
   802
489c9b5090e2 Initial load
duke
parents:
diff changeset
   803
// An interface for accessing/manipulating native jumps
489c9b5090e2 Initial load
duke
parents:
diff changeset
   804
//      jump_to addr
489c9b5090e2 Initial load
duke
parents:
diff changeset
   805
//      == sethi %hi22(addr), temp ;  jumpl reg, %lo10(addr), G0 ;  <delay>
489c9b5090e2 Initial load
duke
parents:
diff changeset
   806
//      jumpl_to addr, lreg
489c9b5090e2 Initial load
duke
parents:
diff changeset
   807
//      == sethi %hi22(addr), temp ;  jumpl reg, %lo10(addr), lreg ;  <delay>
489c9b5090e2 Initial load
duke
parents:
diff changeset
   808
class NativeJump;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   809
inline NativeJump* nativeJump_at(address address);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   810
class NativeJump: public NativeInstruction {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   811
 private:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   812
  void guarantee_displacement(int disp, int width) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   813
    guarantee(fits_in_simm(disp, width + 2), "branch displacement overflow");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   814
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   815
489c9b5090e2 Initial load
duke
parents:
diff changeset
   816
 public:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   817
  enum Sparc_specific_constants {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   818
    sethi_offset           = 0,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   819
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
   820
    jmpl_offset            = 7 * BytesPerInstWord,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   821
    instruction_size       = 9 * BytesPerInstWord  // includes delay slot
489c9b5090e2 Initial load
duke
parents:
diff changeset
   822
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   823
    jmpl_offset            = 1 * BytesPerInstWord,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   824
    instruction_size       = 3 * BytesPerInstWord  // includes delay slot
489c9b5090e2 Initial load
duke
parents:
diff changeset
   825
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   826
  };
489c9b5090e2 Initial load
duke
parents:
diff changeset
   827
489c9b5090e2 Initial load
duke
parents:
diff changeset
   828
  address instruction_address() const       { return addr_at(0); }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   829
  address next_instruction_address() const  { return addr_at(instruction_size); }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   830
489c9b5090e2 Initial load
duke
parents:
diff changeset
   831
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
   832
  address jump_destination() const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   833
    return (address) data64(instruction_address(), long_at(jmpl_offset));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   834
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   835
  void set_jump_destination(address dest) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   836
    set_data64_sethi( instruction_address(), (intptr_t)dest);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   837
    set_long_at(jmpl_offset,  set_data32_simm13( long_at(jmpl_offset),  (intptr_t)dest));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   838
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   839
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   840
  address jump_destination() const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   841
    return (address) data32(long_at(sethi_offset), long_at(jmpl_offset));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   842
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   843
  void set_jump_destination(address dest) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   844
    set_long_at(sethi_offset, set_data32_sethi(  long_at(sethi_offset), (intptr_t)dest));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   845
    set_long_at(jmpl_offset,  set_data32_simm13( long_at(jmpl_offset),  (intptr_t)dest));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   846
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   847
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   848
489c9b5090e2 Initial load
duke
parents:
diff changeset
   849
  // Creation
489c9b5090e2 Initial load
duke
parents:
diff changeset
   850
  friend inline NativeJump* nativeJump_at(address address) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   851
    NativeJump* jump = (NativeJump*)address;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   852
    #ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   853
      jump->verify();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   854
    #endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   855
    return jump;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   856
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   857
489c9b5090e2 Initial load
duke
parents:
diff changeset
   858
  void verify();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   859
  void print();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   860
489c9b5090e2 Initial load
duke
parents:
diff changeset
   861
  // Unit testing stuff
489c9b5090e2 Initial load
duke
parents:
diff changeset
   862
  static void test();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   863
489c9b5090e2 Initial load
duke
parents:
diff changeset
   864
  // Insertion of native jump instruction
489c9b5090e2 Initial load
duke
parents:
diff changeset
   865
  static void insert(address code_pos, address entry);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   866
  // MT-safe insertion of native jump at verified method entry
489c9b5090e2 Initial load
duke
parents:
diff changeset
   867
  static void check_verified_entry_alignment(address entry, address verified_entry) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   868
    // nothing to do for sparc.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   869
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   870
  static void patch_verified_entry(address entry, address verified_entry, address dest);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   871
};
489c9b5090e2 Initial load
duke
parents:
diff changeset
   872
489c9b5090e2 Initial load
duke
parents:
diff changeset
   873
489c9b5090e2 Initial load
duke
parents:
diff changeset
   874
489c9b5090e2 Initial load
duke
parents:
diff changeset
   875
// Despite the name, handles only simple branches.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   876
class NativeGeneralJump;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   877
inline NativeGeneralJump* nativeGeneralJump_at(address address);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   878
class NativeGeneralJump: public NativeInstruction {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   879
 public:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   880
  enum Sparc_specific_constants {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   881
    instruction_size                   = 8
489c9b5090e2 Initial load
duke
parents:
diff changeset
   882
  };
489c9b5090e2 Initial load
duke
parents:
diff changeset
   883
489c9b5090e2 Initial load
duke
parents:
diff changeset
   884
  address instruction_address() const       { return addr_at(0); }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   885
  address jump_destination()    const       { return addr_at(0) + branch_destination_offset(long_at(0)); }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   886
  void set_jump_destination(address dest) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   887
    int patched_instr = patch_branch_destination_offset(dest - addr_at(0), long_at(0));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   888
    set_long_at(0, patched_instr);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   889
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   890
  NativeInstruction *delay_slot_instr() { return nativeInstruction_at(addr_at(4));}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   891
  void fill_delay_slot(int instr) { set_long_at(4, instr);}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   892
  Assembler::Condition condition() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   893
    int x = long_at(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   894
    return (Assembler::Condition) Assembler::inv_cond(x);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   895
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   896
489c9b5090e2 Initial load
duke
parents:
diff changeset
   897
  // Creation
489c9b5090e2 Initial load
duke
parents:
diff changeset
   898
  friend inline NativeGeneralJump* nativeGeneralJump_at(address address) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   899
    NativeGeneralJump* jump = (NativeGeneralJump*)(address);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   900
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   901
      jump->verify();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   902
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   903
    return jump;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   904
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   905
489c9b5090e2 Initial load
duke
parents:
diff changeset
   906
  // Insertion of native general jump instruction
489c9b5090e2 Initial load
duke
parents:
diff changeset
   907
  static void insert_unconditional(address code_pos, address entry);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   908
  static void replace_mt_safe(address instr_addr, address code_buffer);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   909
489c9b5090e2 Initial load
duke
parents:
diff changeset
   910
  void verify();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   911
};
489c9b5090e2 Initial load
duke
parents:
diff changeset
   912
489c9b5090e2 Initial load
duke
parents:
diff changeset
   913
489c9b5090e2 Initial load
duke
parents:
diff changeset
   914
class NativeIllegalInstruction: public NativeInstruction {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   915
 public:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   916
  enum Sparc_specific_constants {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   917
    instruction_size            =    4
489c9b5090e2 Initial load
duke
parents:
diff changeset
   918
  };
489c9b5090e2 Initial load
duke
parents:
diff changeset
   919
489c9b5090e2 Initial load
duke
parents:
diff changeset
   920
  // Insert illegal opcode as specific address
489c9b5090e2 Initial load
duke
parents:
diff changeset
   921
  static void insert(address code_pos);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   922
};
7397
5b173b4ca846 6989984: Use standard include model for Hospot
stefank
parents: 5547
diff changeset
   923
5b173b4ca846 6989984: Use standard include model for Hospot
stefank
parents: 5547
diff changeset
   924
#endif // CPU_SPARC_VM_NATIVEINST_SPARC_HPP