/*

 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.

 * Copyright 2012, 2015 SAP AG. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#include "precompiled.hpp"

#include "asm/assembler.inline.hpp"

#include "asm/macroAssembler.inline.hpp"

#include "compiler/disassembler.hpp"

#include "memory/resourceArea.hpp"

#include "runtime/java.hpp"

#include "runtime/os.hpp"

#include "runtime/stubCodeGenerator.hpp"

#include "utilities/defaultStream.hpp"

#include "utilities/globalDefinitions.hpp"

#include "vm_version_ppc.hpp"

# include <sys/sysinfo.h>

bool VM_Version::_is_determine_features_test_running = false;

#define MSG(flag)   \

  if (flag && !FLAG_IS_DEFAULT(flag))                                  \

      jio_fprintf(defaultStream::error_stream(),                       \

                  "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \

                  "         -XX:+" #flag " will be disabled!\n");

void VM_Version::initialize() {

  // Test which instructions are supported and measure cache line size.

  determine_features();

  // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.

  if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {

    if (VM_Version::has_tcheck() && VM_Version::has_lqarx()) {

      FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8);

    } else if (VM_Version::has_popcntw()) {

      FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);

    } else if (VM_Version::has_cmpb()) {

      FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);

    } else if (VM_Version::has_popcntb()) {

      FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);

    } else {

      FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);

    }

  }

  bool PowerArchitecturePPC64_ok = false;

  switch (PowerArchitecturePPC64) {

    case 8: if (!VM_Version::has_tcheck() ) break;

            if (!VM_Version::has_lqarx()  ) break;

    case 7: if (!VM_Version::has_popcntw()) break;

    case 6: if (!VM_Version::has_cmpb()   ) break;

    case 5: if (!VM_Version::has_popcntb()) break;

    case 0: PowerArchitecturePPC64_ok = true; break;

    default: break;

  }

  guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to "

            UINTX_FORMAT " on this machine", PowerArchitecturePPC64);

  // Power 8: Configure Data Stream Control Register.

  if (PowerArchitecturePPC64 >= 8) {

    config_dscr();

  }

  if (!UseSIGTRAP) {

    MSG(TrapBasedICMissChecks);

    MSG(TrapBasedNotEntrantChecks);

    MSG(TrapBasedNullChecks);

    FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);

    FLAG_SET_ERGO(bool, TrapBasedNullChecks,       false);

    FLAG_SET_ERGO(bool, TrapBasedICMissChecks,     false);

  }

#ifdef COMPILER2

  if (!UseSIGTRAP) {

    MSG(TrapBasedRangeChecks);

    FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);

  }

  // On Power6 test for section size.

  if (PowerArchitecturePPC64 == 6) {

    determine_section_size();

  // TODO: PPC port } else {

  // TODO: PPC port PdScheduling::power6SectorSize = 0x20;

  }

  MaxVectorSize = 8;

#endif

  // Create and print feature-string.

  char buf[(num_features+1) * 16]; // Max 16 chars per feature.

  jio_snprintf(buf, sizeof(buf),

               "ppc64%s%s%s%s%s%s%s%s%s%s%s%s",

               (has_fsqrt()   ? " fsqrt"   : ""),

               (has_isel()    ? " isel"    : ""),

               (has_lxarxeh() ? " lxarxeh" : ""),

               (has_cmpb()    ? " cmpb"    : ""),

               //(has_mftgpr()? " mftgpr"  : ""),

               (has_popcntb() ? " popcntb" : ""),

               (has_popcntw() ? " popcntw" : ""),

               (has_fcfids()  ? " fcfids"  : ""),

               (has_vand()    ? " vand"    : ""),

               (has_lqarx()   ? " lqarx"   : ""),

               (has_vcipher() ? " vcipher" : ""),

               (has_vpmsumb() ? " vpmsumb" : ""),

               (has_tcheck()  ? " tcheck"  : "")

               // Make sure number of %s matches num_features!

              );

  _features_string = os::strdup(buf);

  if (Verbose) {

    print_features();

  }

  // PPC64 supports 8-byte compare-exchange operations (see

  // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr)

  // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).

  _supports_cx8 = true;

  // Used by C1.

  _supports_atomic_getset4 = true;

  _supports_atomic_getadd4 = true;

  _supports_atomic_getset8 = true;

  _supports_atomic_getadd8 = true;

  UseSSE = 0; // Only on x86 and x64

  intx cache_line_size = L1_data_cache_line_size();

  if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;

  if (AllocatePrefetchStyle == 4) {

    AllocatePrefetchStepSize = cache_line_size; // Need exact value.

    if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.

    if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?

  } else {

    if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;

    if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.

    if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?

  }

  assert(AllocatePrefetchLines > 0, "invalid value");

  if (AllocatePrefetchLines < 1) { // Set valid value in product VM.

    AllocatePrefetchLines = 1; // Conservative value.

  }

  if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {

    AllocatePrefetchStyle = 1; // Fall back if inappropriate.

  }

  assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");

  // Implementation does not use any of the vector instructions

  // available with Power8. Their exploitation is still pending.

  if (!UseCRC32Intrinsics) {

    if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {

      FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);

    }

  }

  if (UseCRC32CIntrinsics) {

    if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics))

      warning("CRC32C intrinsics are not available on this CPU");

    FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);

  }

  // The AES intrinsic stubs require AES instruction support.

  if (UseAES) {

    warning("AES instructions are not available on this CPU");

    FLAG_SET_DEFAULT(UseAES, false);

  }

  if (UseAESIntrinsics) {

    if (!FLAG_IS_DEFAULT(UseAESIntrinsics))

      warning("AES intrinsics are not available on this CPU");

    FLAG_SET_DEFAULT(UseAESIntrinsics, false);

  }

  if (UseGHASHIntrinsics) {

    warning("GHASH intrinsics are not available on this CPU");

    FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);

  }

  if (UseSHA) {

    warning("SHA instructions are not available on this CPU");

    FLAG_SET_DEFAULT(UseSHA, false);

  }

  if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {

    warning("SHA intrinsics are not available on this CPU");

    FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);

    FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);

    FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);

  }

  if (UseAdler32Intrinsics) {

    warning("Adler32Intrinsics not available on this CPU.");

    FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);

  }

  if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {

    UseMultiplyToLenIntrinsic = true;

  }

  if (UseVectorizedMismatchIntrinsic) {

    warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");

    FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);

  }

  // Adjust RTM (Restricted Transactional Memory) flags.

  if (UseRTMLocking) {

    // If CPU or OS are too old:

    // Can't continue because UseRTMLocking affects UseBiasedLocking flag

    // setting during arguments processing. See use_biased_locking().

    // VM_Version_init() is executed after UseBiasedLocking is used

    // in Thread::allocate().

    if (!has_tcheck()) {

      vm_exit_during_initialization("RTM instructions are not available on this CPU");

    }

    bool os_too_old = true;

#ifdef AIX

    if (os::Aix::os_version() >= 0x0701031e) { // at least AIX 7.1.3.30

      os_too_old = false;

    }

#endif

#ifdef linux

    // TODO: check kernel version (we currently have too old versions only)

#endif

    if (os_too_old) {

      vm_exit_during_initialization("RTM is not supported on this OS version.");

    }

  }

  if (UseRTMLocking) {

#if INCLUDE_RTM_OPT

    if (!UnlockExperimentalVMOptions) {

      vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. "

                                    "It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");

    } else {

      warning("UseRTMLocking is only available as experimental option on this platform.");

    }

    if (!FLAG_IS_CMDLINE(UseRTMLocking)) {

      // RTM locking should be used only for applications with

      // high lock contention. For now we do not use it by default.

      vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");

    }

    if (!is_power_of_2(RTMTotalCountIncrRate)) {

      warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64");

      FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64);

    }

    if (RTMAbortRatio < 0 || RTMAbortRatio > 100) {

      warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50");

      FLAG_SET_DEFAULT(RTMAbortRatio, 50);

    }

    guarantee(RTMSpinLoopCount > 0, "unsupported");

#else

    // Only C2 does RTM locking optimization.

    // Can't continue because UseRTMLocking affects UseBiasedLocking flag

    // setting during arguments processing. See use_biased_locking().

    vm_exit_during_initialization("RTM locking optimization is not supported in this VM");

#endif

  } else { // !UseRTMLocking

    if (UseRTMForStackLocks) {

      if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {

        warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");

      }

      FLAG_SET_DEFAULT(UseRTMForStackLocks, false);

    }

    if (UseRTMDeopt) {

      FLAG_SET_DEFAULT(UseRTMDeopt, false);

    }

    if (PrintPreciseRTMLockingStatistics) {

      FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);

    }

  }

  // This machine allows unaligned memory accesses

  if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {

    FLAG_SET_DEFAULT(UseUnalignedAccesses, true);

  }

}

bool VM_Version::use_biased_locking() {

#if INCLUDE_RTM_OPT

  // RTM locking is most useful when there is high lock contention and

  // low data contention. With high lock contention the lock is usually

  // inflated and biased locking is not suitable for that case.

  // RTM locking code requires that biased locking is off.

  // Note: we can't switch off UseBiasedLocking in get_processor_features()

  // because it is used by Thread::allocate() which is called before

  // VM_Version::initialize().

  if (UseRTMLocking && UseBiasedLocking) {

    if (FLAG_IS_DEFAULT(UseBiasedLocking)) {

      FLAG_SET_DEFAULT(UseBiasedLocking, false);

    } else {

      warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );

      UseBiasedLocking = false;

    }

  }

#endif

  return UseBiasedLocking;

}

void VM_Version::print_features() {

  tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size());

}

#ifdef COMPILER2

// Determine section size on power6: If section size is 8 instructions,

// there should be a difference between the two testloops of ~15 %. If

// no difference is detected the section is assumed to be 32 instructions.

void VM_Version::determine_section_size() {

  int unroll = 80;

  const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;

  // Allocate space for the code.

  ResourceMark rm;

  CodeBuffer cb("detect_section_size", code_size, 0);

  MacroAssembler* a = new MacroAssembler(&cb);

  uint32_t *code = (uint32_t *)a->pc();

  // Emit code.

  void (*test1)() = (void(*)())(void *)a->function_entry();

  Label l1;

  a->li(R4, 1);

  a->sldi(R4, R4, 28);

  a->b(l1);

  a->align(CodeEntryAlignment);

  a->bind(l1);

  for (int i = 0; i < unroll; i++) {

    // Schleife 1

    // ------- sector 0 ------------

    // ;; 0

    a->nop();                   // 1

    a->fpnop0();                // 2

    a->fpnop1();                // 3

    a->addi(R4,R4, -1); // 4

    // ;;  1

    a->nop();                   // 5

    a->fmr(F6, F6);             // 6

    a->fmr(F7, F7);             // 7

    a->endgroup();              // 8

    // ------- sector 8 ------------

    // ;;  2

    a->nop();                   // 9

    a->nop();                   // 10

    a->fmr(F8, F8);             // 11

    a->fmr(F9, F9);             // 12

    // ;;  3

    a->nop();                   // 13

    a->fmr(F10, F10);           // 14

    a->fmr(F11, F11);           // 15

    a->endgroup();              // 16

    // -------- sector 16 -------------

    // ;;  4

    a->nop();                   // 17

    a->nop();                   // 18

    a->fmr(F15, F15);           // 19

    a->fmr(F16, F16);           // 20

    // ;;  5

    a->nop();                   // 21

    a->fmr(F17, F17);           // 22

    a->fmr(F18, F18);           // 23

    a->endgroup();              // 24

    // ------- sector 24  ------------

    // ;;  6

    a->nop();                   // 25

    a->nop();                   // 26

    a->fmr(F19, F19);           // 27

    a->fmr(F20, F20);           // 28

    // ;;  7

    a->nop();                   // 29

    a->fmr(F21, F21);           // 30

    a->fmr(F22, F22);           // 31

    a->brnop0();                // 32

    // ------- sector 32 ------------

  }

  // ;; 8

  a->cmpdi(CCR0, R4, unroll);   // 33

  a->bge(CCR0, l1);             // 34

  a->blr();

  // Emit code.

  void (*test2)() = (void(*)())(void *)a->function_entry();

  // uint32_t *code = (uint32_t *)a->pc();

  Label l2;

  a->li(R4, 1);

  a->sldi(R4, R4, 28);

  a->b(l2);

  a->align(CodeEntryAlignment);

  a->bind(l2);

  for (int i = 0; i < unroll; i++) {

    // Schleife 2

    // ------- sector 0 ------------

    // ;; 0

    a->brnop0();                  // 1

    a->nop();                     // 2

    //a->cmpdi(CCR0, R4, unroll);

    a->fpnop0();                  // 3

    a->fpnop1();                  // 4

    a->addi(R4,R4, -1);           // 5

    // ;; 1

    a->nop();                     // 6

    a->fmr(F6, F6);               // 7

    a->fmr(F7, F7);               // 8

    // ------- sector 8 ---------------

    // ;; 2

    a->endgroup();                // 9

    // ;; 3

    a->nop();                     // 10

    a->nop();                     // 11

    a->fmr(F8, F8);               // 12

    // ;; 4

    a->fmr(F9, F9);               // 13

    a->nop();                     // 14

    a->fmr(F10, F10);             // 15

    // ;; 5

    a->fmr(F11, F11);             // 16

    // -------- sector 16 -------------

    // ;; 6

    a->endgroup();                // 17

    // ;; 7

    a->nop();                     // 18

    a->nop();                     // 19

    a->fmr(F15, F15);             // 20

    // ;; 8

    a->fmr(F16, F16);             // 21

    a->nop();                     // 22

    a->fmr(F17, F17);             // 23

    // ;; 9

    a->fmr(F18, F18);             // 24

    // -------- sector 24 -------------

    // ;; 10

    a->endgroup();                // 25

    // ;; 11

    a->nop();                     // 26

    a->nop();                     // 27

    a->fmr(F19, F19);             // 28

    // ;; 12

    a->fmr(F20, F20);             // 29

    a->nop();                     // 30

    a->fmr(F21, F21);             // 31

    // ;; 13

    a->fmr(F22, F22);             // 32

  }

  // -------- sector 32 -------------

  // ;; 14

  a->cmpdi(CCR0, R4, unroll); // 33