* Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.

inline void Assembler::avoid_pipeline_stall() {

#ifdef VALIDATE_PIPELINE

  if (_hazard_state == PcHazard) {

    assert(is_cbcond_before() || is_rdpc_before(), "PC-hazard not preceeded by CBCOND or RDPC.");

    assert_no_delay("Must not have PC-hazard state in delay-slot.");

    _hazard_state = NoHazard;

  }

#endif

  bool post_cond = is_cbcond_before();

  bool post_rdpc = is_rdpc_before();

  if (post_cond || post_rdpc) {

    nop();

#ifdef VALIDATE_PIPELINE

    if (_hazard_state != PcHazard) {

      assert(post_cond, "CBCOND before when no hazard @0x%p\n", pc());

      assert(post_rdpc, "RDPC before when no hazard @0x%p\n", pc());

    }

#endif

#ifdef VALIDATE_PIPELINE

  guarantee(_delay_state != AtDelay, "Use delayed() when filling delay-slot");

  _delay_state = NoDelay;

#endif

#ifdef VALIDATE_PIPELINE

  _hazard_state = NoHazard;

#endif

inline void Assembler::emit_data(int x, RelocationHolder const &rspec) {

inline void Assembler::add(Register s1, Register s2, Register d) {

  emit_int32(op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | rs2(s2));

}

inline void Assembler::add(Register s1, int simm13a, Register d) {

  emit_int32(op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));

}

inline void Assembler::addcc(Register s1, Register s2, Register d) {

  emit_int32(op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2));

}

inline void Assembler::addcc(Register s1, int simm13a, Register d) {

  emit_int32(op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));

}

inline void Assembler::addc(Register s1, Register s2, Register d) {

  emit_int32(op(arith_op) | rd(d) | op3(addc_op3) | rs1(s1) | rs2(s2));

}

inline void Assembler::addc(Register s1, int simm13a, Register d) {

  emit_int32(op(arith_op) | rd(d) | op3(addc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));

}

inline void Assembler::addccc(Register s1, Register s2, Register d) {

  emit_int32(op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2));

}

inline void Assembler::addccc(Register s1, int simm13a, Register d) {

  emit_int32(op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));

}

inline void Assembler::aes_eround01(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) {

  aes_only();

  emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_op5) | fs2(s2, FloatRegisterImpl::D));

}

inline void Assembler::aes_eround23(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) {

  aes_only();

  emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_op5) | fs2(s2, FloatRegisterImpl::D));

}

inline void Assembler::aes_dround01(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) {

  aes_only();

  emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_op5) | fs2(s2, FloatRegisterImpl::D));

}

inline void Assembler::aes_dround23(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) {

  aes_only();

  emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_op5) | fs2(s2, FloatRegisterImpl::D));

}

inline void Assembler::aes_eround01_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) {

  aes_only();

  emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_l_op5) | fs2(s2, FloatRegisterImpl::D));

}

inline void Assembler::aes_eround23_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) {

  aes_only();

  emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_l_op5) | fs2(s2, FloatRegisterImpl::D));

}

inline void Assembler::aes_dround01_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) {

  aes_only();

  emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_l_op5) | fs2(s2, FloatRegisterImpl::D));

}

inline void Assembler::aes_dround23_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) {

  aes_only();

  emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_l_op5) | fs2(s2, FloatRegisterImpl::D));

}

inline void Assembler::aes_kexpand1(FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d) {

  aes_only();

  emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | u_field(imm5a, 13, 9) | op5(aes_kexpand1_op5) | fs2(s2, FloatRegisterImpl::D));

}

inline void Assembler::aes_kexpand0(FloatRegister s1, FloatRegister s2, FloatRegister d) {

  aes_only();

  emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand0_opf) | fs2(s2, FloatRegisterImpl::D));

}

inline void Assembler::aes_kexpand2(FloatRegister s1, FloatRegister s2, FloatRegister d) {

  aes_only();

  emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand2_opf) | fs2(s2, FloatRegisterImpl::D));

}

inline void Assembler::bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt) {

  avoid_pipeline_stall();

  cti();

  emit_data(op(branch_op) | annul(a) | cond(c) | op2(bpr_op2) | wdisp16(intptr_t(d), intptr_t(pc())) | predict(p) | rs1(s1), rt);

  induce_delay_slot();

}

inline void Assembler::bpr(RCondition c, bool a, Predict p, Register s1, Label &L) {

  // Note[+]: All assembly emit routines using the 'target()' branch back-patch

  //     resolver must call 'avoid_pipeline_stall()' prior to calling 'target()'

  //     (we must do so even though the call will be made, as here, in the above

  //     implementation of 'bpr()', invoked below). The reason is the assumption

  //     made in 'target()', where using the current PC as the address for back-

  //     patching prevents any additional code to be emitted _after_ the address

  //     has been set (implicitly) in order to refer to the correct instruction.

  avoid_pipeline_stall();

  bpr(c, a, p, s1, target(L));

}

inline void Assembler::fb(Condition c, bool a, address d, relocInfo::relocType rt) {

  v9_dep();

  avoid_pipeline_stall();

  cti();

  emit_data(op(branch_op) | annul(a) | cond(c) | op2(fb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt);

  induce_delay_slot();

}

inline void Assembler::fb(Condition c, bool a, Label &L) {

  avoid_pipeline_stall();

  fb(c, a, target(L));

}

inline void Assembler::fbp(Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt) {

  avoid_pipeline_stall();

  cti();

  emit_data(op(branch_op) | annul(a) | cond(c) | op2(fbp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt);

  induce_delay_slot();

}

inline void Assembler::fbp(Condition c, bool a, CC cc, Predict p, Label &L) {

  avoid_pipeline_stall();

  fbp(c, a, cc, p, target(L));

}

inline void Assembler::br(Condition c, bool a, address d, relocInfo::relocType rt) {

  v9_dep();

  avoid_pipeline_stall();

  cti();

  emit_data(op(branch_op) | annul(a) | cond(c) | op2(br_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt);

  induce_delay_slot();

}

inline void Assembler::br(Condition c, bool a, Label &L) {

  avoid_pipeline_stall();

  br(c, a, target(L));

}

inline void Assembler::bp(Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt) {

  avoid_pipeline_stall();

  cti();

  emit_data(op(branch_op) | annul(a) | cond(c) | op2(bp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt);

  induce_delay_slot();

}

inline void Assembler::bp(Condition c, bool a, CC cc, Predict p, Label &L) {

  avoid_pipeline_stall();

  bp(c, a, cc, p, target(L));

}

inline void Assembler::cbcond(Condition c, CC cc, Register s1, Register s2, Label &L) {

  avoid_pipeline_stall();

  cti();

  emit_data(op(branch_op) | cond_cbcond(c) | op2(bpr_op2) | branchcc(cc) | wdisp10(intptr_t(target(L)), intptr_t(pc())) | rs1(s1) | rs2(s2));

  induce_pc_hazard();

}

inline void Assembler::cbcond(Condition c, CC cc, Register s1, int simm5, Label &L) {

  avoid_pipeline_stall();

  cti();

  emit_data(op(branch_op) | cond_cbcond(c) | op2(bpr_op2) | branchcc(cc) | wdisp10(intptr_t(target(L)), intptr_t(pc())) | rs1(s1) | immed(true) | simm(simm5, 5));

  induce_pc_hazard();

}

inline void Assembler::call(address d, relocInfo::relocType rt) {

  avoid_pipeline_stall();

  cti();

  emit_data(op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rt);

  induce_delay_slot();

  assert(rt != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec");

}

inline void Assembler::call(Label &L, relocInfo::relocType rt) {

  avoid_pipeline_stall();

  call(target(L), rt);

}

inline void Assembler::call(address d, RelocationHolder const &rspec) {

  avoid_pipeline_stall();

  cti();

  emit_data(op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rspec);

  induce_delay_slot();

  assert(rspec.type() != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec");

}

inline void Assembler::casa(Register s1, Register s2, Register d, int ia) {

  emit_int32(op(ldst_op) | rd(d) | op3(casa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2));

}

inline void Assembler::casxa(Register s1, Register s2, Register d, int ia) {

  emit_int32(op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2));

}

inline void Assembler::udiv(Register s1, Register s2, Register d) {

  emit_int32(op(arith_op) | rd(d) | op3(udiv_op3) | rs1(s1) | rs2(s2));

}

inline void Assembler::udiv(Register s1, int simm13a, Register d) {

  emit_int32(op(arith_op) | rd(d) | op3(udiv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));

}

inline void Assembler::sdiv(Register s1, Register s2, Register d) {

  emit_int32(op(arith_op) | rd(d) | op3(sdiv_op3) | rs1(s1) | rs2(s2));

}

inline void Assembler::sdiv(Register s1, int simm13a, Register d) {

  emit_int32(op(arith_op) | rd(d) | op3(sdiv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));

}

inline void Assembler::udivcc(Register s1, Register s2, Register d) {

  emit_int32(op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2));

}

inline void Assembler::udivcc(Register s1, int simm13a, Register d) {

  emit_int32(op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));

}

inline void Assembler::sdivcc(Register s1, Register s2, Register d) {

  emit_int32(op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2));

}

inline void Assembler::sdivcc(Register s1, int simm13a, Register d) {

  emit_int32(op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));

}

inline void Assembler::done() {

  cti();

  emit_int32(op(arith_op) | fcn(0) | op3(done_op3));

}

inline void Assembler::retry() {

  cti();

  emit_int32(op(arith_op) | fcn(1) | op3(retry_op3));

}

inline void Assembler::fadd(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d) {

  emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w));

}

inline void Assembler::fsub(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d) {

  emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w));

}

inline void Assembler::fcmp(FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) {

  emit_int32(op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w));

}

inline void Assembler::fcmpe(FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) {

  emit_int32(op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w));

}

inline void Assembler::ftox(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) {

  emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w));

}

inline void Assembler::ftoi(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) {

  emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w));

}

inline void Assembler::ftof(FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d) {

  emit_int32(op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw));

}

inline void Assembler::fxtof(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) {

  emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, FloatRegisterImpl::D));

}

inline void Assembler::fitof(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) {

  emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, FloatRegisterImpl::S));

}

inline void Assembler::fmov(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) {

  emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w));

}

inline void Assembler::fneg(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) {

  emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w));

}

inline void Assembler::fabs(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) {

  emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w));

}

inline void Assembler::fmul(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d) {

  emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w));

}

inline void Assembler::fmul(FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d) {

  emit_int32(op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw));

}

inline void Assembler::fdiv(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d) {

  emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w));

}

inline void Assembler::fxor(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d) {

  vis1_only();

  emit_int32(op(arith_op) | fd(d, w) | op3(flog3_op3) | fs1(s1, w) | opf(0x6E - w) | fs2(s2, w));

}

inline void Assembler::fsqrt(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) {

  emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w));

}

inline void Assembler::flush(Register s1, Register s2) {

  emit_int32(op(arith_op) | op3(flush_op3) | rs1(s1) | rs2(s2));

}

inline void Assembler::flush(Register s1, int simm13a) {

  emit_data(op(arith_op) | op3(flush_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));

}

inline void Assembler::flushw() {

  emit_int32(op(arith_op) | op3(flushw_op3));

}

inline void Assembler::illtrap(int const22a) {

  emit_int32(op(branch_op) | u_field(const22a, 21, 0));

}

inline void Assembler::impdep1(int id1, int const19a) {

  emit_int32(op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0));

}

inline void Assembler::impdep2(int id1, int const19a) {

  emit_int32(op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0));

}

inline void Assembler::jmpl(Register s1, Register s2, Register d) {

  avoid_pipeline_stall();

  cti();

  emit_int32(op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | rs2(s2));

  induce_delay_slot();

}

inline void Assembler::jmpl(Register s1, int simm13a, Register d, RelocationHolder const &rspec) {

  avoid_pipeline_stall();

  cti();

  emit_data(op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec);

  induce_delay_slot();

}

inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d) {

  emit_int32(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | rs2(s2));

}

inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const &rspec) {

  emit_data(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec);

}

inline void Assembler::ldxfsr(Register s1, Register s2) {

  emit_int32(op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | rs2(s2));

}

inline void Assembler::ldxfsr(Register s1, int simm13a) {

  emit_data(op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));

}

inline void Assembler::ldfa(FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d) {

  emit_int32(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2));

}

inline void Assembler::ldfa(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d) {

  emit_int32(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13));

}

inline void Assembler::ldsb(Register s1, Register s2, Register d) {

  emit_int32(op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | rs2(s2));

}

inline void Assembler::ldsb(Register s1, int simm13a, Register d) {

  emit_data(op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));

}

inline void Assembler::ldsh(Register s1, Register s2, Register d) {

  emit_int32(op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | rs2(s2));

}

inline void Assembler::ldsh(Register s1, int simm13a, Register d) {

  emit_data(op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));

}

inline void Assembler::ldsw(Register s1, Register s2, Register d) {

  emit_int32(op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | rs2(s2));

}

inline void Assembler::ldsw(Register s1, int simm13a, Register d) {

  emit_data(op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));

}

inline void Assembler::ldub(Register s1, Register s2, Register d) {

  emit_int32(op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | rs2(s2));

}

inline void Assembler::ldub(Register s1, int simm13a, Register d) {

  emit_data(op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));

}

inline void Assembler::lduh(Register s1, Register s2, Register d) {

  emit_int32(op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | rs2(s2));

}

inline void Assembler::lduh(Register s1, int simm13a, Register d) {

  emit_data(op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));

}

inline void Assembler::lduw(Register s1, Register s2, Register d) {

  emit_int32(op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | rs2(s2));

}

inline void Assembler::lduw(Register s1, int simm13a, Register d) {

  emit_data(op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));

}

inline void Assembler::ldx(Register s1, Register s2, Register d) {

  emit_int32(op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | rs2(s2));

}

inline void Assembler::ldx(Register s1, int simm13a, Register d) {

  emit_data(op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));

}

inline void Assembler::ldd(Register s1, Register s2, Register d) {

  v9_dep();

  assert(d->is_even(), "not even");

  emit_int32(op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | rs2(s2));

}

inline void Assembler::ldd(Register s1, int simm13a, Register d) {

  v9_dep();

  assert(d->is_even(), "not even");

  emit_data(op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));

}

inline void Assembler::ldsba(Register s1, Register s2, int ia, Register d) {

  emit_int32(op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2));

}

inline void Assembler::ldsba(Register s1, int simm13a, Register d) {

  emit_int32(op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));

}

inline void Assembler::ldsha(Register s1, Register s2, int ia, Register d) {

  emit_int32(op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2));

}

inline void Assembler::ldsha(Register s1, int simm13a, Register d) {

  emit_int32(op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));

}

inline void Assembler::ldswa(Register s1, Register s2, int ia, Register d) {

  emit_int32(op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2));

}

inline void Assembler::ldswa(Register s1, int simm13a, Register d) {

  emit_int32(op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));

}

inline void Assembler::lduba(Register s1, Register s2, int ia, Register d) {

  emit_int32(op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2));

}

inline void Assembler::lduba(Register s1, int simm13a, Register d) {

  emit_int32(op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));

}

inline void Assembler::lduha(Register s1, Register s2, int ia, Register d) {