/*

 * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#include "precompiled.hpp"

#include "asm/assembler.hpp"

#include "assembler_arm.inline.hpp"

#include "code/debugInfoRec.hpp"

#include "code/icBuffer.hpp"

#include "code/vtableStubs.hpp"

#include "interpreter/interpreter.hpp"

#include "logging/log.hpp"

#include "memory/resourceArea.hpp"

#include "oops/compiledICHolder.hpp"

#include "oops/klass.inline.hpp"

#include "runtime/sharedRuntime.hpp"

#include "runtime/vframeArray.hpp"

#include "utilities/align.hpp"

#include "vmreg_arm.inline.hpp"

#ifdef COMPILER1

#include "c1/c1_Runtime1.hpp"

#endif

#ifdef COMPILER2

#include "opto/runtime.hpp"

#endif

#define __ masm->

class RegisterSaver {

public:

  // Special registers:

  //              32-bit ARM     64-bit ARM

  //  Rthread:       R10            R28

  //  LR:            R14            R30

  // Rthread is callee saved in the C ABI and never changed by compiled code:

  // no need to save it.

  // 2 slots for LR: the one at LR_offset and an other one at R14/R30_offset.

  // The one at LR_offset is a return address that is needed by stack walking.

  // A c2 method uses LR as a standard register so it may be live when we

  // branch to the runtime. The slot at R14/R30_offset is for the value of LR

  // in case it's live in the method we are coming from.

  enum RegisterLayout {

    fpu_save_size = FloatRegisterImpl::number_of_registers,

#ifndef __SOFTFP__

    D0_offset = 0,

#endif

    R0_offset = fpu_save_size,

    R1_offset,

    R2_offset,

    R3_offset,

    R4_offset,

    R5_offset,

    R6_offset,

#if (FP_REG_NUM != 7)

    // if not saved as FP

    R7_offset,

#endif

    R8_offset,

    R9_offset,

#if (FP_REG_NUM != 11)

    // if not saved as FP

    R11_offset,

#endif

    R12_offset,

    R14_offset,

    FP_offset,

    LR_offset,

    reg_save_size,

    Rmethod_offset = R9_offset,

    Rtemp_offset = R12_offset,

  };

  // all regs but Rthread (R10), FP (R7 or R11), SP and PC

  // (altFP_7_11 is the one amoung R7 and R11 which is not FP)

#define SAVED_BASE_REGS (RegisterSet(R0, R6) | RegisterSet(R8, R9) | RegisterSet(R12) | R14 | altFP_7_11)

  //  When LR may be live in the nmethod from which we are comming

  //  then lr_saved is true, the return address is saved before the

  //  call to save_live_register by the caller and LR contains the

  //  live value.

  static OopMap* save_live_registers(MacroAssembler* masm,

                                     int* total_frame_words,

                                     bool lr_saved = false);

  static void restore_live_registers(MacroAssembler* masm, bool restore_lr = true);

};

OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm,

                                           int* total_frame_words,

                                           bool lr_saved) {

  *total_frame_words = reg_save_size;

  OopMapSet *oop_maps = new OopMapSet();

  OopMap* map = new OopMap(VMRegImpl::slots_per_word * (*total_frame_words), 0);

  if (lr_saved) {

    __ push(RegisterSet(FP));

  } else {

    __ push(RegisterSet(FP) | RegisterSet(LR));

  }

  __ push(SAVED_BASE_REGS);

  if (HaveVFP) {

    if (VM_Version::has_vfp3_32()) {

      __ fstmdbd(SP, FloatRegisterSet(D16, 16), writeback);

    } else {

      if (FloatRegisterImpl::number_of_registers > 32) {

        assert(FloatRegisterImpl::number_of_registers == 64, "nb fp registers should be 64");

        __ sub(SP, SP, 32 * wordSize);

      }

    }

    __ fstmdbd(SP, FloatRegisterSet(D0, 16), writeback);

  } else {

    __ sub(SP, SP, fpu_save_size * wordSize);

  }

  int i;

  int j=0;

  for (i = R0_offset; i <= R9_offset; i++) {

    if (j == FP_REG_NUM) {

      // skip the FP register, managed below.

      j++;

    }

    map->set_callee_saved(VMRegImpl::stack2reg(i), as_Register(j)->as_VMReg());

    j++;

  }

  assert(j == R10->encoding(), "must be");

#if (FP_REG_NUM != 11)

  // add R11, if not managed as FP

  map->set_callee_saved(VMRegImpl::stack2reg(R11_offset), R11->as_VMReg());

#endif

  map->set_callee_saved(VMRegImpl::stack2reg(R12_offset), R12->as_VMReg());

  map->set_callee_saved(VMRegImpl::stack2reg(R14_offset), R14->as_VMReg());

  if (HaveVFP) {

    for (i = 0; i < (VM_Version::has_vfp3_32() ? 64 : 32); i+=2) {

      map->set_callee_saved(VMRegImpl::stack2reg(i), as_FloatRegister(i)->as_VMReg());

      map->set_callee_saved(VMRegImpl::stack2reg(i + 1), as_FloatRegister(i)->as_VMReg()->next());

    }

  }

  return map;

}

void RegisterSaver::restore_live_registers(MacroAssembler* masm, bool restore_lr) {

  if (HaveVFP) {

    __ fldmiad(SP, FloatRegisterSet(D0, 16), writeback);

    if (VM_Version::has_vfp3_32()) {

      __ fldmiad(SP, FloatRegisterSet(D16, 16), writeback);

    } else {

      if (FloatRegisterImpl::number_of_registers > 32) {

        assert(FloatRegisterImpl::number_of_registers == 64, "nb fp registers should be 64");

        __ add(SP, SP, 32 * wordSize);

      }

    }

  } else {

    __ add(SP, SP, fpu_save_size * wordSize);

  }

  __ pop(SAVED_BASE_REGS);

  if (restore_lr) {

    __ pop(RegisterSet(FP) | RegisterSet(LR));

  } else {

    __ pop(RegisterSet(FP));

  }

}

static void push_result_registers(MacroAssembler* masm, BasicType ret_type) {

#ifdef __ABI_HARD__

  if (ret_type == T_DOUBLE || ret_type == T_FLOAT) {

    __ sub(SP, SP, 8);

    __ fstd(D0, Address(SP));

    return;

  }

#endif // __ABI_HARD__

  __ raw_push(R0, R1);

}

static void pop_result_registers(MacroAssembler* masm, BasicType ret_type) {

#ifdef __ABI_HARD__

  if (ret_type == T_DOUBLE || ret_type == T_FLOAT) {

    __ fldd(D0, Address(SP));

    __ add(SP, SP, 8);

    return;

  }

#endif // __ABI_HARD__

  __ raw_pop(R0, R1);

}

static void push_param_registers(MacroAssembler* masm, int fp_regs_in_arguments) {

  // R1-R3 arguments need to be saved, but we push 4 registers for 8-byte alignment

  __ push(RegisterSet(R0, R3));

#ifdef __ABI_HARD__

  // preserve arguments

  // Likely not needed as the locking code won't probably modify volatile FP registers,

  // but there is no way to guarantee that

  if (fp_regs_in_arguments) {

    // convert fp_regs_in_arguments to a number of double registers

    int double_regs_num = (fp_regs_in_arguments + 1) >> 1;

    __ fstmdbd(SP, FloatRegisterSet(D0, double_regs_num), writeback);

  }

#endif // __ ABI_HARD__

}

static void pop_param_registers(MacroAssembler* masm, int fp_regs_in_arguments) {

#ifdef __ABI_HARD__

  if (fp_regs_in_arguments) {

    int double_regs_num = (fp_regs_in_arguments + 1) >> 1;

    __ fldmiad(SP, FloatRegisterSet(D0, double_regs_num), writeback);

  }

#endif // __ABI_HARD__

  __ pop(RegisterSet(R0, R3));

}

// Is vector's size (in bytes) bigger than a size saved by default?

// All vector registers are saved by default on ARM.

bool SharedRuntime::is_wide_vector(int size) {

  return false;

}

size_t SharedRuntime::trampoline_size() {

  return 16;

}

void SharedRuntime::generate_trampoline(MacroAssembler *masm, address destination) {

  InlinedAddress dest(destination);

  __ indirect_jump(dest, Rtemp);

  __ bind_literal(dest);

}

int SharedRuntime::c_calling_convention(const BasicType *sig_bt,

                                        VMRegPair *regs,

                                        VMRegPair *regs2,

                                        int total_args_passed) {

  assert(regs2 == NULL, "not needed on arm");

  int slot = 0;

  int ireg = 0;

#ifdef __ABI_HARD__

  int fp_slot = 0;

  int single_fpr_slot = 0;

#endif // __ABI_HARD__

  for (int i = 0; i < total_args_passed; i++) {

    switch (sig_bt[i]) {

    case T_SHORT:

    case T_CHAR:

    case T_BYTE:

    case T_BOOLEAN:

    case T_INT:

    case T_ARRAY:

    case T_OBJECT:

    case T_ADDRESS:

    case T_METADATA:

#ifndef __ABI_HARD__

    case T_FLOAT:

#endif // !__ABI_HARD__

      if (ireg < 4) {

        Register r = as_Register(ireg);

        regs[i].set1(r->as_VMReg());

        ireg++;

      } else {

        regs[i].set1(VMRegImpl::stack2reg(slot));

        slot++;

      }

      break;

    case T_LONG:

#ifndef __ABI_HARD__

    case T_DOUBLE:

#endif // !__ABI_HARD__

      assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "missing Half" );

      if (ireg <= 2) {

#if (ALIGN_WIDE_ARGUMENTS == 1)

        if(ireg & 1) ireg++;  // Aligned location required

#endif

        Register r1 = as_Register(ireg);

        Register r2 = as_Register(ireg + 1);

        regs[i].set_pair(r2->as_VMReg(), r1->as_VMReg());

        ireg += 2;

#if (ALIGN_WIDE_ARGUMENTS == 0)

      } else if (ireg == 3) {

        // uses R3 + one stack slot

        Register r = as_Register(ireg);

        regs[i].set_pair(VMRegImpl::stack2reg(slot), r->as_VMReg());

        ireg += 1;

        slot += 1;

#endif

      } else {

        if (slot & 1) slot++; // Aligned location required

        regs[i].set_pair(VMRegImpl::stack2reg(slot+1), VMRegImpl::stack2reg(slot));

        slot += 2;

        ireg = 4;

      }

      break;

    case T_VOID:

      regs[i].set_bad();

      break;

#ifdef __ABI_HARD__

    case T_FLOAT:

      if ((fp_slot < 16)||(single_fpr_slot & 1)) {

        if ((single_fpr_slot & 1) == 0) {

          single_fpr_slot = fp_slot;

          fp_slot += 2;

        }

        FloatRegister r = as_FloatRegister(single_fpr_slot);

        single_fpr_slot++;

        regs[i].set1(r->as_VMReg());

      } else {

        regs[i].set1(VMRegImpl::stack2reg(slot));

        slot++;

      }

      break;

    case T_DOUBLE:

      assert(ALIGN_WIDE_ARGUMENTS == 1, "ABI_HARD not supported with unaligned wide arguments");

      if (fp_slot <= 14) {

        FloatRegister r1 = as_FloatRegister(fp_slot);

        FloatRegister r2 = as_FloatRegister(fp_slot+1);

        regs[i].set_pair(r2->as_VMReg(), r1->as_VMReg());

        fp_slot += 2;

      } else {

        if(slot & 1) slot++;

        regs[i].set_pair(VMRegImpl::stack2reg(slot+1), VMRegImpl::stack2reg(slot));

        slot += 2;

        single_fpr_slot = 16;

      }

      break;

#endif // __ABI_HARD__

    default:

      ShouldNotReachHere();

    }

  }

  return slot;

}

int SharedRuntime::java_calling_convention(const BasicType *sig_bt,

                                           VMRegPair *regs,

                                           int total_args_passed,

                                           int is_outgoing) {

#ifdef __SOFTFP__

  // soft float is the same as the C calling convention.

  return c_calling_convention(sig_bt, regs, NULL, total_args_passed);

#endif // __SOFTFP__

  (void) is_outgoing;

  int slot = 0;

  int ireg = 0;

  int freg = 0;

  int single_fpr = 0;

  for (int i = 0; i < total_args_passed; i++) {

    switch (sig_bt[i]) {

    case T_SHORT:

    case T_CHAR:

    case T_BYTE:

    case T_BOOLEAN:

    case T_INT:

    case T_ARRAY:

    case T_OBJECT:

    case T_ADDRESS:

      if (ireg < 4) {

        Register r = as_Register(ireg++);

        regs[i].set1(r->as_VMReg());

      } else {

        regs[i].set1(VMRegImpl::stack2reg(slot++));

      }

      break;

    case T_FLOAT:

      // C2 utilizes S14/S15 for mem-mem moves

      if ((freg < 16 COMPILER2_PRESENT(-2)) || (single_fpr & 1)) {

        if ((single_fpr & 1) == 0) {

          single_fpr = freg;

          freg += 2;

        }

        FloatRegister r = as_FloatRegister(single_fpr++);

        regs[i].set1(r->as_VMReg());

      } else {

        regs[i].set1(VMRegImpl::stack2reg(slot++));

      }

      break;

    case T_DOUBLE:

      // C2 utilizes S14/S15 for mem-mem moves

      if (freg <= 14 COMPILER2_PRESENT(-2)) {

        FloatRegister r1 = as_FloatRegister(freg);

        FloatRegister r2 = as_FloatRegister(freg + 1);

        regs[i].set_pair(r2->as_VMReg(), r1->as_VMReg());

        freg += 2;

      } else {

        // Keep internally the aligned calling convention,

        // ignoring ALIGN_WIDE_ARGUMENTS

        if (slot & 1) slot++;

        regs[i].set_pair(VMRegImpl::stack2reg(slot + 1), VMRegImpl::stack2reg(slot));

        slot += 2;

        single_fpr = 16;

      }

      break;

    case T_LONG:

      // Keep internally the aligned calling convention,

      // ignoring ALIGN_WIDE_ARGUMENTS

      if (ireg <= 2) {

        if (ireg & 1) ireg++;

        Register r1 = as_Register(ireg);

        Register r2 = as_Register(ireg + 1);

        regs[i].set_pair(r2->as_VMReg(), r1->as_VMReg());

        ireg += 2;

      } else {

        if (slot & 1) slot++;

        regs[i].set_pair(VMRegImpl::stack2reg(slot + 1), VMRegImpl::stack2reg(slot));

        slot += 2;

        ireg = 4;

      }

      break;

    case T_VOID:

      regs[i].set_bad();

      break;

    default:

      ShouldNotReachHere();

    }

  }

  if (slot & 1) slot++;

  return slot;

}

static void patch_callers_callsite(MacroAssembler *masm) {

  Label skip;

  __ ldr(Rtemp, Address(Rmethod, Method::code_offset()));

  __ cbz(Rtemp, skip);

  // Pushing an even number of registers for stack alignment.

  // Selecting R9, which had to be saved anyway for some platforms.

  __ push(RegisterSet(R0, R3) | R9 | LR);

  __ mov(R0, Rmethod);

  __ mov(R1, LR);

  __ call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite));

  __ pop(RegisterSet(R0, R3) | R9 | LR);

  __ bind(skip);

}

void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm,

                                    int total_args_passed, int comp_args_on_stack,

                                    const BasicType *sig_bt, const VMRegPair *regs) {

  // TODO: ARM - May be can use ldm to load arguments

  const Register tmp = Rtemp; // avoid erasing R5_mh

  // Next assert may not be needed but safer. Extra analysis required

  // if this there is not enough free registers and we need to use R5 here.

  assert_different_registers(tmp, R5_mh);

  // 6243940 We might end up in handle_wrong_method if

  // the callee is deoptimized as we race thru here. If that

  // happens we don't want to take a safepoint because the

  // caller frame will look interpreted and arguments are now

  // "compiled" so it is much better to make this transition

  // invisible to the stack walking code. Unfortunately if

  // we try and find the callee by normal means a safepoint

  // is possible. So we stash the desired callee in the thread

  // and the vm will find there should this case occur.

  Address callee_target_addr(Rthread, JavaThread::callee_target_offset());

  __ str(Rmethod, callee_target_addr);

  assert_different_registers(tmp, R0, R1, R2, R3, Rsender_sp, Rmethod);

  const Register initial_sp = Rmethod; // temporarily scratched

  // Old code was modifying R4 but this looks unsafe (particularly with JSR292)

  assert_different_registers(tmp, R0, R1, R2, R3, Rsender_sp, initial_sp);

  __ mov(initial_sp, SP);

  if (comp_args_on_stack) {

    __ sub_slow(SP, SP, comp_args_on_stack * VMRegImpl::stack_slot_size);

  }

  __ bic(SP, SP, StackAlignmentInBytes - 1);

  for (int i = 0; i < total_args_passed; i++) {

    if (sig_bt[i] == T_VOID) {

      assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");

      continue;

    }

    assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(), "must be ordered");

    int arg_offset = Interpreter::expr_offset_in_bytes(total_args_passed - 1 - i);

    VMReg r_1 = regs[i].first();

    VMReg r_2 = regs[i].second();

    if (r_1->is_stack()) {

      int stack_offset = r_1->reg2stack() * VMRegImpl::stack_slot_size;

      if (!r_2->is_valid()) {

        __ ldr(tmp, Address(initial_sp, arg_offset));

        __ str(tmp, Address(SP, stack_offset));

      } else {

        __ ldr(tmp, Address(initial_sp, arg_offset - Interpreter::stackElementSize));