/*

 * Copyright (c) 2008, 2017, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#include "precompiled.hpp"

#include "asm/assembler.hpp"

#include "assembler_arm.inline.hpp"

#include "code/debugInfoRec.hpp"

#include "code/icBuffer.hpp"

#include "code/vtableStubs.hpp"

#include "interpreter/interpreter.hpp"

#include "logging/log.hpp"

#include "memory/resourceArea.hpp"

#include "oops/compiledICHolder.hpp"

#include "runtime/sharedRuntime.hpp"

#include "runtime/vframeArray.hpp"

#include "utilities/align.hpp"

#include "vmreg_arm.inline.hpp"

#ifdef COMPILER1

#include "c1/c1_Runtime1.hpp"

#endif

#ifdef COMPILER2

#include "opto/runtime.hpp"

#endif

#ifdef SHARK

#include "compiler/compileBroker.hpp"

#include "shark/sharkCompiler.hpp"

#endif

#define __ masm->

class RegisterSaver {

public:

  // Special registers:

  //              32-bit ARM     64-bit ARM

  //  Rthread:       R10            R28

  //  LR:            R14            R30

  // Rthread is callee saved in the C ABI and never changed by compiled code:

  // no need to save it.

  // 2 slots for LR: the one at LR_offset and an other one at R14/R30_offset.

  // The one at LR_offset is a return address that is needed by stack walking.

  // A c2 method uses LR as a standard register so it may be live when we

  // branch to the runtime. The slot at R14/R30_offset is for the value of LR

  // in case it's live in the method we are coming from.

#ifdef AARCH64

  //

  // On AArch64 registers save area has the following layout:

  //

  // |---------------------|

  // | return address (LR) |

  // | FP                  |

  // |---------------------|

  // | V31                 |

  // | ...                 |

  // | V0                  |

  // |---------------------|

  // | padding             |

  // | R30 (LR live value) |

  // |---------------------|

  // | R27                 |

  // | ...                 |

  // | R0                  |

  // |---------------------| <-- SP

  //

  enum RegisterLayout {

    number_of_saved_gprs = 28,

    number_of_saved_fprs = FloatRegisterImpl::number_of_registers,

    words_per_fpr = ConcreteRegisterImpl::words_per_fpr,

    R0_offset  = 0,

    R30_offset = R0_offset + number_of_saved_gprs,

    D0_offset  = R30_offset + 2,

    FP_offset  = D0_offset + number_of_saved_fprs * words_per_fpr,

    LR_offset  = FP_offset + 1,

    reg_save_size = LR_offset + 1,

  };

  static const int Rmethod_offset;

  static const int Rtemp_offset;

#else

  enum RegisterLayout {

    fpu_save_size = FloatRegisterImpl::number_of_registers,

#ifndef __SOFTFP__

    D0_offset = 0,

#endif

    R0_offset = fpu_save_size,

    R1_offset,

    R2_offset,

    R3_offset,

    R4_offset,

    R5_offset,

    R6_offset,

#if (FP_REG_NUM != 7)

    // if not saved as FP

    R7_offset,

#endif

    R8_offset,

    R9_offset,

#if (FP_REG_NUM != 11)

    // if not saved as FP

    R11_offset,

#endif

    R12_offset,

    R14_offset,

    FP_offset,

    LR_offset,

    reg_save_size,

    Rmethod_offset = R9_offset,

    Rtemp_offset = R12_offset,

  };

  // all regs but Rthread (R10), FP (R7 or R11), SP and PC

  // (altFP_7_11 is the one amoung R7 and R11 which is not FP)

#define SAVED_BASE_REGS (RegisterSet(R0, R6) | RegisterSet(R8, R9) | RegisterSet(R12) | R14 | altFP_7_11)

#endif // AARCH64

  //  When LR may be live in the nmethod from which we are comming

  //  then lr_saved is true, the return address is saved before the

  //  call to save_live_register by the caller and LR contains the

  //  live value.

  static OopMap* save_live_registers(MacroAssembler* masm,

                                     int* total_frame_words,

                                     bool lr_saved = false);

  static void restore_live_registers(MacroAssembler* masm, bool restore_lr = true);

};

#ifdef AARCH64

const int RegisterSaver::Rmethod_offset = RegisterSaver::R0_offset + Rmethod->encoding();

const int RegisterSaver::Rtemp_offset   = RegisterSaver::R0_offset + Rtemp->encoding();

#endif // AARCH64

OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm,

                                           int* total_frame_words,

                                           bool lr_saved) {

  *total_frame_words = reg_save_size;

  OopMapSet *oop_maps = new OopMapSet();

  OopMap* map = new OopMap(VMRegImpl::slots_per_word * (*total_frame_words), 0);

#ifdef AARCH64

  assert((reg_save_size * wordSize) % StackAlignmentInBytes == 0, "SP should be aligned");

  if (lr_saved) {

    // LR was stashed here, so that jump could use it as a scratch reg

    __ ldr(LR, Address(SP, 0));

    // There are two words on the stack top:

    //  [SP + 0]: placeholder for FP

    //  [SP + wordSize]: saved return address

    __ str(FP, Address(SP, 0));

  } else {

    __ raw_push(FP, LR);

  }

  __ sub(SP, SP, (reg_save_size - 2) * wordSize);

  for (int i = 0; i < number_of_saved_gprs; i += 2) {

    int offset = R0_offset + i;

    __ stp(as_Register(i), as_Register(i+1), Address(SP, offset * wordSize));

    map->set_callee_saved(VMRegImpl::stack2reg((offset + 0) * VMRegImpl::slots_per_word), as_Register(i)->as_VMReg());

    map->set_callee_saved(VMRegImpl::stack2reg((offset + 1) * VMRegImpl::slots_per_word), as_Register(i+1)->as_VMReg());

  }

  __ str(R30, Address(SP, R30_offset * wordSize));

  map->set_callee_saved(VMRegImpl::stack2reg(R30_offset * VMRegImpl::slots_per_word), R30->as_VMReg());

  for (int i = 0; i < number_of_saved_fprs; i += 2) {

    int offset1 = D0_offset + i * words_per_fpr;

    int offset2 = offset1 + words_per_fpr;

    Address base(SP, offset1 * wordSize);

    if (words_per_fpr == 2) {

      // pair of "wide" quad vector registers

      __ stp_q(as_FloatRegister(i), as_FloatRegister(i+1), base);

    } else {

      // pair of double vector registers

      __ stp_d(as_FloatRegister(i), as_FloatRegister(i+1), base);

    }

    map->set_callee_saved(VMRegImpl::stack2reg(offset1 * VMRegImpl::slots_per_word), as_FloatRegister(i)->as_VMReg());

    map->set_callee_saved(VMRegImpl::stack2reg(offset2 * VMRegImpl::slots_per_word), as_FloatRegister(i+1)->as_VMReg());

  }

#else

  if (lr_saved) {

    __ push(RegisterSet(FP));

  } else {

    __ push(RegisterSet(FP) | RegisterSet(LR));

  }

  __ push(SAVED_BASE_REGS);

  if (HaveVFP) {

    if (VM_Version::has_vfp3_32()) {

      __ fstmdbd(SP, FloatRegisterSet(D16, 16), writeback);

    } else {

      if (FloatRegisterImpl::number_of_registers > 32) {

        assert(FloatRegisterImpl::number_of_registers == 64, "nb fp registers should be 64");

        __ sub(SP, SP, 32 * wordSize);

      }

    }

    __ fstmdbd(SP, FloatRegisterSet(D0, 16), writeback);

  } else {

    __ sub(SP, SP, fpu_save_size * wordSize);

  }

  int i;

  int j=0;

  for (i = R0_offset; i <= R9_offset; i++) {

    if (j == FP_REG_NUM) {

      // skip the FP register, managed below.

      j++;

    }

    map->set_callee_saved(VMRegImpl::stack2reg(i), as_Register(j)->as_VMReg());

    j++;

  }

  assert(j == R10->encoding(), "must be");

#if (FP_REG_NUM != 11)

  // add R11, if not managed as FP

  map->set_callee_saved(VMRegImpl::stack2reg(R11_offset), R11->as_VMReg());

#endif

  map->set_callee_saved(VMRegImpl::stack2reg(R12_offset), R12->as_VMReg());

  map->set_callee_saved(VMRegImpl::stack2reg(R14_offset), R14->as_VMReg());

  if (HaveVFP) {

    for (i = 0; i < (VM_Version::has_vfp3_32() ? 64 : 32); i+=2) {

      map->set_callee_saved(VMRegImpl::stack2reg(i), as_FloatRegister(i)->as_VMReg());

      map->set_callee_saved(VMRegImpl::stack2reg(i + 1), as_FloatRegister(i)->as_VMReg()->next());

    }

  }

#endif // AARCH64

  return map;

}

void RegisterSaver::restore_live_registers(MacroAssembler* masm, bool restore_lr) {

#ifdef AARCH64

  for (int i = 0; i < number_of_saved_gprs; i += 2) {

    __ ldp(as_Register(i), as_Register(i+1), Address(SP, (R0_offset + i) * wordSize));

  }

  __ ldr(R30, Address(SP, R30_offset * wordSize));

  for (int i = 0; i < number_of_saved_fprs; i += 2) {

    Address base(SP, (D0_offset + i * words_per_fpr) * wordSize);

    if (words_per_fpr == 2) {

      // pair of "wide" quad vector registers

      __ ldp_q(as_FloatRegister(i), as_FloatRegister(i+1), base);

    } else {

      // pair of double vector registers

      __ ldp_d(as_FloatRegister(i), as_FloatRegister(i+1), base);

    }

  }

  __ add(SP, SP, (reg_save_size - 2) * wordSize);

  if (restore_lr) {

    __ raw_pop(FP, LR);

  } else {

    __ ldr(FP, Address(SP, 0));

  }

#else

  if (HaveVFP) {

    __ fldmiad(SP, FloatRegisterSet(D0, 16), writeback);

    if (VM_Version::has_vfp3_32()) {

      __ fldmiad(SP, FloatRegisterSet(D16, 16), writeback);

    } else {

      if (FloatRegisterImpl::number_of_registers > 32) {

        assert(FloatRegisterImpl::number_of_registers == 64, "nb fp registers should be 64");

        __ add(SP, SP, 32 * wordSize);

      }

    }

  } else {

    __ add(SP, SP, fpu_save_size * wordSize);

  }

  __ pop(SAVED_BASE_REGS);

  if (restore_lr) {

    __ pop(RegisterSet(FP) | RegisterSet(LR));

  } else {

    __ pop(RegisterSet(FP));

  }

#endif // AARCH64

}

#ifdef AARCH64

static void push_result_registers(MacroAssembler* masm, BasicType ret_type) {

  if (ret_type == T_DOUBLE || ret_type == T_FLOAT) {

    __ str_d(D0, Address(SP, -2*wordSize, pre_indexed));

  } else {

    __ raw_push(R0, ZR);

  }

}

static void pop_result_registers(MacroAssembler* masm, BasicType ret_type) {

  if (ret_type == T_DOUBLE || ret_type == T_FLOAT) {

    __ ldr_d(D0, Address(SP, 2*wordSize, post_indexed));

  } else {

    __ raw_pop(R0, ZR);

  }

}

static void push_param_registers(MacroAssembler* masm, int fp_regs_in_arguments) {

  __ raw_push(R0, R1);

  __ raw_push(R2, R3);

  __ raw_push(R4, R5);

  __ raw_push(R6, R7);

  assert(FPR_PARAMS == 8, "adjust this code");

  assert((0 <= fp_regs_in_arguments) && (fp_regs_in_arguments <= FPR_PARAMS), "should be");

  if (fp_regs_in_arguments > 6) __ stp_d(V6, V7, Address(SP, -2 * wordSize, pre_indexed));

  if (fp_regs_in_arguments > 4) __ stp_d(V4, V5, Address(SP, -2 * wordSize, pre_indexed));

  if (fp_regs_in_arguments > 2) __ stp_d(V2, V3, Address(SP, -2 * wordSize, pre_indexed));

  if (fp_regs_in_arguments > 0) __ stp_d(V0, V1, Address(SP, -2 * wordSize, pre_indexed));

}

static void pop_param_registers(MacroAssembler* masm, int fp_regs_in_arguments) {

  assert(FPR_PARAMS == 8, "adjust this code");

  assert((0 <= fp_regs_in_arguments) && (fp_regs_in_arguments <= FPR_PARAMS), "should be");

  if (fp_regs_in_arguments > 0) __ ldp_d(V0, V1, Address(SP, 2 * wordSize, post_indexed));

  if (fp_regs_in_arguments > 2) __ ldp_d(V2, V3, Address(SP, 2 * wordSize, post_indexed));

  if (fp_regs_in_arguments > 4) __ ldp_d(V4, V5, Address(SP, 2 * wordSize, post_indexed));

  if (fp_regs_in_arguments > 6) __ ldp_d(V6, V7, Address(SP, 2 * wordSize, post_indexed));

  __ raw_pop(R6, R7);

  __ raw_pop(R4, R5);

  __ raw_pop(R2, R3);

  __ raw_pop(R0, R1);

}

#else // AARCH64

static void push_result_registers(MacroAssembler* masm, BasicType ret_type) {

#ifdef __ABI_HARD__

  if (ret_type == T_DOUBLE || ret_type == T_FLOAT) {

    __ sub(SP, SP, 8);

    __ fstd(D0, Address(SP));

    return;

  }

#endif // __ABI_HARD__

  __ raw_push(R0, R1);

}

static void pop_result_registers(MacroAssembler* masm, BasicType ret_type) {

#ifdef __ABI_HARD__

  if (ret_type == T_DOUBLE || ret_type == T_FLOAT) {

    __ fldd(D0, Address(SP));

    __ add(SP, SP, 8);

    return;

  }

#endif // __ABI_HARD__

  __ raw_pop(R0, R1);

}

static void push_param_registers(MacroAssembler* masm, int fp_regs_in_arguments) {

  // R1-R3 arguments need to be saved, but we push 4 registers for 8-byte alignment

  __ push(RegisterSet(R0, R3));

#ifdef __ABI_HARD__

  // preserve arguments

  // Likely not needed as the locking code won't probably modify volatile FP registers,

  // but there is no way to guarantee that

  if (fp_regs_in_arguments) {

    // convert fp_regs_in_arguments to a number of double registers

    int double_regs_num = (fp_regs_in_arguments + 1) >> 1;

    __ fstmdbd(SP, FloatRegisterSet(D0, double_regs_num), writeback);

  }

#endif // __ ABI_HARD__

}

static void pop_param_registers(MacroAssembler* masm, int fp_regs_in_arguments) {

#ifdef __ABI_HARD__

  if (fp_regs_in_arguments) {

    int double_regs_num = (fp_regs_in_arguments + 1) >> 1;

    __ fldmiad(SP, FloatRegisterSet(D0, double_regs_num), writeback);

  }

#endif // __ABI_HARD__

  __ pop(RegisterSet(R0, R3));

}

#endif // AARCH64

// Is vector's size (in bytes) bigger than a size saved by default?

// All vector registers are saved by default on ARM.

bool SharedRuntime::is_wide_vector(int size) {

  return false;

}

size_t SharedRuntime::trampoline_size() {

  return 16;

}

void SharedRuntime::generate_trampoline(MacroAssembler *masm, address destination) {

  InlinedAddress dest(destination);

  __ indirect_jump(dest, Rtemp);

  __ bind_literal(dest);

}

int SharedRuntime::c_calling_convention(const BasicType *sig_bt,

                                        VMRegPair *regs,

                                        VMRegPair *regs2,

                                        int total_args_passed) {

  assert(regs2 == NULL, "not needed on arm");

#ifdef AARCH64

  int slot = 0; // counted in 32-bit VMReg slots

  int reg = 0;

  int fp_reg = 0;

  for (int i = 0; i < total_args_passed; i++) {

    switch (sig_bt[i]) {

    case T_SHORT:

    case T_CHAR:

    case T_BYTE:

    case T_BOOLEAN:

    case T_INT:

      if (reg < GPR_PARAMS) {

        Register r = as_Register(reg);

        regs[i].set1(r->as_VMReg());

        reg++;

      } else {

        regs[i].set1(VMRegImpl::stack2reg(slot));

        slot+=2;

      }

      break;

    case T_LONG:

      assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "missing Half" );

      // fall through

    case T_ARRAY:

    case T_OBJECT:

    case T_ADDRESS:

      if (reg < GPR_PARAMS) {

        Register r = as_Register(reg);

        regs[i].set2(r->as_VMReg());

        reg++;

      } else {

        regs[i].set2(VMRegImpl::stack2reg(slot));

        slot+=2;

      }

      break;

    case T_FLOAT:

      if (fp_reg < FPR_PARAMS) {

        FloatRegister r = as_FloatRegister(fp_reg);

        regs[i].set1(r->as_VMReg());

        fp_reg++;

      } else {

        regs[i].set1(VMRegImpl::stack2reg(slot));

        slot+=2;

      }

      break;

    case T_DOUBLE:

      assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "missing Half" );

      if (fp_reg < FPR_PARAMS) {

        FloatRegister r = as_FloatRegister(fp_reg);

        regs[i].set2(r->as_VMReg());

        fp_reg++;

      } else {

        regs[i].set2(VMRegImpl::stack2reg(slot));

        slot+=2;

      }

      break;

    case T_VOID:

      assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");

      regs[i].set_bad();

      break;

    default:

      ShouldNotReachHere();

    }

  }

  return slot;

#else // AARCH64

  int slot = 0;

  int ireg = 0;

#ifdef __ABI_HARD__

  int fp_slot = 0;

  int single_fpr_slot = 0;

#endif // __ABI_HARD__

  for (int i = 0; i < total_args_passed; i++) {

    switch (sig_bt[i]) {

    case T_SHORT:

    case T_CHAR:

    case T_BYTE:

    case T_BOOLEAN:

    case T_INT:

    case T_ARRAY:

    case T_OBJECT:

    case T_ADDRESS:

#ifndef __ABI_HARD__

    case T_FLOAT:

#endif // !__ABI_HARD__

      if (ireg < 4) {

        Register r = as_Register(ireg);

        regs[i].set1(r->as_VMReg());

        ireg++;

      } else {

        regs[i].set1(VMRegImpl::stack2reg(slot));