src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp
author chegar
Thu, 17 Oct 2019 20:54:25 +0100
branchdatagramsocketimpl-branch
changeset 58679 9c3209ff7550
parent 58678 9cf78a70fa4f
parent 58103 689a80d20550
permissions -rw-r--r--
datagramsocketimpl-branch: merge with default
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/*
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 * Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved.
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 * Copyright (c) 2014, 2019, Red Hat Inc. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#include "precompiled.hpp"
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#include "asm/macroAssembler.hpp"
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#include "asm/macroAssembler.inline.hpp"
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#include "gc/shared/barrierSet.hpp"
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#include "gc/shared/barrierSetAssembler.hpp"
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#include "interpreter/interpreter.hpp"
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#include "memory/universe.hpp"
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#include "nativeInst_aarch64.hpp"
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#include "oops/instanceOop.hpp"
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#include "oops/method.hpp"
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#include "oops/objArrayKlass.hpp"
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#include "oops/oop.inline.hpp"
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#include "prims/methodHandles.hpp"
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#include "runtime/frame.inline.hpp"
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#include "runtime/handles.inline.hpp"
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#include "runtime/sharedRuntime.hpp"
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#include "runtime/stubCodeGenerator.hpp"
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#include "runtime/stubRoutines.hpp"
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#include "runtime/thread.inline.hpp"
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#include "utilities/align.hpp"
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#ifdef COMPILER2
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#include "opto/runtime.hpp"
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#endif
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#if INCLUDE_ZGC
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#include "gc/z/zThreadLocalData.hpp"
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#endif
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// Declaration and definition of StubGenerator (no .hpp file).
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// For a more detailed description of the stub routine structure
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// see the comment in stubRoutines.hpp
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#undef __
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#define __ _masm->
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#define TIMES_OOP Address::sxtw(exact_log2(UseCompressedOops ? 4 : 8))
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#ifdef PRODUCT
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#define BLOCK_COMMENT(str) /* nothing */
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#else
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#define BLOCK_COMMENT(str) __ block_comment(str)
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#endif
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#define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
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// Stub Code definitions
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class StubGenerator: public StubCodeGenerator {
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 private:
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#ifdef PRODUCT
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#define inc_counter_np(counter) ((void)0)
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#else
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  void inc_counter_np_(int& counter) {
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    __ lea(rscratch2, ExternalAddress((address)&counter));
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    __ ldrw(rscratch1, Address(rscratch2));
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    __ addw(rscratch1, rscratch1, 1);
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    __ strw(rscratch1, Address(rscratch2));
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  }
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#define inc_counter_np(counter) \
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  BLOCK_COMMENT("inc_counter " #counter); \
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  inc_counter_np_(counter);
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#endif
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  // Call stubs are used to call Java from C
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  //
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  // Arguments:
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  //    c_rarg0:   call wrapper address                   address
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  //    c_rarg1:   result                                 address
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  //    c_rarg2:   result type                            BasicType
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  //    c_rarg3:   method                                 Method*
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  //    c_rarg4:   (interpreter) entry point              address
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  //    c_rarg5:   parameters                             intptr_t*
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  //    c_rarg6:   parameter size (in words)              int
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  //    c_rarg7:   thread                                 Thread*
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  //
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  // There is no return from the stub itself as any Java result
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  // is written to result
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  //
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  // we save r30 (lr) as the return PC at the base of the frame and
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  // link r29 (fp) below it as the frame pointer installing sp (r31)
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  // into fp.
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  //
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  // we save r0-r7, which accounts for all the c arguments.
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  //
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  // TODO: strictly do we need to save them all? they are treated as
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  // volatile by C so could we omit saving the ones we are going to
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  // place in global registers (thread? method?) or those we only use
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  // during setup of the Java call?
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  //
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  // we don't need to save r8 which C uses as an indirect result location
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  // return register.
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  //
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  // we don't need to save r9-r15 which both C and Java treat as
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  // volatile
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  //
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  // we don't need to save r16-18 because Java does not use them
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  //
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  // we save r19-r28 which Java uses as scratch registers and C
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  // expects to be callee-save
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  //
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  // we save the bottom 64 bits of each value stored in v8-v15; it is
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  // the responsibility of the caller to preserve larger values.
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  //
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  // so the stub frame looks like this when we enter Java code
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  //
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  //     [ return_from_Java     ] <--- sp
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  //     [ argument word n      ]
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  //      ...
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  // -27 [ argument word 1      ]
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  // -26 [ saved v15            ] <--- sp_after_call
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  // -25 [ saved v14            ]
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  // -24 [ saved v13            ]
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  // -23 [ saved v12            ]
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  // -22 [ saved v11            ]
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  // -21 [ saved v10            ]
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  // -20 [ saved v9             ]
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  // -19 [ saved v8             ]
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  // -18 [ saved r28            ]
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  // -17 [ saved r27            ]
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  // -16 [ saved r26            ]
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  // -15 [ saved r25            ]
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  // -14 [ saved r24            ]
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  // -13 [ saved r23            ]
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  // -12 [ saved r22            ]
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  // -11 [ saved r21            ]
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  // -10 [ saved r20            ]
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  //  -9 [ saved r19            ]
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  //  -8 [ call wrapper    (r0) ]
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  //  -7 [ result          (r1) ]
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  //  -6 [ result type     (r2) ]
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  //  -5 [ method          (r3) ]
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  //  -4 [ entry point     (r4) ]
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  //  -3 [ parameters      (r5) ]
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  //  -2 [ parameter size  (r6) ]
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  //  -1 [ thread (r7)          ]
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  //   0 [ saved fp       (r29) ] <--- fp == saved sp (r31)
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  //   1 [ saved lr       (r30) ]
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  // Call stub stack layout word offsets from fp
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  enum call_stub_layout {
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    sp_after_call_off = -26,
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    d15_off            = -26,
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    d13_off            = -24,
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    d11_off            = -22,
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    d9_off             = -20,
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    r28_off            = -18,
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    r26_off            = -16,
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    r24_off            = -14,
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    r22_off            = -12,
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    r20_off            = -10,
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    call_wrapper_off   =  -8,
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    result_off         =  -7,
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    result_type_off    =  -6,
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    method_off         =  -5,
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    entry_point_off    =  -4,
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    parameter_size_off =  -2,
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    thread_off         =  -1,
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    fp_f               =   0,
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    retaddr_off        =   1,
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  };
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  address generate_call_stub(address& return_address) {
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    assert((int)frame::entry_frame_after_call_words == -(int)sp_after_call_off + 1 &&
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           (int)frame::entry_frame_call_wrapper_offset == (int)call_wrapper_off,
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           "adjust this code");
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    StubCodeMark mark(this, "StubRoutines", "call_stub");
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    address start = __ pc();
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   195
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    const Address sp_after_call(rfp, sp_after_call_off * wordSize);
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   197
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    const Address call_wrapper  (rfp, call_wrapper_off   * wordSize);
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    const Address result        (rfp, result_off         * wordSize);
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    const Address result_type   (rfp, result_type_off    * wordSize);
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    const Address method        (rfp, method_off         * wordSize);
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    const Address entry_point   (rfp, entry_point_off    * wordSize);
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    const Address parameter_size(rfp, parameter_size_off * wordSize);
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    const Address thread        (rfp, thread_off         * wordSize);
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    const Address d15_save      (rfp, d15_off * wordSize);
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    const Address d13_save      (rfp, d13_off * wordSize);
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    const Address d11_save      (rfp, d11_off * wordSize);
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    const Address d9_save       (rfp, d9_off * wordSize);
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    const Address r28_save      (rfp, r28_off * wordSize);
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    const Address r26_save      (rfp, r26_off * wordSize);
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    const Address r24_save      (rfp, r24_off * wordSize);
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    const Address r22_save      (rfp, r22_off * wordSize);
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    const Address r20_save      (rfp, r20_off * wordSize);
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    // stub code
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    address aarch64_entry = __ pc();
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    // set up frame and move sp to end of save area
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    __ enter();
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    __ sub(sp, rfp, -sp_after_call_off * wordSize);
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    // save register parameters and Java scratch/global registers
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    // n.b. we save thread even though it gets installed in
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    // rthread because we want to sanity check rthread later
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    __ str(c_rarg7,  thread);
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    __ strw(c_rarg6, parameter_size);
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    __ stp(c_rarg4, c_rarg5,  entry_point);
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    __ stp(c_rarg2, c_rarg3,  result_type);
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    __ stp(c_rarg0, c_rarg1,  call_wrapper);
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    __ stp(r20, r19,   r20_save);
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    __ stp(r22, r21,   r22_save);
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    __ stp(r24, r23,   r24_save);
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    __ stp(r26, r25,   r26_save);
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    __ stp(r28, r27,   r28_save);
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    __ stpd(v9,  v8,   d9_save);
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    __ stpd(v11, v10,  d11_save);
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    __ stpd(v13, v12,  d13_save);
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    __ stpd(v15, v14,  d15_save);
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    // install Java thread in global register now we have saved
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    // whatever value it held
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    __ mov(rthread, c_rarg7);
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    // And method
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    __ mov(rmethod, c_rarg3);
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    // set up the heapbase register
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    __ reinit_heapbase();
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#ifdef ASSERT
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    // make sure we have no pending exceptions
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    {
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      Label L;
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      __ ldr(rscratch1, Address(rthread, in_bytes(Thread::pending_exception_offset())));
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      __ cmp(rscratch1, (u1)NULL_WORD);
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      __ br(Assembler::EQ, L);
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      __ stop("StubRoutines::call_stub: entered with pending exception");
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   263
      __ BIND(L);
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   264
    }
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   265
#endif
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   266
    // pass parameters if any
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   267
    __ mov(esp, sp);
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   268
    __ sub(rscratch1, sp, c_rarg6, ext::uxtw, LogBytesPerWord); // Move SP out of the way
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    __ andr(sp, rscratch1, -2 * wordSize);
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   270
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    BLOCK_COMMENT("pass parameters if any");
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    Label parameters_done;
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   273
    // parameter count is still in c_rarg6
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   274
    // and parameter pointer identifying param 1 is in c_rarg5
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   275
    __ cbzw(c_rarg6, parameters_done);
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   276
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    address loop = __ pc();
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   278
    __ ldr(rscratch1, Address(__ post(c_rarg5, wordSize)));
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   279
    __ subsw(c_rarg6, c_rarg6, 1);
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   280
    __ push(rscratch1);
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   281
    __ br(Assembler::GT, loop);
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   282
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    __ BIND(parameters_done);
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   284
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    // call Java entry -- passing methdoOop, and current sp
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    //      rmethod: Method*
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    //      r13: sender sp
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   288
    BLOCK_COMMENT("call Java function");
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   289
    __ mov(r13, sp);
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   290
    __ blr(c_rarg4);
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   291
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   292
    // we do this here because the notify will already have been done
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   293
    // if we get to the next instruction via an exception
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   294
    //
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   295
    // n.b. adding this instruction here affects the calculation of
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   296
    // whether or not a routine returns to the call stub (used when
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   297
    // doing stack walks) since the normal test is to check the return
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   298
    // pc against the address saved below. so we may need to allow for
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   299
    // this extra instruction in the check.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   300
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   301
    // save current address for use by exception handling code
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   302
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   303
    return_address = __ pc();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   304
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   305
    // store result depending on type (everything that is not
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   306
    // T_OBJECT, T_LONG, T_FLOAT or T_DOUBLE is treated as T_INT)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   307
    // n.b. this assumes Java returns an integral result in r0
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   308
    // and a floating result in j_farg0
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   309
    __ ldr(j_rarg2, result);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   310
    Label is_long, is_float, is_double, exit;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   311
    __ ldr(j_rarg1, result_type);
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
   312
    __ cmp(j_rarg1, (u1)T_OBJECT);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   313
    __ br(Assembler::EQ, is_long);
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
   314
    __ cmp(j_rarg1, (u1)T_LONG);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   315
    __ br(Assembler::EQ, is_long);
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
   316
    __ cmp(j_rarg1, (u1)T_FLOAT);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   317
    __ br(Assembler::EQ, is_float);
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
   318
    __ cmp(j_rarg1, (u1)T_DOUBLE);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   319
    __ br(Assembler::EQ, is_double);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   320
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   321
    // handle T_INT case
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   322
    __ strw(r0, Address(j_rarg2));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   323
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   324
    __ BIND(exit);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   325
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   326
    // pop parameters
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   327
    __ sub(esp, rfp, -sp_after_call_off * wordSize);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   328
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   329
#ifdef ASSERT
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   330
    // verify that threads correspond
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   331
    {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   332
      Label L, S;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   333
      __ ldr(rscratch1, thread);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   334
      __ cmp(rthread, rscratch1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   335
      __ br(Assembler::NE, S);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   336
      __ get_thread(rscratch1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   337
      __ cmp(rthread, rscratch1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   338
      __ br(Assembler::EQ, L);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   339
      __ BIND(S);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   340
      __ stop("StubRoutines::call_stub: threads must correspond");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   341
      __ BIND(L);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   342
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   343
#endif
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   344
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   345
    // restore callee-save registers
36340
f1401b7f2d58 8149907: aarch64: use load/store pair instructions in call_stub
fyang
parents: 36326
diff changeset
   346
    __ ldpd(v15, v14,  d15_save);
f1401b7f2d58 8149907: aarch64: use load/store pair instructions in call_stub
fyang
parents: 36326
diff changeset
   347
    __ ldpd(v13, v12,  d13_save);
f1401b7f2d58 8149907: aarch64: use load/store pair instructions in call_stub
fyang
parents: 36326
diff changeset
   348
    __ ldpd(v11, v10,  d11_save);
f1401b7f2d58 8149907: aarch64: use load/store pair instructions in call_stub
fyang
parents: 36326
diff changeset
   349
    __ ldpd(v9,  v8,   d9_save);
f1401b7f2d58 8149907: aarch64: use load/store pair instructions in call_stub
fyang
parents: 36326
diff changeset
   350
f1401b7f2d58 8149907: aarch64: use load/store pair instructions in call_stub
fyang
parents: 36326
diff changeset
   351
    __ ldp(r28, r27,   r28_save);
f1401b7f2d58 8149907: aarch64: use load/store pair instructions in call_stub
fyang
parents: 36326
diff changeset
   352
    __ ldp(r26, r25,   r26_save);
f1401b7f2d58 8149907: aarch64: use load/store pair instructions in call_stub
fyang
parents: 36326
diff changeset
   353
    __ ldp(r24, r23,   r24_save);
f1401b7f2d58 8149907: aarch64: use load/store pair instructions in call_stub
fyang
parents: 36326
diff changeset
   354
    __ ldp(r22, r21,   r22_save);
f1401b7f2d58 8149907: aarch64: use load/store pair instructions in call_stub
fyang
parents: 36326
diff changeset
   355
    __ ldp(r20, r19,   r20_save);
f1401b7f2d58 8149907: aarch64: use load/store pair instructions in call_stub
fyang
parents: 36326
diff changeset
   356
f1401b7f2d58 8149907: aarch64: use load/store pair instructions in call_stub
fyang
parents: 36326
diff changeset
   357
    __ ldp(c_rarg0, c_rarg1,  call_wrapper);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   358
    __ ldrw(c_rarg2, result_type);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   359
    __ ldr(c_rarg3,  method);
36340
f1401b7f2d58 8149907: aarch64: use load/store pair instructions in call_stub
fyang
parents: 36326
diff changeset
   360
    __ ldp(c_rarg4, c_rarg5,  entry_point);
f1401b7f2d58 8149907: aarch64: use load/store pair instructions in call_stub
fyang
parents: 36326
diff changeset
   361
    __ ldp(c_rarg6, c_rarg7,  parameter_size);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   362
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   363
    // leave frame and return to caller
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   364
    __ leave();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   365
    __ ret(lr);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   366
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   367
    // handle return types different from T_INT
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   368
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   369
    __ BIND(is_long);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   370
    __ str(r0, Address(j_rarg2, 0));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   371
    __ br(Assembler::AL, exit);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   372
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   373
    __ BIND(is_float);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   374
    __ strs(j_farg0, Address(j_rarg2, 0));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   375
    __ br(Assembler::AL, exit);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   376
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   377
    __ BIND(is_double);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   378
    __ strd(j_farg0, Address(j_rarg2, 0));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   379
    __ br(Assembler::AL, exit);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   380
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   381
    return start;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   382
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   383
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   384
  // Return point for a Java call if there's an exception thrown in
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   385
  // Java code.  The exception is caught and transformed into a
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   386
  // pending exception stored in JavaThread that can be tested from
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   387
  // within the VM.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   388
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   389
  // Note: Usually the parameters are removed by the callee. In case
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   390
  // of an exception crossing an activation frame boundary, that is
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   391
  // not the case if the callee is compiled code => need to setup the
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   392
  // rsp.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   393
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   394
  // r0: exception oop
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   395
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   396
  address generate_catch_exception() {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   397
    StubCodeMark mark(this, "StubRoutines", "catch_exception");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   398
    address start = __ pc();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   399
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   400
    // same as in generate_call_stub():
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   401
    const Address sp_after_call(rfp, sp_after_call_off * wordSize);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   402
    const Address thread        (rfp, thread_off         * wordSize);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   403
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   404
#ifdef ASSERT
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   405
    // verify that threads correspond
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   406
    {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   407
      Label L, S;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   408
      __ ldr(rscratch1, thread);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   409
      __ cmp(rthread, rscratch1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   410
      __ br(Assembler::NE, S);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   411
      __ get_thread(rscratch1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   412
      __ cmp(rthread, rscratch1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   413
      __ br(Assembler::EQ, L);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   414
      __ bind(S);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   415
      __ stop("StubRoutines::catch_exception: threads must correspond");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   416
      __ bind(L);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   417
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   418
#endif
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   419
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   420
    // set pending exception
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   421
    __ verify_oop(r0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   422
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   423
    __ str(r0, Address(rthread, Thread::pending_exception_offset()));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   424
    __ mov(rscratch1, (address)__FILE__);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   425
    __ str(rscratch1, Address(rthread, Thread::exception_file_offset()));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   426
    __ movw(rscratch1, (int)__LINE__);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   427
    __ strw(rscratch1, Address(rthread, Thread::exception_line_offset()));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   428
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   429
    // complete return to VM
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   430
    assert(StubRoutines::_call_stub_return_address != NULL,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   431
           "_call_stub_return_address must have been generated before");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   432
    __ b(StubRoutines::_call_stub_return_address);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   433
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   434
    return start;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   435
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   436
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   437
  // Continuation point for runtime calls returning with a pending
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   438
  // exception.  The pending exception check happened in the runtime
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   439
  // or native call stub.  The pending exception in Thread is
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   440
  // converted into a Java-level exception.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   441
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   442
  // Contract with Java-level exception handlers:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   443
  // r0: exception
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   444
  // r3: throwing pc
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   445
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   446
  // NOTE: At entry of this stub, exception-pc must be in LR !!
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   447
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   448
  // NOTE: this is always used as a jump target within generated code
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   449
  // so it just needs to be generated code wiht no x86 prolog
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   450
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   451
  address generate_forward_exception() {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   452
    StubCodeMark mark(this, "StubRoutines", "forward exception");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   453
    address start = __ pc();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   454
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   455
    // Upon entry, LR points to the return address returning into
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   456
    // Java (interpreted or compiled) code; i.e., the return address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   457
    // becomes the throwing pc.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   458
    //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   459
    // Arguments pushed before the runtime call are still on the stack
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   460
    // but the exception handler will reset the stack pointer ->
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   461
    // ignore them.  A potential result in registers can be ignored as
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   462
    // well.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   463
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   464
#ifdef ASSERT
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   465
    // make sure this code is only executed if there is a pending exception
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   466
    {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   467
      Label L;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   468
      __ ldr(rscratch1, Address(rthread, Thread::pending_exception_offset()));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   469
      __ cbnz(rscratch1, L);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   470
      __ stop("StubRoutines::forward exception: no pending exception (1)");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   471
      __ bind(L);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   472
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   473
#endif
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   474
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   475
    // compute exception handler into r19
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   476
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   477
    // call the VM to find the handler address associated with the
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   478
    // caller address. pass thread in r0 and caller pc (ret address)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   479
    // in r1. n.b. the caller pc is in lr, unlike x86 where it is on
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   480
    // the stack.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   481
    __ mov(c_rarg1, lr);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   482
    // lr will be trashed by the VM call so we move it to R19
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   483
    // (callee-saved) because we also need to pass it to the handler
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   484
    // returned by this call.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   485
    __ mov(r19, lr);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   486
    BLOCK_COMMENT("call exception_handler_for_return_address");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   487
    __ call_VM_leaf(CAST_FROM_FN_PTR(address,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   488
                         SharedRuntime::exception_handler_for_return_address),
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   489
                    rthread, c_rarg1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   490
    // we should not really care that lr is no longer the callee
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   491
    // address. we saved the value the handler needs in r19 so we can
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   492
    // just copy it to r3. however, the C2 handler will push its own
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   493
    // frame and then calls into the VM and the VM code asserts that
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   494
    // the PC for the frame above the handler belongs to a compiled
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   495
    // Java method. So, we restore lr here to satisfy that assert.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   496
    __ mov(lr, r19);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   497
    // setup r0 & r3 & clear pending exception
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   498
    __ mov(r3, r19);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   499
    __ mov(r19, r0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   500
    __ ldr(r0, Address(rthread, Thread::pending_exception_offset()));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   501
    __ str(zr, Address(rthread, Thread::pending_exception_offset()));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   502
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   503
#ifdef ASSERT
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   504
    // make sure exception is set
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   505
    {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   506
      Label L;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   507
      __ cbnz(r0, L);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   508
      __ stop("StubRoutines::forward exception: no pending exception (2)");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   509
      __ bind(L);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   510
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   511
#endif
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   512
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   513
    // continue at exception handler
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   514
    // r0: exception
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   515
    // r3: throwing pc
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   516
    // r19: exception handler
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   517
    __ verify_oop(r0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   518
    __ br(r19);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   519
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   520
    return start;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   521
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   522
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   523
  // Non-destructive plausibility checks for oops
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   524
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   525
  // Arguments:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   526
  //    r0: oop to verify
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   527
  //    rscratch1: error message
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   528
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   529
  // Stack after saving c_rarg3:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   530
  //    [tos + 0]: saved c_rarg3
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   531
  //    [tos + 1]: saved c_rarg2
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   532
  //    [tos + 2]: saved lr
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   533
  //    [tos + 3]: saved rscratch2
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   534
  //    [tos + 4]: saved r0
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   535
  //    [tos + 5]: saved rscratch1
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   536
  address generate_verify_oop() {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   537
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   538
    StubCodeMark mark(this, "StubRoutines", "verify_oop");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   539
    address start = __ pc();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   540
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   541
    Label exit, error;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   542
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   543
    // save c_rarg2 and c_rarg3
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   544
    __ stp(c_rarg3, c_rarg2, Address(__ pre(sp, -16)));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   545
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   546
    // __ incrementl(ExternalAddress((address) StubRoutines::verify_oop_count_addr()));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   547
    __ lea(c_rarg2, ExternalAddress((address) StubRoutines::verify_oop_count_addr()));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   548
    __ ldr(c_rarg3, Address(c_rarg2));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   549
    __ add(c_rarg3, c_rarg3, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   550
    __ str(c_rarg3, Address(c_rarg2));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   551
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   552
    // object is in r0
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   553
    // make sure object is 'reasonable'
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   554
    __ cbz(r0, exit); // if obj is NULL it is OK
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   555
55379
865775b86780 8214527: ZGC for Aarch64
smonteith
parents: 54991
diff changeset
   556
#if INCLUDE_ZGC
865775b86780 8214527: ZGC for Aarch64
smonteith
parents: 54991
diff changeset
   557
    if (UseZGC) {
865775b86780 8214527: ZGC for Aarch64
smonteith
parents: 54991
diff changeset
   558
      // Check if mask is good.
865775b86780 8214527: ZGC for Aarch64
smonteith
parents: 54991
diff changeset
   559
      // verifies that ZAddressBadMask & r0 == 0
865775b86780 8214527: ZGC for Aarch64
smonteith
parents: 54991
diff changeset
   560
      __ ldr(c_rarg3, Address(rthread, ZThreadLocalData::address_bad_mask_offset()));
865775b86780 8214527: ZGC for Aarch64
smonteith
parents: 54991
diff changeset
   561
      __ andr(c_rarg2, r0, c_rarg3);
865775b86780 8214527: ZGC for Aarch64
smonteith
parents: 54991
diff changeset
   562
      __ cbnz(c_rarg2, error);
865775b86780 8214527: ZGC for Aarch64
smonteith
parents: 54991
diff changeset
   563
    }
865775b86780 8214527: ZGC for Aarch64
smonteith
parents: 54991
diff changeset
   564
#endif
865775b86780 8214527: ZGC for Aarch64
smonteith
parents: 54991
diff changeset
   565
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   566
    // Check if the oop is in the right area of memory
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   567
    __ mov(c_rarg3, (intptr_t) Universe::verify_oop_mask());
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   568
    __ andr(c_rarg2, r0, c_rarg3);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   569
    __ mov(c_rarg3, (intptr_t) Universe::verify_oop_bits());
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   570
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   571
    // Compare c_rarg2 and c_rarg3.  We don't use a compare
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   572
    // instruction here because the flags register is live.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   573
    __ eor(c_rarg2, c_rarg2, c_rarg3);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   574
    __ cbnz(c_rarg2, error);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   575
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   576
    // make sure klass is 'reasonable', which is not zero.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   577
    __ load_klass(r0, r0);  // get klass
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   578
    __ cbz(r0, error);      // if klass is NULL it is broken
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   579
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   580
    // return if everything seems ok
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   581
    __ bind(exit);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   582
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   583
    __ ldp(c_rarg3, c_rarg2, Address(__ post(sp, 16)));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   584
    __ ret(lr);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   585
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   586
    // handle errors
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   587
    __ bind(error);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   588
    __ ldp(c_rarg3, c_rarg2, Address(__ post(sp, 16)));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   589
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   590
    __ push(RegSet::range(r0, r29), sp);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   591
    // debug(char* msg, int64_t pc, int64_t regs[])
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   592
    __ mov(c_rarg0, rscratch1);      // pass address of error message
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   593
    __ mov(c_rarg1, lr);             // pass return address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   594
    __ mov(c_rarg2, sp);             // pass address of regs on stack
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   595
#ifndef PRODUCT
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   596
    assert(frame::arg_reg_save_area_bytes == 0, "not expecting frame reg save area");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   597
#endif
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   598
    BLOCK_COMMENT("call MacroAssembler::debug");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   599
    __ mov(rscratch1, CAST_FROM_FN_PTR(address, MacroAssembler::debug64));
57565
01bca26734bb 8228400: Remove built-in AArch64 simulator
shade
parents: 55490
diff changeset
   600
    __ blr(rscratch1);
58103
689a80d20550 8230762: Change MacroAssembler::debug32/64 to use fatal instead of assert
chagedorn
parents: 57804
diff changeset
   601
    __ hlt(0);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   602
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   603
    return start;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   604
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   605
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   606
  void array_overlap_test(Label& L_no_overlap, Address::sxtw sf) { __ b(L_no_overlap); }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   607
45054
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   608
  // The inner part of zero_words().  This is the bulk operation,
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   609
  // zeroing words in blocks, possibly using DC ZVA to do it.  The
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   610
  // caller is responsible for zeroing the last few words.
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   611
  //
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   612
  // Inputs:
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   613
  // r10: the HeapWord-aligned base address of an array to zero.
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   614
  // r11: the count in HeapWords, r11 > 0.
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   615
  //
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   616
  // Returns r10 and r11, adjusted for the caller to clear.
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   617
  // r10: the base address of the tail of words left to clear.
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   618
  // r11: the number of words in the tail.
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   619
  //      r11 < MacroAssembler::zero_words_block_size.
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   620
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   621
  address generate_zero_blocks() {
51756
4bd35a5ec694 8210676: Remove some unused Label variables
mikael
parents: 51619
diff changeset
   622
    Label done;
45054
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   623
    Label base_aligned;
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   624
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   625
    Register base = r10, cnt = r11;
38143
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 38051
diff changeset
   626
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 38051
diff changeset
   627
    __ align(CodeEntryAlignment);
45054
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   628
    StubCodeMark mark(this, "StubRoutines", "zero_blocks");
38143
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 38051
diff changeset
   629
    address start = __ pc();
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 38051
diff changeset
   630
45054
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   631
    if (UseBlockZeroing) {
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   632
      int zva_length = VM_Version::zva_length();
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   633
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   634
      // Ensure ZVA length can be divided by 16. This is required by
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   635
      // the subsequent operations.
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   636
      assert (zva_length % 16 == 0, "Unexpected ZVA Length");
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   637
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   638
      __ tbz(base, 3, base_aligned);
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   639
      __ str(zr, Address(__ post(base, 8)));
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   640
      __ sub(cnt, cnt, 1);
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   641
      __ bind(base_aligned);
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   642
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   643
      // Ensure count >= zva_length * 2 so that it still deserves a zva after
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   644
      // alignment.
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   645
      Label small;
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   646
      int low_limit = MAX2(zva_length * 2, (int)BlockZeroingLowLimit);
46720
5c3f87b90eff 8184900: AArch64: Fix overflow in immediate cmp instruction
yzhang
parents: 46695
diff changeset
   647
      __ subs(rscratch1, cnt, low_limit >> 3);
45054
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   648
      __ br(Assembler::LT, small);
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   649
      __ zero_dcache_blocks(base, cnt);
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   650
      __ bind(small);
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   651
    }
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   652
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   653
    {
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   654
      // Number of stp instructions we'll unroll
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   655
      const int unroll =
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   656
        MacroAssembler::zero_words_block_size / 2;
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   657
      // Clear the remaining blocks.
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   658
      Label loop;
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   659
      __ subs(cnt, cnt, unroll * 2);
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   660
      __ br(Assembler::LT, done);
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   661
      __ bind(loop);
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   662
      for (int i = 0; i < unroll; i++)
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   663
        __ stp(zr, zr, __ post(base, 16));
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   664
      __ subs(cnt, cnt, unroll * 2);
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   665
      __ br(Assembler::GE, loop);
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   666
      __ bind(done);
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   667
      __ add(cnt, cnt, unroll * 2);
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   668
    }
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   669
38143
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 38051
diff changeset
   670
    __ ret(lr);
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 38051
diff changeset
   671
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 38051
diff changeset
   672
    return start;
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 38051
diff changeset
   673
  }
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 38051
diff changeset
   674
45054
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
   675
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   676
  typedef enum {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   677
    copy_forwards = 1,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   678
    copy_backwards = -1
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   679
  } copy_direction;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   680
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   681
  // Bulk copy of blocks of 8 words.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   682
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   683
  // count is a count of words.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   684
  //
36563
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
   685
  // Precondition: count >= 8
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   686
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   687
  // Postconditions:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   688
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   689
  // The least significant bit of count contains the remaining count
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   690
  // of words to copy.  The rest of count is trash.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   691
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   692
  // s and d are adjusted to point to the remaining words to copy
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   693
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   694
  void generate_copy_longs(Label &start, Register s, Register d, Register count,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   695
                           copy_direction direction) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   696
    int unit = wordSize * direction;
36564
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   697
    int bias = (UseSIMDForMemoryOps ? 4:2) * wordSize;
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   698
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   699
    int offset;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   700
    const Register t0 = r3, t1 = r4, t2 = r5, t3 = r6,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   701
      t4 = r7, t5 = r10, t6 = r11, t7 = r12;
35841
39f8dc1df42b 8149365: aarch64: memory copy does not prefetch on backwards copy
enevill
parents: 35839
diff changeset
   702
    const Register stride = r13;
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   703
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   704
    assert_different_registers(rscratch1, t0, t1, t2, t3, t4, t5, t6, t7);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   705
    assert_different_registers(s, d, count, rscratch1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   706
36563
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
   707
    Label again, drain;
35843
67b6050f5ce8 8149080: AArch64: Recognise disjoint array copy in stub code
hshi
parents: 35841
diff changeset
   708
    const char *stub_name;
67b6050f5ce8 8149080: AArch64: Recognise disjoint array copy in stub code
hshi
parents: 35841
diff changeset
   709
    if (direction == copy_forwards)
46695
aaaac1d98bc5 8183533: AArch64: redundent registers saving in arraycopy stubs
njian
parents: 46625
diff changeset
   710
      stub_name = "forward_copy_longs";
35843
67b6050f5ce8 8149080: AArch64: Recognise disjoint array copy in stub code
hshi
parents: 35841
diff changeset
   711
    else
67b6050f5ce8 8149080: AArch64: Recognise disjoint array copy in stub code
hshi
parents: 35841
diff changeset
   712
      stub_name = "backward_copy_longs";
52977
2e4903f83295 8205421: AARCH64: StubCodeMark should be placed after alignment
dpochepk
parents: 52927
diff changeset
   713
2e4903f83295 8205421: AARCH64: StubCodeMark should be placed after alignment
dpochepk
parents: 52927
diff changeset
   714
    __ align(CodeEntryAlignment);
2e4903f83295 8205421: AARCH64: StubCodeMark should be placed after alignment
dpochepk
parents: 52927
diff changeset
   715
35843
67b6050f5ce8 8149080: AArch64: Recognise disjoint array copy in stub code
hshi
parents: 35841
diff changeset
   716
    StubCodeMark mark(this, "StubRoutines", stub_name);
52977
2e4903f83295 8205421: AARCH64: StubCodeMark should be placed after alignment
dpochepk
parents: 52927
diff changeset
   717
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   718
    __ bind(start);
40023
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   719
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   720
    Label unaligned_copy_long;
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   721
    if (AvoidUnalignedAccesses) {
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   722
      __ tbnz(d, 3, unaligned_copy_long);
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   723
    }
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   724
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   725
    if (direction == copy_forwards) {
36564
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   726
      __ sub(s, s, bias);
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   727
      __ sub(d, d, bias);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   728
    }
36563
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
   729
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
   730
#ifdef ASSERT
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
   731
    // Make sure we are never given < 8 words
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   732
    {
36563
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
   733
      Label L;
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
   734
      __ cmp(count, (u1)8);
36563
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
   735
      __ br(Assembler::GE, L);
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
   736
      __ stop("genrate_copy_longs called with < 8 words");
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
   737
      __ bind(L);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   738
    }
36563
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
   739
#endif
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   740
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   741
    // Fill 8 registers
36564
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   742
    if (UseSIMDForMemoryOps) {
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   743
      __ ldpq(v0, v1, Address(s, 4 * unit));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   744
      __ ldpq(v2, v3, Address(__ pre(s, 8 * unit)));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   745
    } else {
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   746
      __ ldp(t0, t1, Address(s, 2 * unit));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   747
      __ ldp(t2, t3, Address(s, 4 * unit));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   748
      __ ldp(t4, t5, Address(s, 6 * unit));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   749
      __ ldp(t6, t7, Address(__ pre(s, 8 * unit)));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   750
    }
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   751
36563
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
   752
    __ subs(count, count, 16);
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
   753
    __ br(Assembler::LO, drain);
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
   754
35841
39f8dc1df42b 8149365: aarch64: memory copy does not prefetch on backwards copy
enevill
parents: 35839
diff changeset
   755
    int prefetch = PrefetchCopyIntervalInBytes;
39f8dc1df42b 8149365: aarch64: memory copy does not prefetch on backwards copy
enevill
parents: 35839
diff changeset
   756
    bool use_stride = false;
39f8dc1df42b 8149365: aarch64: memory copy does not prefetch on backwards copy
enevill
parents: 35839
diff changeset
   757
    if (direction == copy_backwards) {
39f8dc1df42b 8149365: aarch64: memory copy does not prefetch on backwards copy
enevill
parents: 35839
diff changeset
   758
       use_stride = prefetch > 256;
39f8dc1df42b 8149365: aarch64: memory copy does not prefetch on backwards copy
enevill
parents: 35839
diff changeset
   759
       prefetch = -prefetch;
39f8dc1df42b 8149365: aarch64: memory copy does not prefetch on backwards copy
enevill
parents: 35839
diff changeset
   760
       if (use_stride) __ mov(stride, prefetch);
39f8dc1df42b 8149365: aarch64: memory copy does not prefetch on backwards copy
enevill
parents: 35839
diff changeset
   761
    }
39f8dc1df42b 8149365: aarch64: memory copy does not prefetch on backwards copy
enevill
parents: 35839
diff changeset
   762
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   763
    __ bind(again);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   764
35841
39f8dc1df42b 8149365: aarch64: memory copy does not prefetch on backwards copy
enevill
parents: 35839
diff changeset
   765
    if (PrefetchCopyIntervalInBytes > 0)
39f8dc1df42b 8149365: aarch64: memory copy does not prefetch on backwards copy
enevill
parents: 35839
diff changeset
   766
      __ prfm(use_stride ? Address(s, stride) : Address(s, prefetch), PLDL1KEEP);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   767
36564
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   768
    if (UseSIMDForMemoryOps) {
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   769
      __ stpq(v0, v1, Address(d, 4 * unit));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   770
      __ ldpq(v0, v1, Address(s, 4 * unit));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   771
      __ stpq(v2, v3, Address(__ pre(d, 8 * unit)));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   772
      __ ldpq(v2, v3, Address(__ pre(s, 8 * unit)));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   773
    } else {
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   774
      __ stp(t0, t1, Address(d, 2 * unit));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   775
      __ ldp(t0, t1, Address(s, 2 * unit));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   776
      __ stp(t2, t3, Address(d, 4 * unit));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   777
      __ ldp(t2, t3, Address(s, 4 * unit));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   778
      __ stp(t4, t5, Address(d, 6 * unit));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   779
      __ ldp(t4, t5, Address(s, 6 * unit));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   780
      __ stp(t6, t7, Address(__ pre(d, 8 * unit)));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   781
      __ ldp(t6, t7, Address(__ pre(s, 8 * unit)));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   782
    }
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   783
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   784
    __ subs(count, count, 8);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   785
    __ br(Assembler::HS, again);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   786
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   787
    // Drain
36563
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
   788
    __ bind(drain);
36564
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   789
    if (UseSIMDForMemoryOps) {
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   790
      __ stpq(v0, v1, Address(d, 4 * unit));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   791
      __ stpq(v2, v3, Address(__ pre(d, 8 * unit)));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   792
    } else {
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   793
      __ stp(t0, t1, Address(d, 2 * unit));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   794
      __ stp(t2, t3, Address(d, 4 * unit));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   795
      __ stp(t4, t5, Address(d, 6 * unit));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   796
      __ stp(t6, t7, Address(__ pre(d, 8 * unit)));
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   797
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   798
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   799
    {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   800
      Label L1, L2;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   801
      __ tbz(count, exact_log2(4), L1);
36564
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   802
      if (UseSIMDForMemoryOps) {
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   803
        __ ldpq(v0, v1, Address(__ pre(s, 4 * unit)));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   804
        __ stpq(v0, v1, Address(__ pre(d, 4 * unit)));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   805
      } else {
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   806
        __ ldp(t0, t1, Address(s, 2 * unit));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   807
        __ ldp(t2, t3, Address(__ pre(s, 4 * unit)));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   808
        __ stp(t0, t1, Address(d, 2 * unit));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   809
        __ stp(t2, t3, Address(__ pre(d, 4 * unit)));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   810
      }
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   811
      __ bind(L1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   812
36564
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   813
      if (direction == copy_forwards) {
36595
3322a76f3a00 8151502: optimize pd_disjoint_words and pd_conjoint_words
enevill
parents: 36564
diff changeset
   814
        __ add(s, s, bias);
3322a76f3a00 8151502: optimize pd_disjoint_words and pd_conjoint_words
enevill
parents: 36564
diff changeset
   815
        __ add(d, d, bias);
36564
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   816
      }
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
   817
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   818
      __ tbz(count, 1, L2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   819
      __ ldp(t0, t1, Address(__ adjust(s, 2 * unit, direction == copy_backwards)));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   820
      __ stp(t0, t1, Address(__ adjust(d, 2 * unit, direction == copy_backwards)));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   821
      __ bind(L2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   822
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   823
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   824
    __ ret(lr);
40023
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   825
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   826
    if (AvoidUnalignedAccesses) {
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   827
      Label drain, again;
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   828
      // Register order for storing. Order is different for backward copy.
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   829
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   830
      __ bind(unaligned_copy_long);
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   831
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   832
      // source address is even aligned, target odd aligned
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   833
      //
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   834
      // when forward copying word pairs we read long pairs at offsets
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   835
      // {0, 2, 4, 6} (in long words). when backwards copying we read
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   836
      // long pairs at offsets {-2, -4, -6, -8}. We adjust the source
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   837
      // address by -2 in the forwards case so we can compute the
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   838
      // source offsets for both as {2, 4, 6, 8} * unit where unit = 1
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   839
      // or -1.
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   840
      //
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   841
      // when forward copying we need to store 1 word, 3 pairs and
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   842
      // then 1 word at offsets {0, 1, 3, 5, 7}. Rather thna use a
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   843
      // zero offset We adjust the destination by -1 which means we
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   844
      // have to use offsets { 1, 2, 4, 6, 8} * unit for the stores.
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   845
      //
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   846
      // When backwards copyng we need to store 1 word, 3 pairs and
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   847
      // then 1 word at offsets {-1, -3, -5, -7, -8} i.e. we use
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   848
      // offsets {1, 3, 5, 7, 8} * unit.
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   849
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   850
      if (direction == copy_forwards) {
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   851
        __ sub(s, s, 16);
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   852
        __ sub(d, d, 8);
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   853
      }
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   854
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   855
      // Fill 8 registers
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   856
      //
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   857
      // for forwards copy s was offset by -16 from the original input
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   858
      // value of s so the register contents are at these offsets
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   859
      // relative to the 64 bit block addressed by that original input
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   860
      // and so on for each successive 64 byte block when s is updated
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   861
      //
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   862
      // t0 at offset 0,  t1 at offset 8
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   863
      // t2 at offset 16, t3 at offset 24
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   864
      // t4 at offset 32, t5 at offset 40
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   865
      // t6 at offset 48, t7 at offset 56
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   866
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   867
      // for backwards copy s was not offset so the register contents
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   868
      // are at these offsets into the preceding 64 byte block
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   869
      // relative to that original input and so on for each successive
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   870
      // preceding 64 byte block when s is updated. this explains the
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   871
      // slightly counter-intuitive looking pattern of register usage
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   872
      // in the stp instructions for backwards copy.
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   873
      //
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   874
      // t0 at offset -16, t1 at offset -8
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   875
      // t2 at offset -32, t3 at offset -24
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   876
      // t4 at offset -48, t5 at offset -40
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   877
      // t6 at offset -64, t7 at offset -56
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   878
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   879
      __ ldp(t0, t1, Address(s, 2 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   880
      __ ldp(t2, t3, Address(s, 4 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   881
      __ ldp(t4, t5, Address(s, 6 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   882
      __ ldp(t6, t7, Address(__ pre(s, 8 * unit)));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   883
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   884
      __ subs(count, count, 16);
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   885
      __ br(Assembler::LO, drain);
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   886
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   887
      int prefetch = PrefetchCopyIntervalInBytes;
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   888
      bool use_stride = false;
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   889
      if (direction == copy_backwards) {
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   890
         use_stride = prefetch > 256;
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   891
         prefetch = -prefetch;
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   892
         if (use_stride) __ mov(stride, prefetch);
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   893
      }
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   894
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   895
      __ bind(again);
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   896
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   897
      if (PrefetchCopyIntervalInBytes > 0)
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   898
        __ prfm(use_stride ? Address(s, stride) : Address(s, prefetch), PLDL1KEEP);
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   899
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   900
      if (direction == copy_forwards) {
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   901
       // allowing for the offset of -8 the store instructions place
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   902
       // registers into the target 64 bit block at the following
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   903
       // offsets
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   904
       //
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   905
       // t0 at offset 0
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   906
       // t1 at offset 8,  t2 at offset 16
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   907
       // t3 at offset 24, t4 at offset 32
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   908
       // t5 at offset 40, t6 at offset 48
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   909
       // t7 at offset 56
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   910
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   911
        __ str(t0, Address(d, 1 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   912
        __ stp(t1, t2, Address(d, 2 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   913
        __ ldp(t0, t1, Address(s, 2 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   914
        __ stp(t3, t4, Address(d, 4 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   915
        __ ldp(t2, t3, Address(s, 4 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   916
        __ stp(t5, t6, Address(d, 6 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   917
        __ ldp(t4, t5, Address(s, 6 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   918
        __ str(t7, Address(__ pre(d, 8 * unit)));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   919
        __ ldp(t6, t7, Address(__ pre(s, 8 * unit)));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   920
      } else {
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   921
       // d was not offset when we started so the registers are
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   922
       // written into the 64 bit block preceding d with the following
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   923
       // offsets
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   924
       //
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   925
       // t1 at offset -8
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   926
       // t3 at offset -24, t0 at offset -16
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   927
       // t5 at offset -48, t2 at offset -32
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   928
       // t7 at offset -56, t4 at offset -48
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   929
       //                   t6 at offset -64
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   930
       //
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   931
       // note that this matches the offsets previously noted for the
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   932
       // loads
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   933
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   934
        __ str(t1, Address(d, 1 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   935
        __ stp(t3, t0, Address(d, 3 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   936
        __ ldp(t0, t1, Address(s, 2 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   937
        __ stp(t5, t2, Address(d, 5 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   938
        __ ldp(t2, t3, Address(s, 4 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   939
        __ stp(t7, t4, Address(d, 7 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   940
        __ ldp(t4, t5, Address(s, 6 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   941
        __ str(t6, Address(__ pre(d, 8 * unit)));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   942
        __ ldp(t6, t7, Address(__ pre(s, 8 * unit)));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   943
      }
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   944
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   945
      __ subs(count, count, 8);
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   946
      __ br(Assembler::HS, again);
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   947
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   948
      // Drain
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   949
      //
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   950
      // this uses the same pattern of offsets and register arguments
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   951
      // as above
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   952
      __ bind(drain);
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   953
      if (direction == copy_forwards) {
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   954
        __ str(t0, Address(d, 1 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   955
        __ stp(t1, t2, Address(d, 2 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   956
        __ stp(t3, t4, Address(d, 4 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   957
        __ stp(t5, t6, Address(d, 6 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   958
        __ str(t7, Address(__ pre(d, 8 * unit)));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   959
      } else {
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   960
        __ str(t1, Address(d, 1 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   961
        __ stp(t3, t0, Address(d, 3 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   962
        __ stp(t5, t2, Address(d, 5 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   963
        __ stp(t7, t4, Address(d, 7 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   964
        __ str(t6, Address(__ pre(d, 8 * unit)));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   965
      }
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   966
      // now we need to copy any remaining part block which may
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   967
      // include a 4 word block subblock and/or a 2 word subblock.
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   968
      // bits 2 and 1 in the count are the tell-tale for whetehr we
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   969
      // have each such subblock
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   970
      {
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   971
        Label L1, L2;
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   972
        __ tbz(count, exact_log2(4), L1);
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   973
       // this is the same as above but copying only 4 longs hence
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   974
       // with ony one intervening stp between the str instructions
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   975
       // but note that the offsets and registers still follow the
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   976
       // same pattern
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   977
        __ ldp(t0, t1, Address(s, 2 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   978
        __ ldp(t2, t3, Address(__ pre(s, 4 * unit)));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   979
        if (direction == copy_forwards) {
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   980
          __ str(t0, Address(d, 1 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   981
          __ stp(t1, t2, Address(d, 2 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   982
          __ str(t3, Address(__ pre(d, 4 * unit)));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   983
        } else {
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   984
          __ str(t1, Address(d, 1 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   985
          __ stp(t3, t0, Address(d, 3 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   986
          __ str(t2, Address(__ pre(d, 4 * unit)));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   987
        }
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   988
        __ bind(L1);
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   989
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   990
        __ tbz(count, 1, L2);
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   991
       // this is the same as above but copying only 2 longs hence
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   992
       // there is no intervening stp between the str instructions
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   993
       // but note that the offset and register patterns are still
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   994
       // the same
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   995
        __ ldp(t0, t1, Address(__ pre(s, 2 * unit)));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   996
        if (direction == copy_forwards) {
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   997
          __ str(t0, Address(d, 1 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   998
          __ str(t1, Address(__ pre(d, 2 * unit)));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
   999
        } else {
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
  1000
          __ str(t1, Address(d, 1 * unit));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
  1001
          __ str(t0, Address(__ pre(d, 2 * unit)));
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
  1002
        }
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
  1003
        __ bind(L2);
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
  1004
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
  1005
       // for forwards copy we need to re-adjust the offsets we
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
  1006
       // applied so that s and d are follow the last words written
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
  1007
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
  1008
       if (direction == copy_forwards) {
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
  1009
         __ add(s, s, 16);
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
  1010
         __ add(d, d, 8);
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
  1011
       }
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
  1012
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
  1013
      }
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
  1014
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
  1015
      __ ret(lr);
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
  1016
      }
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1017
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1018
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1019
  // Small copy: less than 16 bytes.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1020
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1021
  // NB: Ignores all of the bits of count which represent more than 15
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1022
  // bytes, so a caller doesn't have to mask them.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1023
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1024
  void copy_memory_small(Register s, Register d, Register count, Register tmp, int step) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1025
    bool is_backwards = step < 0;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1026
    size_t granularity = uabs(step);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1027
    int direction = is_backwards ? -1 : 1;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1028
    int unit = wordSize * direction;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1029
51756
4bd35a5ec694 8210676: Remove some unused Label variables
mikael
parents: 51619
diff changeset
  1030
    Label Lword, Lint, Lshort, Lbyte;
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1031
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1032
    assert(granularity
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1033
           && granularity <= sizeof (jlong), "Impossible granularity in copy_memory_small");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1034
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1035
    const Register t0 = r3, t1 = r4, t2 = r5, t3 = r6;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1036
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1037
    // ??? I don't know if this bit-test-and-branch is the right thing
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1038
    // to do.  It does a lot of jumping, resulting in several
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1039
    // mispredicted branches.  It might make more sense to do this
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1040
    // with something like Duff's device with a single computed branch.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1041
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1042
    __ tbz(count, 3 - exact_log2(granularity), Lword);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1043
    __ ldr(tmp, Address(__ adjust(s, unit, is_backwards)));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1044
    __ str(tmp, Address(__ adjust(d, unit, is_backwards)));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1045
    __ bind(Lword);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1046
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1047
    if (granularity <= sizeof (jint)) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1048
      __ tbz(count, 2 - exact_log2(granularity), Lint);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1049
      __ ldrw(tmp, Address(__ adjust(s, sizeof (jint) * direction, is_backwards)));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1050
      __ strw(tmp, Address(__ adjust(d, sizeof (jint) * direction, is_backwards)));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1051
      __ bind(Lint);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1052
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1053
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1054
    if (granularity <= sizeof (jshort)) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1055
      __ tbz(count, 1 - exact_log2(granularity), Lshort);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1056
      __ ldrh(tmp, Address(__ adjust(s, sizeof (jshort) * direction, is_backwards)));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1057
      __ strh(tmp, Address(__ adjust(d, sizeof (jshort) * direction, is_backwards)));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1058
      __ bind(Lshort);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1059
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1060
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1061
    if (granularity <= sizeof (jbyte)) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1062
      __ tbz(count, 0, Lbyte);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1063
      __ ldrb(tmp, Address(__ adjust(s, sizeof (jbyte) * direction, is_backwards)));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1064
      __ strb(tmp, Address(__ adjust(d, sizeof (jbyte) * direction, is_backwards)));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1065
      __ bind(Lbyte);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1066
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1067
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1068
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1069
  Label copy_f, copy_b;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1070
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1071
  // All-singing all-dancing memory copy.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1072
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1073
  // Copy count units of memory from s to d.  The size of a unit is
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1074
  // step, which can be positive or negative depending on the direction
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1075
  // of copy.  If is_aligned is false, we align the source address.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1076
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1077
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1078
  void copy_memory(bool is_aligned, Register s, Register d,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1079
                   Register count, Register tmp, int step) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1080
    copy_direction direction = step < 0 ? copy_backwards : copy_forwards;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1081
    bool is_backwards = step < 0;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1082
    int granularity = uabs(step);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1083
    const Register t0 = r3, t1 = r4;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1084
36563
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1085
    // <= 96 bytes do inline. Direction doesn't matter because we always
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1086
    // load all the data before writing anything
51756
4bd35a5ec694 8210676: Remove some unused Label variables
mikael
parents: 51619
diff changeset
  1087
    Label copy4, copy8, copy16, copy32, copy80, copy_big, finish;
36563
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1088
    const Register t2 = r5, t3 = r6, t4 = r7, t5 = r8;
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1089
    const Register t6 = r9, t7 = r10, t8 = r11, t9 = r12;
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1090
    const Register send = r17, dend = r18;
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1091
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1092
    if (PrefetchCopyIntervalInBytes > 0)
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1093
      __ prfm(Address(s, 0), PLDL1KEEP);
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
  1094
    __ cmp(count, u1((UseSIMDForMemoryOps ? 96:80)/granularity));
36563
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1095
    __ br(Assembler::HI, copy_big);
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1096
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1097
    __ lea(send, Address(s, count, Address::lsl(exact_log2(granularity))));
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1098
    __ lea(dend, Address(d, count, Address::lsl(exact_log2(granularity))));
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1099
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
  1100
    __ cmp(count, u1(16/granularity));
36563
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1101
    __ br(Assembler::LS, copy16);
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1102
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
  1103
    __ cmp(count, u1(64/granularity));
36563
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1104
    __ br(Assembler::HI, copy80);
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1105
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
  1106
    __ cmp(count, u1(32/granularity));
36563
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1107
    __ br(Assembler::LS, copy32);
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1108
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1109
    // 33..64 bytes
36564
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1110
    if (UseSIMDForMemoryOps) {
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1111
      __ ldpq(v0, v1, Address(s, 0));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1112
      __ ldpq(v2, v3, Address(send, -32));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1113
      __ stpq(v0, v1, Address(d, 0));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1114
      __ stpq(v2, v3, Address(dend, -32));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1115
    } else {
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1116
      __ ldp(t0, t1, Address(s, 0));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1117
      __ ldp(t2, t3, Address(s, 16));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1118
      __ ldp(t4, t5, Address(send, -32));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1119
      __ ldp(t6, t7, Address(send, -16));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1120
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1121
      __ stp(t0, t1, Address(d, 0));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1122
      __ stp(t2, t3, Address(d, 16));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1123
      __ stp(t4, t5, Address(dend, -32));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1124
      __ stp(t6, t7, Address(dend, -16));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1125
    }
36563
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1126
    __ b(finish);
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1127
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1128
    // 17..32 bytes
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1129
    __ bind(copy32);
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1130
    __ ldp(t0, t1, Address(s, 0));
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1131
    __ ldp(t2, t3, Address(send, -16));
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1132
    __ stp(t0, t1, Address(d, 0));
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1133
    __ stp(t2, t3, Address(dend, -16));
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1134
    __ b(finish);
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1135
36564
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1136
    // 65..80/96 bytes
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1137
    // (96 bytes if SIMD because we do 32 byes per instruction)
36563
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1138
    __ bind(copy80);
36564
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1139
    if (UseSIMDForMemoryOps) {
40023
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
  1140
      __ ld4(v0, v1, v2, v3, __ T16B, Address(s, 0));
36564
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1141
      __ ldpq(v4, v5, Address(send, -32));
40023
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
enevill
parents: 39265
diff changeset
  1142
      __ st4(v0, v1, v2, v3, __ T16B, Address(d, 0));
36564
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1143
      __ stpq(v4, v5, Address(dend, -32));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1144
    } else {
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1145
      __ ldp(t0, t1, Address(s, 0));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1146
      __ ldp(t2, t3, Address(s, 16));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1147
      __ ldp(t4, t5, Address(s, 32));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1148
      __ ldp(t6, t7, Address(s, 48));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1149
      __ ldp(t8, t9, Address(send, -16));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1150
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1151
      __ stp(t0, t1, Address(d, 0));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1152
      __ stp(t2, t3, Address(d, 16));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1153
      __ stp(t4, t5, Address(d, 32));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1154
      __ stp(t6, t7, Address(d, 48));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1155
      __ stp(t8, t9, Address(dend, -16));
9442bb67de26 8150313: aarch64: optimise array copy using SIMD instructions
enevill
parents: 36563
diff changeset
  1156
    }
36563
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1157
    __ b(finish);
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1158
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1159
    // 0..16 bytes
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1160
    __ bind(copy16);
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
  1161
    __ cmp(count, u1(8/granularity));
36563
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1162
    __ br(Assembler::LO, copy8);
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1163
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1164
    // 8..16 bytes
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1165
    __ ldr(t0, Address(s, 0));
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1166
    __ ldr(t1, Address(send, -8));
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1167
    __ str(t0, Address(d, 0));
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1168
    __ str(t1, Address(dend, -8));
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1169
    __ b(finish);
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1170
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1171
    if (granularity < 8) {
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1172
      // 4..7 bytes
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1173
      __ bind(copy8);
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1174
      __ tbz(count, 2 - exact_log2(granularity), copy4);
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1175
      __ ldrw(t0, Address(s, 0));
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1176
      __ ldrw(t1, Address(send, -4));
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1177
      __ strw(t0, Address(d, 0));
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1178
      __ strw(t1, Address(dend, -4));
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1179
      __ b(finish);
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1180
      if (granularity < 4) {
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1181
        // 0..3 bytes
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1182
        __ bind(copy4);
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1183
        __ cbz(count, finish); // get rid of 0 case
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1184
        if (granularity == 2) {
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1185
          __ ldrh(t0, Address(s, 0));
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1186
          __ strh(t0, Address(d, 0));
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1187
        } else { // granularity == 1
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1188
          // Now 1..3 bytes. Handle the 1 and 2 byte case by copying
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1189
          // the first and last byte.
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1190
          // Handle the 3 byte case by loading and storing base + count/2
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1191
          // (count == 1 (s+0)->(d+0), count == 2,3 (s+1) -> (d+1))
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1192
          // This does means in the 1 byte case we load/store the same
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1193
          // byte 3 times.
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1194
          __ lsr(count, count, 1);
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1195
          __ ldrb(t0, Address(s, 0));
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1196
          __ ldrb(t1, Address(send, -1));
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1197
          __ ldrb(t2, Address(s, count));
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1198
          __ strb(t0, Address(d, 0));
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1199
          __ strb(t1, Address(dend, -1));
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1200
          __ strb(t2, Address(d, count));
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1201
        }
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1202
        __ b(finish);
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1203
      }
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1204
    }
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1205
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1206
    __ bind(copy_big);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1207
    if (is_backwards) {
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1208
      __ lea(s, Address(s, count, Address::lsl(exact_log2(-step))));
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1209
      __ lea(d, Address(d, count, Address::lsl(exact_log2(-step))));
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1210
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1211
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1212
    // Now we've got the small case out of the way we can align the
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1213
    // source address on a 2-word boundary.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1214
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1215
    Label aligned;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1216
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1217
    if (is_aligned) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1218
      // We may have to adjust by 1 word to get s 2-word-aligned.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1219
      __ tbz(s, exact_log2(wordSize), aligned);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1220
      __ ldr(tmp, Address(__ adjust(s, direction * wordSize, is_backwards)));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1221
      __ str(tmp, Address(__ adjust(d, direction * wordSize, is_backwards)));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1222
      __ sub(count, count, wordSize/granularity);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1223
    } else {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1224
      if (is_backwards) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1225
        __ andr(rscratch2, s, 2 * wordSize - 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1226
      } else {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1227
        __ neg(rscratch2, s);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1228
        __ andr(rscratch2, rscratch2, 2 * wordSize - 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1229
      }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1230
      // rscratch2 is the byte adjustment needed to align s.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1231
      __ cbz(rscratch2, aligned);
35752
16265e7c7a53 8148328: aarch64: redundant lsr instructions in stub code.
fyang
parents: 35579
diff changeset
  1232
      int shift = exact_log2(granularity);
16265e7c7a53 8148328: aarch64: redundant lsr instructions in stub code.
fyang
parents: 35579
diff changeset
  1233
      if (shift)  __ lsr(rscratch2, rscratch2, shift);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1234
      __ sub(count, count, rscratch2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1235
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1236
#if 0
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1237
      // ?? This code is only correct for a disjoint copy.  It may or
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1238
      // may not make sense to use it in that case.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1239
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1240
      // Copy the first pair; s and d may not be aligned.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1241
      __ ldp(t0, t1, Address(s, is_backwards ? -2 * wordSize : 0));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1242
      __ stp(t0, t1, Address(d, is_backwards ? -2 * wordSize : 0));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1243
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1244
      // Align s and d, adjust count
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1245
      if (is_backwards) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1246
        __ sub(s, s, rscratch2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1247
        __ sub(d, d, rscratch2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1248
      } else {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1249
        __ add(s, s, rscratch2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1250
        __ add(d, d, rscratch2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1251
      }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1252
#else
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1253
      copy_memory_small(s, d, rscratch2, rscratch1, step);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1254
#endif
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1255
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1256
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1257
    __ bind(aligned);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1258
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1259
    // s is now 2-word-aligned.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1260
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1261
    // We have a count of units and some trailing bytes.  Adjust the
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1262
    // count and do a bulk copy of words.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1263
    __ lsr(rscratch2, count, exact_log2(wordSize/granularity));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1264
    if (direction == copy_forwards)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1265
      __ bl(copy_f);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1266
    else
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1267
      __ bl(copy_b);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1268
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1269
    // And the tail.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1270
    copy_memory_small(s, d, count, tmp, step);
36563
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1271
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1272
    if (granularity >= 8) __ bind(copy8);
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1273
    if (granularity >= 4) __ bind(copy4);
0b48c2c8ad13 8150082: aarch64: optimise small array copy
enevill
parents: 36340
diff changeset
  1274
    __ bind(finish);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1275
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1276
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1277
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1278
  void clobber_registers() {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1279
#ifdef ASSERT
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1280
    __ mov(rscratch1, (uint64_t)0xdeadbeef);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1281
    __ orr(rscratch1, rscratch1, rscratch1, Assembler::LSL, 32);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1282
    for (Register r = r3; r <= r18; r++)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1283
      if (r != rscratch1) __ mov(r, rscratch1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1284
#endif
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1285
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1286
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1287
  // Scan over array at a for count oops, verifying each one.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1288
  // Preserves a and count, clobbers rscratch1 and rscratch2.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1289
  void verify_oop_array (size_t size, Register a, Register count, Register temp) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1290
    Label loop, end;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1291
    __ mov(rscratch1, a);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1292
    __ mov(rscratch2, zr);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1293
    __ bind(loop);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1294
    __ cmp(rscratch2, count);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1295
    __ br(Assembler::HS, end);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1296
    if (size == (size_t)wordSize) {
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1297
      __ ldr(temp, Address(a, rscratch2, Address::lsl(exact_log2(size))));
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1298
      __ verify_oop(temp);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1299
    } else {
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1300
      __ ldrw(r16, Address(a, rscratch2, Address::lsl(exact_log2(size))));
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1301
      __ decode_heap_oop(temp); // calls verify_oop
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1302
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1303
    __ add(rscratch2, rscratch2, size);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1304
    __ b(loop);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1305
    __ bind(end);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1306
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1307
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1308
  // Arguments:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1309
  //   aligned - true => Input and output aligned on a HeapWord == 8-byte boundary
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1310
  //             ignored
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1311
  //   is_oop  - true => oop array, so generate store check code
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1312
  //   name    - stub name string
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1313
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1314
  // Inputs:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1315
  //   c_rarg0   - source array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1316
  //   c_rarg1   - destination array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1317
  //   c_rarg2   - element count, treated as ssize_t, can be zero
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1318
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1319
  // If 'from' and/or 'to' are aligned on 4-byte boundaries, we let
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1320
  // the hardware handle it.  The two dwords within qwords that span
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1321
  // cache line boundaries will still be loaded and stored atomicly.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1322
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1323
  // Side Effects:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1324
  //   disjoint_int_copy_entry is set to the no-overlap entry point
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1325
  //   used by generate_conjoint_int_oop_copy().
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1326
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1327
  address generate_disjoint_copy(size_t size, bool aligned, bool is_oop, address *entry,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1328
                                  const char *name, bool dest_uninitialized = false) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1329
    Register s = c_rarg0, d = c_rarg1, count = c_rarg2;
46695
aaaac1d98bc5 8183533: AArch64: redundent registers saving in arraycopy stubs
njian
parents: 46625
diff changeset
  1330
    RegSet saved_reg = RegSet::of(s, d, count);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1331
    __ align(CodeEntryAlignment);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1332
    StubCodeMark mark(this, "StubRoutines", name);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1333
    address start = __ pc();
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1334
    __ enter();
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1335
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1336
    if (entry != NULL) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1337
      *entry = __ pc();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1338
      // caller can pass a 64-bit byte count here (from Unsafe.copyMemory)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1339
      BLOCK_COMMENT("Entry:");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1340
    }
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1341
50728
9375184cec98 8205459: Rename Access API flag decorators
kbarrett
parents: 50242
diff changeset
  1342
    DecoratorSet decorators = IN_HEAP | IS_ARRAY | ARRAYCOPY_DISJOINT;
49484
ee8fa73b90f9 8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents: 49455
diff changeset
  1343
    if (dest_uninitialized) {
50728
9375184cec98 8205459: Rename Access API flag decorators
kbarrett
parents: 50242
diff changeset
  1344
      decorators |= IS_DEST_UNINITIALIZED;
49484
ee8fa73b90f9 8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents: 49455
diff changeset
  1345
    }
ee8fa73b90f9 8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents: 49455
diff changeset
  1346
    if (aligned) {
ee8fa73b90f9 8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents: 49455
diff changeset
  1347
      decorators |= ARRAYCOPY_ALIGNED;
ee8fa73b90f9 8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents: 49455
diff changeset
  1348
    }
ee8fa73b90f9 8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents: 49455
diff changeset
  1349
49754
ee93c1087584 8201362: Remove CollectedHeap::barrier_set()
pliden
parents: 49724
diff changeset
  1350
    BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
54979
f982c1a6582c 8224187: Refactor arraycopy_prologue to allow ZGC read barriers on arraycopy
smonteith
parents: 54786
diff changeset
  1351
    bs->arraycopy_prologue(_masm, decorators, is_oop, s, d, count, saved_reg);
49484
ee8fa73b90f9 8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents: 49455
diff changeset
  1352
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1353
    if (is_oop) {
46695
aaaac1d98bc5 8183533: AArch64: redundent registers saving in arraycopy stubs
njian
parents: 46625
diff changeset
  1354
      // save regs before copy_memory
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1355
      __ push(RegSet::of(d, count), sp);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1356
    }
55490
3f3dc00a69a5 8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents: 55379
diff changeset
  1357
    {
3f3dc00a69a5 8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents: 55379
diff changeset
  1358
      // UnsafeCopyMemory page error: continue after ucm
3f3dc00a69a5 8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents: 55379
diff changeset
  1359
      bool add_entry = !is_oop && (!aligned || sizeof(jlong) == size);
3f3dc00a69a5 8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents: 55379
diff changeset
  1360
      UnsafeCopyMemoryMark ucmm(this, add_entry, true);
3f3dc00a69a5 8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents: 55379
diff changeset
  1361
      copy_memory(aligned, s, d, count, rscratch1, size);
3f3dc00a69a5 8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents: 55379
diff changeset
  1362
    }
49484
ee8fa73b90f9 8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents: 49455
diff changeset
  1363
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1364
    if (is_oop) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1365
      __ pop(RegSet::of(d, count), sp);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1366
      if (VerifyOops)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1367
        verify_oop_array(size, d, count, r16);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1368
    }
49484
ee8fa73b90f9 8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents: 49455
diff changeset
  1369
ee8fa73b90f9 8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents: 49455
diff changeset
  1370
    bs->arraycopy_epilogue(_masm, decorators, is_oop, d, count, rscratch1, RegSet());
ee8fa73b90f9 8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents: 49455
diff changeset
  1371
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1372
    __ leave();
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1373
    __ mov(r0, zr); // return 0
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1374
    __ ret(lr);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1375
    return start;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1376
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1377
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1378
  // Arguments:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1379
  //   aligned - true => Input and output aligned on a HeapWord == 8-byte boundary
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1380
  //             ignored
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1381
  //   is_oop  - true => oop array, so generate store check code
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1382
  //   name    - stub name string
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1383
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1384
  // Inputs:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1385
  //   c_rarg0   - source array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1386
  //   c_rarg1   - destination array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1387
  //   c_rarg2   - element count, treated as ssize_t, can be zero
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1388
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1389
  // If 'from' and/or 'to' are aligned on 4-byte boundaries, we let
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1390
  // the hardware handle it.  The two dwords within qwords that span
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1391
  // cache line boundaries will still be loaded and stored atomicly.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1392
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1393
  address generate_conjoint_copy(size_t size, bool aligned, bool is_oop, address nooverlap_target,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1394
                                 address *entry, const char *name,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1395
                                 bool dest_uninitialized = false) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1396
    Register s = c_rarg0, d = c_rarg1, count = c_rarg2;
46695
aaaac1d98bc5 8183533: AArch64: redundent registers saving in arraycopy stubs
njian
parents: 46625
diff changeset
  1397
    RegSet saved_regs = RegSet::of(s, d, count);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1398
    StubCodeMark mark(this, "StubRoutines", name);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1399
    address start = __ pc();
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1400
    __ enter();
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1401
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1402
    if (entry != NULL) {
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1403
      *entry = __ pc();
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1404
      // caller can pass a 64-bit byte count here (from Unsafe.copyMemory)
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1405
      BLOCK_COMMENT("Entry:");
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1406
    }
35843
67b6050f5ce8 8149080: AArch64: Recognise disjoint array copy in stub code
hshi
parents: 35841
diff changeset
  1407
67b6050f5ce8 8149080: AArch64: Recognise disjoint array copy in stub code
hshi
parents: 35841
diff changeset
  1408
    // use fwd copy when (d-s) above_equal (count*size)
67b6050f5ce8 8149080: AArch64: Recognise disjoint array copy in stub code
hshi
parents: 35841
diff changeset
  1409
    __ sub(rscratch1, d, s);
67b6050f5ce8 8149080: AArch64: Recognise disjoint array copy in stub code
hshi
parents: 35841
diff changeset
  1410
    __ cmp(rscratch1, count, Assembler::LSL, exact_log2(size));
67b6050f5ce8 8149080: AArch64: Recognise disjoint array copy in stub code
hshi
parents: 35841
diff changeset
  1411
    __ br(Assembler::HS, nooverlap_target);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1412
50728
9375184cec98 8205459: Rename Access API flag decorators
kbarrett
parents: 50242
diff changeset
  1413
    DecoratorSet decorators = IN_HEAP | IS_ARRAY;
49484
ee8fa73b90f9 8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents: 49455
diff changeset
  1414
    if (dest_uninitialized) {
50728
9375184cec98 8205459: Rename Access API flag decorators
kbarrett
parents: 50242
diff changeset
  1415
      decorators |= IS_DEST_UNINITIALIZED;
49484
ee8fa73b90f9 8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents: 49455
diff changeset
  1416
    }
ee8fa73b90f9 8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents: 49455
diff changeset
  1417
    if (aligned) {
ee8fa73b90f9 8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents: 49455
diff changeset
  1418
      decorators |= ARRAYCOPY_ALIGNED;
ee8fa73b90f9 8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents: 49455
diff changeset
  1419
    }
ee8fa73b90f9 8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents: 49455
diff changeset
  1420
49754
ee93c1087584 8201362: Remove CollectedHeap::barrier_set()
pliden
parents: 49724
diff changeset
  1421
    BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
54979
f982c1a6582c 8224187: Refactor arraycopy_prologue to allow ZGC read barriers on arraycopy
smonteith
parents: 54786
diff changeset
  1422
    bs->arraycopy_prologue(_masm, decorators, is_oop, s, d, count, saved_regs);
49484
ee8fa73b90f9 8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents: 49455
diff changeset
  1423
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1424
    if (is_oop) {
46695
aaaac1d98bc5 8183533: AArch64: redundent registers saving in arraycopy stubs
njian
parents: 46625
diff changeset
  1425
      // save regs before copy_memory
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1426
      __ push(RegSet::of(d, count), sp);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1427
    }
55490
3f3dc00a69a5 8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents: 55379
diff changeset
  1428
    {
3f3dc00a69a5 8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents: 55379
diff changeset
  1429
      // UnsafeCopyMemory page error: continue after ucm
3f3dc00a69a5 8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents: 55379
diff changeset
  1430
      bool add_entry = !is_oop && (!aligned || sizeof(jlong) == size);
3f3dc00a69a5 8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents: 55379
diff changeset
  1431
      UnsafeCopyMemoryMark ucmm(this, add_entry, true);
3f3dc00a69a5 8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents: 55379
diff changeset
  1432
      copy_memory(aligned, s, d, count, rscratch1, -size);
3f3dc00a69a5 8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents: 55379
diff changeset
  1433
    }
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1434
    if (is_oop) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1435
      __ pop(RegSet::of(d, count), sp);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1436
      if (VerifyOops)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1437
        verify_oop_array(size, d, count, r16);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1438
    }
49484
ee8fa73b90f9 8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents: 49455
diff changeset
  1439
    bs->arraycopy_epilogue(_masm, decorators, is_oop, d, count, rscratch1, RegSet());
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1440
    __ leave();
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1441
    __ mov(r0, zr); // return 0
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1442
    __ ret(lr);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1443
    return start;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1444
}
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1445
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1446
  // Arguments:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1447
  //   aligned - true => Input and output aligned on a HeapWord == 8-byte boundary
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1448
  //             ignored
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1449
  //   name    - stub name string
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1450
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1451
  // Inputs:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1452
  //   c_rarg0   - source array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1453
  //   c_rarg1   - destination array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1454
  //   c_rarg2   - element count, treated as ssize_t, can be zero
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1455
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1456
  // If 'from' and/or 'to' are aligned on 4-, 2-, or 1-byte boundaries,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1457
  // we let the hardware handle it.  The one to eight bytes within words,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1458
  // dwords or qwords that span cache line boundaries will still be loaded
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1459
  // and stored atomically.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1460
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1461
  // Side Effects:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1462
  //   disjoint_byte_copy_entry is set to the no-overlap entry point  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1463
  // If 'from' and/or 'to' are aligned on 4-, 2-, or 1-byte boundaries,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1464
  // we let the hardware handle it.  The one to eight bytes within words,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1465
  // dwords or qwords that span cache line boundaries will still be loaded
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1466
  // and stored atomically.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1467
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1468
  // Side Effects:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1469
  //   disjoint_byte_copy_entry is set to the no-overlap entry point
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1470
  //   used by generate_conjoint_byte_copy().
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1471
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1472
  address generate_disjoint_byte_copy(bool aligned, address* entry, const char *name) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1473
    const bool not_oop = false;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1474
    return generate_disjoint_copy(sizeof (jbyte), aligned, not_oop, entry, name);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1475
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1476
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1477
  // Arguments:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1478
  //   aligned - true => Input and output aligned on a HeapWord == 8-byte boundary
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1479
  //             ignored
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1480
  //   name    - stub name string
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1481
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1482
  // Inputs:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1483
  //   c_rarg0   - source array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1484
  //   c_rarg1   - destination array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1485
  //   c_rarg2   - element count, treated as ssize_t, can be zero
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1486
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1487
  // If 'from' and/or 'to' are aligned on 4-, 2-, or 1-byte boundaries,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1488
  // we let the hardware handle it.  The one to eight bytes within words,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1489
  // dwords or qwords that span cache line boundaries will still be loaded
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1490
  // and stored atomically.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1491
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1492
  address generate_conjoint_byte_copy(bool aligned, address nooverlap_target,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1493
                                      address* entry, const char *name) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1494
    const bool not_oop = false;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1495
    return generate_conjoint_copy(sizeof (jbyte), aligned, not_oop, nooverlap_target, entry, name);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1496
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1497
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1498
  // Arguments:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1499
  //   aligned - true => Input and output aligned on a HeapWord == 8-byte boundary
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1500
  //             ignored
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1501
  //   name    - stub name string
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1502
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1503
  // Inputs:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1504
  //   c_rarg0   - source array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1505
  //   c_rarg1   - destination array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1506
  //   c_rarg2   - element count, treated as ssize_t, can be zero
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1507
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1508
  // If 'from' and/or 'to' are aligned on 4- or 2-byte boundaries, we
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1509
  // let the hardware handle it.  The two or four words within dwords
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1510
  // or qwords that span cache line boundaries will still be loaded
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1511
  // and stored atomically.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1512
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1513
  // Side Effects:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1514
  //   disjoint_short_copy_entry is set to the no-overlap entry point
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1515
  //   used by generate_conjoint_short_copy().
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1516
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1517
  address generate_disjoint_short_copy(bool aligned,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1518
                                       address* entry, const char *name) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1519
    const bool not_oop = false;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1520
    return generate_disjoint_copy(sizeof (jshort), aligned, not_oop, entry, name);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1521
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1522
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1523
  // Arguments:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1524
  //   aligned - true => Input and output aligned on a HeapWord == 8-byte boundary
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1525
  //             ignored
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1526
  //   name    - stub name string
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1527
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1528
  // Inputs:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1529
  //   c_rarg0   - source array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1530
  //   c_rarg1   - destination array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1531
  //   c_rarg2   - element count, treated as ssize_t, can be zero
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1532
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1533
  // If 'from' and/or 'to' are aligned on 4- or 2-byte boundaries, we
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1534
  // let the hardware handle it.  The two or four words within dwords
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1535
  // or qwords that span cache line boundaries will still be loaded
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1536
  // and stored atomically.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1537
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1538
  address generate_conjoint_short_copy(bool aligned, address nooverlap_target,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1539
                                       address *entry, const char *name) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1540
    const bool not_oop = false;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1541
    return generate_conjoint_copy(sizeof (jshort), aligned, not_oop, nooverlap_target, entry, name);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1542
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1543
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1544
  // Arguments:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1545
  //   aligned - true => Input and output aligned on a HeapWord == 8-byte boundary
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1546
  //             ignored
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1547
  //   name    - stub name string
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1548
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1549
  // Inputs:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1550
  //   c_rarg0   - source array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1551
  //   c_rarg1   - destination array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1552
  //   c_rarg2   - element count, treated as ssize_t, can be zero
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1553
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1554
  // If 'from' and/or 'to' are aligned on 4-byte boundaries, we let
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1555
  // the hardware handle it.  The two dwords within qwords that span
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1556
  // cache line boundaries will still be loaded and stored atomicly.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1557
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1558
  // Side Effects:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1559
  //   disjoint_int_copy_entry is set to the no-overlap entry point
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1560
  //   used by generate_conjoint_int_oop_copy().
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1561
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1562
  address generate_disjoint_int_copy(bool aligned, address *entry,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1563
                                         const char *name, bool dest_uninitialized = false) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1564
    const bool not_oop = false;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1565
    return generate_disjoint_copy(sizeof (jint), aligned, not_oop, entry, name);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1566
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1567
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1568
  // Arguments:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1569
  //   aligned - true => Input and output aligned on a HeapWord == 8-byte boundary
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1570
  //             ignored
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1571
  //   name    - stub name string
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1572
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1573
  // Inputs:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1574
  //   c_rarg0   - source array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1575
  //   c_rarg1   - destination array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1576
  //   c_rarg2   - element count, treated as ssize_t, can be zero
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1577
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1578
  // If 'from' and/or 'to' are aligned on 4-byte boundaries, we let
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1579
  // the hardware handle it.  The two dwords within qwords that span
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1580
  // cache line boundaries will still be loaded and stored atomicly.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1581
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1582
  address generate_conjoint_int_copy(bool aligned, address nooverlap_target,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1583
                                     address *entry, const char *name,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1584
                                     bool dest_uninitialized = false) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1585
    const bool not_oop = false;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1586
    return generate_conjoint_copy(sizeof (jint), aligned, not_oop, nooverlap_target, entry, name);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1587
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1588
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1589
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1590
  // Arguments:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1591
  //   aligned - true => Input and output aligned on a HeapWord boundary == 8 bytes
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1592
  //             ignored
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1593
  //   name    - stub name string
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1594
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1595
  // Inputs:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1596
  //   c_rarg0   - source array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1597
  //   c_rarg1   - destination array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1598
  //   c_rarg2   - element count, treated as size_t, can be zero
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1599
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1600
  // Side Effects:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1601
  //   disjoint_oop_copy_entry or disjoint_long_copy_entry is set to the
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1602
  //   no-overlap entry point used by generate_conjoint_long_oop_copy().
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1603
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1604
  address generate_disjoint_long_copy(bool aligned, address *entry,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1605
                                          const char *name, bool dest_uninitialized = false) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1606
    const bool not_oop = false;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1607
    return generate_disjoint_copy(sizeof (jlong), aligned, not_oop, entry, name);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1608
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1609
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1610
  // Arguments:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1611
  //   aligned - true => Input and output aligned on a HeapWord boundary == 8 bytes
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1612
  //             ignored
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1613
  //   name    - stub name string
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1614
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1615
  // Inputs:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1616
  //   c_rarg0   - source array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1617
  //   c_rarg1   - destination array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1618
  //   c_rarg2   - element count, treated as size_t, can be zero
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1619
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1620
  address generate_conjoint_long_copy(bool aligned,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1621
                                      address nooverlap_target, address *entry,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1622
                                      const char *name, bool dest_uninitialized = false) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1623
    const bool not_oop = false;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1624
    return generate_conjoint_copy(sizeof (jlong), aligned, not_oop, nooverlap_target, entry, name);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1625
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1626
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1627
  // Arguments:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1628
  //   aligned - true => Input and output aligned on a HeapWord boundary == 8 bytes
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1629
  //             ignored
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1630
  //   name    - stub name string
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1631
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1632
  // Inputs:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1633
  //   c_rarg0   - source array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1634
  //   c_rarg1   - destination array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1635
  //   c_rarg2   - element count, treated as size_t, can be zero
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1636
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1637
  // Side Effects:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1638
  //   disjoint_oop_copy_entry or disjoint_long_copy_entry is set to the
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1639
  //   no-overlap entry point used by generate_conjoint_long_oop_copy().
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1640
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1641
  address generate_disjoint_oop_copy(bool aligned, address *entry,
36326
d25af58cfc94 8150045: arraycopy causes segfaults in SATB during garbage collection
aph
parents: 35843
diff changeset
  1642
                                     const char *name, bool dest_uninitialized) {
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1643
    const bool is_oop = true;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1644
    const size_t size = UseCompressedOops ? sizeof (jint) : sizeof (jlong);
36326
d25af58cfc94 8150045: arraycopy causes segfaults in SATB during garbage collection
aph
parents: 35843
diff changeset
  1645
    return generate_disjoint_copy(size, aligned, is_oop, entry, name, dest_uninitialized);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1646
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1647
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1648
  // Arguments:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1649
  //   aligned - true => Input and output aligned on a HeapWord boundary == 8 bytes
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1650
  //             ignored
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1651
  //   name    - stub name string
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1652
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1653
  // Inputs:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1654
  //   c_rarg0   - source array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1655
  //   c_rarg1   - destination array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1656
  //   c_rarg2   - element count, treated as size_t, can be zero
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1657
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1658
  address generate_conjoint_oop_copy(bool aligned,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1659
                                     address nooverlap_target, address *entry,
36326
d25af58cfc94 8150045: arraycopy causes segfaults in SATB during garbage collection
aph
parents: 35843
diff changeset
  1660
                                     const char *name, bool dest_uninitialized) {
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1661
    const bool is_oop = true;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1662
    const size_t size = UseCompressedOops ? sizeof (jint) : sizeof (jlong);
36326
d25af58cfc94 8150045: arraycopy causes segfaults in SATB during garbage collection
aph
parents: 35843
diff changeset
  1663
    return generate_conjoint_copy(size, aligned, is_oop, nooverlap_target, entry,
d25af58cfc94 8150045: arraycopy causes segfaults in SATB during garbage collection
aph
parents: 35843
diff changeset
  1664
                                  name, dest_uninitialized);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1665
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1666
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1667
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1668
  // Helper for generating a dynamic type check.
53777
9bfeac2ee88a 8219006: AArch64: Register corruption in slow subtype check
aph
parents: 52977
diff changeset
  1669
  // Smashes rscratch1, rscratch2.
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1670
  void generate_type_check(Register sub_klass,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1671
                           Register super_check_offset,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1672
                           Register super_klass,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1673
                           Label& L_success) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1674
    assert_different_registers(sub_klass, super_check_offset, super_klass);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1675
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1676
    BLOCK_COMMENT("type_check:");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1677
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1678
    Label L_miss;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1679
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1680
    __ check_klass_subtype_fast_path(sub_klass, super_klass, noreg,        &L_success, &L_miss, NULL,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1681
                                     super_check_offset);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1682
    __ check_klass_subtype_slow_path(sub_klass, super_klass, noreg, noreg, &L_success, NULL);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1683
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1684
    // Fall through on failure!
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1685
    __ BIND(L_miss);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1686
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1687
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1688
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1689
  //  Generate checkcasting array copy stub
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1690
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1691
  //  Input:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1692
  //    c_rarg0   - source array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1693
  //    c_rarg1   - destination array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1694
  //    c_rarg2   - element count, treated as ssize_t, can be zero
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1695
  //    c_rarg3   - size_t ckoff (super_check_offset)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1696
  //    c_rarg4   - oop ckval (super_klass)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1697
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1698
  //  Output:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1699
  //    r0 ==  0  -  success
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1700
  //    r0 == -1^K - failure, where K is partial transfer count
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1701
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1702
  address generate_checkcast_copy(const char *name, address *entry,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1703
                                  bool dest_uninitialized = false) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1704
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1705
    Label L_load_element, L_store_element, L_do_card_marks, L_done, L_done_pop;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1706
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1707
    // Input registers (after setup_arg_regs)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1708
    const Register from        = c_rarg0;   // source array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1709
    const Register to          = c_rarg1;   // destination array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1710
    const Register count       = c_rarg2;   // elementscount
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1711
    const Register ckoff       = c_rarg3;   // super_check_offset
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1712
    const Register ckval       = c_rarg4;   // super_klass
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1713
46695
aaaac1d98bc5 8183533: AArch64: redundent registers saving in arraycopy stubs
njian
parents: 46625
diff changeset
  1714
    RegSet wb_pre_saved_regs = RegSet::range(c_rarg0, c_rarg4);
aaaac1d98bc5 8183533: AArch64: redundent registers saving in arraycopy stubs
njian
parents: 46625
diff changeset
  1715
    RegSet wb_post_saved_regs = RegSet::of(count);
aaaac1d98bc5 8183533: AArch64: redundent registers saving in arraycopy stubs
njian
parents: 46625
diff changeset
  1716
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1717
    // Registers used as temps (r18, r19, r20 are save-on-entry)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1718
    const Register count_save  = r21;       // orig elementscount
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1719
    const Register start_to    = r20;       // destination array start address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1720
    const Register copied_oop  = r18;       // actual oop copied
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1721
    const Register r19_klass   = r19;       // oop._klass
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1722
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1723
    //---------------------------------------------------------------
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1724
    // Assembler stub will be used for this call to arraycopy
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1725
    // if the two arrays are subtypes of Object[] but the
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1726
    // destination array type is not equal to or a supertype
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1727
    // of the source type.  Each element must be separately
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1728
    // checked.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1729
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1730
    assert_different_registers(from, to, count, ckoff, ckval, start_to,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1731
                               copied_oop, r19_klass, count_save);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1732
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1733
    __ align(CodeEntryAlignment);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1734
    StubCodeMark mark(this, "StubRoutines", name);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1735
    address start = __ pc();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1736
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1737
    __ enter(); // required for proper stackwalking of RuntimeStub frame
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1738
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1739
#ifdef ASSERT
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1740
    // caller guarantees that the arrays really are different
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1741
    // otherwise, we would have to make conjoint checks
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1742
    { Label L;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1743
      array_overlap_test(L, TIMES_OOP);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1744
      __ stop("checkcast_copy within a single array");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1745
      __ bind(L);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1746
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1747
#endif //ASSERT
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1748
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1749
    // Caller of this entry point must set up the argument registers.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1750
    if (entry != NULL) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1751
      *entry = __ pc();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1752
      BLOCK_COMMENT("Entry:");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1753
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1754
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1755
     // Empty array:  Nothing to do.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1756
    __ cbz(count, L_done);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1757
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1758
    __ push(RegSet::of(r18, r19, r20, r21), sp);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1759
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1760
#ifdef ASSERT
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1761
    BLOCK_COMMENT("assert consistent ckoff/ckval");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1762
    // The ckoff and ckval must be mutually consistent,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1763
    // even though caller generates both.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1764
    { Label L;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1765
      int sco_offset = in_bytes(Klass::super_check_offset_offset());
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1766
      __ ldrw(start_to, Address(ckval, sco_offset));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1767
      __ cmpw(ckoff, start_to);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1768
      __ br(Assembler::EQ, L);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1769
      __ stop("super_check_offset inconsistent");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1770
      __ bind(L);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1771
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1772
#endif //ASSERT
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1773
54755
de34f4b370b0 8223244: Fix usage of ARRAYCOPY_DISJOINT decorator
rkennke
parents: 54266
diff changeset
  1774
    DecoratorSet decorators = IN_HEAP | IS_ARRAY | ARRAYCOPY_CHECKCAST | ARRAYCOPY_DISJOINT;
49484
ee8fa73b90f9 8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents: 49455
diff changeset
  1775
    bool is_oop = true;
ee8fa73b90f9 8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents: 49455
diff changeset
  1776
    if (dest_uninitialized) {
50728
9375184cec98 8205459: Rename Access API flag decorators
kbarrett
parents: 50242
diff changeset
  1777
      decorators |= IS_DEST_UNINITIALIZED;
49484
ee8fa73b90f9 8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents: 49455
diff changeset
  1778
    }
ee8fa73b90f9 8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents: 49455
diff changeset
  1779
49754
ee93c1087584 8201362: Remove CollectedHeap::barrier_set()
pliden
parents: 49724
diff changeset
  1780
    BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
54979
f982c1a6582c 8224187: Refactor arraycopy_prologue to allow ZGC read barriers on arraycopy
smonteith
parents: 54786
diff changeset
  1781
    bs->arraycopy_prologue(_masm, decorators, is_oop, from, to, count, wb_pre_saved_regs);
36326
d25af58cfc94 8150045: arraycopy causes segfaults in SATB during garbage collection
aph
parents: 35843
diff changeset
  1782
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1783
    // save the original count
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1784
    __ mov(count_save, count);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1785
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1786
    // Copy from low to high addresses
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1787
    __ mov(start_to, to);              // Save destination array start address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1788
    __ b(L_load_element);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1789
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1790
    // ======== begin loop ========
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1791
    // (Loop is rotated; its entry is L_load_element.)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1792
    // Loop control:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1793
    //   for (; count != 0; count--) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1794
    //     copied_oop = load_heap_oop(from++);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1795
    //     ... generate_type_check ...;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1796
    //     store_heap_oop(to++, copied_oop);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1797
    //   }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1798
    __ align(OptoLoopAlignment);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1799
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1800
    __ BIND(L_store_element);
50110
3d98842c8677 8202714: Create a MacroAssembler::access_load/store_at wrapper for AArch64
rkennke
parents: 49754
diff changeset
  1801
    __ store_heap_oop(__ post(to, UseCompressedOops ? 4 : 8), copied_oop, noreg, noreg, AS_RAW);  // store the oop
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1802
    __ sub(count, count, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1803
    __ cbz(count, L_do_card_marks);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1804
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1805
    // ======== loop entry is here ========
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1806
    __ BIND(L_load_element);
50110
3d98842c8677 8202714: Create a MacroAssembler::access_load/store_at wrapper for AArch64
rkennke
parents: 49754
diff changeset
  1807
    __ load_heap_oop(copied_oop, __ post(from, UseCompressedOops ? 4 : 8), noreg, noreg, AS_RAW); // load the oop
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1808
    __ cbz(copied_oop, L_store_element);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1809
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1810
    __ load_klass(r19_klass, copied_oop);// query the object klass
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1811
    generate_type_check(r19_klass, ckoff, ckval, L_store_element);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1812
    // ======== end loop ========
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1813
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1814
    // It was a real error; we must depend on the caller to finish the job.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1815
    // Register count = remaining oops, count_orig = total oops.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1816
    // Emit GC store barriers for the oops we have copied and report
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1817
    // their number to the caller.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1818
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1819
    __ subs(count, count_save, count);     // K = partially copied oop count
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1820
    __ eon(count, count, zr);                   // report (-1^K) to caller
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1821
    __ br(Assembler::EQ, L_done_pop);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1822
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1823
    __ BIND(L_do_card_marks);
54266
7816d989bf21 8216989: CardTableBarrierSetAssembler::gen_write_ref_array_post_barrier() does not check for zero length on AARCH64
dpochepk
parents: 53967
diff changeset
  1824
    bs->arraycopy_epilogue(_masm, decorators, is_oop, start_to, count_save, rscratch1, wb_post_saved_regs);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1825
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1826
    __ bind(L_done_pop);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1827
    __ pop(RegSet::of(r18, r19, r20, r21), sp);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1828
    inc_counter_np(SharedRuntime::_checkcast_array_copy_ctr);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1829
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1830
    __ bind(L_done);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1831
    __ mov(r0, count);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1832
    __ leave();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1833
    __ ret(lr);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1834
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1835
    return start;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1836
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1837
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1838
  // Perform range checks on the proposed arraycopy.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1839
  // Kills temp, but nothing else.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1840
  // Also, clean the sign bits of src_pos and dst_pos.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1841
  void arraycopy_range_checks(Register src,     // source array oop (c_rarg0)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1842
                              Register src_pos, // source position (c_rarg1)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1843
                              Register dst,     // destination array oo (c_rarg2)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1844
                              Register dst_pos, // destination position (c_rarg3)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1845
                              Register length,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1846
                              Register temp,
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1847
                              Label& L_failed) {
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1848
    BLOCK_COMMENT("arraycopy_range_checks:");
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1849
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1850
    assert_different_registers(rscratch1, temp);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1851
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1852
    //  if (src_pos + length > arrayOop(src)->length())  FAIL;
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1853
    __ ldrw(rscratch1, Address(src, arrayOopDesc::length_offset_in_bytes()));
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1854
    __ addw(temp, length, src_pos);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1855
    __ cmpw(temp, rscratch1);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1856
    __ br(Assembler::HI, L_failed);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1857
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1858
    //  if (dst_pos + length > arrayOop(dst)->length())  FAIL;
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1859
    __ ldrw(rscratch1, Address(dst, arrayOopDesc::length_offset_in_bytes()));
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1860
    __ addw(temp, length, dst_pos);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1861
    __ cmpw(temp, rscratch1);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1862
    __ br(Assembler::HI, L_failed);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1863
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1864
    // Have to clean up high 32 bits of 'src_pos' and 'dst_pos'.
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1865
    __ movw(src_pos, src_pos);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1866
    __ movw(dst_pos, dst_pos);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1867
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1868
    BLOCK_COMMENT("arraycopy_range_checks done");
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1869
  }
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1870
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1871
  // These stubs get called from some dumb test routine.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1872
  // I'll write them properly when they're called from
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1873
  // something that's actually doing something.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1874
  static void fake_arraycopy_stub(address src, address dst, int count) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1875
    assert(count == 0, "huh?");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1876
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1877
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1878
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1879
  //
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1880
  //  Generate 'unsafe' array copy stub
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1881
  //  Though just as safe as the other stubs, it takes an unscaled
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1882
  //  size_t argument instead of an element count.
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1883
  //
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1884
  //  Input:
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1885
  //    c_rarg0   - source array address
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1886
  //    c_rarg1   - destination array address
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1887
  //    c_rarg2   - byte count, treated as ssize_t, can be zero
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1888
  //
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1889
  // Examines the alignment of the operands and dispatches
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1890
  // to a long, int, short, or byte copy loop.
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1891
  //
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1892
  address generate_unsafe_copy(const char *name,
37271
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1893
                               address byte_copy_entry,
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1894
                               address short_copy_entry,
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1895
                               address int_copy_entry,
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1896
                               address long_copy_entry) {
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1897
    Label L_long_aligned, L_int_aligned, L_short_aligned;
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1898
    Register s = c_rarg0, d = c_rarg1, count = c_rarg2;
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1899
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1900
    __ align(CodeEntryAlignment);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1901
    StubCodeMark mark(this, "StubRoutines", name);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1902
    address start = __ pc();
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1903
    __ enter(); // required for proper stackwalking of RuntimeStub frame
37271
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1904
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1905
    // bump this on entry, not on exit:
37271
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1906
    inc_counter_np(SharedRuntime::_unsafe_array_copy_ctr);
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1907
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1908
    __ orr(rscratch1, s, d);
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1909
    __ orr(rscratch1, rscratch1, count);
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1910
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1911
    __ andr(rscratch1, rscratch1, BytesPerLong-1);
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1912
    __ cbz(rscratch1, L_long_aligned);
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1913
    __ andr(rscratch1, rscratch1, BytesPerInt-1);
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1914
    __ cbz(rscratch1, L_int_aligned);
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1915
    __ tbz(rscratch1, 0, L_short_aligned);
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1916
    __ b(RuntimeAddress(byte_copy_entry));
37271
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1917
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1918
    __ BIND(L_short_aligned);
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1919
    __ lsr(count, count, LogBytesPerShort);  // size => short_count
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1920
    __ b(RuntimeAddress(short_copy_entry));
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1921
    __ BIND(L_int_aligned);
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1922
    __ lsr(count, count, LogBytesPerInt);    // size => int_count
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1923
    __ b(RuntimeAddress(int_copy_entry));
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1924
    __ BIND(L_long_aligned);
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1925
    __ lsr(count, count, LogBytesPerLong);   // size => long_count
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1926
    __ b(RuntimeAddress(long_copy_entry));
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  1927
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1928
    return start;
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1929
  }
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1930
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1931
  //
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1932
  //  Generate generic array copy stubs
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1933
  //
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1934
  //  Input:
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1935
  //    c_rarg0    -  src oop
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1936
  //    c_rarg1    -  src_pos (32-bits)
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1937
  //    c_rarg2    -  dst oop
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1938
  //    c_rarg3    -  dst_pos (32-bits)
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1939
  //    c_rarg4    -  element count (32-bits)
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1940
  //
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1941
  //  Output:
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1942
  //    r0 ==  0  -  success
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1943
  //    r0 == -1^K - failure, where K is partial transfer count
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1944
  //
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1945
  address generate_generic_copy(const char *name,
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1946
                                address byte_copy_entry, address short_copy_entry,
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1947
                                address int_copy_entry, address oop_copy_entry,
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1948
                                address long_copy_entry, address checkcast_copy_entry) {
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1949
51756
4bd35a5ec694 8210676: Remove some unused Label variables
mikael
parents: 51619
diff changeset
  1950
    Label L_failed, L_objArray;
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1951
    Label L_copy_bytes, L_copy_shorts, L_copy_ints, L_copy_longs;
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1952
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1953
    // Input registers
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1954
    const Register src        = c_rarg0;  // source array oop
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1955
    const Register src_pos    = c_rarg1;  // source position
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1956
    const Register dst        = c_rarg2;  // destination array oop
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1957
    const Register dst_pos    = c_rarg3;  // destination position
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1958
    const Register length     = c_rarg4;
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1959
53777
9bfeac2ee88a 8219006: AArch64: Register corruption in slow subtype check
aph
parents: 52977
diff changeset
  1960
9bfeac2ee88a 8219006: AArch64: Register corruption in slow subtype check
aph
parents: 52977
diff changeset
  1961
    // Registers used as temps
9bfeac2ee88a 8219006: AArch64: Register corruption in slow subtype check
aph
parents: 52977
diff changeset
  1962
    const Register dst_klass  = c_rarg5;
9bfeac2ee88a 8219006: AArch64: Register corruption in slow subtype check
aph
parents: 52977
diff changeset
  1963
52977
2e4903f83295 8205421: AARCH64: StubCodeMark should be placed after alignment
dpochepk
parents: 52927
diff changeset
  1964
    __ align(CodeEntryAlignment);
2e4903f83295 8205421: AARCH64: StubCodeMark should be placed after alignment
dpochepk
parents: 52927
diff changeset
  1965
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1966
    StubCodeMark mark(this, "StubRoutines", name);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1967
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1968
    address start = __ pc();
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1969
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1970
    __ enter(); // required for proper stackwalking of RuntimeStub frame
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1971
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1972
    // bump this on entry, not on exit:
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1973
    inc_counter_np(SharedRuntime::_generic_array_copy_ctr);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1974
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1975
    //-----------------------------------------------------------------------
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1976
    // Assembler stub will be used for this call to arraycopy
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1977
    // if the following conditions are met:
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1978
    //
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1979
    // (1) src and dst must not be null.
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1980
    // (2) src_pos must not be negative.
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1981
    // (3) dst_pos must not be negative.
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1982
    // (4) length  must not be negative.
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1983
    // (5) src klass and dst klass should be the same and not NULL.
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1984
    // (6) src and dst should be arrays.
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1985
    // (7) src_pos + length must not exceed length of src.
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1986
    // (8) dst_pos + length must not exceed length of dst.
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1987
    //
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1988
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1989
    //  if (src == NULL) return -1;
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1990
    __ cbz(src, L_failed);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1991
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1992
    //  if (src_pos < 0) return -1;
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1993
    __ tbnz(src_pos, 31, L_failed);  // i.e. sign bit set
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1994
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1995
    //  if (dst == NULL) return -1;
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1996
    __ cbz(dst, L_failed);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1997
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1998
    //  if (dst_pos < 0) return -1;
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  1999
    __ tbnz(dst_pos, 31, L_failed);  // i.e. sign bit set
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2000
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2001
    // registers used as temp
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2002
    const Register scratch_length    = r16; // elements count to copy
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2003
    const Register scratch_src_klass = r17; // array klass
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2004
    const Register lh                = r18; // layout helper
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2005
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2006
    //  if (length < 0) return -1;
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2007
    __ movw(scratch_length, length);        // length (elements count, 32-bits value)
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2008
    __ tbnz(scratch_length, 31, L_failed);  // i.e. sign bit set
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2009
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2010
    __ load_klass(scratch_src_klass, src);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2011
#ifdef ASSERT
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2012
    //  assert(src->klass() != NULL);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2013
    {
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2014
      BLOCK_COMMENT("assert klasses not null {");
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2015
      Label L1, L2;
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2016
      __ cbnz(scratch_src_klass, L2);   // it is broken if klass is NULL
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2017
      __ bind(L1);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2018
      __ stop("broken null klass");
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2019
      __ bind(L2);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2020
      __ load_klass(rscratch1, dst);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2021
      __ cbz(rscratch1, L1);     // this would be broken also
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2022
      BLOCK_COMMENT("} assert klasses not null done");
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2023
    }
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2024
#endif
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2025
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2026
    // Load layout helper (32-bits)
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2027
    //
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2028
    //  |array_tag|     | header_size | element_type |     |log2_element_size|
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2029
    // 32        30    24            16              8     2                 0
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2030
    //
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2031
    //   array_tag: typeArray = 0x3, objArray = 0x2, non-array = 0x0
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2032
    //
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2033
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2034
    const int lh_offset = in_bytes(Klass::layout_helper_offset());
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2035
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2036
    // Handle objArrays completely differently...
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2037
    const jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2038
    __ ldrw(lh, Address(scratch_src_klass, lh_offset));
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2039
    __ movw(rscratch1, objArray_lh);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2040
    __ eorw(rscratch2, lh, rscratch1);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2041
    __ cbzw(rscratch2, L_objArray);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2042
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2043
    //  if (src->klass() != dst->klass()) return -1;
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2044
    __ load_klass(rscratch2, dst);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2045
    __ eor(rscratch2, rscratch2, scratch_src_klass);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2046
    __ cbnz(rscratch2, L_failed);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2047
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2048
    //  if (!src->is_Array()) return -1;
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2049
    __ tbz(lh, 31, L_failed);  // i.e. (lh >= 0)
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2050
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2051
    // At this point, it is known to be a typeArray (array_tag 0x3).
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2052
#ifdef ASSERT
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2053
    {
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2054
      BLOCK_COMMENT("assert primitive array {");
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2055
      Label L;
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2056
      __ movw(rscratch2, Klass::_lh_array_tag_type_value << Klass::_lh_array_tag_shift);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2057
      __ cmpw(lh, rscratch2);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2058
      __ br(Assembler::GE, L);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2059
      __ stop("must be a primitive array");
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2060
      __ bind(L);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2061
      BLOCK_COMMENT("} assert primitive array done");
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2062
    }
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2063
#endif
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2064
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2065
    arraycopy_range_checks(src, src_pos, dst, dst_pos, scratch_length,
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2066
                           rscratch2, L_failed);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2067
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2068
    // TypeArrayKlass
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2069
    //
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2070
    // src_addr = (src + array_header_in_bytes()) + (src_pos << log2elemsize);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2071
    // dst_addr = (dst + array_header_in_bytes()) + (dst_pos << log2elemsize);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2072
    //
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2073
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2074
    const Register rscratch1_offset = rscratch1;    // array offset
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2075
    const Register r18_elsize = lh; // element size
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2076
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2077
    __ ubfx(rscratch1_offset, lh, Klass::_lh_header_size_shift,
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2078
           exact_log2(Klass::_lh_header_size_mask+1));   // array_offset
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2079
    __ add(src, src, rscratch1_offset);           // src array offset
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2080
    __ add(dst, dst, rscratch1_offset);           // dst array offset
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2081
    BLOCK_COMMENT("choose copy loop based on element size");
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2082
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2083
    // next registers should be set before the jump to corresponding stub
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2084
    const Register from     = c_rarg0;  // source array address
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2085
    const Register to       = c_rarg1;  // destination array address
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2086
    const Register count    = c_rarg2;  // elements count
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2087
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2088
    // 'from', 'to', 'count' registers should be set in such order
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2089
    // since they are the same as 'src', 'src_pos', 'dst'.
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2090
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2091
    assert(Klass::_lh_log2_element_size_shift == 0, "fix this code");
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2092
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2093
    // The possible values of elsize are 0-3, i.e. exact_log2(element
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2094
    // size in bytes).  We do a simple bitwise binary search.
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2095
  __ BIND(L_copy_bytes);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2096
    __ tbnz(r18_elsize, 1, L_copy_ints);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2097
    __ tbnz(r18_elsize, 0, L_copy_shorts);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2098
    __ lea(from, Address(src, src_pos));// src_addr
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2099
    __ lea(to,   Address(dst, dst_pos));// dst_addr
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2100
    __ movw(count, scratch_length); // length
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2101
    __ b(RuntimeAddress(byte_copy_entry));
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2102
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2103
  __ BIND(L_copy_shorts);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2104
    __ lea(from, Address(src, src_pos, Address::lsl(1)));// src_addr
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2105
    __ lea(to,   Address(dst, dst_pos, Address::lsl(1)));// dst_addr
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2106
    __ movw(count, scratch_length); // length
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2107
    __ b(RuntimeAddress(short_copy_entry));
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2108
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2109
  __ BIND(L_copy_ints);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2110
    __ tbnz(r18_elsize, 0, L_copy_longs);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2111
    __ lea(from, Address(src, src_pos, Address::lsl(2)));// src_addr
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2112
    __ lea(to,   Address(dst, dst_pos, Address::lsl(2)));// dst_addr
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2113
    __ movw(count, scratch_length); // length
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2114
    __ b(RuntimeAddress(int_copy_entry));
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2115
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2116
  __ BIND(L_copy_longs);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2117
#ifdef ASSERT
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2118
    {
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2119
      BLOCK_COMMENT("assert long copy {");
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2120
      Label L;
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2121
      __ andw(lh, lh, Klass::_lh_log2_element_size_mask); // lh -> r18_elsize
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2122
      __ cmpw(r18_elsize, LogBytesPerLong);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2123
      __ br(Assembler::EQ, L);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2124
      __ stop("must be long copy, but elsize is wrong");
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2125
      __ bind(L);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2126
      BLOCK_COMMENT("} assert long copy done");
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2127
    }
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2128
#endif
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2129
    __ lea(from, Address(src, src_pos, Address::lsl(3)));// src_addr
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2130
    __ lea(to,   Address(dst, dst_pos, Address::lsl(3)));// dst_addr
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2131
    __ movw(count, scratch_length); // length
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2132
    __ b(RuntimeAddress(long_copy_entry));
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2133
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2134
    // ObjArrayKlass
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2135
  __ BIND(L_objArray);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2136
    // live at this point:  scratch_src_klass, scratch_length, src[_pos], dst[_pos]
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2137
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2138
    Label L_plain_copy, L_checkcast_copy;
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2139
    //  test array classes for subtyping
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2140
    __ load_klass(r18, dst);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2141
    __ cmp(scratch_src_klass, r18); // usual case is exact equality
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2142
    __ br(Assembler::NE, L_checkcast_copy);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2143
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2144
    // Identically typed arrays can be copied without element-wise checks.
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2145
    arraycopy_range_checks(src, src_pos, dst, dst_pos, scratch_length,
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2146
                           rscratch2, L_failed);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2147
39232
118d17fef4f9 8156731: aarch64: java/util/Arrays/Correct.java fails due to _generic_arraycopy stub routine
fyang
parents: 38233
diff changeset
  2148
    __ lea(from, Address(src, src_pos, Address::lsl(LogBytesPerHeapOop)));
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2149
    __ add(from, from, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
39232
118d17fef4f9 8156731: aarch64: java/util/Arrays/Correct.java fails due to _generic_arraycopy stub routine
fyang
parents: 38233
diff changeset
  2150
    __ lea(to, Address(dst, dst_pos, Address::lsl(LogBytesPerHeapOop)));
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2151
    __ add(to, to, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2152
    __ movw(count, scratch_length); // length
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2153
  __ BIND(L_plain_copy);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2154
    __ b(RuntimeAddress(oop_copy_entry));
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2155
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2156
  __ BIND(L_checkcast_copy);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2157
    // live at this point:  scratch_src_klass, scratch_length, r18 (dst_klass)
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2158
    {
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2159
      // Before looking at dst.length, make sure dst is also an objArray.
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2160
      __ ldrw(rscratch1, Address(r18, lh_offset));
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2161
      __ movw(rscratch2, objArray_lh);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2162
      __ eorw(rscratch1, rscratch1, rscratch2);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2163
      __ cbnzw(rscratch1, L_failed);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2164
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2165
      // It is safe to examine both src.length and dst.length.
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2166
      arraycopy_range_checks(src, src_pos, dst, dst_pos, scratch_length,
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2167
                             r18, L_failed);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2168
53777
9bfeac2ee88a 8219006: AArch64: Register corruption in slow subtype check
aph
parents: 52977
diff changeset
  2169
      __ load_klass(dst_klass, dst); // reload
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2170
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2171
      // Marshal the base address arguments now, freeing registers.
39232
118d17fef4f9 8156731: aarch64: java/util/Arrays/Correct.java fails due to _generic_arraycopy stub routine
fyang
parents: 38233
diff changeset
  2172
      __ lea(from, Address(src, src_pos, Address::lsl(LogBytesPerHeapOop)));
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2173
      __ add(from, from, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
39232
118d17fef4f9 8156731: aarch64: java/util/Arrays/Correct.java fails due to _generic_arraycopy stub routine
fyang
parents: 38233
diff changeset
  2174
      __ lea(to, Address(dst, dst_pos, Address::lsl(LogBytesPerHeapOop)));
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2175
      __ add(to, to, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2176
      __ movw(count, length);           // length (reloaded)
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2177
      Register sco_temp = c_rarg3;      // this register is free now
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2178
      assert_different_registers(from, to, count, sco_temp,
53777
9bfeac2ee88a 8219006: AArch64: Register corruption in slow subtype check
aph
parents: 52977
diff changeset
  2179
                                 dst_klass, scratch_src_klass);
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2180
      // assert_clean_int(count, sco_temp);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2181
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2182
      // Generate the type check.
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2183
      const int sco_offset = in_bytes(Klass::super_check_offset_offset());
53777
9bfeac2ee88a 8219006: AArch64: Register corruption in slow subtype check
aph
parents: 52977
diff changeset
  2184
      __ ldrw(sco_temp, Address(dst_klass, sco_offset));
9bfeac2ee88a 8219006: AArch64: Register corruption in slow subtype check
aph
parents: 52977
diff changeset
  2185
9bfeac2ee88a 8219006: AArch64: Register corruption in slow subtype check
aph
parents: 52977
diff changeset
  2186
      // Smashes rscratch1, rscratch2
9bfeac2ee88a 8219006: AArch64: Register corruption in slow subtype check
aph
parents: 52977
diff changeset
  2187
      generate_type_check(scratch_src_klass, sco_temp, dst_klass, L_plain_copy);
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2188
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2189
      // Fetch destination element klass from the ObjArrayKlass header.
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2190
      int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
53777
9bfeac2ee88a 8219006: AArch64: Register corruption in slow subtype check
aph
parents: 52977
diff changeset
  2191
      __ ldr(dst_klass, Address(dst_klass, ek_offset));
9bfeac2ee88a 8219006: AArch64: Register corruption in slow subtype check
aph
parents: 52977
diff changeset
  2192
      __ ldrw(sco_temp, Address(dst_klass, sco_offset));
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2193
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2194
      // the checkcast_copy loop needs two extra arguments:
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2195
      assert(c_rarg3 == sco_temp, "#3 already in place");
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2196
      // Set up arguments for checkcast_copy_entry.
53777
9bfeac2ee88a 8219006: AArch64: Register corruption in slow subtype check
aph
parents: 52977
diff changeset
  2197
      __ mov(c_rarg4, dst_klass);  // dst.klass.element_klass
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2198
      __ b(RuntimeAddress(checkcast_copy_entry));
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2199
    }
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2200
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2201
  __ BIND(L_failed);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2202
    __ mov(r0, -1);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2203
    __ leave();   // required for proper stackwalking of RuntimeStub frame
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2204
    __ ret(lr);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2205
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2206
    return start;
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2207
  }
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2208
38028
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2209
  //
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2210
  // Generate stub for array fill. If "aligned" is true, the
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2211
  // "to" address is assumed to be heapword aligned.
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2212
  //
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2213
  // Arguments for generated stub:
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2214
  //   to:    c_rarg0
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2215
  //   value: c_rarg1
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2216
  //   count: c_rarg2 treated as signed
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2217
  //
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2218
  address generate_fill(BasicType t, bool aligned, const char *name) {
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2219
    __ align(CodeEntryAlignment);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2220
    StubCodeMark mark(this, "StubRoutines", name);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2221
    address start = __ pc();
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2222
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2223
    BLOCK_COMMENT("Entry:");
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2224
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2225
    const Register to        = c_rarg0;  // source array address
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2226
    const Register value     = c_rarg1;  // value
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2227
    const Register count     = c_rarg2;  // elements count
38233
9f784c50b967 8155967: aarch64: fix register usage in block zeroing
enevill
parents: 38225
diff changeset
  2228
9f784c50b967 8155967: aarch64: fix register usage in block zeroing
enevill
parents: 38225
diff changeset
  2229
    const Register bz_base = r10;        // base for block_zero routine
9f784c50b967 8155967: aarch64: fix register usage in block zeroing
enevill
parents: 38225
diff changeset
  2230
    const Register cnt_words = r11;      // temp register
38028
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2231
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2232
    __ enter();
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2233
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2234
    Label L_fill_elements, L_exit1;
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2235
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2236
    int shift = -1;
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2237
    switch (t) {
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2238
      case T_BYTE:
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2239
        shift = 0;
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2240
        __ cmpw(count, 8 >> shift); // Short arrays (< 8 bytes) fill by element
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2241
        __ bfi(value, value, 8, 8);   // 8 bit -> 16 bit
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2242
        __ bfi(value, value, 16, 16); // 16 bit -> 32 bit
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2243
        __ br(Assembler::LO, L_fill_elements);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2244
        break;
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2245
      case T_SHORT:
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2246
        shift = 1;
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2247
        __ cmpw(count, 8 >> shift); // Short arrays (< 8 bytes) fill by element
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2248
        __ bfi(value, value, 16, 16); // 16 bit -> 32 bit
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2249
        __ br(Assembler::LO, L_fill_elements);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2250
        break;
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2251
      case T_INT:
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2252
        shift = 2;
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2253
        __ cmpw(count, 8 >> shift); // Short arrays (< 8 bytes) fill by element
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2254
        __ br(Assembler::LO, L_fill_elements);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2255
        break;
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2256
      default: ShouldNotReachHere();
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2257
    }
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2258
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2259
    // Align source address at 8 bytes address boundary.
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2260
    Label L_skip_align1, L_skip_align2, L_skip_align4;
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2261
    if (!aligned) {
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2262
      switch (t) {
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2263
        case T_BYTE:
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2264
          // One byte misalignment happens only for byte arrays.
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2265
          __ tbz(to, 0, L_skip_align1);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2266
          __ strb(value, Address(__ post(to, 1)));
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2267
          __ subw(count, count, 1);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2268
          __ bind(L_skip_align1);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2269
          // Fallthrough
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2270
        case T_SHORT:
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2271
          // Two bytes misalignment happens only for byte and short (char) arrays.
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2272
          __ tbz(to, 1, L_skip_align2);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2273
          __ strh(value, Address(__ post(to, 2)));
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2274
          __ subw(count, count, 2 >> shift);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2275
          __ bind(L_skip_align2);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2276
          // Fallthrough
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2277
        case T_INT:
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2278
          // Align to 8 bytes, we know we are 4 byte aligned to start.
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2279
          __ tbz(to, 2, L_skip_align4);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2280
          __ strw(value, Address(__ post(to, 4)));
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2281
          __ subw(count, count, 4 >> shift);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2282
          __ bind(L_skip_align4);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2283
          break;
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2284
        default: ShouldNotReachHere();
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2285
      }
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2286
    }
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2287
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2288
    //
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2289
    //  Fill large chunks
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2290
    //
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2291
    __ lsrw(cnt_words, count, 3 - shift); // number of words
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2292
    __ bfi(value, value, 32, 32);         // 32 bit -> 64 bit
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2293
    __ subw(count, count, cnt_words, Assembler::LSL, 3 - shift);
38143
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 38051
diff changeset
  2294
    if (UseBlockZeroing) {
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 38051
diff changeset
  2295
      Label non_block_zeroing, rest;
45054
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
  2296
      // If the fill value is zero we can use the fast zero_words().
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
  2297
      __ cbnz(value, non_block_zeroing);
38233
9f784c50b967 8155967: aarch64: fix register usage in block zeroing
enevill
parents: 38225
diff changeset
  2298
      __ mov(bz_base, to);
45054
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
  2299
      __ add(to, to, cnt_words, Assembler::LSL, LogBytesPerWord);
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
  2300
      __ zero_words(bz_base, cnt_words);
38143
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 38051
diff changeset
  2301
      __ b(rest);
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 38051
diff changeset
  2302
      __ bind(non_block_zeroing);
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 38051
diff changeset
  2303
      __ fill_words(to, cnt_words, value);
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 38051
diff changeset
  2304
      __ bind(rest);
45054
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
  2305
    } else {
38143
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 38051
diff changeset
  2306
      __ fill_words(to, cnt_words, value);
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 38051
diff changeset
  2307
    }
38028
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2308
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2309
    // Remaining count is less than 8 bytes. Fill it by a single store.
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2310
    // Note that the total length is no less than 8 bytes.
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2311
    if (t == T_BYTE || t == T_SHORT) {
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2312
      Label L_exit1;
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2313
      __ cbzw(count, L_exit1);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2314
      __ add(to, to, count, Assembler::LSL, shift); // points to the end
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2315
      __ str(value, Address(to, -8));    // overwrite some elements
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2316
      __ bind(L_exit1);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2317
      __ leave();
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2318
      __ ret(lr);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2319
    }
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2320
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2321
    // Handle copies less than 8 bytes.
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2322
    Label L_fill_2, L_fill_4, L_exit2;
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2323
    __ bind(L_fill_elements);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2324
    switch (t) {
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2325
      case T_BYTE:
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2326
        __ tbz(count, 0, L_fill_2);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2327
        __ strb(value, Address(__ post(to, 1)));
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2328
        __ bind(L_fill_2);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2329
        __ tbz(count, 1, L_fill_4);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2330
        __ strh(value, Address(__ post(to, 2)));
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2331
        __ bind(L_fill_4);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2332
        __ tbz(count, 2, L_exit2);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2333
        __ strw(value, Address(to));
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2334
        break;
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2335
      case T_SHORT:
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2336
        __ tbz(count, 0, L_fill_4);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2337
        __ strh(value, Address(__ post(to, 2)));
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2338
        __ bind(L_fill_4);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2339
        __ tbz(count, 1, L_exit2);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2340
        __ strw(value, Address(to));
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2341
        break;
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2342
      case T_INT:
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2343
        __ cbzw(count, L_exit2);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2344
        __ strw(value, Address(to));
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2345
        break;
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2346
      default: ShouldNotReachHere();
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2347
    }
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2348
    __ bind(L_exit2);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2349
    __ leave();
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2350
    __ ret(lr);
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2351
    return start;
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2352
  }
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2353
57804
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2354
  address generate_data_cache_writeback() {
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2355
    const Register line        = c_rarg0;  // address of line to write back
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2356
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2357
    __ align(CodeEntryAlignment);
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2358
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2359
    StubCodeMark mark(this, "StubRoutines", "_data_cache_writeback");
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2360
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2361
    address start = __ pc();
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2362
    __ enter();
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2363
    __ cache_wb(Address(line, 0));
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2364
    __ leave();
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2365
    __ ret(lr);
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2366
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2367
    return start;
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2368
  }
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2369
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2370
  address generate_data_cache_writeback_sync() {
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2371
    const Register is_pre     = c_rarg0;  // pre or post sync
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2372
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2373
    __ align(CodeEntryAlignment);
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2374
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2375
    StubCodeMark mark(this, "StubRoutines", "_data_cache_writeback_sync");
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2376
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2377
    // pre wbsync is a no-op
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2378
    // post wbsync translates to an sfence
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2379
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2380
    Label skip;
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2381
    address start = __ pc();
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2382
    __ enter();
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2383
    __ cbnz(is_pre, skip);
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2384
    __ cache_wbsync(false);
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2385
    __ bind(skip);
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2386
    __ leave();
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2387
    __ ret(lr);
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2388
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2389
    return start;
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2390
  }
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  2391
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2392
  void generate_arraycopy_stubs() {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2393
    address entry;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2394
    address entry_jbyte_arraycopy;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2395
    address entry_jshort_arraycopy;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2396
    address entry_jint_arraycopy;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2397
    address entry_oop_arraycopy;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2398
    address entry_jlong_arraycopy;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2399
    address entry_checkcast_arraycopy;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2400
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2401
    generate_copy_longs(copy_f, r0, r1, rscratch2, copy_forwards);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2402
    generate_copy_longs(copy_b, r0, r1, rscratch2, copy_backwards);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2403
45054
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
  2404
    StubRoutines::aarch64::_zero_blocks = generate_zero_blocks();
38143
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 38051
diff changeset
  2405
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2406
    //*** jbyte
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2407
    // Always need aligned and unaligned versions
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2408
    StubRoutines::_jbyte_disjoint_arraycopy         = generate_disjoint_byte_copy(false, &entry,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2409
                                                                                  "jbyte_disjoint_arraycopy");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2410
    StubRoutines::_jbyte_arraycopy                  = generate_conjoint_byte_copy(false, entry,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2411
                                                                                  &entry_jbyte_arraycopy,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2412
                                                                                  "jbyte_arraycopy");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2413
    StubRoutines::_arrayof_jbyte_disjoint_arraycopy = generate_disjoint_byte_copy(true, &entry,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2414
                                                                                  "arrayof_jbyte_disjoint_arraycopy");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2415
    StubRoutines::_arrayof_jbyte_arraycopy          = generate_conjoint_byte_copy(true, entry, NULL,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2416
                                                                                  "arrayof_jbyte_arraycopy");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2417
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2418
    //*** jshort
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2419
    // Always need aligned and unaligned versions
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2420
    StubRoutines::_jshort_disjoint_arraycopy         = generate_disjoint_short_copy(false, &entry,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2421
                                                                                    "jshort_disjoint_arraycopy");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2422
    StubRoutines::_jshort_arraycopy                  = generate_conjoint_short_copy(false, entry,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2423
                                                                                    &entry_jshort_arraycopy,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2424
                                                                                    "jshort_arraycopy");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2425
    StubRoutines::_arrayof_jshort_disjoint_arraycopy = generate_disjoint_short_copy(true, &entry,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2426
                                                                                    "arrayof_jshort_disjoint_arraycopy");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2427
    StubRoutines::_arrayof_jshort_arraycopy          = generate_conjoint_short_copy(true, entry, NULL,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2428
                                                                                    "arrayof_jshort_arraycopy");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2429
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2430
    //*** jint
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2431
    // Aligned versions
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2432
    StubRoutines::_arrayof_jint_disjoint_arraycopy = generate_disjoint_int_copy(true, &entry,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2433
                                                                                "arrayof_jint_disjoint_arraycopy");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2434
    StubRoutines::_arrayof_jint_arraycopy          = generate_conjoint_int_copy(true, entry, &entry_jint_arraycopy,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2435
                                                                                "arrayof_jint_arraycopy");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2436
    // In 64 bit we need both aligned and unaligned versions of jint arraycopy.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2437
    // entry_jint_arraycopy always points to the unaligned version
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2438
    StubRoutines::_jint_disjoint_arraycopy         = generate_disjoint_int_copy(false, &entry,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2439
                                                                                "jint_disjoint_arraycopy");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2440
    StubRoutines::_jint_arraycopy                  = generate_conjoint_int_copy(false, entry,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2441
                                                                                &entry_jint_arraycopy,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2442
                                                                                "jint_arraycopy");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2443
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2444
    //*** jlong
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2445
    // It is always aligned
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2446
    StubRoutines::_arrayof_jlong_disjoint_arraycopy = generate_disjoint_long_copy(true, &entry,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2447
                                                                                  "arrayof_jlong_disjoint_arraycopy");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2448
    StubRoutines::_arrayof_jlong_arraycopy          = generate_conjoint_long_copy(true, entry, &entry_jlong_arraycopy,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2449
                                                                                  "arrayof_jlong_arraycopy");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2450
    StubRoutines::_jlong_disjoint_arraycopy         = StubRoutines::_arrayof_jlong_disjoint_arraycopy;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2451
    StubRoutines::_jlong_arraycopy                  = StubRoutines::_arrayof_jlong_arraycopy;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2452
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2453
    //*** oops
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2454
    {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2455
      // With compressed oops we need unaligned versions; notice that
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2456
      // we overwrite entry_oop_arraycopy.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2457
      bool aligned = !UseCompressedOops;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2458
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2459
      StubRoutines::_arrayof_oop_disjoint_arraycopy
36326
d25af58cfc94 8150045: arraycopy causes segfaults in SATB during garbage collection
aph
parents: 35843
diff changeset
  2460
        = generate_disjoint_oop_copy(aligned, &entry, "arrayof_oop_disjoint_arraycopy",
d25af58cfc94 8150045: arraycopy causes segfaults in SATB during garbage collection
aph
parents: 35843
diff changeset
  2461
                                     /*dest_uninitialized*/false);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2462
      StubRoutines::_arrayof_oop_arraycopy
36326
d25af58cfc94 8150045: arraycopy causes segfaults in SATB during garbage collection
aph
parents: 35843
diff changeset
  2463
        = generate_conjoint_oop_copy(aligned, entry, &entry_oop_arraycopy, "arrayof_oop_arraycopy",
d25af58cfc94 8150045: arraycopy causes segfaults in SATB during garbage collection
aph
parents: 35843
diff changeset
  2464
                                     /*dest_uninitialized*/false);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2465
      // Aligned versions without pre-barriers
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2466
      StubRoutines::_arrayof_oop_disjoint_arraycopy_uninit
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2467
        = generate_disjoint_oop_copy(aligned, &entry, "arrayof_oop_disjoint_arraycopy_uninit",
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2468
                                     /*dest_uninitialized*/true);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2469
      StubRoutines::_arrayof_oop_arraycopy_uninit
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2470
        = generate_conjoint_oop_copy(aligned, entry, NULL, "arrayof_oop_arraycopy_uninit",
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2471
                                     /*dest_uninitialized*/true);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2472
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2473
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2474
    StubRoutines::_oop_disjoint_arraycopy            = StubRoutines::_arrayof_oop_disjoint_arraycopy;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2475
    StubRoutines::_oop_arraycopy                     = StubRoutines::_arrayof_oop_arraycopy;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2476
    StubRoutines::_oop_disjoint_arraycopy_uninit     = StubRoutines::_arrayof_oop_disjoint_arraycopy_uninit;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2477
    StubRoutines::_oop_arraycopy_uninit              = StubRoutines::_arrayof_oop_arraycopy_uninit;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2478
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2479
    StubRoutines::_checkcast_arraycopy        = generate_checkcast_copy("checkcast_arraycopy", &entry_checkcast_arraycopy);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2480
    StubRoutines::_checkcast_arraycopy_uninit = generate_checkcast_copy("checkcast_arraycopy_uninit", NULL,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2481
                                                                        /*dest_uninitialized*/true);
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2482
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2483
    StubRoutines::_unsafe_arraycopy    = generate_unsafe_copy("unsafe_arraycopy",
37271
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  2484
                                                              entry_jbyte_arraycopy,
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  2485
                                                              entry_jshort_arraycopy,
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  2486
                                                              entry_jint_arraycopy,
95774d8b3cc2 8152840: aarch64: improve _unsafe_arraycopy stub routine
fyang
parents: 36595
diff changeset
  2487
                                                              entry_jlong_arraycopy);
35119
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2488
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2489
    StubRoutines::_generic_arraycopy   = generate_generic_copy("generic_arraycopy",
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2490
                                                               entry_jbyte_arraycopy,
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2491
                                                               entry_jshort_arraycopy,
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2492
                                                               entry_jint_arraycopy,
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2493
                                                               entry_oop_arraycopy,
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2494
                                                               entry_jlong_arraycopy,
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2495
                                                               entry_checkcast_arraycopy);
7af8d9f08a25 8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
aph
parents: 33198
diff changeset
  2496
38028
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2497
    StubRoutines::_jbyte_fill = generate_fill(T_BYTE, false, "jbyte_fill");
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2498
    StubRoutines::_jshort_fill = generate_fill(T_SHORT, false, "jshort_fill");
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2499
    StubRoutines::_jint_fill = generate_fill(T_INT, false, "jint_fill");
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2500
    StubRoutines::_arrayof_jbyte_fill = generate_fill(T_BYTE, true, "arrayof_jbyte_fill");
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2501
    StubRoutines::_arrayof_jshort_fill = generate_fill(T_SHORT, true, "arrayof_jshort_fill");
be8cc044b136 8153797: aarch64: Add Arrays.fill stub code
enevill
parents: 37271
diff changeset
  2502
    StubRoutines::_arrayof_jint_fill = generate_fill(T_INT, true, "arrayof_jint_fill");
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2503
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2504
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2505
  void generate_math_stubs() { Unimplemented(); }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2506
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2507
  // Arguments:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2508
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2509
  // Inputs:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2510
  //   c_rarg0   - source byte array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2511
  //   c_rarg1   - destination byte array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2512
  //   c_rarg2   - K (key) in little endian int array
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2513
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2514
  address generate_aescrypt_encryptBlock() {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2515
    __ align(CodeEntryAlignment);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2516
    StubCodeMark mark(this, "StubRoutines", "aescrypt_encryptBlock");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2517
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2518
    Label L_doLast;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2519
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2520
    const Register from        = c_rarg0;  // source array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2521
    const Register to          = c_rarg1;  // destination array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2522
    const Register key         = c_rarg2;  // key array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2523
    const Register keylen      = rscratch1;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2524
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2525
    address start = __ pc();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2526
    __ enter();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2527
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2528
    __ ldrw(keylen, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2529
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2530
    __ ld1(v0, __ T16B, from); // get 16 bytes of input
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2531
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2532
    __ ld1(v1, v2, v3, v4, __ T16B, __ post(key, 64));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2533
    __ rev32(v1, __ T16B, v1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2534
    __ rev32(v2, __ T16B, v2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2535
    __ rev32(v3, __ T16B, v3);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2536
    __ rev32(v4, __ T16B, v4);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2537
    __ aese(v0, v1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2538
    __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2539
    __ aese(v0, v2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2540
    __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2541
    __ aese(v0, v3);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2542
    __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2543
    __ aese(v0, v4);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2544
    __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2545
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2546
    __ ld1(v1, v2, v3, v4, __ T16B, __ post(key, 64));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2547
    __ rev32(v1, __ T16B, v1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2548
    __ rev32(v2, __ T16B, v2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2549
    __ rev32(v3, __ T16B, v3);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2550
    __ rev32(v4, __ T16B, v4);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2551
    __ aese(v0, v1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2552
    __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2553
    __ aese(v0, v2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2554
    __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2555
    __ aese(v0, v3);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2556
    __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2557
    __ aese(v0, v4);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2558
    __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2559
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2560
    __ ld1(v1, v2, __ T16B, __ post(key, 32));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2561
    __ rev32(v1, __ T16B, v1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2562
    __ rev32(v2, __ T16B, v2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2563
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2564
    __ cmpw(keylen, 44);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2565
    __ br(Assembler::EQ, L_doLast);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2566
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2567
    __ aese(v0, v1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2568
    __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2569
    __ aese(v0, v2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2570
    __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2571
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2572
    __ ld1(v1, v2, __ T16B, __ post(key, 32));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2573
    __ rev32(v1, __ T16B, v1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2574
    __ rev32(v2, __ T16B, v2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2575
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2576
    __ cmpw(keylen, 52);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2577
    __ br(Assembler::EQ, L_doLast);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2578
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2579
    __ aese(v0, v1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2580
    __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2581
    __ aese(v0, v2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2582
    __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2583
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2584
    __ ld1(v1, v2, __ T16B, __ post(key, 32));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2585
    __ rev32(v1, __ T16B, v1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2586
    __ rev32(v2, __ T16B, v2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2587
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2588
    __ BIND(L_doLast);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2589
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2590
    __ aese(v0, v1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2591
    __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2592
    __ aese(v0, v2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2593
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2594
    __ ld1(v1, __ T16B, key);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2595
    __ rev32(v1, __ T16B, v1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2596
    __ eor(v0, __ T16B, v0, v1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2597
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2598
    __ st1(v0, __ T16B, to);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2599
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2600
    __ mov(r0, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2601
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2602
    __ leave();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2603
    __ ret(lr);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2604
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2605
    return start;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2606
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2607
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2608
  // Arguments:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2609
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2610
  // Inputs:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2611
  //   c_rarg0   - source byte array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2612
  //   c_rarg1   - destination byte array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2613
  //   c_rarg2   - K (key) in little endian int array
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2614
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2615
  address generate_aescrypt_decryptBlock() {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2616
    assert(UseAES, "need AES instructions and misaligned SSE support");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2617
    __ align(CodeEntryAlignment);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2618
    StubCodeMark mark(this, "StubRoutines", "aescrypt_decryptBlock");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2619
    Label L_doLast;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2620
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2621
    const Register from        = c_rarg0;  // source array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2622
    const Register to          = c_rarg1;  // destination array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2623
    const Register key         = c_rarg2;  // key array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2624
    const Register keylen      = rscratch1;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2625
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2626
    address start = __ pc();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2627
    __ enter(); // required for proper stackwalking of RuntimeStub frame
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2628
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2629
    __ ldrw(keylen, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2630
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2631
    __ ld1(v0, __ T16B, from); // get 16 bytes of input
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2632
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2633
    __ ld1(v5, __ T16B, __ post(key, 16));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2634
    __ rev32(v5, __ T16B, v5);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2635
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2636
    __ ld1(v1, v2, v3, v4, __ T16B, __ post(key, 64));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2637
    __ rev32(v1, __ T16B, v1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2638
    __ rev32(v2, __ T16B, v2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2639
    __ rev32(v3, __ T16B, v3);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2640
    __ rev32(v4, __ T16B, v4);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2641
    __ aesd(v0, v1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2642
    __ aesimc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2643
    __ aesd(v0, v2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2644
    __ aesimc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2645
    __ aesd(v0, v3);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2646
    __ aesimc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2647
    __ aesd(v0, v4);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2648
    __ aesimc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2649
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2650
    __ ld1(v1, v2, v3, v4, __ T16B, __ post(key, 64));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2651
    __ rev32(v1, __ T16B, v1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2652
    __ rev32(v2, __ T16B, v2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2653
    __ rev32(v3, __ T16B, v3);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2654
    __ rev32(v4, __ T16B, v4);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2655
    __ aesd(v0, v1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2656
    __ aesimc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2657
    __ aesd(v0, v2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2658
    __ aesimc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2659
    __ aesd(v0, v3);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2660
    __ aesimc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2661
    __ aesd(v0, v4);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2662
    __ aesimc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2663
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2664
    __ ld1(v1, v2, __ T16B, __ post(key, 32));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2665
    __ rev32(v1, __ T16B, v1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2666
    __ rev32(v2, __ T16B, v2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2667
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2668
    __ cmpw(keylen, 44);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2669
    __ br(Assembler::EQ, L_doLast);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2670
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2671
    __ aesd(v0, v1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2672
    __ aesimc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2673
    __ aesd(v0, v2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2674
    __ aesimc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2675
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2676
    __ ld1(v1, v2, __ T16B, __ post(key, 32));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2677
    __ rev32(v1, __ T16B, v1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2678
    __ rev32(v2, __ T16B, v2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2679
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2680
    __ cmpw(keylen, 52);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2681
    __ br(Assembler::EQ, L_doLast);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2682
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2683
    __ aesd(v0, v1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2684
    __ aesimc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2685
    __ aesd(v0, v2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2686
    __ aesimc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2687
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2688
    __ ld1(v1, v2, __ T16B, __ post(key, 32));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2689
    __ rev32(v1, __ T16B, v1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2690
    __ rev32(v2, __ T16B, v2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2691
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2692
    __ BIND(L_doLast);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2693
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2694
    __ aesd(v0, v1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2695
    __ aesimc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2696
    __ aesd(v0, v2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2697
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2698
    __ eor(v0, __ T16B, v0, v5);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2699
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2700
    __ st1(v0, __ T16B, to);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2701
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2702
    __ mov(r0, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2703
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2704
    __ leave();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2705
    __ ret(lr);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2706
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2707
    return start;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2708
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2709
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2710
  // Arguments:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2711
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2712
  // Inputs:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2713
  //   c_rarg0   - source byte array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2714
  //   c_rarg1   - destination byte array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2715
  //   c_rarg2   - K (key) in little endian int array
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2716
  //   c_rarg3   - r vector byte array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2717
  //   c_rarg4   - input length
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2718
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2719
  // Output:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2720
  //   x0        - input length
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2721
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2722
  address generate_cipherBlockChaining_encryptAESCrypt() {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2723
    assert(UseAES, "need AES instructions and misaligned SSE support");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2724
    __ align(CodeEntryAlignment);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2725
    StubCodeMark mark(this, "StubRoutines", "cipherBlockChaining_encryptAESCrypt");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2726
42577
c47121f6307d 8169529: AArch64: Revert old JDK-8167595 changes after JDK-8159035 fix is pushed
rraghavan
parents: 41729
diff changeset
  2727
    Label L_loadkeys_44, L_loadkeys_52, L_aes_loop, L_rounds_44, L_rounds_52;
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2728
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2729
    const Register from        = c_rarg0;  // source array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2730
    const Register to          = c_rarg1;  // destination array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2731
    const Register key         = c_rarg2;  // key array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2732
    const Register rvec        = c_rarg3;  // r byte array initialized from initvector array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2733
                                           // and left with the results of the last encryption block
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2734
    const Register len_reg     = c_rarg4;  // src len (must be multiple of blocksize 16)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2735
    const Register keylen      = rscratch1;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2736
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2737
    address start = __ pc();
41729
d852f04fa9df 8167595: AArch64: SEGV in stub code cipherBlockChaining_decryptAESCrypt
aph
parents: 40643
diff changeset
  2738
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2739
      __ enter();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2740
42577
c47121f6307d 8169529: AArch64: Revert old JDK-8167595 changes after JDK-8159035 fix is pushed
rraghavan
parents: 41729
diff changeset
  2741
      __ movw(rscratch2, len_reg);
41729
d852f04fa9df 8167595: AArch64: SEGV in stub code cipherBlockChaining_decryptAESCrypt
aph
parents: 40643
diff changeset
  2742
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2743
      __ ldrw(keylen, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2744
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2745
      __ ld1(v0, __ T16B, rvec);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2746
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2747
      __ cmpw(keylen, 52);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2748
      __ br(Assembler::CC, L_loadkeys_44);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2749
      __ br(Assembler::EQ, L_loadkeys_52);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2750
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2751
      __ ld1(v17, v18, __ T16B, __ post(key, 32));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2752
      __ rev32(v17, __ T16B, v17);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2753
      __ rev32(v18, __ T16B, v18);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2754
    __ BIND(L_loadkeys_52);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2755
      __ ld1(v19, v20, __ T16B, __ post(key, 32));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2756
      __ rev32(v19, __ T16B, v19);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2757
      __ rev32(v20, __ T16B, v20);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2758
    __ BIND(L_loadkeys_44);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2759
      __ ld1(v21, v22, v23, v24, __ T16B, __ post(key, 64));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2760
      __ rev32(v21, __ T16B, v21);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2761
      __ rev32(v22, __ T16B, v22);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2762
      __ rev32(v23, __ T16B, v23);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2763
      __ rev32(v24, __ T16B, v24);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2764
      __ ld1(v25, v26, v27, v28, __ T16B, __ post(key, 64));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2765
      __ rev32(v25, __ T16B, v25);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2766
      __ rev32(v26, __ T16B, v26);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2767
      __ rev32(v27, __ T16B, v27);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2768
      __ rev32(v28, __ T16B, v28);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2769
      __ ld1(v29, v30, v31, __ T16B, key);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2770
      __ rev32(v29, __ T16B, v29);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2771
      __ rev32(v30, __ T16B, v30);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2772
      __ rev32(v31, __ T16B, v31);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2773
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2774
    __ BIND(L_aes_loop);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2775
      __ ld1(v1, __ T16B, __ post(from, 16));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2776
      __ eor(v0, __ T16B, v0, v1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2777
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2778
      __ br(Assembler::CC, L_rounds_44);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2779
      __ br(Assembler::EQ, L_rounds_52);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2780
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2781
      __ aese(v0, v17); __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2782
      __ aese(v0, v18); __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2783
    __ BIND(L_rounds_52);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2784
      __ aese(v0, v19); __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2785
      __ aese(v0, v20); __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2786
    __ BIND(L_rounds_44);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2787
      __ aese(v0, v21); __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2788
      __ aese(v0, v22); __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2789
      __ aese(v0, v23); __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2790
      __ aese(v0, v24); __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2791
      __ aese(v0, v25); __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2792
      __ aese(v0, v26); __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2793
      __ aese(v0, v27); __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2794
      __ aese(v0, v28); __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2795
      __ aese(v0, v29); __ aesmc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2796
      __ aese(v0, v30);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2797
      __ eor(v0, __ T16B, v0, v31);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2798
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2799
      __ st1(v0, __ T16B, __ post(to, 16));
41729
d852f04fa9df 8167595: AArch64: SEGV in stub code cipherBlockChaining_decryptAESCrypt
aph
parents: 40643
diff changeset
  2800
d852f04fa9df 8167595: AArch64: SEGV in stub code cipherBlockChaining_decryptAESCrypt
aph
parents: 40643
diff changeset
  2801
      __ subw(len_reg, len_reg, 16);
d852f04fa9df 8167595: AArch64: SEGV in stub code cipherBlockChaining_decryptAESCrypt
aph
parents: 40643
diff changeset
  2802
      __ cbnzw(len_reg, L_aes_loop);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2803
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2804
      __ st1(v0, __ T16B, rvec);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2805
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2806
      __ mov(r0, rscratch2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2807
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2808
      __ leave();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2809
      __ ret(lr);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2810
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2811
      return start;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2812
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2813
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2814
  // Arguments:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2815
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2816
  // Inputs:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2817
  //   c_rarg0   - source byte array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2818
  //   c_rarg1   - destination byte array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2819
  //   c_rarg2   - K (key) in little endian int array
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2820
  //   c_rarg3   - r vector byte array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2821
  //   c_rarg4   - input length
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2822
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2823
  // Output:
35135
twisti
parents: 35119 34664
diff changeset
  2824
  //   r0        - input length
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2825
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2826
  address generate_cipherBlockChaining_decryptAESCrypt() {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2827
    assert(UseAES, "need AES instructions and misaligned SSE support");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2828
    __ align(CodeEntryAlignment);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2829
    StubCodeMark mark(this, "StubRoutines", "cipherBlockChaining_decryptAESCrypt");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2830
42577
c47121f6307d 8169529: AArch64: Revert old JDK-8167595 changes after JDK-8159035 fix is pushed
rraghavan
parents: 41729
diff changeset
  2831
    Label L_loadkeys_44, L_loadkeys_52, L_aes_loop, L_rounds_44, L_rounds_52;
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2832
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2833
    const Register from        = c_rarg0;  // source array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2834
    const Register to          = c_rarg1;  // destination array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2835
    const Register key         = c_rarg2;  // key array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2836
    const Register rvec        = c_rarg3;  // r byte array initialized from initvector array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2837
                                           // and left with the results of the last encryption block
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2838
    const Register len_reg     = c_rarg4;  // src len (must be multiple of blocksize 16)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2839
    const Register keylen      = rscratch1;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2840
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2841
    address start = __ pc();
41729
d852f04fa9df 8167595: AArch64: SEGV in stub code cipherBlockChaining_decryptAESCrypt
aph
parents: 40643
diff changeset
  2842
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2843
      __ enter();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2844
42577
c47121f6307d 8169529: AArch64: Revert old JDK-8167595 changes after JDK-8159035 fix is pushed
rraghavan
parents: 41729
diff changeset
  2845
      __ movw(rscratch2, len_reg);
41729
d852f04fa9df 8167595: AArch64: SEGV in stub code cipherBlockChaining_decryptAESCrypt
aph
parents: 40643
diff changeset
  2846
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2847
      __ ldrw(keylen, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2848
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2849
      __ ld1(v2, __ T16B, rvec);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2850
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2851
      __ ld1(v31, __ T16B, __ post(key, 16));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2852
      __ rev32(v31, __ T16B, v31);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2853
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2854
      __ cmpw(keylen, 52);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2855
      __ br(Assembler::CC, L_loadkeys_44);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2856
      __ br(Assembler::EQ, L_loadkeys_52);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2857
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2858
      __ ld1(v17, v18, __ T16B, __ post(key, 32));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2859
      __ rev32(v17, __ T16B, v17);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2860
      __ rev32(v18, __ T16B, v18);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2861
    __ BIND(L_loadkeys_52);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2862
      __ ld1(v19, v20, __ T16B, __ post(key, 32));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2863
      __ rev32(v19, __ T16B, v19);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2864
      __ rev32(v20, __ T16B, v20);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2865
    __ BIND(L_loadkeys_44);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2866
      __ ld1(v21, v22, v23, v24, __ T16B, __ post(key, 64));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2867
      __ rev32(v21, __ T16B, v21);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2868
      __ rev32(v22, __ T16B, v22);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2869
      __ rev32(v23, __ T16B, v23);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2870
      __ rev32(v24, __ T16B, v24);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2871
      __ ld1(v25, v26, v27, v28, __ T16B, __ post(key, 64));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2872
      __ rev32(v25, __ T16B, v25);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2873
      __ rev32(v26, __ T16B, v26);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2874
      __ rev32(v27, __ T16B, v27);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2875
      __ rev32(v28, __ T16B, v28);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2876
      __ ld1(v29, v30, __ T16B, key);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2877
      __ rev32(v29, __ T16B, v29);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2878
      __ rev32(v30, __ T16B, v30);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2879
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2880
    __ BIND(L_aes_loop);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2881
      __ ld1(v0, __ T16B, __ post(from, 16));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2882
      __ orr(v1, __ T16B, v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2883
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2884
      __ br(Assembler::CC, L_rounds_44);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2885
      __ br(Assembler::EQ, L_rounds_52);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2886
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2887
      __ aesd(v0, v17); __ aesimc(v0, v0);
34664
41c821224dd7 8144201: aarch64: jdk/test/com/sun/net/httpserver/Test6a.java fails with --enable-unlimited-crypto
fyang
parents: 33198
diff changeset
  2888
      __ aesd(v0, v18); __ aesimc(v0, v0);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2889
    __ BIND(L_rounds_52);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2890
      __ aesd(v0, v19); __ aesimc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2891
      __ aesd(v0, v20); __ aesimc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2892
    __ BIND(L_rounds_44);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2893
      __ aesd(v0, v21); __ aesimc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2894
      __ aesd(v0, v22); __ aesimc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2895
      __ aesd(v0, v23); __ aesimc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2896
      __ aesd(v0, v24); __ aesimc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2897
      __ aesd(v0, v25); __ aesimc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2898
      __ aesd(v0, v26); __ aesimc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2899
      __ aesd(v0, v27); __ aesimc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2900
      __ aesd(v0, v28); __ aesimc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2901
      __ aesd(v0, v29); __ aesimc(v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2902
      __ aesd(v0, v30);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2903
      __ eor(v0, __ T16B, v0, v31);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2904
      __ eor(v0, __ T16B, v0, v2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2905
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2906
      __ st1(v0, __ T16B, __ post(to, 16));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2907
      __ orr(v2, __ T16B, v1, v1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2908
41729
d852f04fa9df 8167595: AArch64: SEGV in stub code cipherBlockChaining_decryptAESCrypt
aph
parents: 40643
diff changeset
  2909
      __ subw(len_reg, len_reg, 16);
d852f04fa9df 8167595: AArch64: SEGV in stub code cipherBlockChaining_decryptAESCrypt
aph
parents: 40643
diff changeset
  2910
      __ cbnzw(len_reg, L_aes_loop);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2911
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2912
      __ st1(v2, __ T16B, rvec);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2913
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2914
      __ mov(r0, rscratch2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2915
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2916
      __ leave();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2917
      __ ret(lr);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2918
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2919
    return start;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2920
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2921
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2922
  // Arguments:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2923
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2924
  // Inputs:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2925
  //   c_rarg0   - byte[]  source+offset
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2926
  //   c_rarg1   - int[]   SHA.state
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2927
  //   c_rarg2   - int     offset
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2928
  //   c_rarg3   - int     limit
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2929
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2930
  address generate_sha1_implCompress(bool multi_block, const char *name) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2931
    __ align(CodeEntryAlignment);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2932
    StubCodeMark mark(this, "StubRoutines", name);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2933
    address start = __ pc();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2934
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2935
    Register buf   = c_rarg0;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2936
    Register state = c_rarg1;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2937
    Register ofs   = c_rarg2;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2938
    Register limit = c_rarg3;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2939
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2940
    Label keys;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2941
    Label sha1_loop;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2942
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2943
    // load the keys into v0..v3
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2944
    __ adr(rscratch1, keys);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2945
    __ ld4r(v0, v1, v2, v3, __ T4S, Address(rscratch1));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2946
    // load 5 words state into v6, v7
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2947
    __ ldrq(v6, Address(state, 0));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2948
    __ ldrs(v7, Address(state, 16));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2949
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2950
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2951
    __ BIND(sha1_loop);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2952
    // load 64 bytes of data into v16..v19
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2953
    __ ld1(v16, v17, v18, v19, __ T4S, multi_block ? __ post(buf, 64) : buf);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2954
    __ rev32(v16, __ T16B, v16);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2955
    __ rev32(v17, __ T16B, v17);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2956
    __ rev32(v18, __ T16B, v18);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2957
    __ rev32(v19, __ T16B, v19);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2958
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2959
    // do the sha1
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2960
    __ addv(v4, __ T4S, v16, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2961
    __ orr(v20, __ T16B, v6, v6);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2962
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2963
    FloatRegister d0 = v16;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2964
    FloatRegister d1 = v17;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2965
    FloatRegister d2 = v18;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2966
    FloatRegister d3 = v19;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2967
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2968
    for (int round = 0; round < 20; round++) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2969
      FloatRegister tmp1 = (round & 1) ? v4 : v5;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2970
      FloatRegister tmp2 = (round & 1) ? v21 : v22;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2971
      FloatRegister tmp3 = round ? ((round & 1) ? v22 : v21) : v7;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2972
      FloatRegister tmp4 = (round & 1) ? v5 : v4;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2973
      FloatRegister key = (round < 4) ? v0 : ((round < 9) ? v1 : ((round < 14) ? v2 : v3));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2974
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2975
      if (round < 16) __ sha1su0(d0, __ T4S, d1, d2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2976
      if (round < 19) __ addv(tmp1, __ T4S, d1, key);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2977
      __ sha1h(tmp2, __ T4S, v20);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2978
      if (round < 5)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2979
        __ sha1c(v20, __ T4S, tmp3, tmp4);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2980
      else if (round < 10 || round >= 15)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2981
        __ sha1p(v20, __ T4S, tmp3, tmp4);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2982
      else
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2983
        __ sha1m(v20, __ T4S, tmp3, tmp4);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2984
      if (round < 16) __ sha1su1(d0, __ T4S, d3);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2985
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2986
      tmp1 = d0; d0 = d1; d1 = d2; d2 = d3; d3 = tmp1;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2987
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2988
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2989
    __ addv(v7, __ T2S, v7, v21);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2990
    __ addv(v6, __ T4S, v6, v20);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2991
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2992
    if (multi_block) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2993
      __ add(ofs, ofs, 64);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2994
      __ cmp(ofs, limit);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2995
      __ br(Assembler::LE, sha1_loop);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2996
      __ mov(c_rarg0, ofs); // return ofs
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2997
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2998
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2999
    __ strq(v6, Address(state, 0));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3000
    __ strs(v7, Address(state, 16));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3001
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3002
    __ ret(lr);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3003
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3004
    __ bind(keys);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3005
    __ emit_int32(0x5a827999);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3006
    __ emit_int32(0x6ed9eba1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3007
    __ emit_int32(0x8f1bbcdc);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3008
    __ emit_int32(0xca62c1d6);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3009
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3010
    return start;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3011
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3012
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3013
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3014
  // Arguments:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3015
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3016
  // Inputs:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3017
  //   c_rarg0   - byte[]  source+offset
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3018
  //   c_rarg1   - int[]   SHA.state
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3019
  //   c_rarg2   - int     offset
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3020
  //   c_rarg3   - int     limit
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3021
  //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3022
  address generate_sha256_implCompress(bool multi_block, const char *name) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3023
    static const uint32_t round_consts[64] = {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3024
      0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3025
      0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3026
      0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3027
      0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3028
      0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3029
      0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3030
      0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3031
      0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3032
      0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3033
      0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3034
      0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3035
      0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3036
      0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3037
      0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3038
      0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3039
      0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3040
    };
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3041
    __ align(CodeEntryAlignment);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3042
    StubCodeMark mark(this, "StubRoutines", name);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3043
    address start = __ pc();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3044
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3045
    Register buf   = c_rarg0;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3046
    Register state = c_rarg1;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3047
    Register ofs   = c_rarg2;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3048
    Register limit = c_rarg3;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3049
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3050
    Label sha1_loop;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3051
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3052
    __ stpd(v8, v9, __ pre(sp, -32));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3053
    __ stpd(v10, v11, Address(sp, 16));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3054
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3055
// dga == v0
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3056
// dgb == v1
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3057
// dg0 == v2
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3058
// dg1 == v3
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3059
// dg2 == v4
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3060
// t0 == v6
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3061
// t1 == v7
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3062
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3063
    // load 16 keys to v16..v31
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3064
    __ lea(rscratch1, ExternalAddress((address)round_consts));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3065
    __ ld1(v16, v17, v18, v19, __ T4S, __ post(rscratch1, 64));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3066
    __ ld1(v20, v21, v22, v23, __ T4S, __ post(rscratch1, 64));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3067
    __ ld1(v24, v25, v26, v27, __ T4S, __ post(rscratch1, 64));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3068
    __ ld1(v28, v29, v30, v31, __ T4S, rscratch1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3069
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3070
    // load 8 words (256 bits) state
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3071
    __ ldpq(v0, v1, state);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3072
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3073
    __ BIND(sha1_loop);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3074
    // load 64 bytes of data into v8..v11
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3075
    __ ld1(v8, v9, v10, v11, __ T4S, multi_block ? __ post(buf, 64) : buf);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3076
    __ rev32(v8, __ T16B, v8);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3077
    __ rev32(v9, __ T16B, v9);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3078
    __ rev32(v10, __ T16B, v10);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3079
    __ rev32(v11, __ T16B, v11);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3080
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3081
    __ addv(v6, __ T4S, v8, v16);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3082
    __ orr(v2, __ T16B, v0, v0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3083
    __ orr(v3, __ T16B, v1, v1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3084
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3085
    FloatRegister d0 = v8;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3086
    FloatRegister d1 = v9;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3087
    FloatRegister d2 = v10;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3088
    FloatRegister d3 = v11;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3089
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3090
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3091
    for (int round = 0; round < 16; round++) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3092
      FloatRegister tmp1 = (round & 1) ? v6 : v7;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3093
      FloatRegister tmp2 = (round & 1) ? v7 : v6;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3094
      FloatRegister tmp3 = (round & 1) ? v2 : v4;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3095
      FloatRegister tmp4 = (round & 1) ? v4 : v2;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3096
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3097
      if (round < 12) __ sha256su0(d0, __ T4S, d1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3098
       __ orr(v4, __ T16B, v2, v2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3099
      if (round < 15)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3100
        __ addv(tmp1, __ T4S, d1, as_FloatRegister(round + 17));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3101
      __ sha256h(v2, __ T4S, v3, tmp2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3102
      __ sha256h2(v3, __ T4S, v4, tmp2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3103
      if (round < 12) __ sha256su1(d0, __ T4S, d2, d3);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3104
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3105
      tmp1 = d0; d0 = d1; d1 = d2; d2 = d3; d3 = tmp1;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3106
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3107
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3108
    __ addv(v0, __ T4S, v0, v2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3109
    __ addv(v1, __ T4S, v1, v3);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3110
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3111
    if (multi_block) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3112
      __ add(ofs, ofs, 64);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3113
      __ cmp(ofs, limit);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3114
      __ br(Assembler::LE, sha1_loop);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3115
      __ mov(c_rarg0, ofs); // return ofs
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3116
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3117
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3118
    __ ldpd(v10, v11, Address(sp, 16));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3119
    __ ldpd(v8, v9, __ post(sp, 32));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3120
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3121
    __ stpq(v0, v1, state);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3122
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3123
    __ ret(lr);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3124
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3125
    return start;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3126
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3127
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3128
  // Safefetch stubs.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3129
  void generate_safefetch(const char* name, int size, address* entry,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3130
                          address* fault_pc, address* continuation_pc) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3131
    // safefetch signatures:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3132
    //   int      SafeFetch32(int*      adr, int      errValue);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3133
    //   intptr_t SafeFetchN (intptr_t* adr, intptr_t errValue);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3134
    //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3135
    // arguments:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3136
    //   c_rarg0 = adr
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3137
    //   c_rarg1 = errValue
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3138
    //
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3139
    // result:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3140
    //   PPC_RET  = *adr or errValue
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3141
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3142
    StubCodeMark mark(this, "StubRoutines", name);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3143
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3144
    // Entry point, pc or function descriptor.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3145
    *entry = __ pc();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3146
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3147
    // Load *adr into c_rarg1, may fault.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3148
    *fault_pc = __ pc();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3149
    switch (size) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3150
      case 4:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3151
        // int32_t
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3152
        __ ldrw(c_rarg1, Address(c_rarg0, 0));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3153
        break;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3154
      case 8:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3155
        // int64_t
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3156
        __ ldr(c_rarg1, Address(c_rarg0, 0));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3157
        break;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3158
      default:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3159
        ShouldNotReachHere();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3160
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3161
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3162
    // return errValue or *adr
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3163
    *continuation_pc = __ pc();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3164
    __ mov(r0, c_rarg1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3165
    __ ret(lr);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3166
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3167
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3168
  /**
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3169
   *  Arguments:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3170
   *
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3171
   * Inputs:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3172
   *   c_rarg0   - int crc
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3173
   *   c_rarg1   - byte* buf
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3174
   *   c_rarg2   - int length
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3175
   *
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3176
   * Ouput:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3177
   *       rax   - int crc result
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3178
   */
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3179
  address generate_updateBytesCRC32() {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3180
    assert(UseCRC32Intrinsics, "what are we doing here?");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3181
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3182
    __ align(CodeEntryAlignment);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3183
    StubCodeMark mark(this, "StubRoutines", "updateBytesCRC32");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3184
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3185
    address start = __ pc();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3186
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3187
    const Register crc   = c_rarg0;  // crc
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3188
    const Register buf   = c_rarg1;  // source java byte array address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3189
    const Register len   = c_rarg2;  // length
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3190
    const Register table0 = c_rarg3; // crc_table address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3191
    const Register table1 = c_rarg4;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3192
    const Register table2 = c_rarg5;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3193
    const Register table3 = c_rarg6;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3194
    const Register tmp3 = c_rarg7;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3195
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3196
    BLOCK_COMMENT("Entry:");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3197
    __ enter(); // required for proper stackwalking of RuntimeStub frame
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3198
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3199
    __ kernel_crc32(crc, buf, len,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3200
              table0, table1, table2, table3, rscratch1, rscratch2, tmp3);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3201
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3202
    __ leave(); // required for proper stackwalking of RuntimeStub frame
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3203
    __ ret(lr);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3204
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3205
    return start;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3206
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3207
30225
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3208
  /**
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3209
   *  Arguments:
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3210
   *
31591
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3211
   * Inputs:
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3212
   *   c_rarg0   - int crc
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3213
   *   c_rarg1   - byte* buf
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3214
   *   c_rarg2   - int length
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3215
   *   c_rarg3   - int* table
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3216
   *
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3217
   * Ouput:
32574
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3218
   *       r0   - int crc result
31591
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3219
   */
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3220
  address generate_updateBytesCRC32C() {
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3221
    assert(UseCRC32CIntrinsics, "what are we doing here?");
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3222
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3223
    __ align(CodeEntryAlignment);
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3224
    StubCodeMark mark(this, "StubRoutines", "updateBytesCRC32C");
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3225
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3226
    address start = __ pc();
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3227
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3228
    const Register crc   = c_rarg0;  // crc
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3229
    const Register buf   = c_rarg1;  // source java byte array address
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3230
    const Register len   = c_rarg2;  // length
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3231
    const Register table0 = c_rarg3; // crc_table address
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3232
    const Register table1 = c_rarg4;
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3233
    const Register table2 = c_rarg5;
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3234
    const Register table3 = c_rarg6;
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3235
    const Register tmp3 = c_rarg7;
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3236
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3237
    BLOCK_COMMENT("Entry:");
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3238
    __ enter(); // required for proper stackwalking of RuntimeStub frame
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3239
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3240
    __ kernel_crc32c(crc, buf, len,
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3241
              table0, table1, table2, table3, rscratch1, rscratch2, tmp3);
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3242
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3243
    __ leave(); // required for proper stackwalking of RuntimeStub frame
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3244
    __ ret(lr);
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3245
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3246
    return start;
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3247
  }
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3248
33176
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3249
  /***
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3250
   *  Arguments:
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3251
   *
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3252
   *  Inputs:
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3253
   *   c_rarg0   - int   adler
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3254
   *   c_rarg1   - byte* buff
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3255
   *   c_rarg2   - int   len
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3256
   *
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3257
   * Output:
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3258
   *   c_rarg0   - int adler result
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3259
   */
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3260
  address generate_updateBytesAdler32() {
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3261
    __ align(CodeEntryAlignment);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3262
    StubCodeMark mark(this, "StubRoutines", "updateBytesAdler32");
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3263
    address start = __ pc();
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3264
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3265
    Label L_simple_by1_loop, L_nmax, L_nmax_loop, L_by16, L_by16_loop, L_by1_loop, L_do_mod, L_combine, L_by1;
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3266
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3267
    // Aliases
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3268
    Register adler  = c_rarg0;
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3269
    Register s1     = c_rarg0;
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3270
    Register s2     = c_rarg3;
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3271
    Register buff   = c_rarg1;
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3272
    Register len    = c_rarg2;
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3273
    Register nmax  = r4;
53950
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3274
    Register base  = r5;
33176
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3275
    Register count = r6;
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3276
    Register temp0 = rscratch1;
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3277
    Register temp1 = rscratch2;
53950
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3278
    FloatRegister vbytes = v0;
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3279
    FloatRegister vs1acc = v1;
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3280
    FloatRegister vs2acc = v2;
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3281
    FloatRegister vtable = v3;
33176
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3282
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3283
    // Max number of bytes we can process before having to take the mod
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3284
    // 0x15B0 is 5552 in decimal, the largest n such that 255n(n+1)/2 + (n+1)(BASE-1) <= 2^32-1
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3285
    unsigned long BASE = 0xfff1;
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3286
    unsigned long NMAX = 0x15B0;
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3287
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3288
    __ mov(base, BASE);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3289
    __ mov(nmax, NMAX);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3290
53950
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3291
    // Load accumulation coefficients for the upper 16 bits
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3292
    __ lea(temp0, ExternalAddress((address) StubRoutines::aarch64::_adler_table));
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3293
    __ ld1(vtable, __ T16B, Address(temp0));
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3294
33176
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3295
    // s1 is initialized to the lower 16 bits of adler
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3296
    // s2 is initialized to the upper 16 bits of adler
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3297
    __ ubfx(s2, adler, 16, 16);  // s2 = ((adler >> 16) & 0xffff)
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3298
    __ uxth(s1, adler);          // s1 = (adler & 0xffff)
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3299
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3300
    // The pipelined loop needs at least 16 elements for 1 iteration
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3301
    // It does check this, but it is more effective to skip to the cleanup loop
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
  3302
    __ cmp(len, (u1)16);
33176
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3303
    __ br(Assembler::HS, L_nmax);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3304
    __ cbz(len, L_combine);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3305
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3306
    __ bind(L_simple_by1_loop);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3307
    __ ldrb(temp0, Address(__ post(buff, 1)));
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3308
    __ add(s1, s1, temp0);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3309
    __ add(s2, s2, s1);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3310
    __ subs(len, len, 1);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3311
    __ br(Assembler::HI, L_simple_by1_loop);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3312
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3313
    // s1 = s1 % BASE
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3314
    __ subs(temp0, s1, base);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3315
    __ csel(s1, temp0, s1, Assembler::HS);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3316
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3317
    // s2 = s2 % BASE
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3318
    __ lsr(temp0, s2, 16);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3319
    __ lsl(temp1, temp0, 4);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3320
    __ sub(temp1, temp1, temp0);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3321
    __ add(s2, temp1, s2, ext::uxth);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3322
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3323
    __ subs(temp0, s2, base);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3324
    __ csel(s2, temp0, s2, Assembler::HS);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3325
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3326
    __ b(L_combine);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3327
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3328
    __ bind(L_nmax);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3329
    __ subs(len, len, nmax);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3330
    __ sub(count, nmax, 16);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3331
    __ br(Assembler::LO, L_by16);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3332
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3333
    __ bind(L_nmax_loop);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3334
53950
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3335
    generate_updateBytesAdler32_accum(s1, s2, buff, temp0, temp1,
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3336
                                      vbytes, vs1acc, vs2acc, vtable);
33176
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3337
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3338
    __ subs(count, count, 16);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3339
    __ br(Assembler::HS, L_nmax_loop);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3340
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3341
    // s1 = s1 % BASE
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3342
    __ lsr(temp0, s1, 16);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3343
    __ lsl(temp1, temp0, 4);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3344
    __ sub(temp1, temp1, temp0);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3345
    __ add(temp1, temp1, s1, ext::uxth);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3346
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3347
    __ lsr(temp0, temp1, 16);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3348
    __ lsl(s1, temp0, 4);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3349
    __ sub(s1, s1, temp0);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3350
    __ add(s1, s1, temp1, ext:: uxth);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3351
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3352
    __ subs(temp0, s1, base);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3353
    __ csel(s1, temp0, s1, Assembler::HS);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3354
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3355
    // s2 = s2 % BASE
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3356
    __ lsr(temp0, s2, 16);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3357
    __ lsl(temp1, temp0, 4);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3358
    __ sub(temp1, temp1, temp0);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3359
    __ add(temp1, temp1, s2, ext::uxth);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3360
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3361
    __ lsr(temp0, temp1, 16);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3362
    __ lsl(s2, temp0, 4);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3363
    __ sub(s2, s2, temp0);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3364
    __ add(s2, s2, temp1, ext:: uxth);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3365
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3366
    __ subs(temp0, s2, base);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3367
    __ csel(s2, temp0, s2, Assembler::HS);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3368
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3369
    __ subs(len, len, nmax);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3370
    __ sub(count, nmax, 16);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3371
    __ br(Assembler::HS, L_nmax_loop);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3372
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3373
    __ bind(L_by16);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3374
    __ adds(len, len, count);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3375
    __ br(Assembler::LO, L_by1);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3376
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3377
    __ bind(L_by16_loop);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3378
53950
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3379
    generate_updateBytesAdler32_accum(s1, s2, buff, temp0, temp1,
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3380
                                      vbytes, vs1acc, vs2acc, vtable);
33176
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3381
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3382
    __ subs(len, len, 16);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3383
    __ br(Assembler::HS, L_by16_loop);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3384
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3385
    __ bind(L_by1);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3386
    __ adds(len, len, 15);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3387
    __ br(Assembler::LO, L_do_mod);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3388
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3389
    __ bind(L_by1_loop);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3390
    __ ldrb(temp0, Address(__ post(buff, 1)));
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3391
    __ add(s1, temp0, s1);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3392
    __ add(s2, s2, s1);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3393
    __ subs(len, len, 1);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3394
    __ br(Assembler::HS, L_by1_loop);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3395
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3396
    __ bind(L_do_mod);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3397
    // s1 = s1 % BASE
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3398
    __ lsr(temp0, s1, 16);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3399
    __ lsl(temp1, temp0, 4);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3400
    __ sub(temp1, temp1, temp0);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3401
    __ add(temp1, temp1, s1, ext::uxth);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3402
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3403
    __ lsr(temp0, temp1, 16);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3404
    __ lsl(s1, temp0, 4);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3405
    __ sub(s1, s1, temp0);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3406
    __ add(s1, s1, temp1, ext:: uxth);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3407
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3408
    __ subs(temp0, s1, base);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3409
    __ csel(s1, temp0, s1, Assembler::HS);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3410
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3411
    // s2 = s2 % BASE
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3412
    __ lsr(temp0, s2, 16);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3413
    __ lsl(temp1, temp0, 4);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3414
    __ sub(temp1, temp1, temp0);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3415
    __ add(temp1, temp1, s2, ext::uxth);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3416
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3417
    __ lsr(temp0, temp1, 16);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3418
    __ lsl(s2, temp0, 4);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3419
    __ sub(s2, s2, temp0);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3420
    __ add(s2, s2, temp1, ext:: uxth);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3421
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3422
    __ subs(temp0, s2, base);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3423
    __ csel(s2, temp0, s2, Assembler::HS);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3424
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3425
    // Combine lower bits and higher bits
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3426
    __ bind(L_combine);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3427
    __ orr(s1, s1, s2, Assembler::LSL, 16); // adler = s1 | (s2 << 16)
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3428
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3429
    __ ret(lr);
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3430
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3431
    return start;
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3432
  }
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  3433
53950
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3434
  void generate_updateBytesAdler32_accum(Register s1, Register s2, Register buff,
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3435
          Register temp0, Register temp1, FloatRegister vbytes,
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3436
          FloatRegister vs1acc, FloatRegister vs2acc, FloatRegister vtable) {
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3437
    // Below is a vectorized implementation of updating s1 and s2 for 16 bytes.
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3438
    // We use b1, b2, ..., b16 to denote the 16 bytes loaded in each iteration.
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3439
    // In non-vectorized code, we update s1 and s2 as:
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3440
    //   s1 <- s1 + b1
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3441
    //   s2 <- s2 + s1
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3442
    //   s1 <- s1 + b2
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3443
    //   s2 <- s2 + b1
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3444
    //   ...
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3445
    //   s1 <- s1 + b16
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3446
    //   s2 <- s2 + s1
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3447
    // Putting above assignments together, we have:
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3448
    //   s1_new = s1 + b1 + b2 + ... + b16
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3449
    //   s2_new = s2 + (s1 + b1) + (s1 + b1 + b2) + ... + (s1 + b1 + b2 + ... + b16)
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3450
    //          = s2 + s1 * 16 + (b1 * 16 + b2 * 15 + ... + b16 * 1)
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3451
    //          = s2 + s1 * 16 + (b1, b2, ... b16) dot (16, 15, ... 1)
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3452
    __ ld1(vbytes, __ T16B, Address(__ post(buff, 16)));
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3453
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3454
    // s2 = s2 + s1 * 16
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3455
    __ add(s2, s2, s1, Assembler::LSL, 4);
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3456
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3457
    // vs1acc = b1 + b2 + b3 + ... + b16
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3458
    // vs2acc = (b1 * 16) + (b2 * 15) + (b3 * 14) + ... + (b16 * 1)
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3459
    __ umullv(vs2acc, __ T8B, vtable, vbytes);
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3460
    __ umlalv(vs2acc, __ T16B, vtable, vbytes);
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3461
    __ uaddlv(vs1acc, __ T16B, vbytes);
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3462
    __ uaddlv(vs2acc, __ T8H, vs2acc);
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3463
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3464
    // s1 = s1 + vs1acc, s2 = s2 + vs2acc
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3465
    __ fmovd(temp0, vs1acc);
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3466
    __ fmovd(temp1, vs2acc);
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3467
    __ add(s1, s1, temp0);
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3468
    __ add(s2, s2, temp1);
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3469
  }
cf47efcf7771 8216259: AArch64: Vectorize Adler32 intrinsics
pli
parents: 53777
diff changeset
  3470
31591
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3471
  /**
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3472
   *  Arguments:
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 30553
diff changeset
  3473
   *
30225
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3474
   *  Input:
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3475
   *    c_rarg0   - x address
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3476
   *    c_rarg1   - x length
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3477
   *    c_rarg2   - y address
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3478
   *    c_rarg3   - y lenth
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3479
   *    c_rarg4   - z address
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3480
   *    c_rarg5   - z length
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3481
   */
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3482
  address generate_multiplyToLen() {
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3483
    __ align(CodeEntryAlignment);
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3484
    StubCodeMark mark(this, "StubRoutines", "multiplyToLen");
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3485
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3486
    address start = __ pc();
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3487
    const Register x     = r0;
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3488
    const Register xlen  = r1;
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3489
    const Register y     = r2;
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3490
    const Register ylen  = r3;
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3491
    const Register z     = r4;
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3492
    const Register zlen  = r5;
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3493
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3494
    const Register tmp1  = r10;
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3495
    const Register tmp2  = r11;
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3496
    const Register tmp3  = r12;
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3497
    const Register tmp4  = r13;
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3498
    const Register tmp5  = r14;
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3499
    const Register tmp6  = r15;
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3500
    const Register tmp7  = r16;
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3501
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3502
    BLOCK_COMMENT("Entry:");
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3503
    __ enter(); // required for proper stackwalking of RuntimeStub frame
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3504
    __ multiply_to_len(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7);
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3505
    __ leave(); // required for proper stackwalking of RuntimeStub frame
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3506
    __ ret(lr);
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3507
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3508
    return start;
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  3509
  }
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  3510
47571
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3511
  address generate_squareToLen() {
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3512
    // squareToLen algorithm for sizes 1..127 described in java code works
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3513
    // faster than multiply_to_len on some CPUs and slower on others, but
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3514
    // multiply_to_len shows a bit better overall results
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3515
    __ align(CodeEntryAlignment);
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3516
    StubCodeMark mark(this, "StubRoutines", "squareToLen");
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3517
    address start = __ pc();
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3518
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3519
    const Register x     = r0;
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3520
    const Register xlen  = r1;
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3521
    const Register z     = r2;
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3522
    const Register zlen  = r3;
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3523
    const Register y     = r4; // == x
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3524
    const Register ylen  = r5; // == xlen
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3525
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3526
    const Register tmp1  = r10;
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3527
    const Register tmp2  = r11;
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3528
    const Register tmp3  = r12;
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3529
    const Register tmp4  = r13;
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3530
    const Register tmp5  = r14;
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3531
    const Register tmp6  = r15;
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3532
    const Register tmp7  = r16;
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3533
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3534
    RegSet spilled_regs = RegSet::of(y, ylen);
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3535
    BLOCK_COMMENT("Entry:");
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3536
    __ enter();
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3537
    __ push(spilled_regs, sp);
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3538
    __ mov(y, x);
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3539
    __ mov(ylen, xlen);
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3540
    __ multiply_to_len(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7);
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3541
    __ pop(spilled_regs, sp);
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3542
    __ leave();
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3543
    __ ret(lr);
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3544
    return start;
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3545
  }
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3546
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3547
  address generate_mulAdd() {
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3548
    __ align(CodeEntryAlignment);
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3549
    StubCodeMark mark(this, "StubRoutines", "mulAdd");
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3550
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3551
    address start = __ pc();
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3552
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3553
    const Register out     = r0;
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3554
    const Register in      = r1;
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3555
    const Register offset  = r2;
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3556
    const Register len     = r3;
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3557
    const Register k       = r4;
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3558
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3559
    BLOCK_COMMENT("Entry:");
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3560
    __ enter();
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3561
    __ mul_add(out, in, offset, len, k);
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3562
    __ leave();
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3563
    __ ret(lr);
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3564
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3565
    return start;
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3566
  }
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  3567
32574
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3568
  void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3569
                      FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3570
                      FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3, FloatRegister tmp4) {
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3571
    // Karatsuba multiplication performs a 128*128 -> 256-bit
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3572
    // multiplication in three 128-bit multiplications and a few
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3573
    // additions.
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3574
    //
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3575
    // (C1:C0) = A1*B1, (D1:D0) = A0*B0, (E1:E0) = (A0+A1)(B0+B1)
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3576
    // (A1:A0)(B1:B0) = C1:(C0+C1+D1+E1):(D1+C0+D0+E0):D0
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3577
    //
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3578
    // Inputs:
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3579
    //
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3580
    // A0 in a.d[0]     (subkey)
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3581
    // A1 in a.d[1]
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3582
    // (A1+A0) in a1_xor_a0.d[0]
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3583
    //
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3584
    // B0 in b.d[0]     (state)
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3585
    // B1 in b.d[1]
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3586
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3587
    __ ext(tmp1, __ T16B, b, b, 0x08);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3588
    __ pmull2(result_hi, __ T1Q, b, a, __ T2D);  // A1*B1
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3589
    __ eor(tmp1, __ T16B, tmp1, b);            // (B1+B0)
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3590
    __ pmull(result_lo,  __ T1Q, b, a, __ T1D);  // A0*B0
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3591
    __ pmull(tmp2, __ T1Q, tmp1, a1_xor_a0, __ T1D); // (A1+A0)(B1+B0)
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3592
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3593
    __ ext(tmp4, __ T16B, result_lo, result_hi, 0x08);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3594
    __ eor(tmp3, __ T16B, result_hi, result_lo); // A1*B1+A0*B0
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3595
    __ eor(tmp2, __ T16B, tmp2, tmp4);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3596
    __ eor(tmp2, __ T16B, tmp2, tmp3);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3597
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3598
    // Register pair <result_hi:result_lo> holds the result of carry-less multiplication
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3599
    __ ins(result_hi, __ D, tmp2, 0, 1);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3600
    __ ins(result_lo, __ D, tmp2, 1, 0);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3601
  }
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3602
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3603
  void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3604
                    FloatRegister p, FloatRegister z, FloatRegister t1) {
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3605
    const FloatRegister t0 = result;
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3606
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3607
    // The GCM field polynomial f is z^128 + p(z), where p =
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3608
    // z^7+z^2+z+1.
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3609
    //
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3610
    //    z^128 === -p(z)  (mod (z^128 + p(z)))
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3611
    //
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3612
    // so, given that the product we're reducing is
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3613
    //    a == lo + hi * z^128
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3614
    // substituting,
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3615
    //      === lo - hi * p(z)  (mod (z^128 + p(z)))
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3616
    //
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3617
    // we reduce by multiplying hi by p(z) and subtracting the result
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3618
    // from (i.e. XORing it with) lo.  Because p has no nonzero high
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3619
    // bits we can do this with two 64-bit multiplications, lo*p and
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3620
    // hi*p.
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3621
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3622
    __ pmull2(t0, __ T1Q, hi, p, __ T2D);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3623
    __ ext(t1, __ T16B, t0, z, 8);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3624
    __ eor(hi, __ T16B, hi, t1);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3625
    __ ext(t1, __ T16B, z, t0, 8);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3626
    __ eor(lo, __ T16B, lo, t1);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3627
    __ pmull(t0, __ T1Q, hi, p, __ T1D);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3628
    __ eor(result, __ T16B, lo, t0);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3629
  }
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  3630
46814
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3631
  address generate_has_negatives(address &has_negatives_long) {
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
  3632
    const u1 large_loop_size = 64;
46814
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3633
    const uint64_t UPPER_BIT_MASK=0x8080808080808080;
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3634
    int dcache_line = VM_Version::dcache_line_size();
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3635
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3636
    Register ary1 = r1, len = r2, result = r0;
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3637
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3638
    __ align(CodeEntryAlignment);
52977
2e4903f83295 8205421: AARCH64: StubCodeMark should be placed after alignment
dpochepk
parents: 52927
diff changeset
  3639
2e4903f83295 8205421: AARCH64: StubCodeMark should be placed after alignment
dpochepk
parents: 52927
diff changeset
  3640
    StubCodeMark mark(this, "StubRoutines", "has_negatives");
2e4903f83295 8205421: AARCH64: StubCodeMark should be placed after alignment
dpochepk
parents: 52927
diff changeset
  3641
46814
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3642
    address entry = __ pc();
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3643
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3644
    __ enter();
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3645
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3646
  Label RET_TRUE, RET_TRUE_NO_POP, RET_FALSE, ALIGNED, LOOP16, CHECK_16, DONE,
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3647
        LARGE_LOOP, POST_LOOP16, LEN_OVER_15, LEN_OVER_8, POST_LOOP16_LOAD_TAIL;
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3648
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
  3649
  __ cmp(len, (u1)15);
46814
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3650
  __ br(Assembler::GT, LEN_OVER_15);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3651
  // The only case when execution falls into this code is when pointer is near
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3652
  // the end of memory page and we have to avoid reading next page
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3653
  __ add(ary1, ary1, len);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3654
  __ subs(len, len, 8);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3655
  __ br(Assembler::GT, LEN_OVER_8);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3656
  __ ldr(rscratch2, Address(ary1, -8));
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3657
  __ sub(rscratch1, zr, len, __ LSL, 3);  // LSL 3 is to get bits from bytes.
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3658
  __ lsrv(rscratch2, rscratch2, rscratch1);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3659
  __ tst(rscratch2, UPPER_BIT_MASK);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3660
  __ cset(result, Assembler::NE);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3661
  __ leave();
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3662
  __ ret(lr);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3663
  __ bind(LEN_OVER_8);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3664
  __ ldp(rscratch1, rscratch2, Address(ary1, -16));
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3665
  __ sub(len, len, 8); // no data dep., then sub can be executed while loading
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3666
  __ tst(rscratch2, UPPER_BIT_MASK);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3667
  __ br(Assembler::NE, RET_TRUE_NO_POP);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3668
  __ sub(rscratch2, zr, len, __ LSL, 3); // LSL 3 is to get bits from bytes
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3669
  __ lsrv(rscratch1, rscratch1, rscratch2);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3670
  __ tst(rscratch1, UPPER_BIT_MASK);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3671
  __ cset(result, Assembler::NE);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3672
  __ leave();
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3673
  __ ret(lr);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3674
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3675
  Register tmp1 = r3, tmp2 = r4, tmp3 = r5, tmp4 = r6, tmp5 = r7, tmp6 = r10;
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3676
  const RegSet spilled_regs = RegSet::range(tmp1, tmp5) + tmp6;
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3677
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3678
  has_negatives_long = __ pc(); // 2nd entry point
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3679
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3680
  __ enter();
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3681
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3682
  __ bind(LEN_OVER_15);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3683
    __ push(spilled_regs, sp);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3684
    __ andr(rscratch2, ary1, 15); // check pointer for 16-byte alignment
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3685
    __ cbz(rscratch2, ALIGNED);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3686
    __ ldp(tmp6, tmp1, Address(ary1));
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3687
    __ mov(tmp5, 16);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3688
    __ sub(rscratch1, tmp5, rscratch2); // amount of bytes until aligned address
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3689
    __ add(ary1, ary1, rscratch1);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3690
    __ sub(len, len, rscratch1);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3691
    __ orr(tmp6, tmp6, tmp1);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3692
    __ tst(tmp6, UPPER_BIT_MASK);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3693
    __ br(Assembler::NE, RET_TRUE);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3694
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3695
  __ bind(ALIGNED);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3696
    __ cmp(len, large_loop_size);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3697
    __ br(Assembler::LT, CHECK_16);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3698
    // Perform 16-byte load as early return in pre-loop to handle situation
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3699
    // when initially aligned large array has negative values at starting bytes,
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3700
    // so LARGE_LOOP would do 4 reads instead of 1 (in worst case), which is
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3701
    // slower. Cases with negative bytes further ahead won't be affected that
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3702
    // much. In fact, it'll be faster due to early loads, less instructions and
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3703
    // less branches in LARGE_LOOP.
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3704
    __ ldp(tmp6, tmp1, Address(__ post(ary1, 16)));
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3705
    __ sub(len, len, 16);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3706
    __ orr(tmp6, tmp6, tmp1);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3707
    __ tst(tmp6, UPPER_BIT_MASK);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3708
    __ br(Assembler::NE, RET_TRUE);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3709
    __ cmp(len, large_loop_size);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3710
    __ br(Assembler::LT, CHECK_16);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3711
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3712
    if (SoftwarePrefetchHintDistance >= 0
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3713
        && SoftwarePrefetchHintDistance >= dcache_line) {
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3714
      // initial prefetch
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3715
      __ prfm(Address(ary1, SoftwarePrefetchHintDistance - dcache_line));
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3716
    }
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3717
  __ bind(LARGE_LOOP);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3718
    if (SoftwarePrefetchHintDistance >= 0) {
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3719
      __ prfm(Address(ary1, SoftwarePrefetchHintDistance));
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3720
    }
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3721
    // Issue load instructions first, since it can save few CPU/MEM cycles, also
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3722
    // instead of 4 triples of "orr(...), addr(...);cbnz(...);" (for each ldp)
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3723
    // better generate 7 * orr(...) + 1 andr(...) + 1 cbnz(...) which saves 3
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3724
    // instructions per cycle and have less branches, but this approach disables
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3725
    // early return, thus, all 64 bytes are loaded and checked every time.
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3726
    __ ldp(tmp2, tmp3, Address(ary1));
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3727
    __ ldp(tmp4, tmp5, Address(ary1, 16));
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3728
    __ ldp(rscratch1, rscratch2, Address(ary1, 32));
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3729
    __ ldp(tmp6, tmp1, Address(ary1, 48));
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3730
    __ add(ary1, ary1, large_loop_size);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3731
    __ sub(len, len, large_loop_size);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3732
    __ orr(tmp2, tmp2, tmp3);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3733
    __ orr(tmp4, tmp4, tmp5);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3734
    __ orr(rscratch1, rscratch1, rscratch2);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3735
    __ orr(tmp6, tmp6, tmp1);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3736
    __ orr(tmp2, tmp2, tmp4);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3737
    __ orr(rscratch1, rscratch1, tmp6);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3738
    __ orr(tmp2, tmp2, rscratch1);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3739
    __ tst(tmp2, UPPER_BIT_MASK);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3740
    __ br(Assembler::NE, RET_TRUE);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3741
    __ cmp(len, large_loop_size);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3742
    __ br(Assembler::GE, LARGE_LOOP);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3743
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3744
  __ bind(CHECK_16); // small 16-byte load pre-loop
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
  3745
    __ cmp(len, (u1)16);
46814
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3746
    __ br(Assembler::LT, POST_LOOP16);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3747
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3748
  __ bind(LOOP16); // small 16-byte load loop
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3749
    __ ldp(tmp2, tmp3, Address(__ post(ary1, 16)));
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3750
    __ sub(len, len, 16);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3751
    __ orr(tmp2, tmp2, tmp3);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3752
    __ tst(tmp2, UPPER_BIT_MASK);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3753
    __ br(Assembler::NE, RET_TRUE);
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
  3754
    __ cmp(len, (u1)16);
46814
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3755
    __ br(Assembler::GE, LOOP16); // 16-byte load loop end
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3756
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3757
  __ bind(POST_LOOP16); // 16-byte aligned, so we can read unconditionally
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
  3758
    __ cmp(len, (u1)8);
46814
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3759
    __ br(Assembler::LE, POST_LOOP16_LOAD_TAIL);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3760
    __ ldr(tmp3, Address(__ post(ary1, 8)));
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3761
    __ sub(len, len, 8);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3762
    __ tst(tmp3, UPPER_BIT_MASK);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3763
    __ br(Assembler::NE, RET_TRUE);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3764
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3765
  __ bind(POST_LOOP16_LOAD_TAIL);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3766
    __ cbz(len, RET_FALSE); // Can't shift left by 64 when len==0
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3767
    __ ldr(tmp1, Address(ary1));
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3768
    __ mov(tmp2, 64);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3769
    __ sub(tmp4, tmp2, len, __ LSL, 3);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3770
    __ lslv(tmp1, tmp1, tmp4);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3771
    __ tst(tmp1, UPPER_BIT_MASK);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3772
    __ br(Assembler::NE, RET_TRUE);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3773
    // Fallthrough
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3774
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3775
  __ bind(RET_FALSE);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3776
    __ pop(spilled_regs, sp);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3777
    __ leave();
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3778
    __ mov(result, zr);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3779
    __ ret(lr);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3780
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3781
  __ bind(RET_TRUE);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3782
    __ pop(spilled_regs, sp);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3783
  __ bind(RET_TRUE_NO_POP);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3784
    __ leave();
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3785
    __ mov(result, 1);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3786
    __ ret(lr);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3787
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3788
  __ bind(DONE);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3789
    __ pop(spilled_regs, sp);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3790
    __ leave();
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3791
    __ ret(lr);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3792
    return entry;
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  3793
  }
49724
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3794
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3795
  void generate_large_array_equals_loop_nonsimd(int loopThreshold,
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3796
        bool usePrefetch, Label &NOT_EQUAL) {
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3797
    Register a1 = r1, a2 = r2, result = r0, cnt1 = r10, tmp1 = rscratch1,
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3798
        tmp2 = rscratch2, tmp3 = r3, tmp4 = r4, tmp5 = r5, tmp6 = r11,
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3799
        tmp7 = r12, tmp8 = r13;
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3800
    Label LOOP;
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3801
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3802
    __ ldp(tmp1, tmp3, Address(__ post(a1, 2 * wordSize)));
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3803
    __ ldp(tmp2, tmp4, Address(__ post(a2, 2 * wordSize)));
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3804
    __ bind(LOOP);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3805
    if (usePrefetch) {
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3806
      __ prfm(Address(a1, SoftwarePrefetchHintDistance));
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3807
      __ prfm(Address(a2, SoftwarePrefetchHintDistance));
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3808
    }
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3809
    __ ldp(tmp5, tmp7, Address(__ post(a1, 2 * wordSize)));
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3810
    __ eor(tmp1, tmp1, tmp2);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3811
    __ eor(tmp3, tmp3, tmp4);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3812
    __ ldp(tmp6, tmp8, Address(__ post(a2, 2 * wordSize)));
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3813
    __ orr(tmp1, tmp1, tmp3);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3814
    __ cbnz(tmp1, NOT_EQUAL);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3815
    __ ldp(tmp1, tmp3, Address(__ post(a1, 2 * wordSize)));
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3816
    __ eor(tmp5, tmp5, tmp6);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3817
    __ eor(tmp7, tmp7, tmp8);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3818
    __ ldp(tmp2, tmp4, Address(__ post(a2, 2 * wordSize)));
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3819
    __ orr(tmp5, tmp5, tmp7);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3820
    __ cbnz(tmp5, NOT_EQUAL);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3821
    __ ldp(tmp5, tmp7, Address(__ post(a1, 2 * wordSize)));
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3822
    __ eor(tmp1, tmp1, tmp2);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3823
    __ eor(tmp3, tmp3, tmp4);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3824
    __ ldp(tmp6, tmp8, Address(__ post(a2, 2 * wordSize)));
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3825
    __ orr(tmp1, tmp1, tmp3);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3826
    __ cbnz(tmp1, NOT_EQUAL);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3827
    __ ldp(tmp1, tmp3, Address(__ post(a1, 2 * wordSize)));
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3828
    __ eor(tmp5, tmp5, tmp6);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3829
    __ sub(cnt1, cnt1, 8 * wordSize);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3830
    __ eor(tmp7, tmp7, tmp8);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3831
    __ ldp(tmp2, tmp4, Address(__ post(a2, 2 * wordSize)));
50242
9a87afc49148 8203041: AArch64: fix overflow in immediate cmp/cmn instruction
fyang
parents: 50179
diff changeset
  3832
    // tmp6 is not used. MacroAssembler::subs is used here (rather than
9a87afc49148 8203041: AArch64: fix overflow in immediate cmp/cmn instruction
fyang
parents: 50179
diff changeset
  3833
    // cmp) because subs allows an unlimited range of immediate operand.
9a87afc49148 8203041: AArch64: fix overflow in immediate cmp/cmn instruction
fyang
parents: 50179
diff changeset
  3834
    __ subs(tmp6, cnt1, loopThreshold);
49724
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3835
    __ orr(tmp5, tmp5, tmp7);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3836
    __ cbnz(tmp5, NOT_EQUAL);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3837
    __ br(__ GE, LOOP);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3838
    // post-loop
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3839
    __ eor(tmp1, tmp1, tmp2);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3840
    __ eor(tmp3, tmp3, tmp4);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3841
    __ orr(tmp1, tmp1, tmp3);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3842
    __ sub(cnt1, cnt1, 2 * wordSize);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3843
    __ cbnz(tmp1, NOT_EQUAL);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3844
  }
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3845
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3846
  void generate_large_array_equals_loop_simd(int loopThreshold,
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3847
        bool usePrefetch, Label &NOT_EQUAL) {
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3848
    Register a1 = r1, a2 = r2, result = r0, cnt1 = r10, tmp1 = rscratch1,
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3849
        tmp2 = rscratch2;
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3850
    Label LOOP;
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3851
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3852
    __ bind(LOOP);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3853
    if (usePrefetch) {
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3854
      __ prfm(Address(a1, SoftwarePrefetchHintDistance));
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3855
      __ prfm(Address(a2, SoftwarePrefetchHintDistance));
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3856
    }
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3857
    __ ld1(v0, v1, v2, v3, __ T2D, Address(__ post(a1, 4 * 2 * wordSize)));
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3858
    __ sub(cnt1, cnt1, 8 * wordSize);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3859
    __ ld1(v4, v5, v6, v7, __ T2D, Address(__ post(a2, 4 * 2 * wordSize)));
50242
9a87afc49148 8203041: AArch64: fix overflow in immediate cmp/cmn instruction
fyang
parents: 50179
diff changeset
  3860
    __ subs(tmp1, cnt1, loopThreshold);
49724
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3861
    __ eor(v0, __ T16B, v0, v4);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3862
    __ eor(v1, __ T16B, v1, v5);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3863
    __ eor(v2, __ T16B, v2, v6);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3864
    __ eor(v3, __ T16B, v3, v7);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3865
    __ orr(v0, __ T16B, v0, v1);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3866
    __ orr(v1, __ T16B, v2, v3);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3867
    __ orr(v0, __ T16B, v0, v1);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3868
    __ umov(tmp1, v0, __ D, 0);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3869
    __ umov(tmp2, v0, __ D, 1);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3870
    __ orr(tmp1, tmp1, tmp2);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3871
    __ cbnz(tmp1, NOT_EQUAL);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3872
    __ br(__ GE, LOOP);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3873
  }
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3874
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3875
  // a1 = r1 - array1 address
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3876
  // a2 = r2 - array2 address
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3877
  // result = r0 - return value. Already contains "false"
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3878
  // cnt1 = r10 - amount of elements left to check, reduced by wordSize
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3879
  // r3-r5 are reserved temporary registers
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3880
  address generate_large_array_equals() {
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3881
    Register a1 = r1, a2 = r2, result = r0, cnt1 = r10, tmp1 = rscratch1,
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3882
        tmp2 = rscratch2, tmp3 = r3, tmp4 = r4, tmp5 = r5, tmp6 = r11,
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3883
        tmp7 = r12, tmp8 = r13;
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3884
    Label TAIL, NOT_EQUAL, EQUAL, NOT_EQUAL_NO_POP, NO_PREFETCH_LARGE_LOOP,
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3885
        SMALL_LOOP, POST_LOOP;
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3886
    const int PRE_LOOP_SIZE = UseSIMDForArrayEquals ? 0 : 16;
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3887
    // calculate if at least 32 prefetched bytes are used
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3888
    int prefetchLoopThreshold = SoftwarePrefetchHintDistance + 32;
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3889
    int nonPrefetchLoopThreshold = (64 + PRE_LOOP_SIZE);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3890
    RegSet spilled_regs = RegSet::range(tmp6, tmp8);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3891
    assert_different_registers(a1, a2, result, cnt1, tmp1, tmp2, tmp3, tmp4,
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3892
        tmp5, tmp6, tmp7, tmp8);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3893
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3894
    __ align(CodeEntryAlignment);
52977
2e4903f83295 8205421: AARCH64: StubCodeMark should be placed after alignment
dpochepk
parents: 52927
diff changeset
  3895
2e4903f83295 8205421: AARCH64: StubCodeMark should be placed after alignment
dpochepk
parents: 52927
diff changeset
  3896
    StubCodeMark mark(this, "StubRoutines", "large_array_equals");
2e4903f83295 8205421: AARCH64: StubCodeMark should be placed after alignment
dpochepk
parents: 52927
diff changeset
  3897
49724
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3898
    address entry = __ pc();
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3899
    __ enter();
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3900
    __ sub(cnt1, cnt1, wordSize);  // first 8 bytes were loaded outside of stub
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3901
    // also advance pointers to use post-increment instead of pre-increment
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3902
    __ add(a1, a1, wordSize);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3903
    __ add(a2, a2, wordSize);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3904
    if (AvoidUnalignedAccesses) {
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3905
      // both implementations (SIMD/nonSIMD) are using relatively large load
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3906
      // instructions (ld1/ldp), which has huge penalty (up to x2 exec time)
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3907
      // on some CPUs in case of address is not at least 16-byte aligned.
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3908
      // Arrays are 8-byte aligned currently, so, we can make additional 8-byte
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3909
      // load if needed at least for 1st address and make if 16-byte aligned.
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3910
      Label ALIGNED16;
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3911
      __ tbz(a1, 3, ALIGNED16);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3912
      __ ldr(tmp1, Address(__ post(a1, wordSize)));
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3913
      __ ldr(tmp2, Address(__ post(a2, wordSize)));
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3914
      __ sub(cnt1, cnt1, wordSize);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3915
      __ eor(tmp1, tmp1, tmp2);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3916
      __ cbnz(tmp1, NOT_EQUAL_NO_POP);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3917
      __ bind(ALIGNED16);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3918
    }
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3919
    if (UseSIMDForArrayEquals) {
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3920
      if (SoftwarePrefetchHintDistance >= 0) {
50242
9a87afc49148 8203041: AArch64: fix overflow in immediate cmp/cmn instruction
fyang
parents: 50179
diff changeset
  3921
        __ subs(tmp1, cnt1, prefetchLoopThreshold);
49724
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3922
        __ br(__ LE, NO_PREFETCH_LARGE_LOOP);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3923
        generate_large_array_equals_loop_simd(prefetchLoopThreshold,
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3924
            /* prfm = */ true, NOT_EQUAL);
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
  3925
        __ subs(zr, cnt1, nonPrefetchLoopThreshold);
49724
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3926
        __ br(__ LT, TAIL);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3927
      }
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3928
      __ bind(NO_PREFETCH_LARGE_LOOP);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3929
      generate_large_array_equals_loop_simd(nonPrefetchLoopThreshold,
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3930
          /* prfm = */ false, NOT_EQUAL);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3931
    } else {
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3932
      __ push(spilled_regs, sp);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3933
      if (SoftwarePrefetchHintDistance >= 0) {
50242
9a87afc49148 8203041: AArch64: fix overflow in immediate cmp/cmn instruction
fyang
parents: 50179
diff changeset
  3934
        __ subs(tmp1, cnt1, prefetchLoopThreshold);
49724
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3935
        __ br(__ LE, NO_PREFETCH_LARGE_LOOP);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3936
        generate_large_array_equals_loop_nonsimd(prefetchLoopThreshold,
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3937
            /* prfm = */ true, NOT_EQUAL);
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
  3938
        __ subs(zr, cnt1, nonPrefetchLoopThreshold);
49724
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3939
        __ br(__ LT, TAIL);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3940
      }
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3941
      __ bind(NO_PREFETCH_LARGE_LOOP);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3942
      generate_large_array_equals_loop_nonsimd(nonPrefetchLoopThreshold,
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3943
          /* prfm = */ false, NOT_EQUAL);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3944
    }
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3945
    __ bind(TAIL);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3946
      __ cbz(cnt1, EQUAL);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3947
      __ subs(cnt1, cnt1, wordSize);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3948
      __ br(__ LE, POST_LOOP);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3949
    __ bind(SMALL_LOOP);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3950
      __ ldr(tmp1, Address(__ post(a1, wordSize)));
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3951
      __ ldr(tmp2, Address(__ post(a2, wordSize)));
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3952
      __ subs(cnt1, cnt1, wordSize);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3953
      __ eor(tmp1, tmp1, tmp2);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3954
      __ cbnz(tmp1, NOT_EQUAL);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3955
      __ br(__ GT, SMALL_LOOP);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3956
    __ bind(POST_LOOP);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3957
      __ ldr(tmp1, Address(a1, cnt1));
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3958
      __ ldr(tmp2, Address(a2, cnt1));
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3959
      __ eor(tmp1, tmp1, tmp2);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3960
      __ cbnz(tmp1, NOT_EQUAL);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3961
    __ bind(EQUAL);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3962
      __ mov(result, true);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3963
    __ bind(NOT_EQUAL);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3964
      if (!UseSIMDForArrayEquals) {
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3965
        __ pop(spilled_regs, sp);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3966
      }
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3967
    __ bind(NOT_EQUAL_NO_POP);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3968
    __ leave();
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3969
    __ ret(lr);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3970
    return entry;
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3971
  }
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3972
50754
ccb8aa083958 8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents: 50753
diff changeset
  3973
  address generate_dsin_dcos(bool isCos) {
ccb8aa083958 8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents: 50753
diff changeset
  3974
    __ align(CodeEntryAlignment);
ccb8aa083958 8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents: 50753
diff changeset
  3975
    StubCodeMark mark(this, "StubRoutines", isCos ? "libmDcos" : "libmDsin");
ccb8aa083958 8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents: 50753
diff changeset
  3976
    address start = __ pc();
ccb8aa083958 8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents: 50753
diff changeset
  3977
    __ generate_dsin_dcos(isCos, (address)StubRoutines::aarch64::_npio2_hw,
ccb8aa083958 8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents: 50753
diff changeset
  3978
        (address)StubRoutines::aarch64::_two_over_pi,
ccb8aa083958 8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents: 50753
diff changeset
  3979
        (address)StubRoutines::aarch64::_pio2,
ccb8aa083958 8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents: 50753
diff changeset
  3980
        (address)StubRoutines::aarch64::_dsin_coef,
ccb8aa083958 8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents: 50753
diff changeset
  3981
        (address)StubRoutines::aarch64::_dcos_coef);
ccb8aa083958 8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents: 50753
diff changeset
  3982
    return start;
ccb8aa083958 8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents: 50753
diff changeset
  3983
  }
ccb8aa083958 8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents: 50753
diff changeset
  3984
50753
4449b45900f1 8196402: AARCH64: create intrinsic for Math.log
dpochepk
parents: 50728
diff changeset
  3985
  address generate_dlog() {
4449b45900f1 8196402: AARCH64: create intrinsic for Math.log
dpochepk
parents: 50728
diff changeset
  3986
    __ align(CodeEntryAlignment);
4449b45900f1 8196402: AARCH64: create intrinsic for Math.log
dpochepk
parents: 50728
diff changeset
  3987
    StubCodeMark mark(this, "StubRoutines", "dlog");
4449b45900f1 8196402: AARCH64: create intrinsic for Math.log
dpochepk
parents: 50728
diff changeset
  3988
    address entry = __ pc();
4449b45900f1 8196402: AARCH64: create intrinsic for Math.log
dpochepk
parents: 50728
diff changeset
  3989
    FloatRegister vtmp0 = v0, vtmp1 = v1, vtmp2 = v2, vtmp3 = v3, vtmp4 = v4,
4449b45900f1 8196402: AARCH64: create intrinsic for Math.log
dpochepk
parents: 50728
diff changeset
  3990
        vtmp5 = v5, tmpC1 = v16, tmpC2 = v17, tmpC3 = v18, tmpC4 = v19;
4449b45900f1 8196402: AARCH64: create intrinsic for Math.log
dpochepk
parents: 50728
diff changeset
  3991
    Register tmp1 = r0, tmp2 = r1, tmp3 = r2, tmp4 = r3, tmp5 = r4;
4449b45900f1 8196402: AARCH64: create intrinsic for Math.log
dpochepk
parents: 50728
diff changeset
  3992
    __ fast_log(vtmp0, vtmp1, vtmp2, vtmp3, vtmp4, vtmp5, tmpC1, tmpC2, tmpC3,
4449b45900f1 8196402: AARCH64: create intrinsic for Math.log
dpochepk
parents: 50728
diff changeset
  3993
        tmpC4, tmp1, tmp2, tmp3, tmp4, tmp5);
4449b45900f1 8196402: AARCH64: create intrinsic for Math.log
dpochepk
parents: 50728
diff changeset
  3994
    return entry;
4449b45900f1 8196402: AARCH64: create intrinsic for Math.log
dpochepk
parents: 50728
diff changeset
  3995
  }
49724
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  3996
50756
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  3997
  // code for comparing 16 bytes of strings with same encoding
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  3998
  void compare_string_16_bytes_same(Label &DIFF1, Label &DIFF2) {
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  3999
    Register result = r0, str1 = r1, cnt1 = r2, str2 = r3, tmp1 = r10, tmp2 = r11;
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4000
    __ ldr(rscratch1, Address(__ post(str1, 8)));
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4001
    __ eor(rscratch2, tmp1, tmp2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4002
    __ ldr(cnt1, Address(__ post(str2, 8)));
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4003
    __ cbnz(rscratch2, DIFF1);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4004
    __ ldr(tmp1, Address(__ post(str1, 8)));
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4005
    __ eor(rscratch2, rscratch1, cnt1);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4006
    __ ldr(tmp2, Address(__ post(str2, 8)));
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4007
    __ cbnz(rscratch2, DIFF2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4008
  }
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4009
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4010
  // code for comparing 16 characters of strings with Latin1 and Utf16 encoding
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4011
  void compare_string_16_x_LU(Register tmpL, Register tmpU, Label &DIFF1,
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4012
      Label &DIFF2) {
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4013
    Register cnt1 = r2, tmp1 = r10, tmp2 = r11, tmp3 = r12;
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4014
    FloatRegister vtmp = v1, vtmpZ = v0, vtmp3 = v2;
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4015
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4016
    __ ldrq(vtmp, Address(__ post(tmp2, 16)));
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4017
    __ ldr(tmpU, Address(__ post(cnt1, 8)));
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4018
    __ zip1(vtmp3, __ T16B, vtmp, vtmpZ);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4019
    // now we have 32 bytes of characters (converted to U) in vtmp:vtmp3
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4020
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4021
    __ fmovd(tmpL, vtmp3);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4022
    __ eor(rscratch2, tmp3, tmpL);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4023
    __ cbnz(rscratch2, DIFF2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4024
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4025
    __ ldr(tmp3, Address(__ post(cnt1, 8)));
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4026
    __ umov(tmpL, vtmp3, __ D, 1);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4027
    __ eor(rscratch2, tmpU, tmpL);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4028
    __ cbnz(rscratch2, DIFF1);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4029
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4030
    __ zip2(vtmp, __ T16B, vtmp, vtmpZ);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4031
    __ ldr(tmpU, Address(__ post(cnt1, 8)));
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4032
    __ fmovd(tmpL, vtmp);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4033
    __ eor(rscratch2, tmp3, tmpL);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4034
    __ cbnz(rscratch2, DIFF2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4035
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4036
    __ ldr(tmp3, Address(__ post(cnt1, 8)));
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4037
    __ umov(tmpL, vtmp, __ D, 1);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4038
    __ eor(rscratch2, tmpU, tmpL);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4039
    __ cbnz(rscratch2, DIFF1);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4040
  }
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4041
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4042
  // r0  = result
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4043
  // r1  = str1
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4044
  // r2  = cnt1
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4045
  // r3  = str2
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4046
  // r4  = cnt2
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4047
  // r10 = tmp1
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4048
  // r11 = tmp2
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4049
  address generate_compare_long_string_different_encoding(bool isLU) {
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4050
    __ align(CodeEntryAlignment);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4051
    StubCodeMark mark(this, "StubRoutines", isLU
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4052
        ? "compare_long_string_different_encoding LU"
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4053
        : "compare_long_string_different_encoding UL");
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4054
    address entry = __ pc();
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4055
    Label SMALL_LOOP, TAIL, TAIL_LOAD_16, LOAD_LAST, DIFF1, DIFF2,
54991
82fd8793ba5e 8218966: AArch64: String.compareTo() can read memory after string
dpochepk
parents: 54990
diff changeset
  4056
        DONE, CALCULATE_DIFFERENCE, LARGE_LOOP_PREFETCH, NO_PREFETCH,
50756
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4057
        LARGE_LOOP_PREFETCH_REPEAT1, LARGE_LOOP_PREFETCH_REPEAT2;
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4058
    Register result = r0, str1 = r1, cnt1 = r2, str2 = r3, cnt2 = r4,
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4059
        tmp1 = r10, tmp2 = r11, tmp3 = r12, tmp4 = r14;
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4060
    FloatRegister vtmpZ = v0, vtmp = v1, vtmp3 = v2;
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4061
    RegSet spilled_regs = RegSet::of(tmp3, tmp4);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4062
54991
82fd8793ba5e 8218966: AArch64: String.compareTo() can read memory after string
dpochepk
parents: 54990
diff changeset
  4063
    int prefetchLoopExitCondition = MAX(64, SoftwarePrefetchHintDistance/2);
50756
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4064
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4065
    __ eor(vtmpZ, __ T16B, vtmpZ, vtmpZ);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4066
    // cnt2 == amount of characters left to compare
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4067
    // Check already loaded first 4 symbols(vtmp and tmp2(LU)/tmp1(UL))
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4068
    __ zip1(vtmp, __ T8B, vtmp, vtmpZ);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4069
    __ add(str1, str1, isLU ? wordSize/2 : wordSize);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4070
    __ add(str2, str2, isLU ? wordSize : wordSize/2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4071
    __ fmovd(isLU ? tmp1 : tmp2, vtmp);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4072
    __ subw(cnt2, cnt2, 8); // Already loaded 4 symbols. Last 4 is special case.
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4073
    __ add(str1, str1, cnt2, __ LSL, isLU ? 0 : 1);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4074
    __ eor(rscratch2, tmp1, tmp2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4075
    __ add(str2, str2, cnt2, __ LSL, isLU ? 1 : 0);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4076
    __ mov(rscratch1, tmp2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4077
    __ cbnz(rscratch2, CALCULATE_DIFFERENCE);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4078
    Register strU = isLU ? str2 : str1,
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4079
             strL = isLU ? str1 : str2,
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4080
             tmpU = isLU ? rscratch1 : tmp1, // where to keep U for comparison
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4081
             tmpL = isLU ? tmp1 : rscratch1; // where to keep L for comparison
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4082
    __ push(spilled_regs, sp);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4083
    __ sub(tmp2, strL, cnt2); // strL pointer to load from
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4084
    __ sub(cnt1, strU, cnt2, __ LSL, 1); // strU pointer to load from
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4085
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4086
    __ ldr(tmp3, Address(__ post(cnt1, 8)));
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4087
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4088
    if (SoftwarePrefetchHintDistance >= 0) {
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
  4089
      __ subs(rscratch2, cnt2, prefetchLoopExitCondition);
54991
82fd8793ba5e 8218966: AArch64: String.compareTo() can read memory after string
dpochepk
parents: 54990
diff changeset
  4090
      __ br(__ LT, NO_PREFETCH);
50756
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4091
      __ bind(LARGE_LOOP_PREFETCH);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4092
        __ prfm(Address(tmp2, SoftwarePrefetchHintDistance));
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4093
        __ mov(tmp4, 2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4094
        __ prfm(Address(cnt1, SoftwarePrefetchHintDistance));
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4095
        __ bind(LARGE_LOOP_PREFETCH_REPEAT1);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4096
          compare_string_16_x_LU(tmpL, tmpU, DIFF1, DIFF2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4097
          __ subs(tmp4, tmp4, 1);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4098
          __ br(__ GT, LARGE_LOOP_PREFETCH_REPEAT1);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4099
          __ prfm(Address(cnt1, SoftwarePrefetchHintDistance));
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4100
          __ mov(tmp4, 2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4101
        __ bind(LARGE_LOOP_PREFETCH_REPEAT2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4102
          compare_string_16_x_LU(tmpL, tmpU, DIFF1, DIFF2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4103
          __ subs(tmp4, tmp4, 1);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4104
          __ br(__ GT, LARGE_LOOP_PREFETCH_REPEAT2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4105
          __ sub(cnt2, cnt2, 64);
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
  4106
          __ subs(rscratch2, cnt2, prefetchLoopExitCondition);
50756
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4107
          __ br(__ GE, LARGE_LOOP_PREFETCH);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4108
    }
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4109
    __ cbz(cnt2, LOAD_LAST); // no characters left except last load
54991
82fd8793ba5e 8218966: AArch64: String.compareTo() can read memory after string
dpochepk
parents: 54990
diff changeset
  4110
    __ bind(NO_PREFETCH);
50756
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4111
    __ subs(cnt2, cnt2, 16);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4112
    __ br(__ LT, TAIL);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4113
    __ bind(SMALL_LOOP); // smaller loop
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4114
      __ subs(cnt2, cnt2, 16);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4115
      compare_string_16_x_LU(tmpL, tmpU, DIFF1, DIFF2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4116
      __ br(__ GE, SMALL_LOOP);
54991
82fd8793ba5e 8218966: AArch64: String.compareTo() can read memory after string
dpochepk
parents: 54990
diff changeset
  4117
      __ cmn(cnt2, (u1)16);
82fd8793ba5e 8218966: AArch64: String.compareTo() can read memory after string
dpochepk
parents: 54990
diff changeset
  4118
      __ br(__ EQ, LOAD_LAST);
82fd8793ba5e 8218966: AArch64: String.compareTo() can read memory after string
dpochepk
parents: 54990
diff changeset
  4119
    __ bind(TAIL); // 1..15 characters left until last load (last 4 characters)
82fd8793ba5e 8218966: AArch64: String.compareTo() can read memory after string
dpochepk
parents: 54990
diff changeset
  4120
      __ add(cnt1, cnt1, cnt2, __ LSL, 1); // Address of 8 bytes before last 4 characters in UTF-16 string
82fd8793ba5e 8218966: AArch64: String.compareTo() can read memory after string
dpochepk
parents: 54990
diff changeset
  4121
      __ add(tmp2, tmp2, cnt2); // Address of 16 bytes before last 4 characters in Latin1 string
82fd8793ba5e 8218966: AArch64: String.compareTo() can read memory after string
dpochepk
parents: 54990
diff changeset
  4122
      __ ldr(tmp3, Address(cnt1, -8));
82fd8793ba5e 8218966: AArch64: String.compareTo() can read memory after string
dpochepk
parents: 54990
diff changeset
  4123
      compare_string_16_x_LU(tmpL, tmpU, DIFF1, DIFF2); // last 16 characters before last load
50756
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4124
      __ b(LOAD_LAST);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4125
    __ bind(DIFF2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4126
      __ mov(tmpU, tmp3);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4127
    __ bind(DIFF1);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4128
      __ pop(spilled_regs, sp);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4129
      __ b(CALCULATE_DIFFERENCE);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4130
    __ bind(LOAD_LAST);
54991
82fd8793ba5e 8218966: AArch64: String.compareTo() can read memory after string
dpochepk
parents: 54990
diff changeset
  4131
      // Last 4 UTF-16 characters are already pre-loaded into tmp3 by compare_string_16_x_LU.
82fd8793ba5e 8218966: AArch64: String.compareTo() can read memory after string
dpochepk
parents: 54990
diff changeset
  4132
      // No need to load it again
82fd8793ba5e 8218966: AArch64: String.compareTo() can read memory after string
dpochepk
parents: 54990
diff changeset
  4133
      __ mov(tmpU, tmp3);
50756
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4134
      __ pop(spilled_regs, sp);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4135
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4136
      __ ldrs(vtmp, Address(strL));
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4137
      __ zip1(vtmp, __ T8B, vtmp, vtmpZ);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4138
      __ fmovd(tmpL, vtmp);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4139
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4140
      __ eor(rscratch2, tmpU, tmpL);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4141
      __ cbz(rscratch2, DONE);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4142
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4143
    // Find the first different characters in the longwords and
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4144
    // compute their difference.
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4145
    __ bind(CALCULATE_DIFFERENCE);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4146
      __ rev(rscratch2, rscratch2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4147
      __ clz(rscratch2, rscratch2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4148
      __ andr(rscratch2, rscratch2, -16);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4149
      __ lsrv(tmp1, tmp1, rscratch2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4150
      __ uxthw(tmp1, tmp1);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4151
      __ lsrv(rscratch1, rscratch1, rscratch2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4152
      __ uxthw(rscratch1, rscratch1);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4153
      __ subw(result, tmp1, rscratch1);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4154
    __ bind(DONE);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4155
      __ ret(lr);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4156
    return entry;
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4157
  }
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4158
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4159
  // r0  = result
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4160
  // r1  = str1
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4161
  // r2  = cnt1
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4162
  // r3  = str2
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4163
  // r4  = cnt2
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4164
  // r10 = tmp1
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4165
  // r11 = tmp2
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4166
  address generate_compare_long_string_same_encoding(bool isLL) {
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4167
    __ align(CodeEntryAlignment);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4168
    StubCodeMark mark(this, "StubRoutines", isLL
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4169
        ? "compare_long_string_same_encoding LL"
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4170
        : "compare_long_string_same_encoding UU");
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4171
    address entry = __ pc();
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4172
    Register result = r0, str1 = r1, cnt1 = r2, str2 = r3, cnt2 = r4,
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4173
        tmp1 = r10, tmp2 = r11;
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4174
    Label SMALL_LOOP, LARGE_LOOP_PREFETCH, CHECK_LAST, DIFF2, TAIL,
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4175
        LENGTH_DIFF, DIFF, LAST_CHECK_AND_LENGTH_DIFF,
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4176
        DIFF_LAST_POSITION, DIFF_LAST_POSITION2;
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4177
    // exit from large loop when less than 64 bytes left to read or we're about
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4178
    // to prefetch memory behind array border
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4179
    int largeLoopExitCondition = MAX(64, SoftwarePrefetchHintDistance)/(isLL ? 1 : 2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4180
    // cnt1/cnt2 contains amount of characters to compare. cnt1 can be re-used
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4181
    // update cnt2 counter with already loaded 8 bytes
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4182
    __ sub(cnt2, cnt2, wordSize/(isLL ? 1 : 2));
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4183
    // update pointers, because of previous read
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4184
    __ add(str1, str1, wordSize);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4185
    __ add(str2, str2, wordSize);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4186
    if (SoftwarePrefetchHintDistance >= 0) {
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4187
      __ bind(LARGE_LOOP_PREFETCH);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4188
        __ prfm(Address(str1, SoftwarePrefetchHintDistance));
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4189
        __ prfm(Address(str2, SoftwarePrefetchHintDistance));
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4190
        compare_string_16_bytes_same(DIFF, DIFF2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4191
        compare_string_16_bytes_same(DIFF, DIFF2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4192
        __ sub(cnt2, cnt2, isLL ? 64 : 32);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4193
        compare_string_16_bytes_same(DIFF, DIFF2);
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
  4194
        __ subs(rscratch2, cnt2, largeLoopExitCondition);
50756
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4195
        compare_string_16_bytes_same(DIFF, DIFF2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4196
        __ br(__ GT, LARGE_LOOP_PREFETCH);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4197
        __ cbz(cnt2, LAST_CHECK_AND_LENGTH_DIFF); // no more chars left?
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4198
    }
54991
82fd8793ba5e 8218966: AArch64: String.compareTo() can read memory after string
dpochepk
parents: 54990
diff changeset
  4199
    // less than 16 bytes left?
82fd8793ba5e 8218966: AArch64: String.compareTo() can read memory after string
dpochepk
parents: 54990
diff changeset
  4200
    __ subs(cnt2, cnt2, isLL ? 16 : 8);
82fd8793ba5e 8218966: AArch64: String.compareTo() can read memory after string
dpochepk
parents: 54990
diff changeset
  4201
    __ br(__ LT, TAIL);
50756
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4202
    __ bind(SMALL_LOOP);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4203
      compare_string_16_bytes_same(DIFF, DIFF2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4204
      __ subs(cnt2, cnt2, isLL ? 16 : 8);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4205
      __ br(__ GE, SMALL_LOOP);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4206
    __ bind(TAIL);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4207
      __ adds(cnt2, cnt2, isLL ? 16 : 8);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4208
      __ br(__ EQ, LAST_CHECK_AND_LENGTH_DIFF);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4209
      __ subs(cnt2, cnt2, isLL ? 8 : 4);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4210
      __ br(__ LE, CHECK_LAST);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4211
      __ eor(rscratch2, tmp1, tmp2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4212
      __ cbnz(rscratch2, DIFF);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4213
      __ ldr(tmp1, Address(__ post(str1, 8)));
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4214
      __ ldr(tmp2, Address(__ post(str2, 8)));
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4215
      __ sub(cnt2, cnt2, isLL ? 8 : 4);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4216
    __ bind(CHECK_LAST);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4217
      if (!isLL) {
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4218
        __ add(cnt2, cnt2, cnt2); // now in bytes
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4219
      }
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4220
      __ eor(rscratch2, tmp1, tmp2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4221
      __ cbnz(rscratch2, DIFF);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4222
      __ ldr(rscratch1, Address(str1, cnt2));
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4223
      __ ldr(cnt1, Address(str2, cnt2));
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4224
      __ eor(rscratch2, rscratch1, cnt1);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4225
      __ cbz(rscratch2, LENGTH_DIFF);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4226
      // Find the first different characters in the longwords and
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4227
      // compute their difference.
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4228
    __ bind(DIFF2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4229
      __ rev(rscratch2, rscratch2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4230
      __ clz(rscratch2, rscratch2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4231
      __ andr(rscratch2, rscratch2, isLL ? -8 : -16);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4232
      __ lsrv(rscratch1, rscratch1, rscratch2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4233
      if (isLL) {
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4234
        __ lsrv(cnt1, cnt1, rscratch2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4235
        __ uxtbw(rscratch1, rscratch1);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4236
        __ uxtbw(cnt1, cnt1);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4237
      } else {
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4238
        __ lsrv(cnt1, cnt1, rscratch2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4239
        __ uxthw(rscratch1, rscratch1);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4240
        __ uxthw(cnt1, cnt1);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4241
      }
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4242
      __ subw(result, rscratch1, cnt1);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4243
      __ b(LENGTH_DIFF);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4244
    __ bind(DIFF);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4245
      __ rev(rscratch2, rscratch2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4246
      __ clz(rscratch2, rscratch2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4247
      __ andr(rscratch2, rscratch2, isLL ? -8 : -16);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4248
      __ lsrv(tmp1, tmp1, rscratch2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4249
      if (isLL) {
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4250
        __ lsrv(tmp2, tmp2, rscratch2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4251
        __ uxtbw(tmp1, tmp1);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4252
        __ uxtbw(tmp2, tmp2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4253
      } else {
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4254
        __ lsrv(tmp2, tmp2, rscratch2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4255
        __ uxthw(tmp1, tmp1);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4256
        __ uxthw(tmp2, tmp2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4257
      }
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4258
      __ subw(result, tmp1, tmp2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4259
      __ b(LENGTH_DIFF);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4260
    __ bind(LAST_CHECK_AND_LENGTH_DIFF);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4261
      __ eor(rscratch2, tmp1, tmp2);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4262
      __ cbnz(rscratch2, DIFF);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4263
    __ bind(LENGTH_DIFF);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4264
      __ ret(lr);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4265
    return entry;
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4266
  }
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4267
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4268
  void generate_compare_long_strings() {
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4269
      StubRoutines::aarch64::_compare_long_string_LL
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4270
          = generate_compare_long_string_same_encoding(true);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4271
      StubRoutines::aarch64::_compare_long_string_UU
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4272
          = generate_compare_long_string_same_encoding(false);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4273
      StubRoutines::aarch64::_compare_long_string_LU
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4274
          = generate_compare_long_string_different_encoding(true);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4275
      StubRoutines::aarch64::_compare_long_string_UL
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4276
          = generate_compare_long_string_different_encoding(false);
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4277
  }
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  4278
50757
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4279
  // R0 = result
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4280
  // R1 = str2
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4281
  // R2 = cnt1
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4282
  // R3 = str1
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4283
  // R4 = cnt2
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4284
  // This generic linear code use few additional ideas, which makes it faster:
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4285
  // 1) we can safely keep at least 1st register of pattern(since length >= 8)
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4286
  // in order to skip initial loading(help in systems with 1 ld pipeline)
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4287
  // 2) we can use "fast" algorithm of finding single character to search for
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4288
  // first symbol with less branches(1 branch per each loaded register instead
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4289
  // of branch for each symbol), so, this is where constants like
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4290
  // 0x0101...01, 0x00010001...0001, 0x7f7f...7f, 0x7fff7fff...7fff comes from
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4291
  // 3) after loading and analyzing 1st register of source string, it can be
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4292
  // used to search for every 1st character entry, saving few loads in
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4293
  // comparison with "simplier-but-slower" implementation
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4294
  // 4) in order to avoid lots of push/pop operations, code below is heavily
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4295
  // re-using/re-initializing/compressing register values, which makes code
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4296
  // larger and a bit less readable, however, most of extra operations are
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4297
  // issued during loads or branches, so, penalty is minimal
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4298
  address generate_string_indexof_linear(bool str1_isL, bool str2_isL) {
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4299
    const char* stubName = str1_isL
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4300
        ? (str2_isL ? "indexof_linear_ll" : "indexof_linear_ul")
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4301
        : "indexof_linear_uu";
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4302
    __ align(CodeEntryAlignment);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4303
    StubCodeMark mark(this, "StubRoutines", stubName);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4304
    address entry = __ pc();
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4305
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4306
    int str1_chr_size = str1_isL ? 1 : 2;
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4307
    int str2_chr_size = str2_isL ? 1 : 2;
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4308
    int str1_chr_shift = str1_isL ? 0 : 1;
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4309
    int str2_chr_shift = str2_isL ? 0 : 1;
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4310
    bool isL = str1_isL && str2_isL;
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4311
   // parameters
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4312
    Register result = r0, str2 = r1, cnt1 = r2, str1 = r3, cnt2 = r4;
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4313
    // temporary registers
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4314
    Register tmp1 = r20, tmp2 = r21, tmp3 = r22, tmp4 = r23;
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4315
    RegSet spilled_regs = RegSet::range(tmp1, tmp4);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4316
    // redefinitions
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4317
    Register ch1 = rscratch1, ch2 = rscratch2, first = tmp3;
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4318
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4319
    __ push(spilled_regs, sp);
51756
4bd35a5ec694 8210676: Remove some unused Label variables
mikael
parents: 51619
diff changeset
  4320
    Label L_LOOP, L_LOOP_PROCEED, L_SMALL, L_HAS_ZERO,
50757
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4321
        L_HAS_ZERO_LOOP, L_CMP_LOOP, L_CMP_LOOP_NOMATCH, L_SMALL_PROCEED,
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4322
        L_SMALL_HAS_ZERO_LOOP, L_SMALL_CMP_LOOP_NOMATCH, L_SMALL_CMP_LOOP,
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4323
        L_POST_LOOP, L_CMP_LOOP_LAST_CMP, L_HAS_ZERO_LOOP_NOMATCH,
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4324
        L_SMALL_CMP_LOOP_LAST_CMP, L_SMALL_CMP_LOOP_LAST_CMP2,
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4325
        L_CMP_LOOP_LAST_CMP2, DONE, NOMATCH;
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4326
    // Read whole register from str1. It is safe, because length >=8 here
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4327
    __ ldr(ch1, Address(str1));
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4328
    // Read whole register from str2. It is safe, because length >=8 here
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4329
    __ ldr(ch2, Address(str2));
54990
cbc557f166f2 8215792: AArch64: String.indexOf generates incorrect result
dpochepk
parents: 54979
diff changeset
  4330
    __ sub(cnt2, cnt2, cnt1);
50757
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4331
    __ andr(first, ch1, str1_isL ? 0xFF : 0xFFFF);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4332
    if (str1_isL != str2_isL) {
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4333
      __ eor(v0, __ T16B, v0, v0);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4334
    }
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4335
    __ mov(tmp1, str2_isL ? 0x0101010101010101 : 0x0001000100010001);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4336
    __ mul(first, first, tmp1);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4337
    // check if we have less than 1 register to check
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4338
    __ subs(cnt2, cnt2, wordSize/str2_chr_size - 1);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4339
    if (str1_isL != str2_isL) {
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4340
      __ fmovd(v1, ch1);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4341
    }
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4342
    __ br(__ LE, L_SMALL);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4343
    __ eor(ch2, first, ch2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4344
    if (str1_isL != str2_isL) {
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4345
      __ zip1(v1, __ T16B, v1, v0);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4346
    }
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4347
    __ sub(tmp2, ch2, tmp1);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4348
    __ orr(ch2, ch2, str2_isL ? 0x7f7f7f7f7f7f7f7f : 0x7fff7fff7fff7fff);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4349
    __ bics(tmp2, tmp2, ch2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4350
    if (str1_isL != str2_isL) {
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4351
      __ fmovd(ch1, v1);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4352
    }
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4353
    __ br(__ NE, L_HAS_ZERO);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4354
    __ subs(cnt2, cnt2, wordSize/str2_chr_size);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4355
    __ add(result, result, wordSize/str2_chr_size);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4356
    __ add(str2, str2, wordSize);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4357
    __ br(__ LT, L_POST_LOOP);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4358
    __ BIND(L_LOOP);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4359
      __ ldr(ch2, Address(str2));
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4360
      __ eor(ch2, first, ch2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4361
      __ sub(tmp2, ch2, tmp1);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4362
      __ orr(ch2, ch2, str2_isL ? 0x7f7f7f7f7f7f7f7f : 0x7fff7fff7fff7fff);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4363
      __ bics(tmp2, tmp2, ch2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4364
      __ br(__ NE, L_HAS_ZERO);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4365
    __ BIND(L_LOOP_PROCEED);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4366
      __ subs(cnt2, cnt2, wordSize/str2_chr_size);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4367
      __ add(str2, str2, wordSize);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4368
      __ add(result, result, wordSize/str2_chr_size);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4369
      __ br(__ GE, L_LOOP);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4370
    __ BIND(L_POST_LOOP);
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
  4371
      __ subs(zr, cnt2, -wordSize/str2_chr_size); // no extra characters to check
50757
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4372
      __ br(__ LE, NOMATCH);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4373
      __ ldr(ch2, Address(str2));
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4374
      __ sub(cnt2, zr, cnt2, __ LSL, LogBitsPerByte + str2_chr_shift);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4375
      __ eor(ch2, first, ch2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4376
      __ sub(tmp2, ch2, tmp1);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4377
      __ orr(ch2, ch2, str2_isL ? 0x7f7f7f7f7f7f7f7f : 0x7fff7fff7fff7fff);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4378
      __ mov(tmp4, -1); // all bits set
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4379
      __ b(L_SMALL_PROCEED);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4380
    __ align(OptoLoopAlignment);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4381
    __ BIND(L_SMALL);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4382
      __ sub(cnt2, zr, cnt2, __ LSL, LogBitsPerByte + str2_chr_shift);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4383
      __ eor(ch2, first, ch2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4384
      if (str1_isL != str2_isL) {
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4385
        __ zip1(v1, __ T16B, v1, v0);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4386
      }
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4387
      __ sub(tmp2, ch2, tmp1);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4388
      __ mov(tmp4, -1); // all bits set
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4389
      __ orr(ch2, ch2, str2_isL ? 0x7f7f7f7f7f7f7f7f : 0x7fff7fff7fff7fff);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4390
      if (str1_isL != str2_isL) {
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4391
        __ fmovd(ch1, v1); // move converted 4 symbols
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4392
      }
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4393
    __ BIND(L_SMALL_PROCEED);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4394
      __ lsrv(tmp4, tmp4, cnt2); // mask. zeroes on useless bits.
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4395
      __ bic(tmp2, tmp2, ch2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4396
      __ ands(tmp2, tmp2, tmp4); // clear useless bits and check
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4397
      __ rbit(tmp2, tmp2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4398
      __ br(__ EQ, NOMATCH);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4399
    __ BIND(L_SMALL_HAS_ZERO_LOOP);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4400
      __ clz(tmp4, tmp2); // potentially long. Up to 4 cycles on some cpu's
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
  4401
      __ cmp(cnt1, u1(wordSize/str2_chr_size));
50757
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4402
      __ br(__ LE, L_SMALL_CMP_LOOP_LAST_CMP2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4403
      if (str2_isL) { // LL
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4404
        __ add(str2, str2, tmp4, __ LSR, LogBitsPerByte); // address of "index"
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4405
        __ ldr(ch2, Address(str2)); // read whole register of str2. Safe.
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4406
        __ lslv(tmp2, tmp2, tmp4); // shift off leading zeroes from match info
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4407
        __ add(result, result, tmp4, __ LSR, LogBitsPerByte);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4408
        __ lsl(tmp2, tmp2, 1); // shift off leading "1" from match info
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4409
      } else {
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4410
        __ mov(ch2, 0xE); // all bits in byte set except last one
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4411
        __ andr(ch2, ch2, tmp4, __ LSR, LogBitsPerByte); // byte shift amount
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4412
        __ ldr(ch2, Address(str2, ch2)); // read whole register of str2. Safe.
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4413
        __ lslv(tmp2, tmp2, tmp4);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4414
        __ add(result, result, tmp4, __ LSR, LogBitsPerByte + str2_chr_shift);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4415
        __ add(str2, str2, tmp4, __ LSR, LogBitsPerByte + str2_chr_shift);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4416
        __ lsl(tmp2, tmp2, 1); // shift off leading "1" from match info
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4417
        __ add(str2, str2, tmp4, __ LSR, LogBitsPerByte + str2_chr_shift);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4418
      }
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4419
      __ cmp(ch1, ch2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4420
      __ mov(tmp4, wordSize/str2_chr_size);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4421
      __ br(__ NE, L_SMALL_CMP_LOOP_NOMATCH);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4422
    __ BIND(L_SMALL_CMP_LOOP);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4423
      str1_isL ? __ ldrb(first, Address(str1, tmp4, Address::lsl(str1_chr_shift)))
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4424
               : __ ldrh(first, Address(str1, tmp4, Address::lsl(str1_chr_shift)));
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4425
      str2_isL ? __ ldrb(ch2, Address(str2, tmp4, Address::lsl(str2_chr_shift)))
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4426
               : __ ldrh(ch2, Address(str2, tmp4, Address::lsl(str2_chr_shift)));
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4427
      __ add(tmp4, tmp4, 1);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4428
      __ cmp(tmp4, cnt1);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4429
      __ br(__ GE, L_SMALL_CMP_LOOP_LAST_CMP);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4430
      __ cmp(first, ch2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4431
      __ br(__ EQ, L_SMALL_CMP_LOOP);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4432
    __ BIND(L_SMALL_CMP_LOOP_NOMATCH);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4433
      __ cbz(tmp2, NOMATCH); // no more matches. exit
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4434
      __ clz(tmp4, tmp2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4435
      __ add(result, result, 1); // advance index
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4436
      __ add(str2, str2, str2_chr_size); // advance pointer
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4437
      __ b(L_SMALL_HAS_ZERO_LOOP);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4438
    __ align(OptoLoopAlignment);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4439
    __ BIND(L_SMALL_CMP_LOOP_LAST_CMP);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4440
      __ cmp(first, ch2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4441
      __ br(__ NE, L_SMALL_CMP_LOOP_NOMATCH);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4442
      __ b(DONE);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4443
    __ align(OptoLoopAlignment);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4444
    __ BIND(L_SMALL_CMP_LOOP_LAST_CMP2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4445
      if (str2_isL) { // LL
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4446
        __ add(str2, str2, tmp4, __ LSR, LogBitsPerByte); // address of "index"
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4447
        __ ldr(ch2, Address(str2)); // read whole register of str2. Safe.
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4448
        __ lslv(tmp2, tmp2, tmp4); // shift off leading zeroes from match info
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4449
        __ add(result, result, tmp4, __ LSR, LogBitsPerByte);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4450
        __ lsl(tmp2, tmp2, 1); // shift off leading "1" from match info
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4451
      } else {
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4452
        __ mov(ch2, 0xE); // all bits in byte set except last one
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4453
        __ andr(ch2, ch2, tmp4, __ LSR, LogBitsPerByte); // byte shift amount
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4454
        __ ldr(ch2, Address(str2, ch2)); // read whole register of str2. Safe.
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4455
        __ lslv(tmp2, tmp2, tmp4);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4456
        __ add(result, result, tmp4, __ LSR, LogBitsPerByte + str2_chr_shift);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4457
        __ add(str2, str2, tmp4, __ LSR, LogBitsPerByte + str2_chr_shift);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4458
        __ lsl(tmp2, tmp2, 1); // shift off leading "1" from match info
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4459
        __ add(str2, str2, tmp4, __ LSR, LogBitsPerByte + str2_chr_shift);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4460
      }
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4461
      __ cmp(ch1, ch2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4462
      __ br(__ NE, L_SMALL_CMP_LOOP_NOMATCH);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4463
      __ b(DONE);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4464
    __ align(OptoLoopAlignment);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4465
    __ BIND(L_HAS_ZERO);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4466
      __ rbit(tmp2, tmp2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4467
      __ clz(tmp4, tmp2); // potentially long. Up to 4 cycles on some CPU's
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4468
      // Now, perform compression of counters(cnt2 and cnt1) into one register.
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4469
      // It's fine because both counters are 32bit and are not changed in this
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4470
      // loop. Just restore it on exit. So, cnt1 can be re-used in this loop.
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4471
      __ orr(cnt2, cnt2, cnt1, __ LSL, BitsPerByte * wordSize / 2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4472
      __ sub(result, result, 1);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4473
    __ BIND(L_HAS_ZERO_LOOP);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4474
      __ mov(cnt1, wordSize/str2_chr_size);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4475
      __ cmp(cnt1, cnt2, __ LSR, BitsPerByte * wordSize / 2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4476
      __ br(__ GE, L_CMP_LOOP_LAST_CMP2); // case of 8 bytes only to compare
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4477
      if (str2_isL) {
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4478
        __ lsr(ch2, tmp4, LogBitsPerByte + str2_chr_shift); // char index
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4479
        __ ldr(ch2, Address(str2, ch2)); // read whole register of str2. Safe.
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4480
        __ lslv(tmp2, tmp2, tmp4);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4481
        __ add(str2, str2, tmp4, __ LSR, LogBitsPerByte + str2_chr_shift);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4482
        __ add(tmp4, tmp4, 1);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4483
        __ add(result, result, tmp4, __ LSR, LogBitsPerByte + str2_chr_shift);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4484
        __ lsl(tmp2, tmp2, 1);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4485
        __ mov(tmp4, wordSize/str2_chr_size);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4486
      } else {
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4487
        __ mov(ch2, 0xE);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4488
        __ andr(ch2, ch2, tmp4, __ LSR, LogBitsPerByte); // byte shift amount
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4489
        __ ldr(ch2, Address(str2, ch2)); // read whole register of str2. Safe.
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4490
        __ lslv(tmp2, tmp2, tmp4);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4491
        __ add(tmp4, tmp4, 1);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4492
        __ add(result, result, tmp4, __ LSR, LogBitsPerByte + str2_chr_shift);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4493
        __ add(str2, str2, tmp4, __ LSR, LogBitsPerByte);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4494
        __ lsl(tmp2, tmp2, 1);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4495
        __ mov(tmp4, wordSize/str2_chr_size);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4496
        __ sub(str2, str2, str2_chr_size);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4497
      }
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4498
      __ cmp(ch1, ch2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4499
      __ mov(tmp4, wordSize/str2_chr_size);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4500
      __ br(__ NE, L_CMP_LOOP_NOMATCH);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4501
    __ BIND(L_CMP_LOOP);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4502
      str1_isL ? __ ldrb(cnt1, Address(str1, tmp4, Address::lsl(str1_chr_shift)))
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4503
               : __ ldrh(cnt1, Address(str1, tmp4, Address::lsl(str1_chr_shift)));
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4504
      str2_isL ? __ ldrb(ch2, Address(str2, tmp4, Address::lsl(str2_chr_shift)))
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4505
               : __ ldrh(ch2, Address(str2, tmp4, Address::lsl(str2_chr_shift)));
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4506
      __ add(tmp4, tmp4, 1);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4507
      __ cmp(tmp4, cnt2, __ LSR, BitsPerByte * wordSize / 2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4508
      __ br(__ GE, L_CMP_LOOP_LAST_CMP);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4509
      __ cmp(cnt1, ch2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4510
      __ br(__ EQ, L_CMP_LOOP);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4511
    __ BIND(L_CMP_LOOP_NOMATCH);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4512
      // here we're not matched
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4513
      __ cbz(tmp2, L_HAS_ZERO_LOOP_NOMATCH); // no more matches. Proceed to main loop
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4514
      __ clz(tmp4, tmp2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4515
      __ add(str2, str2, str2_chr_size); // advance pointer
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4516
      __ b(L_HAS_ZERO_LOOP);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4517
    __ align(OptoLoopAlignment);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4518
    __ BIND(L_CMP_LOOP_LAST_CMP);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4519
      __ cmp(cnt1, ch2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4520
      __ br(__ NE, L_CMP_LOOP_NOMATCH);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4521
      __ b(DONE);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4522
    __ align(OptoLoopAlignment);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4523
    __ BIND(L_CMP_LOOP_LAST_CMP2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4524
      if (str2_isL) {
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4525
        __ lsr(ch2, tmp4, LogBitsPerByte + str2_chr_shift); // char index
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4526
        __ ldr(ch2, Address(str2, ch2)); // read whole register of str2. Safe.
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4527
        __ lslv(tmp2, tmp2, tmp4);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4528
        __ add(str2, str2, tmp4, __ LSR, LogBitsPerByte + str2_chr_shift);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4529
        __ add(tmp4, tmp4, 1);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4530
        __ add(result, result, tmp4, __ LSR, LogBitsPerByte + str2_chr_shift);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4531
        __ lsl(tmp2, tmp2, 1);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4532
      } else {
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4533
        __ mov(ch2, 0xE);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4534
        __ andr(ch2, ch2, tmp4, __ LSR, LogBitsPerByte); // byte shift amount
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4535
        __ ldr(ch2, Address(str2, ch2)); // read whole register of str2. Safe.
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4536
        __ lslv(tmp2, tmp2, tmp4);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4537
        __ add(tmp4, tmp4, 1);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4538
        __ add(result, result, tmp4, __ LSR, LogBitsPerByte + str2_chr_shift);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4539
        __ add(str2, str2, tmp4, __ LSR, LogBitsPerByte);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4540
        __ lsl(tmp2, tmp2, 1);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4541
        __ sub(str2, str2, str2_chr_size);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4542
      }
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4543
      __ cmp(ch1, ch2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4544
      __ br(__ NE, L_CMP_LOOP_NOMATCH);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4545
      __ b(DONE);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4546
    __ align(OptoLoopAlignment);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4547
    __ BIND(L_HAS_ZERO_LOOP_NOMATCH);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4548
      // 1) Restore "result" index. Index was wordSize/str2_chr_size * N until
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4549
      // L_HAS_ZERO block. Byte octet was analyzed in L_HAS_ZERO_LOOP,
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4550
      // so, result was increased at max by wordSize/str2_chr_size - 1, so,
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4551
      // respective high bit wasn't changed. L_LOOP_PROCEED will increase
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4552
      // result by analyzed characters value, so, we can just reset lower bits
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4553
      // in result here. Clear 2 lower bits for UU/UL and 3 bits for LL
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4554
      // 2) restore cnt1 and cnt2 values from "compressed" cnt2
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4555
      // 3) advance str2 value to represent next str2 octet. result & 7/3 is
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4556
      // index of last analyzed substring inside current octet. So, str2 in at
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4557
      // respective start address. We need to advance it to next octet
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4558
      __ andr(tmp2, result, wordSize/str2_chr_size - 1); // symbols analyzed
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4559
      __ lsr(cnt1, cnt2, BitsPerByte * wordSize / 2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4560
      __ bfm(result, zr, 0, 2 - str2_chr_shift);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4561
      __ sub(str2, str2, tmp2, __ LSL, str2_chr_shift); // restore str2
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4562
      __ movw(cnt2, cnt2);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4563
      __ b(L_LOOP_PROCEED);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4564
    __ align(OptoLoopAlignment);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4565
    __ BIND(NOMATCH);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4566
      __ mov(result, -1);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4567
    __ BIND(DONE);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4568
      __ pop(spilled_regs, sp);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4569
      __ ret(lr);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4570
    return entry;
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4571
  }
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4572
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4573
  void generate_string_indexof_stubs() {
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4574
    StubRoutines::aarch64::_string_indexof_linear_ll = generate_string_indexof_linear(true, true);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4575
    StubRoutines::aarch64::_string_indexof_linear_uu = generate_string_indexof_linear(false, false);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4576
    StubRoutines::aarch64::_string_indexof_linear_ul = generate_string_indexof_linear(true, false);
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4577
  }
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  4578
50758
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4579
  void inflate_and_store_2_fp_registers(bool generatePrfm,
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4580
      FloatRegister src1, FloatRegister src2) {
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4581
    Register dst = r1;
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4582
    __ zip1(v1, __ T16B, src1, v0);
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4583
    __ zip2(v2, __ T16B, src1, v0);
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4584
    if (generatePrfm) {
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4585
      __ prfm(Address(dst, SoftwarePrefetchHintDistance), PSTL1STRM);
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4586
    }
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4587
    __ zip1(v3, __ T16B, src2, v0);
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4588
    __ zip2(v4, __ T16B, src2, v0);
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4589
    __ st1(v1, v2, v3, v4, __ T16B, Address(__ post(dst, 64)));
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4590
  }
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4591
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4592
  // R0 = src
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4593
  // R1 = dst
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4594
  // R2 = len
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4595
  // R3 = len >> 3
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4596
  // V0 = 0
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4597
  // v1 = loaded 8 bytes
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4598
  address generate_large_byte_array_inflate() {
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4599
    __ align(CodeEntryAlignment);
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4600
    StubCodeMark mark(this, "StubRoutines", "large_byte_array_inflate");
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4601
    address entry = __ pc();
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4602
    Label LOOP, LOOP_START, LOOP_PRFM, LOOP_PRFM_START, DONE;
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4603
    Register src = r0, dst = r1, len = r2, octetCounter = r3;
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4604
    const int large_loop_threshold = MAX(64, SoftwarePrefetchHintDistance)/8 + 4;
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4605
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4606
    // do one more 8-byte read to have address 16-byte aligned in most cases
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4607
    // also use single store instruction
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4608
    __ ldrd(v2, __ post(src, 8));
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4609
    __ sub(octetCounter, octetCounter, 2);
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4610
    __ zip1(v1, __ T16B, v1, v0);
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4611
    __ zip1(v2, __ T16B, v2, v0);
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4612
    __ st1(v1, v2, __ T16B, __ post(dst, 32));
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4613
    __ ld1(v3, v4, v5, v6, __ T16B, Address(__ post(src, 64)));
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
  4614
    __ subs(rscratch1, octetCounter, large_loop_threshold);
50758
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4615
    __ br(__ LE, LOOP_START);
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4616
    __ b(LOOP_PRFM_START);
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4617
    __ bind(LOOP_PRFM);
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4618
      __ ld1(v3, v4, v5, v6, __ T16B, Address(__ post(src, 64)));
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4619
    __ bind(LOOP_PRFM_START);
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4620
      __ prfm(Address(src, SoftwarePrefetchHintDistance));
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4621
      __ sub(octetCounter, octetCounter, 8);
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
  4622
      __ subs(rscratch1, octetCounter, large_loop_threshold);
50758
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4623
      inflate_and_store_2_fp_registers(true, v3, v4);
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4624
      inflate_and_store_2_fp_registers(true, v5, v6);
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4625
      __ br(__ GT, LOOP_PRFM);
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
  4626
      __ cmp(octetCounter, (u1)8);
50758
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4627
      __ br(__ LT, DONE);
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4628
    __ bind(LOOP);
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4629
      __ ld1(v3, v4, v5, v6, __ T16B, Address(__ post(src, 64)));
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4630
      __ bind(LOOP_START);
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4631
      __ sub(octetCounter, octetCounter, 8);
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
  4632
      __ cmp(octetCounter, (u1)8);
50758
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4633
      inflate_and_store_2_fp_registers(false, v3, v4);
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4634
      inflate_and_store_2_fp_registers(false, v5, v6);
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4635
      __ br(__ GE, LOOP);
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4636
    __ bind(DONE);
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4637
      __ ret(lr);
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4638
    return entry;
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4639
  }
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  4640
31961
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4641
  /**
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4642
   *  Arguments:
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4643
   *
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4644
   *  Input:
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4645
   *  c_rarg0   - current state address
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4646
   *  c_rarg1   - H key address
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4647
   *  c_rarg2   - data address
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4648
   *  c_rarg3   - number of blocks
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4649
   *
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4650
   *  Output:
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4651
   *  Updated state at c_rarg0
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4652
   */
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4653
  address generate_ghash_processBlocks() {
32574
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4654
    // Bafflingly, GCM uses little-endian for the byte order, but
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4655
    // big-endian for the bit order.  For example, the polynomial 1 is
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4656
    // represented as the 16-byte string 80 00 00 00 | 12 bytes of 00.
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4657
    //
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4658
    // So, we must either reverse the bytes in each word and do
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4659
    // everything big-endian or reverse the bits in each byte and do
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4660
    // it little-endian.  On AArch64 it's more idiomatic to reverse
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4661
    // the bits in each byte (we have an instruction, RBIT, to do
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4662
    // that) and keep the data in little-endian bit order throught the
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4663
    // calculation, bit-reversing the inputs and outputs.
31961
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4664
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4665
    StubCodeMark mark(this, "StubRoutines", "ghash_processBlocks");
32574
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4666
    __ align(wordSize * 2);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4667
    address p = __ pc();
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4668
    __ emit_int64(0x87);  // The low-order bits of the field
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4669
                          // polynomial (i.e. p = z^7+z^2+z+1)
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4670
                          // repeated in the low and high parts of a
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4671
                          // 128-bit vector
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4672
    __ emit_int64(0x87);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4673
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4674
    __ align(CodeEntryAlignment);
31961
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4675
    address start = __ pc();
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4676
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4677
    Register state   = c_rarg0;
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4678
    Register subkeyH = c_rarg1;
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4679
    Register data    = c_rarg2;
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4680
    Register blocks  = c_rarg3;
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4681
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4682
    FloatRegister vzr = v30;
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4683
    __ eor(vzr, __ T16B, vzr, vzr); // zero register
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4684
32574
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4685
    __ ldrq(v0, Address(state));
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4686
    __ ldrq(v1, Address(subkeyH));
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4687
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4688
    __ rev64(v0, __ T16B, v0);          // Bit-reverse words in state and subkeyH
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4689
    __ rbit(v0, __ T16B, v0);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4690
    __ rev64(v1, __ T16B, v1);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4691
    __ rbit(v1, __ T16B, v1);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4692
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4693
    __ ldrq(v26, p);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4694
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4695
    __ ext(v16, __ T16B, v1, v1, 0x08); // long-swap subkeyH into v1
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4696
    __ eor(v16, __ T16B, v16, v1);      // xor subkeyH into subkeyL (Karatsuba: (A1+A0))
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4697
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4698
    {
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4699
      Label L_ghash_loop;
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4700
      __ bind(L_ghash_loop);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4701
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4702
      __ ldrq(v2, Address(__ post(data, 0x10))); // Load the data, bit
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4703
                                                 // reversing each byte
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4704
      __ rbit(v2, __ T16B, v2);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4705
      __ eor(v2, __ T16B, v0, v2);   // bit-swapped data ^ bit-swapped state
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4706
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4707
      // Multiply state in v2 by subkey in v1
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4708
      ghash_multiply(/*result_lo*/v5, /*result_hi*/v7,
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4709
                     /*a*/v1, /*b*/v2, /*a1_xor_a0*/v16,
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4710
                     /*temps*/v6, v20, v18, v21);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4711
      // Reduce v7:v5 by the field polynomial
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4712
      ghash_reduce(v0, v5, v7, v26, vzr, v20);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4713
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4714
      __ sub(blocks, blocks, 1);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4715
      __ cbnz(blocks, L_ghash_loop);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4716
    }
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4717
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4718
    // The bit-reversed result is at this point in v0
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4719
    __ rev64(v1, __ T16B, v0);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4720
    __ rbit(v1, __ T16B, v1);
6c3b890aa5d9 8134869: AARCH64: GHASH intrinsic is not optimal
aph
parents: 31961
diff changeset
  4721
31961
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4722
    __ st1(v1, __ T16B, state);
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4723
    __ ret(lr);
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4724
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4725
    return start;
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4726
  }
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  4727
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4728
  // Continuation point for throwing of implicit exceptions that are
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4729
  // not handled in the current activation. Fabricates an exception
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4730
  // oop and initiates normal exception dispatching in this
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4731
  // frame. Since we need to preserve callee-saved values (currently
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4732
  // only for C2, but done for C1 as well) we need a callee-saved oop
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4733
  // map and therefore have to make these stubs into RuntimeStubs
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4734
  // rather than BufferBlobs.  If the compiler needs all registers to
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4735
  // be preserved between the fault point and the exception handler
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4736
  // then it must assume responsibility for that in
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4737
  // AbstractCompiler::continuation_for_implicit_null_exception or
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4738
  // continuation_for_implicit_division_by_zero_exception. All other
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4739
  // implicit exceptions (e.g., NullPointerException or
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4740
  // AbstractMethodError on entry) are either at call sites or
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4741
  // otherwise assume that stack unwinding will be initiated, so
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4742
  // caller saved registers were assumed volatile in the compiler.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4743
30225
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  4744
#undef __
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  4745
#define __ masm->
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  4746
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4747
  address generate_throw_exception(const char* name,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4748
                                   address runtime_entry,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4749
                                   Register arg1 = noreg,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4750
                                   Register arg2 = noreg) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4751
    // Information about frame layout at time of blocking runtime call.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4752
    // Note that we only have to preserve callee-saved registers since
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4753
    // the compilers are responsible for supplying a continuation point
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4754
    // if they expect all registers to be preserved.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4755
    // n.b. aarch64 asserts that frame::arg_reg_save_area_bytes == 0
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4756
    enum layout {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4757
      rfp_off = 0,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4758
      rfp_off2,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4759
      return_off,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4760
      return_off2,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4761
      framesize // inclusive of return address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4762
    };
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4763
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4764
    int insts_size = 512;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4765
    int locs_size  = 64;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4766
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4767
    CodeBuffer code(name, insts_size, locs_size);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4768
    OopMapSet* oop_maps  = new OopMapSet();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4769
    MacroAssembler* masm = new MacroAssembler(&code);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4770
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4771
    address start = __ pc();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4772
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4773
    // This is an inlined and slightly modified version of call_VM
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4774
    // which has the ability to fetch the return PC out of
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4775
    // thread-local storage and also sets up last_Java_sp slightly
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4776
    // differently than the real call_VM
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4777
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4778
    __ enter(); // Save FP and LR before call
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4779
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4780
    assert(is_even(framesize/2), "sp not 16-byte aligned");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4781
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4782
    // lr and fp are already in place
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4783
    __ sub(sp, rfp, ((unsigned)framesize-4) << LogBytesPerInt); // prolog
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4784
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4785
    int frame_complete = __ pc() - start;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4786
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4787
    // Set up last_Java_sp and last_Java_fp
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4788
    address the_pc = __ pc();
53967
2bd3e05d4c6f 8209413: AArch64: NPE in clhsdb jstack command
ngasson
parents: 53950
diff changeset
  4789
    __ set_last_Java_frame(sp, rfp, the_pc, rscratch1);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4790
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4791
    // Call runtime
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4792
    if (arg1 != noreg) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4793
      assert(arg2 != c_rarg1, "clobbered");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4794
      __ mov(c_rarg1, arg1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4795
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4796
    if (arg2 != noreg) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4797
      __ mov(c_rarg2, arg2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4798
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4799
    __ mov(c_rarg0, rthread);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4800
    BLOCK_COMMENT("call runtime_entry");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4801
    __ mov(rscratch1, runtime_entry);
57565
01bca26734bb 8228400: Remove built-in AArch64 simulator
shade
parents: 55490
diff changeset
  4802
    __ blr(rscratch1);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4803
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4804
    // Generate oop map
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4805
    OopMap* map = new OopMap(framesize, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4806
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4807
    oop_maps->add_gc_map(the_pc - start, map);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4808
40643
49539fc14e5a 8164113: AArch64: follow-up the fix for 8161598
aph
parents: 40080
diff changeset
  4809
    __ reset_last_Java_frame(true);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4810
    __ maybe_isb();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4811
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4812
    __ leave();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4813
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4814
    // check for pending exceptions
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4815
#ifdef ASSERT
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4816
    Label L;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4817
    __ ldr(rscratch1, Address(rthread, Thread::pending_exception_offset()));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4818
    __ cbnz(rscratch1, L);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4819
    __ should_not_reach_here();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4820
    __ bind(L);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4821
#endif // ASSERT
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4822
    __ far_jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4823
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4824
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4825
    // codeBlob framesize is in words (not VMRegImpl::slot_size)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4826
    RuntimeStub* stub =
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4827
      RuntimeStub::new_runtime_stub(name,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4828
                                    &code,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4829
                                    frame_complete,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4830
                                    (framesize >> (LogBytesPerWord - LogBytesPerInt)),
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4831
                                    oop_maps, false);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4832
    return stub->entry_point();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4833
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  4834
31955
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4835
  class MontgomeryMultiplyGenerator : public MacroAssembler {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4836
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4837
    Register Pa_base, Pb_base, Pn_base, Pm_base, inv, Rlen, Ra, Rb, Rm, Rn,
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4838
      Pa, Pb, Pn, Pm, Rhi_ab, Rlo_ab, Rhi_mn, Rlo_mn, t0, t1, t2, Ri, Rj;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4839
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4840
    RegSet _toSave;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4841
    bool _squaring;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4842
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4843
  public:
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4844
    MontgomeryMultiplyGenerator (Assembler *as, bool squaring)
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4845
      : MacroAssembler(as->code()), _squaring(squaring) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4846
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4847
      // Register allocation
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4848
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4849
      Register reg = c_rarg0;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4850
      Pa_base = reg;       // Argument registers
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4851
      if (squaring)
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4852
        Pb_base = Pa_base;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4853
      else
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4854
        Pb_base = ++reg;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4855
      Pn_base = ++reg;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4856
      Rlen= ++reg;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4857
      inv = ++reg;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4858
      Pm_base = ++reg;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4859
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4860
                          // Working registers:
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4861
      Ra =  ++reg;        // The current digit of a, b, n, and m.
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4862
      Rb =  ++reg;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4863
      Rm =  ++reg;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4864
      Rn =  ++reg;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4865
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4866
      Pa =  ++reg;        // Pointers to the current/next digit of a, b, n, and m.
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4867
      Pb =  ++reg;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4868
      Pm =  ++reg;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4869
      Pn =  ++reg;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4870
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4871
      t0 =  ++reg;        // Three registers which form a
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4872
      t1 =  ++reg;        // triple-precision accumuator.
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4873
      t2 =  ++reg;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4874
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4875
      Ri =  ++reg;        // Inner and outer loop indexes.
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4876
      Rj =  ++reg;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4877
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4878
      Rhi_ab = ++reg;     // Product registers: low and high parts
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4879
      Rlo_ab = ++reg;     // of a*b and m*n.
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4880
      Rhi_mn = ++reg;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4881
      Rlo_mn = ++reg;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4882
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4883
      // r19 and up are callee-saved.
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4884
      _toSave = RegSet::range(r19, reg) + Pm_base;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4885
    }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4886
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4887
  private:
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4888
    void save_regs() {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4889
      push(_toSave, sp);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4890
    }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4891
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4892
    void restore_regs() {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4893
      pop(_toSave, sp);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4894
    }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4895
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4896
    template <typename T>
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4897
    void unroll_2(Register count, T block) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4898
      Label loop, end, odd;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4899
      tbnz(count, 0, odd);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4900
      cbz(count, end);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4901
      align(16);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4902
      bind(loop);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4903
      (this->*block)();
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4904
      bind(odd);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4905
      (this->*block)();
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4906
      subs(count, count, 2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4907
      br(Assembler::GT, loop);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4908
      bind(end);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4909
    }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4910
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4911
    template <typename T>
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4912
    void unroll_2(Register count, T block, Register d, Register s, Register tmp) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4913
      Label loop, end, odd;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4914
      tbnz(count, 0, odd);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4915
      cbz(count, end);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4916
      align(16);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4917
      bind(loop);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4918
      (this->*block)(d, s, tmp);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4919
      bind(odd);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4920
      (this->*block)(d, s, tmp);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4921
      subs(count, count, 2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4922
      br(Assembler::GT, loop);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4923
      bind(end);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4924
    }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4925
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4926
    void pre1(RegisterOrConstant i) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4927
      block_comment("pre1");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4928
      // Pa = Pa_base;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4929
      // Pb = Pb_base + i;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4930
      // Pm = Pm_base;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4931
      // Pn = Pn_base + i;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4932
      // Ra = *Pa;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4933
      // Rb = *Pb;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4934
      // Rm = *Pm;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4935
      // Rn = *Pn;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4936
      ldr(Ra, Address(Pa_base));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4937
      ldr(Rb, Address(Pb_base, i, Address::uxtw(LogBytesPerWord)));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4938
      ldr(Rm, Address(Pm_base));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4939
      ldr(Rn, Address(Pn_base, i, Address::uxtw(LogBytesPerWord)));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4940
      lea(Pa, Address(Pa_base));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4941
      lea(Pb, Address(Pb_base, i, Address::uxtw(LogBytesPerWord)));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4942
      lea(Pm, Address(Pm_base));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4943
      lea(Pn, Address(Pn_base, i, Address::uxtw(LogBytesPerWord)));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4944
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4945
      // Zero the m*n result.
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4946
      mov(Rhi_mn, zr);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4947
      mov(Rlo_mn, zr);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4948
    }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4949
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4950
    // The core multiply-accumulate step of a Montgomery
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4951
    // multiplication.  The idea is to schedule operations as a
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4952
    // pipeline so that instructions with long latencies (loads and
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4953
    // multiplies) have time to complete before their results are
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4954
    // used.  This most benefits in-order implementations of the
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4955
    // architecture but out-of-order ones also benefit.
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4956
    void step() {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4957
      block_comment("step");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4958
      // MACC(Ra, Rb, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4959
      // Ra = *++Pa;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4960
      // Rb = *--Pb;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4961
      umulh(Rhi_ab, Ra, Rb);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4962
      mul(Rlo_ab, Ra, Rb);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4963
      ldr(Ra, pre(Pa, wordSize));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4964
      ldr(Rb, pre(Pb, -wordSize));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4965
      acc(Rhi_mn, Rlo_mn, t0, t1, t2); // The pending m*n from the
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4966
                                       // previous iteration.
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4967
      // MACC(Rm, Rn, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4968
      // Rm = *++Pm;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4969
      // Rn = *--Pn;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4970
      umulh(Rhi_mn, Rm, Rn);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4971
      mul(Rlo_mn, Rm, Rn);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4972
      ldr(Rm, pre(Pm, wordSize));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4973
      ldr(Rn, pre(Pn, -wordSize));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4974
      acc(Rhi_ab, Rlo_ab, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4975
    }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4976
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4977
    void post1() {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4978
      block_comment("post1");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4979
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4980
      // MACC(Ra, Rb, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4981
      // Ra = *++Pa;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4982
      // Rb = *--Pb;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4983
      umulh(Rhi_ab, Ra, Rb);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4984
      mul(Rlo_ab, Ra, Rb);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4985
      acc(Rhi_mn, Rlo_mn, t0, t1, t2);  // The pending m*n
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4986
      acc(Rhi_ab, Rlo_ab, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4987
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4988
      // *Pm = Rm = t0 * inv;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4989
      mul(Rm, t0, inv);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4990
      str(Rm, Address(Pm));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4991
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4992
      // MACC(Rm, Rn, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4993
      // t0 = t1; t1 = t2; t2 = 0;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4994
      umulh(Rhi_mn, Rm, Rn);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4995
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4996
#ifndef PRODUCT
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4997
      // assert(m[i] * n[0] + t0 == 0, "broken Montgomery multiply");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4998
      {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  4999
        mul(Rlo_mn, Rm, Rn);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5000
        add(Rlo_mn, t0, Rlo_mn);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5001
        Label ok;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5002
        cbz(Rlo_mn, ok); {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5003
          stop("broken Montgomery multiply");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5004
        } bind(ok);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5005
      }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5006
#endif
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5007
      // We have very carefully set things up so that
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5008
      // m[i]*n[0] + t0 == 0 (mod b), so we don't have to calculate
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5009
      // the lower half of Rm * Rn because we know the result already:
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5010
      // it must be -t0.  t0 + (-t0) must generate a carry iff
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5011
      // t0 != 0.  So, rather than do a mul and an adds we just set
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5012
      // the carry flag iff t0 is nonzero.
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5013
      //
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5014
      // mul(Rlo_mn, Rm, Rn);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5015
      // adds(zr, t0, Rlo_mn);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5016
      subs(zr, t0, 1); // Set carry iff t0 is nonzero
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5017
      adcs(t0, t1, Rhi_mn);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5018
      adc(t1, t2, zr);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5019
      mov(t2, zr);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5020
    }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5021
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5022
    void pre2(RegisterOrConstant i, RegisterOrConstant len) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5023
      block_comment("pre2");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5024
      // Pa = Pa_base + i-len;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5025
      // Pb = Pb_base + len;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5026
      // Pm = Pm_base + i-len;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5027
      // Pn = Pn_base + len;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5028
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5029
      if (i.is_register()) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5030
        sub(Rj, i.as_register(), len);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5031
      } else {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5032
        mov(Rj, i.as_constant());
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5033
        sub(Rj, Rj, len);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5034
      }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5035
      // Rj == i-len
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5036
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5037
      lea(Pa, Address(Pa_base, Rj, Address::uxtw(LogBytesPerWord)));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5038
      lea(Pb, Address(Pb_base, len, Address::uxtw(LogBytesPerWord)));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5039
      lea(Pm, Address(Pm_base, Rj, Address::uxtw(LogBytesPerWord)));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5040
      lea(Pn, Address(Pn_base, len, Address::uxtw(LogBytesPerWord)));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5041
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5042
      // Ra = *++Pa;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5043
      // Rb = *--Pb;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5044
      // Rm = *++Pm;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5045
      // Rn = *--Pn;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5046
      ldr(Ra, pre(Pa, wordSize));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5047
      ldr(Rb, pre(Pb, -wordSize));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5048
      ldr(Rm, pre(Pm, wordSize));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5049
      ldr(Rn, pre(Pn, -wordSize));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5050
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5051
      mov(Rhi_mn, zr);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5052
      mov(Rlo_mn, zr);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5053
    }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5054
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5055
    void post2(RegisterOrConstant i, RegisterOrConstant len) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5056
      block_comment("post2");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5057
      if (i.is_constant()) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5058
        mov(Rj, i.as_constant()-len.as_constant());
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5059
      } else {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5060
        sub(Rj, i.as_register(), len);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5061
      }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5062
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5063
      adds(t0, t0, Rlo_mn); // The pending m*n, low part
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5064
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5065
      // As soon as we know the least significant digit of our result,
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5066
      // store it.
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5067
      // Pm_base[i-len] = t0;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5068
      str(t0, Address(Pm_base, Rj, Address::uxtw(LogBytesPerWord)));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5069
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5070
      // t0 = t1; t1 = t2; t2 = 0;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5071
      adcs(t0, t1, Rhi_mn); // The pending m*n, high part
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5072
      adc(t1, t2, zr);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5073
      mov(t2, zr);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5074
    }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5075
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5076
    // A carry in t0 after Montgomery multiplication means that we
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5077
    // should subtract multiples of n from our result in m.  We'll
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5078
    // keep doing that until there is no carry.
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5079
    void normalize(RegisterOrConstant len) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5080
      block_comment("normalize");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5081
      // while (t0)
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5082
      //   t0 = sub(Pm_base, Pn_base, t0, len);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5083
      Label loop, post, again;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5084
      Register cnt = t1, i = t2; // Re-use registers; we're done with them now
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5085
      cbz(t0, post); {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5086
        bind(again); {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5087
          mov(i, zr);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5088
          mov(cnt, len);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5089
          ldr(Rm, Address(Pm_base, i, Address::uxtw(LogBytesPerWord)));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5090
          ldr(Rn, Address(Pn_base, i, Address::uxtw(LogBytesPerWord)));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5091
          subs(zr, zr, zr); // set carry flag, i.e. no borrow
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5092
          align(16);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5093
          bind(loop); {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5094
            sbcs(Rm, Rm, Rn);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5095
            str(Rm, Address(Pm_base, i, Address::uxtw(LogBytesPerWord)));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5096
            add(i, i, 1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5097
            ldr(Rm, Address(Pm_base, i, Address::uxtw(LogBytesPerWord)));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5098
            ldr(Rn, Address(Pn_base, i, Address::uxtw(LogBytesPerWord)));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5099
            sub(cnt, cnt, 1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5100
          } cbnz(cnt, loop);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5101
          sbc(t0, t0, zr);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5102
        } cbnz(t0, again);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5103
      } bind(post);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5104
    }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5105
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5106
    // Move memory at s to d, reversing words.
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5107
    //    Increments d to end of copied memory
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5108
    //    Destroys tmp1, tmp2
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5109
    //    Preserves len
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5110
    //    Leaves s pointing to the address which was in d at start
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5111
    void reverse(Register d, Register s, Register len, Register tmp1, Register tmp2) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5112
      assert(tmp1 < r19 && tmp2 < r19, "register corruption");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5113
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5114
      lea(s, Address(s, len, Address::uxtw(LogBytesPerWord)));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5115
      mov(tmp1, len);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5116
      unroll_2(tmp1, &MontgomeryMultiplyGenerator::reverse1, d, s, tmp2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5117
      sub(s, d, len, ext::uxtw, LogBytesPerWord);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5118
    }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5119
    // where
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5120
    void reverse1(Register d, Register s, Register tmp) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5121
      ldr(tmp, pre(s, -wordSize));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5122
      ror(tmp, tmp, 32);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5123
      str(tmp, post(d, wordSize));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5124
    }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5125
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5126
    void step_squaring() {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5127
      // An extra ACC
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5128
      step();
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5129
      acc(Rhi_ab, Rlo_ab, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5130
    }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5131
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5132
    void last_squaring(RegisterOrConstant i) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5133
      Label dont;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5134
      // if ((i & 1) == 0) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5135
      tbnz(i.as_register(), 0, dont); {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5136
        // MACC(Ra, Rb, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5137
        // Ra = *++Pa;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5138
        // Rb = *--Pb;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5139
        umulh(Rhi_ab, Ra, Rb);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5140
        mul(Rlo_ab, Ra, Rb);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5141
        acc(Rhi_ab, Rlo_ab, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5142
      } bind(dont);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5143
    }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5144
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5145
    void extra_step_squaring() {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5146
      acc(Rhi_mn, Rlo_mn, t0, t1, t2);  // The pending m*n
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5147
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5148
      // MACC(Rm, Rn, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5149
      // Rm = *++Pm;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5150
      // Rn = *--Pn;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5151
      umulh(Rhi_mn, Rm, Rn);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5152
      mul(Rlo_mn, Rm, Rn);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5153
      ldr(Rm, pre(Pm, wordSize));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5154
      ldr(Rn, pre(Pn, -wordSize));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5155
    }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5156
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5157
    void post1_squaring() {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5158
      acc(Rhi_mn, Rlo_mn, t0, t1, t2);  // The pending m*n
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5159
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5160
      // *Pm = Rm = t0 * inv;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5161
      mul(Rm, t0, inv);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5162
      str(Rm, Address(Pm));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5163
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5164
      // MACC(Rm, Rn, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5165
      // t0 = t1; t1 = t2; t2 = 0;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5166
      umulh(Rhi_mn, Rm, Rn);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5167
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5168
#ifndef PRODUCT
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5169
      // assert(m[i] * n[0] + t0 == 0, "broken Montgomery multiply");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5170
      {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5171
        mul(Rlo_mn, Rm, Rn);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5172
        add(Rlo_mn, t0, Rlo_mn);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5173
        Label ok;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5174
        cbz(Rlo_mn, ok); {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5175
          stop("broken Montgomery multiply");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5176
        } bind(ok);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5177
      }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5178
#endif
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5179
      // We have very carefully set things up so that
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5180
      // m[i]*n[0] + t0 == 0 (mod b), so we don't have to calculate
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5181
      // the lower half of Rm * Rn because we know the result already:
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5182
      // it must be -t0.  t0 + (-t0) must generate a carry iff
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5183
      // t0 != 0.  So, rather than do a mul and an adds we just set
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5184
      // the carry flag iff t0 is nonzero.
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5185
      //
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5186
      // mul(Rlo_mn, Rm, Rn);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5187
      // adds(zr, t0, Rlo_mn);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5188
      subs(zr, t0, 1); // Set carry iff t0 is nonzero
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5189
      adcs(t0, t1, Rhi_mn);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5190
      adc(t1, t2, zr);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5191
      mov(t2, zr);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5192
    }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5193
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5194
    void acc(Register Rhi, Register Rlo,
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5195
             Register t0, Register t1, Register t2) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5196
      adds(t0, t0, Rlo);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5197
      adcs(t1, t1, Rhi);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5198
      adc(t2, t2, zr);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5199
    }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5200
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5201
  public:
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5202
    /**
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5203
     * Fast Montgomery multiplication.  The derivation of the
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5204
     * algorithm is in A Cryptographic Library for the Motorola
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5205
     * DSP56000, Dusse and Kaliski, Proc. EUROCRYPT 90, pp. 230-237.
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5206
     *
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5207
     * Arguments:
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5208
     *
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5209
     * Inputs for multiplication:
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5210
     *   c_rarg0   - int array elements a
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5211
     *   c_rarg1   - int array elements b
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5212
     *   c_rarg2   - int array elements n (the modulus)
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5213
     *   c_rarg3   - int length
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5214
     *   c_rarg4   - int inv
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5215
     *   c_rarg5   - int array elements m (the result)
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5216
     *
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5217
     * Inputs for squaring:
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5218
     *   c_rarg0   - int array elements a
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5219
     *   c_rarg1   - int array elements n (the modulus)
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5220
     *   c_rarg2   - int length
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5221
     *   c_rarg3   - int inv
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5222
     *   c_rarg4   - int array elements m (the result)
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5223
     *
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5224
     */
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5225
    address generate_multiply() {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5226
      Label argh, nothing;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5227
      bind(argh);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5228
      stop("MontgomeryMultiply total_allocation must be <= 8192");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5229
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5230
      align(CodeEntryAlignment);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5231
      address entry = pc();
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5232
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5233
      cbzw(Rlen, nothing);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5234
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5235
      enter();
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5236
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5237
      // Make room.
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5238
      cmpw(Rlen, 512);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5239
      br(Assembler::HI, argh);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5240
      sub(Ra, sp, Rlen, ext::uxtw, exact_log2(4 * sizeof (jint)));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5241
      andr(sp, Ra, -2 * wordSize);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5242
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5243
      lsrw(Rlen, Rlen, 1);  // length in longwords = len/2
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5244
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5245
      {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5246
        // Copy input args, reversing as we go.  We use Ra as a
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5247
        // temporary variable.
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5248
        reverse(Ra, Pa_base, Rlen, t0, t1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5249
        if (!_squaring)
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5250
          reverse(Ra, Pb_base, Rlen, t0, t1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5251
        reverse(Ra, Pn_base, Rlen, t0, t1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5252
      }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5253
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5254
      // Push all call-saved registers and also Pm_base which we'll need
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5255
      // at the end.
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5256
      save_regs();
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5257
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5258
#ifndef PRODUCT
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5259
      // assert(inv * n[0] == -1UL, "broken inverse in Montgomery multiply");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5260
      {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5261
        ldr(Rn, Address(Pn_base, 0));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5262
        mul(Rlo_mn, Rn, inv);
51374
7be0084191ed 8206895: aarch64: rework error-prone cmp instuction
bulasevich
parents: 50758
diff changeset
  5263
        subs(zr, Rlo_mn, -1);
31955
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5264
        Label ok;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5265
        br(EQ, ok); {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5266
          stop("broken inverse in Montgomery multiply");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5267
        } bind(ok);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5268
      }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5269
#endif
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5270
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5271
      mov(Pm_base, Ra);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5272
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5273
      mov(t0, zr);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5274
      mov(t1, zr);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5275
      mov(t2, zr);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5276
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5277
      block_comment("for (int i = 0; i < len; i++) {");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5278
      mov(Ri, zr); {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5279
        Label loop, end;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5280
        cmpw(Ri, Rlen);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5281
        br(Assembler::GE, end);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5282
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5283
        bind(loop);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5284
        pre1(Ri);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5285
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5286
        block_comment("  for (j = i; j; j--) {"); {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5287
          movw(Rj, Ri);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5288
          unroll_2(Rj, &MontgomeryMultiplyGenerator::step);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5289
        } block_comment("  } // j");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5290
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5291
        post1();
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5292
        addw(Ri, Ri, 1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5293
        cmpw(Ri, Rlen);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5294
        br(Assembler::LT, loop);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5295
        bind(end);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5296
        block_comment("} // i");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5297
      }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5298
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5299
      block_comment("for (int i = len; i < 2*len; i++) {");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5300
      mov(Ri, Rlen); {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5301
        Label loop, end;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5302
        cmpw(Ri, Rlen, Assembler::LSL, 1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5303
        br(Assembler::GE, end);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5304
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5305
        bind(loop);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5306
        pre2(Ri, Rlen);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5307
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5308
        block_comment("  for (j = len*2-i-1; j; j--) {"); {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5309
          lslw(Rj, Rlen, 1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5310
          subw(Rj, Rj, Ri);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5311
          subw(Rj, Rj, 1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5312
          unroll_2(Rj, &MontgomeryMultiplyGenerator::step);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5313
        } block_comment("  } // j");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5314
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5315
        post2(Ri, Rlen);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5316
        addw(Ri, Ri, 1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5317
        cmpw(Ri, Rlen, Assembler::LSL, 1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5318
        br(Assembler::LT, loop);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5319
        bind(end);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5320
      }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5321
      block_comment("} // i");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5322
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5323
      normalize(Rlen);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5324
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5325
      mov(Ra, Pm_base);  // Save Pm_base in Ra
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5326
      restore_regs();  // Restore caller's Pm_base
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5327
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5328
      // Copy our result into caller's Pm_base
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5329
      reverse(Pm_base, Ra, Rlen, t0, t1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5330
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5331
      leave();
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5332
      bind(nothing);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5333
      ret(lr);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5334
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5335
      return entry;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5336
    }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5337
    // In C, approximately:
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5338
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5339
    // void
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5340
    // montgomery_multiply(unsigned long Pa_base[], unsigned long Pb_base[],
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5341
    //                     unsigned long Pn_base[], unsigned long Pm_base[],
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5342
    //                     unsigned long inv, int len) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5343
    //   unsigned long t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5344
    //   unsigned long *Pa, *Pb, *Pn, *Pm;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5345
    //   unsigned long Ra, Rb, Rn, Rm;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5346
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5347
    //   int i;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5348
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5349
    //   assert(inv * Pn_base[0] == -1UL, "broken inverse in Montgomery multiply");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5350
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5351
    //   for (i = 0; i < len; i++) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5352
    //     int j;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5353
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5354
    //     Pa = Pa_base;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5355
    //     Pb = Pb_base + i;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5356
    //     Pm = Pm_base;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5357
    //     Pn = Pn_base + i;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5358
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5359
    //     Ra = *Pa;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5360
    //     Rb = *Pb;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5361
    //     Rm = *Pm;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5362
    //     Rn = *Pn;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5363
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5364
    //     int iters = i;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5365
    //     for (j = 0; iters--; j++) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5366
    //       assert(Ra == Pa_base[j] && Rb == Pb_base[i-j], "must be");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5367
    //       MACC(Ra, Rb, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5368
    //       Ra = *++Pa;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5369
    //       Rb = *--Pb;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5370
    //       assert(Rm == Pm_base[j] && Rn == Pn_base[i-j], "must be");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5371
    //       MACC(Rm, Rn, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5372
    //       Rm = *++Pm;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5373
    //       Rn = *--Pn;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5374
    //     }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5375
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5376
    //     assert(Ra == Pa_base[i] && Rb == Pb_base[0], "must be");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5377
    //     MACC(Ra, Rb, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5378
    //     *Pm = Rm = t0 * inv;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5379
    //     assert(Rm == Pm_base[i] && Rn == Pn_base[0], "must be");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5380
    //     MACC(Rm, Rn, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5381
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5382
    //     assert(t0 == 0, "broken Montgomery multiply");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5383
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5384
    //     t0 = t1; t1 = t2; t2 = 0;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5385
    //   }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5386
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5387
    //   for (i = len; i < 2*len; i++) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5388
    //     int j;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5389
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5390
    //     Pa = Pa_base + i-len;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5391
    //     Pb = Pb_base + len;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5392
    //     Pm = Pm_base + i-len;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5393
    //     Pn = Pn_base + len;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5394
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5395
    //     Ra = *++Pa;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5396
    //     Rb = *--Pb;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5397
    //     Rm = *++Pm;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5398
    //     Rn = *--Pn;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5399
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5400
    //     int iters = len*2-i-1;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5401
    //     for (j = i-len+1; iters--; j++) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5402
    //       assert(Ra == Pa_base[j] && Rb == Pb_base[i-j], "must be");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5403
    //       MACC(Ra, Rb, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5404
    //       Ra = *++Pa;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5405
    //       Rb = *--Pb;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5406
    //       assert(Rm == Pm_base[j] && Rn == Pn_base[i-j], "must be");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5407
    //       MACC(Rm, Rn, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5408
    //       Rm = *++Pm;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5409
    //       Rn = *--Pn;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5410
    //     }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5411
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5412
    //     Pm_base[i-len] = t0;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5413
    //     t0 = t1; t1 = t2; t2 = 0;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5414
    //   }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5415
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5416
    //   while (t0)
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5417
    //     t0 = sub(Pm_base, Pn_base, t0, len);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5418
    // }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5419
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5420
    /**
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5421
     * Fast Montgomery squaring.  This uses asymptotically 25% fewer
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5422
     * multiplies than Montgomery multiplication so it should be up to
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5423
     * 25% faster.  However, its loop control is more complex and it
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5424
     * may actually run slower on some machines.
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5425
     *
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5426
     * Arguments:
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5427
     *
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5428
     * Inputs:
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5429
     *   c_rarg0   - int array elements a
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5430
     *   c_rarg1   - int array elements n (the modulus)
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5431
     *   c_rarg2   - int length
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5432
     *   c_rarg3   - int inv
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5433
     *   c_rarg4   - int array elements m (the result)
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5434
     *
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5435
     */
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5436
    address generate_square() {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5437
      Label argh;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5438
      bind(argh);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5439
      stop("MontgomeryMultiply total_allocation must be <= 8192");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5440
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5441
      align(CodeEntryAlignment);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5442
      address entry = pc();
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5443
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5444
      enter();
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5445
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5446
      // Make room.
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5447
      cmpw(Rlen, 512);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5448
      br(Assembler::HI, argh);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5449
      sub(Ra, sp, Rlen, ext::uxtw, exact_log2(4 * sizeof (jint)));
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5450
      andr(sp, Ra, -2 * wordSize);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5451
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5452
      lsrw(Rlen, Rlen, 1);  // length in longwords = len/2
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5453
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5454
      {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5455
        // Copy input args, reversing as we go.  We use Ra as a
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5456
        // temporary variable.
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5457
        reverse(Ra, Pa_base, Rlen, t0, t1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5458
        reverse(Ra, Pn_base, Rlen, t0, t1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5459
      }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5460
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5461
      // Push all call-saved registers and also Pm_base which we'll need
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5462
      // at the end.
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5463
      save_regs();
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5464
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5465
      mov(Pm_base, Ra);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5466
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5467
      mov(t0, zr);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5468
      mov(t1, zr);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5469
      mov(t2, zr);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5470
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5471
      block_comment("for (int i = 0; i < len; i++) {");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5472
      mov(Ri, zr); {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5473
        Label loop, end;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5474
        bind(loop);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5475
        cmp(Ri, Rlen);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5476
        br(Assembler::GE, end);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5477
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5478
        pre1(Ri);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5479
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5480
        block_comment("for (j = (i+1)/2; j; j--) {"); {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5481
          add(Rj, Ri, 1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5482
          lsr(Rj, Rj, 1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5483
          unroll_2(Rj, &MontgomeryMultiplyGenerator::step_squaring);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5484
        } block_comment("  } // j");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5485
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5486
        last_squaring(Ri);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5487
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5488
        block_comment("  for (j = i/2; j; j--) {"); {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5489
          lsr(Rj, Ri, 1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5490
          unroll_2(Rj, &MontgomeryMultiplyGenerator::extra_step_squaring);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5491
        } block_comment("  } // j");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5492
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5493
        post1_squaring();
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5494
        add(Ri, Ri, 1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5495
        cmp(Ri, Rlen);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5496
        br(Assembler::LT, loop);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5497
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5498
        bind(end);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5499
        block_comment("} // i");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5500
      }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5501
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5502
      block_comment("for (int i = len; i < 2*len; i++) {");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5503
      mov(Ri, Rlen); {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5504
        Label loop, end;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5505
        bind(loop);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5506
        cmp(Ri, Rlen, Assembler::LSL, 1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5507
        br(Assembler::GE, end);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5508
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5509
        pre2(Ri, Rlen);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5510
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5511
        block_comment("  for (j = (2*len-i-1)/2; j; j--) {"); {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5512
          lsl(Rj, Rlen, 1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5513
          sub(Rj, Rj, Ri);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5514
          sub(Rj, Rj, 1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5515
          lsr(Rj, Rj, 1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5516
          unroll_2(Rj, &MontgomeryMultiplyGenerator::step_squaring);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5517
        } block_comment("  } // j");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5518
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5519
        last_squaring(Ri);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5520
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5521
        block_comment("  for (j = (2*len-i)/2; j; j--) {"); {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5522
          lsl(Rj, Rlen, 1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5523
          sub(Rj, Rj, Ri);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5524
          lsr(Rj, Rj, 1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5525
          unroll_2(Rj, &MontgomeryMultiplyGenerator::extra_step_squaring);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5526
        } block_comment("  } // j");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5527
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5528
        post2(Ri, Rlen);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5529
        add(Ri, Ri, 1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5530
        cmp(Ri, Rlen, Assembler::LSL, 1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5531
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5532
        br(Assembler::LT, loop);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5533
        bind(end);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5534
        block_comment("} // i");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5535
      }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5536
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5537
      normalize(Rlen);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5538
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5539
      mov(Ra, Pm_base);  // Save Pm_base in Ra
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5540
      restore_regs();  // Restore caller's Pm_base
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5541
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5542
      // Copy our result into caller's Pm_base
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5543
      reverse(Pm_base, Ra, Rlen, t0, t1);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5544
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5545
      leave();
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5546
      ret(lr);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5547
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5548
      return entry;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5549
    }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5550
    // In C, approximately:
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5551
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5552
    // void
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5553
    // montgomery_square(unsigned long Pa_base[], unsigned long Pn_base[],
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5554
    //                   unsigned long Pm_base[], unsigned long inv, int len) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5555
    //   unsigned long t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5556
    //   unsigned long *Pa, *Pb, *Pn, *Pm;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5557
    //   unsigned long Ra, Rb, Rn, Rm;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5558
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5559
    //   int i;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5560
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5561
    //   assert(inv * Pn_base[0] == -1UL, "broken inverse in Montgomery multiply");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5562
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5563
    //   for (i = 0; i < len; i++) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5564
    //     int j;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5565
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5566
    //     Pa = Pa_base;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5567
    //     Pb = Pa_base + i;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5568
    //     Pm = Pm_base;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5569
    //     Pn = Pn_base + i;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5570
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5571
    //     Ra = *Pa;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5572
    //     Rb = *Pb;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5573
    //     Rm = *Pm;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5574
    //     Rn = *Pn;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5575
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5576
    //     int iters = (i+1)/2;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5577
    //     for (j = 0; iters--; j++) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5578
    //       assert(Ra == Pa_base[j] && Rb == Pa_base[i-j], "must be");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5579
    //       MACC2(Ra, Rb, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5580
    //       Ra = *++Pa;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5581
    //       Rb = *--Pb;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5582
    //       assert(Rm == Pm_base[j] && Rn == Pn_base[i-j], "must be");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5583
    //       MACC(Rm, Rn, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5584
    //       Rm = *++Pm;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5585
    //       Rn = *--Pn;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5586
    //     }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5587
    //     if ((i & 1) == 0) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5588
    //       assert(Ra == Pa_base[j], "must be");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5589
    //       MACC(Ra, Ra, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5590
    //     }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5591
    //     iters = i/2;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5592
    //     assert(iters == i-j, "must be");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5593
    //     for (; iters--; j++) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5594
    //       assert(Rm == Pm_base[j] && Rn == Pn_base[i-j], "must be");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5595
    //       MACC(Rm, Rn, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5596
    //       Rm = *++Pm;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5597
    //       Rn = *--Pn;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5598
    //     }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5599
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5600
    //     *Pm = Rm = t0 * inv;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5601
    //     assert(Rm == Pm_base[i] && Rn == Pn_base[0], "must be");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5602
    //     MACC(Rm, Rn, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5603
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5604
    //     assert(t0 == 0, "broken Montgomery multiply");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5605
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5606
    //     t0 = t1; t1 = t2; t2 = 0;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5607
    //   }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5608
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5609
    //   for (i = len; i < 2*len; i++) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5610
    //     int start = i-len+1;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5611
    //     int end = start + (len - start)/2;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5612
    //     int j;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5613
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5614
    //     Pa = Pa_base + i-len;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5615
    //     Pb = Pa_base + len;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5616
    //     Pm = Pm_base + i-len;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5617
    //     Pn = Pn_base + len;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5618
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5619
    //     Ra = *++Pa;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5620
    //     Rb = *--Pb;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5621
    //     Rm = *++Pm;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5622
    //     Rn = *--Pn;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5623
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5624
    //     int iters = (2*len-i-1)/2;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5625
    //     assert(iters == end-start, "must be");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5626
    //     for (j = start; iters--; j++) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5627
    //       assert(Ra == Pa_base[j] && Rb == Pa_base[i-j], "must be");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5628
    //       MACC2(Ra, Rb, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5629
    //       Ra = *++Pa;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5630
    //       Rb = *--Pb;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5631
    //       assert(Rm == Pm_base[j] && Rn == Pn_base[i-j], "must be");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5632
    //       MACC(Rm, Rn, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5633
    //       Rm = *++Pm;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5634
    //       Rn = *--Pn;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5635
    //     }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5636
    //     if ((i & 1) == 0) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5637
    //       assert(Ra == Pa_base[j], "must be");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5638
    //       MACC(Ra, Ra, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5639
    //     }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5640
    //     iters =  (2*len-i)/2;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5641
    //     assert(iters == len-j, "must be");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5642
    //     for (; iters--; j++) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5643
    //       assert(Rm == Pm_base[j] && Rn == Pn_base[i-j], "must be");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5644
    //       MACC(Rm, Rn, t0, t1, t2);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5645
    //       Rm = *++Pm;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5646
    //       Rn = *--Pn;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5647
    //     }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5648
    //     Pm_base[i-len] = t0;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5649
    //     t0 = t1; t1 = t2; t2 = 0;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5650
    //   }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5651
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5652
    //   while (t0)
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5653
    //     t0 = sub(Pm_base, Pn_base, t0, len);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5654
    // }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5655
  };
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5656
46814
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  5657
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5658
  // Initialization
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5659
  void generate_initial() {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5660
    // Generate initial stubs and initializes the entry points
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5661
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5662
    // entry points that exist in all platforms Note: This is code
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5663
    // that could be shared among different platforms - however the
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5664
    // benefit seems to be smaller than the disadvantage of having a
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5665
    // much more complicated generator structure. See also comment in
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5666
    // stubRoutines.hpp.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5667
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5668
    StubRoutines::_forward_exception_entry = generate_forward_exception();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5669
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5670
    StubRoutines::_call_stub_entry =
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5671
      generate_call_stub(StubRoutines::_call_stub_return_address);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5672
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5673
    // is referenced by megamorphic call
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5674
    StubRoutines::_catch_exception_entry = generate_catch_exception();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5675
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5676
    // Build this early so it's available for the interpreter.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5677
    StubRoutines::_throw_StackOverflowError_entry =
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5678
      generate_throw_exception("StackOverflowError throw_exception",
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5679
                               CAST_FROM_FN_PTR(address,
43439
5e03c9ba74f3 8172144: AArch64: Implement "JEP 270: Reserved Stack Areas for Critical Sections"
aph
parents: 42577
diff changeset
  5680
                                                SharedRuntime::throw_StackOverflowError));
5e03c9ba74f3 8172144: AArch64: Implement "JEP 270: Reserved Stack Areas for Critical Sections"
aph
parents: 42577
diff changeset
  5681
    StubRoutines::_throw_delayed_StackOverflowError_entry =
5e03c9ba74f3 8172144: AArch64: Implement "JEP 270: Reserved Stack Areas for Critical Sections"
aph
parents: 42577
diff changeset
  5682
      generate_throw_exception("delayed StackOverflowError throw_exception",
5e03c9ba74f3 8172144: AArch64: Implement "JEP 270: Reserved Stack Areas for Critical Sections"
aph
parents: 42577
diff changeset
  5683
                               CAST_FROM_FN_PTR(address,
5e03c9ba74f3 8172144: AArch64: Implement "JEP 270: Reserved Stack Areas for Critical Sections"
aph
parents: 42577
diff changeset
  5684
                                                SharedRuntime::throw_delayed_StackOverflowError));
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5685
    if (UseCRC32Intrinsics) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5686
      // set table address before stub generation which use it
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5687
      StubRoutines::_crc_table_adr = (address)StubRoutines::aarch64::_crc_table;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5688
      StubRoutines::_updateBytesCRC32 = generate_updateBytesCRC32();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5689
    }
47767
107622f2695c 8189745: AARCH64: Use CRC32C intrinsic code in interpreter and C1
dchuyko
parents: 47571
diff changeset
  5690
107622f2695c 8189745: AARCH64: Use CRC32C intrinsic code in interpreter and C1
dchuyko
parents: 47571
diff changeset
  5691
    if (UseCRC32CIntrinsics) {
107622f2695c 8189745: AARCH64: Use CRC32C intrinsic code in interpreter and C1
dchuyko
parents: 47571
diff changeset
  5692
      StubRoutines::_updateBytesCRC32C = generate_updateBytesCRC32C();
107622f2695c 8189745: AARCH64: Use CRC32C intrinsic code in interpreter and C1
dchuyko
parents: 47571
diff changeset
  5693
    }
50753
4449b45900f1 8196402: AARCH64: create intrinsic for Math.log
dpochepk
parents: 50728
diff changeset
  5694
52927
226c451bd954 8215133: AARCH64: disable Math.log intrinsic publishing
dpochepk
parents: 51756
diff changeset
  5695
    // Disabled until JDK-8210858 is fixed
226c451bd954 8215133: AARCH64: disable Math.log intrinsic publishing
dpochepk
parents: 51756
diff changeset
  5696
    // if (vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dlog)) {
226c451bd954 8215133: AARCH64: disable Math.log intrinsic publishing
dpochepk
parents: 51756
diff changeset
  5697
    //   StubRoutines::_dlog = generate_dlog();
226c451bd954 8215133: AARCH64: disable Math.log intrinsic publishing
dpochepk
parents: 51756
diff changeset
  5698
    // }
50755
680d04ae76e9 8204289: AARCH64: enable math intrinsics usage in interpreter and C1
dpochepk
parents: 50754
diff changeset
  5699
680d04ae76e9 8204289: AARCH64: enable math intrinsics usage in interpreter and C1
dpochepk
parents: 50754
diff changeset
  5700
    if (vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dsin)) {
680d04ae76e9 8204289: AARCH64: enable math intrinsics usage in interpreter and C1
dpochepk
parents: 50754
diff changeset
  5701
      StubRoutines::_dsin = generate_dsin_dcos(/* isCos = */ false);
680d04ae76e9 8204289: AARCH64: enable math intrinsics usage in interpreter and C1
dpochepk
parents: 50754
diff changeset
  5702
    }
680d04ae76e9 8204289: AARCH64: enable math intrinsics usage in interpreter and C1
dpochepk
parents: 50754
diff changeset
  5703
680d04ae76e9 8204289: AARCH64: enable math intrinsics usage in interpreter and C1
dpochepk
parents: 50754
diff changeset
  5704
    if (vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dcos)) {
680d04ae76e9 8204289: AARCH64: enable math intrinsics usage in interpreter and C1
dpochepk
parents: 50754
diff changeset
  5705
      StubRoutines::_dcos = generate_dsin_dcos(/* isCos = */ true);
680d04ae76e9 8204289: AARCH64: enable math intrinsics usage in interpreter and C1
dpochepk
parents: 50754
diff changeset
  5706
    }
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5707
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5708
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5709
  void generate_all() {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5710
    // support for verify_oop (must happen after universe_init)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5711
    StubRoutines::_verify_oop_subroutine_entry     = generate_verify_oop();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5712
    StubRoutines::_throw_AbstractMethodError_entry =
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5713
      generate_throw_exception("AbstractMethodError throw_exception",
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5714
                               CAST_FROM_FN_PTR(address,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5715
                                                SharedRuntime::
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5716
                                                throw_AbstractMethodError));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5717
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5718
    StubRoutines::_throw_IncompatibleClassChangeError_entry =
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5719
      generate_throw_exception("IncompatibleClassChangeError throw_exception",
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5720
                               CAST_FROM_FN_PTR(address,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5721
                                                SharedRuntime::
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5722
                                                throw_IncompatibleClassChangeError));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5723
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5724
    StubRoutines::_throw_NullPointerException_at_call_entry =
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5725
      generate_throw_exception("NullPointerException at call throw_exception",
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5726
                               CAST_FROM_FN_PTR(address,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5727
                                                SharedRuntime::
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5728
                                                throw_NullPointerException_at_call));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5729
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5730
    // arraycopy stubs used by compilers
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5731
    generate_arraycopy_stubs();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5732
46814
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  5733
    // has negatives stub for large arrays.
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  5734
    StubRoutines::aarch64::_has_negatives = generate_has_negatives(StubRoutines::aarch64::_has_negatives_long);
2e45cd2fdcb6 8184943: AARCH64: Intrinsify hasNegatives
dpochepk
parents: 46720
diff changeset
  5735
49724
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  5736
    // array equals stub for large arrays.
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  5737
    if (!UseSimpleArrayEquals) {
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  5738
      StubRoutines::aarch64::_large_array_equals = generate_large_array_equals();
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  5739
    }
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49484
diff changeset
  5740
50756
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  5741
    generate_compare_long_strings();
7ad092f40454 8202326: AARCH64: optimize string compare intrinsic
dpochepk
parents: 50755
diff changeset
  5742
50757
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  5743
    generate_string_indexof_stubs();
866c9aa29ee4 8189103: AARCH64: optimize String indexOf intrinsic
dpochepk
parents: 50756
diff changeset
  5744
50758
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  5745
    // byte_array_inflate stub for large arrays.
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  5746
    StubRoutines::aarch64::_large_byte_array_inflate = generate_large_byte_array_inflate();
afca3c78ea0f 8189113: AARCH64: StringLatin1 inflate intrinsic doesn't use prefetch instruction
dpochepk
parents: 50757
diff changeset
  5747
51619
dca697c71e5d 8207247: AARCH64: Enable Minimal and Client VM builds
avoitylov
parents: 51374
diff changeset
  5748
#ifdef COMPILER2
30225
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  5749
    if (UseMultiplyToLenIntrinsic) {
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  5750
      StubRoutines::_multiplyToLen = generate_multiplyToLen();
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  5751
    }
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29695
diff changeset
  5752
47571
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  5753
    if (UseSquareToLenIntrinsic) {
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  5754
      StubRoutines::_squareToLen = generate_squareToLen();
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  5755
    }
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  5756
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  5757
    if (UseMulAddIntrinsic) {
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  5758
      StubRoutines::_mulAdd = generate_mulAdd();
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  5759
    }
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
  5760
31955
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5761
    if (UseMontgomeryMultiplyIntrinsic) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5762
      StubCodeMark mark(this, "StubRoutines", "montgomeryMultiply");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5763
      MontgomeryMultiplyGenerator g(_masm, /*squaring*/false);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5764
      StubRoutines::_montgomeryMultiply = g.generate_multiply();
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5765
    }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5766
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5767
    if (UseMontgomerySquareIntrinsic) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5768
      StubCodeMark mark(this, "StubRoutines", "montgomerySquare");
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5769
      MontgomeryMultiplyGenerator g(_masm, /*squaring*/true);
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5770
      // We use generate_multiply() rather than generate_square()
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5771
      // because it's faster for the sizes of modulus we care about.
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5772
      StubRoutines::_montgomerySquare = g.generate_multiply();
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5773
    }
51619
dca697c71e5d 8207247: AARCH64: Enable Minimal and Client VM builds
avoitylov
parents: 51374
diff changeset
  5774
#endif // COMPILER2
31955
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
  5775
31961
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  5776
    // generate GHASH intrinsics code
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  5777
    if (UseGHASHIntrinsics) {
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  5778
      StubRoutines::_ghash_processBlocks = generate_ghash_processBlocks();
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  5779
    }
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31955
diff changeset
  5780
57804
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  5781
    // data cache line writeback
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  5782
    StubRoutines::_data_cache_writeback = generate_data_cache_writeback();
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  5783
    StubRoutines::_data_cache_writeback_sync = generate_data_cache_writeback_sync();
9b7b9f16dfd9 8224974: Implement JEP 352
adinn
parents: 57565
diff changeset
  5784
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5785
    if (UseAESIntrinsics) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5786
      StubRoutines::_aescrypt_encryptBlock = generate_aescrypt_encryptBlock();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5787
      StubRoutines::_aescrypt_decryptBlock = generate_aescrypt_decryptBlock();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5788
      StubRoutines::_cipherBlockChaining_encryptAESCrypt = generate_cipherBlockChaining_encryptAESCrypt();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5789
      StubRoutines::_cipherBlockChaining_decryptAESCrypt = generate_cipherBlockChaining_decryptAESCrypt();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5790
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5791
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5792
    if (UseSHA1Intrinsics) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5793
      StubRoutines::_sha1_implCompress     = generate_sha1_implCompress(false,   "sha1_implCompress");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5794
      StubRoutines::_sha1_implCompressMB   = generate_sha1_implCompress(true,    "sha1_implCompressMB");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5795
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5796
    if (UseSHA256Intrinsics) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5797
      StubRoutines::_sha256_implCompress   = generate_sha256_implCompress(false, "sha256_implCompress");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5798
      StubRoutines::_sha256_implCompressMB = generate_sha256_implCompress(true,  "sha256_implCompressMB");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5799
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5800
33176
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  5801
    // generate Adler32 intrinsics code
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  5802
    if (UseAdler32Intrinsics) {
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  5803
      StubRoutines::_updateBytesAdler32 = generate_updateBytesAdler32();
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  5804
    }
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32627
diff changeset
  5805
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5806
    // Safefetch stubs.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5807
    generate_safefetch("SafeFetch32", sizeof(int),     &StubRoutines::_safefetch32_entry,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5808
                                                       &StubRoutines::_safefetch32_fault_pc,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5809
                                                       &StubRoutines::_safefetch32_continuation_pc);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5810
    generate_safefetch("SafeFetchN", sizeof(intptr_t), &StubRoutines::_safefetchN_entry,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5811
                                                       &StubRoutines::_safefetchN_fault_pc,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5812
                                                       &StubRoutines::_safefetchN_continuation_pc);
45054
c09733aaf97f 8179444: AArch64: Put zero_words on a diet
aph
parents: 43439
diff changeset
  5813
    StubRoutines::aarch64::set_completed();
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5814
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5815
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5816
 public:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5817
  StubGenerator(CodeBuffer* code, bool all) : StubCodeGenerator(code) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5818
    if (all) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5819
      generate_all();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5820
    } else {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5821
      generate_initial();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5822
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5823
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5824
}; // end class declaration
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5825
55490
3f3dc00a69a5 8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents: 55379
diff changeset
  5826
#define UCM_TABLE_MAX_ENTRIES 8
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5827
void StubGenerator_generate(CodeBuffer* code, bool all) {
55490
3f3dc00a69a5 8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents: 55379
diff changeset
  5828
  if (UnsafeCopyMemory::_table == NULL) {
3f3dc00a69a5 8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents: 55379
diff changeset
  5829
    UnsafeCopyMemory::create_table(UCM_TABLE_MAX_ENTRIES);
3f3dc00a69a5 8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents: 55379
diff changeset
  5830
  }
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5831
  StubGenerator g(code, all);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  5832
}