author | coleenp |
Thu, 10 Jan 2019 15:13:51 -0500 | |
changeset 53244 | 9807daeb47c4 |
parent 47216 | 71c04702a3d5 |
permissions | -rw-r--r-- |
29184 | 1 |
/* |
53244
9807daeb47c4
8216167: Update include guards to reflect correct directories
coleenp
parents:
47216
diff
changeset
|
2 |
* Copyright (c) 1999, 2019, Oracle and/or its affiliates. All rights reserved. |
29184 | 3 |
* Copyright (c) 2014, Red Hat Inc. All rights reserved. |
4 |
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
|
5 |
* |
|
6 |
* This code is free software; you can redistribute it and/or modify it |
|
7 |
* under the terms of the GNU General Public License version 2 only, as |
|
8 |
* published by the Free Software Foundation. |
|
9 |
* |
|
10 |
* This code is distributed in the hope that it will be useful, but WITHOUT |
|
11 |
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
|
12 |
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
|
13 |
* version 2 for more details (a copy is included in the LICENSE file that |
|
14 |
* accompanied this code). |
|
15 |
* |
|
16 |
* You should have received a copy of the GNU General Public License version |
|
17 |
* 2 along with this work; if not, write to the Free Software Foundation, |
|
18 |
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
|
19 |
* |
|
20 |
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
21 |
* or visit www.oracle.com if you need additional information or have any |
|
22 |
* questions. |
|
23 |
* |
|
24 |
*/ |
|
25 |
||
53244
9807daeb47c4
8216167: Update include guards to reflect correct directories
coleenp
parents:
47216
diff
changeset
|
26 |
#ifndef CPU_AARCH64_C1_FRAMEMAP_AARCH64_HPP |
9807daeb47c4
8216167: Update include guards to reflect correct directories
coleenp
parents:
47216
diff
changeset
|
27 |
#define CPU_AARCH64_C1_FRAMEMAP_AARCH64_HPP |
29184 | 28 |
|
29 |
// On AArch64 the frame looks as follows: |
|
30 |
// |
|
31 |
// +-----------------------------+---------+----------------------------------------+----------------+----------- |
|
32 |
// | size_arguments-nof_reg_args | 2 words | size_locals-size_arguments+numreg_args | _size_monitors | spilling . |
|
33 |
// +-----------------------------+---------+----------------------------------------+----------------+----------- |
|
34 |
||
35 |
public: |
|
36 |
static const int pd_c_runtime_reserved_arg_size; |
|
37 |
||
38 |
enum { |
|
39 |
first_available_sp_in_frame = 0, |
|
40 |
frame_pad_in_bytes = 16, |
|
41 |
nof_reg_args = 8 |
|
42 |
}; |
|
43 |
||
44 |
public: |
|
45 |
static LIR_Opr receiver_opr; |
|
46 |
||
47 |
static LIR_Opr r0_opr; |
|
48 |
static LIR_Opr r1_opr; |
|
49 |
static LIR_Opr r2_opr; |
|
50 |
static LIR_Opr r3_opr; |
|
51 |
static LIR_Opr r4_opr; |
|
52 |
static LIR_Opr r5_opr; |
|
53 |
static LIR_Opr r6_opr; |
|
54 |
static LIR_Opr r7_opr; |
|
55 |
static LIR_Opr r8_opr; |
|
56 |
static LIR_Opr r9_opr; |
|
57 |
static LIR_Opr r10_opr; |
|
58 |
static LIR_Opr r11_opr; |
|
59 |
static LIR_Opr r12_opr; |
|
60 |
static LIR_Opr r13_opr; |
|
61 |
static LIR_Opr r14_opr; |
|
62 |
static LIR_Opr r15_opr; |
|
63 |
static LIR_Opr r16_opr; |
|
64 |
static LIR_Opr r17_opr; |
|
65 |
static LIR_Opr r18_opr; |
|
66 |
static LIR_Opr r19_opr; |
|
67 |
static LIR_Opr r20_opr; |
|
68 |
static LIR_Opr r21_opr; |
|
69 |
static LIR_Opr r22_opr; |
|
70 |
static LIR_Opr r23_opr; |
|
71 |
static LIR_Opr r24_opr; |
|
72 |
static LIR_Opr r25_opr; |
|
73 |
static LIR_Opr r26_opr; |
|
74 |
static LIR_Opr r27_opr; |
|
75 |
static LIR_Opr r28_opr; |
|
76 |
static LIR_Opr r29_opr; |
|
77 |
static LIR_Opr r30_opr; |
|
78 |
static LIR_Opr rfp_opr; |
|
79 |
static LIR_Opr sp_opr; |
|
80 |
||
81 |
static LIR_Opr r0_oop_opr; |
|
82 |
static LIR_Opr r1_oop_opr; |
|
83 |
static LIR_Opr r2_oop_opr; |
|
84 |
static LIR_Opr r3_oop_opr; |
|
85 |
static LIR_Opr r4_oop_opr; |
|
86 |
static LIR_Opr r5_oop_opr; |
|
87 |
static LIR_Opr r6_oop_opr; |
|
88 |
static LIR_Opr r7_oop_opr; |
|
89 |
static LIR_Opr r8_oop_opr; |
|
90 |
static LIR_Opr r9_oop_opr; |
|
91 |
static LIR_Opr r10_oop_opr; |
|
92 |
static LIR_Opr r11_oop_opr; |
|
93 |
static LIR_Opr r12_oop_opr; |
|
94 |
static LIR_Opr r13_oop_opr; |
|
95 |
static LIR_Opr r14_oop_opr; |
|
96 |
static LIR_Opr r15_oop_opr; |
|
97 |
static LIR_Opr r16_oop_opr; |
|
98 |
static LIR_Opr r17_oop_opr; |
|
99 |
static LIR_Opr r18_oop_opr; |
|
100 |
static LIR_Opr r19_oop_opr; |
|
101 |
static LIR_Opr r20_oop_opr; |
|
102 |
static LIR_Opr r21_oop_opr; |
|
103 |
static LIR_Opr r22_oop_opr; |
|
104 |
static LIR_Opr r23_oop_opr; |
|
105 |
static LIR_Opr r24_oop_opr; |
|
106 |
static LIR_Opr r25_oop_opr; |
|
107 |
static LIR_Opr r26_oop_opr; |
|
108 |
static LIR_Opr r27_oop_opr; |
|
109 |
static LIR_Opr r28_oop_opr; |
|
110 |
static LIR_Opr r29_oop_opr; |
|
111 |
static LIR_Opr r30_oop_opr; |
|
112 |
||
113 |
static LIR_Opr rscratch1_opr; |
|
114 |
static LIR_Opr rscratch2_opr; |
|
115 |
static LIR_Opr rscratch1_long_opr; |
|
116 |
static LIR_Opr rscratch2_long_opr; |
|
117 |
||
118 |
static LIR_Opr r0_metadata_opr; |
|
119 |
static LIR_Opr r1_metadata_opr; |
|
120 |
static LIR_Opr r2_metadata_opr; |
|
121 |
static LIR_Opr r3_metadata_opr; |
|
122 |
static LIR_Opr r4_metadata_opr; |
|
123 |
static LIR_Opr r5_metadata_opr; |
|
124 |
||
125 |
static LIR_Opr long0_opr; |
|
126 |
static LIR_Opr long1_opr; |
|
127 |
static LIR_Opr fpu0_float_opr; |
|
128 |
static LIR_Opr fpu0_double_opr; |
|
129 |
||
130 |
static LIR_Opr as_long_opr(Register r) { |
|
131 |
return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r)); |
|
132 |
} |
|
133 |
static LIR_Opr as_pointer_opr(Register r) { |
|
134 |
return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r)); |
|
135 |
} |
|
136 |
||
137 |
// VMReg name for spilled physical FPU stack slot n |
|
138 |
static VMReg fpu_regname (int n); |
|
139 |
||
140 |
static bool is_caller_save_register (LIR_Opr opr) { return true; } |
|
141 |
static bool is_caller_save_register (Register r) { return true; } |
|
142 |
||
143 |
static int nof_caller_save_cpu_regs() { return pd_nof_caller_save_cpu_regs_frame_map; } |
|
144 |
static int last_cpu_reg() { return pd_last_cpu_reg; } |
|
145 |
static int last_byte_reg() { return pd_last_byte_reg; } |
|
146 |
||
53244
9807daeb47c4
8216167: Update include guards to reflect correct directories
coleenp
parents:
47216
diff
changeset
|
147 |
#endif // CPU_AARCH64_C1_FRAMEMAP_AARCH64_HPP |