author | iveresov |
Fri, 03 Sep 2010 17:51:07 -0700 | |
changeset 6453 | 970dc585ab63 |
parent 5702 | 201c5cde25bb |
child 6460 | 6f5143b00f4c |
permissions | -rw-r--r-- |
1 | 1 |
/* |
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* Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
1 | 22 |
* |
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*/ |
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24 |
||
25 |
# include "incls/_precompiled.incl" |
|
26 |
# include "incls/_c1_LIRAssembler_x86.cpp.incl" |
|
27 |
||
28 |
||
29 |
// These masks are used to provide 128-bit aligned bitmasks to the XMM |
|
30 |
// instructions, to allow sign-masking or sign-bit flipping. They allow |
|
31 |
// fast versions of NegF/NegD and AbsF/AbsD. |
|
32 |
||
33 |
// Note: 'double' and 'long long' have 32-bits alignment on x86. |
|
34 |
static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { |
|
35 |
// Use the expression (adr)&(~0xF) to provide 128-bits aligned address |
|
36 |
// of 128-bits operands for SSE instructions. |
|
37 |
jlong *operand = (jlong*)(((long)adr)&((long)(~0xF))); |
|
38 |
// Store the value to a 128-bits operand. |
|
39 |
operand[0] = lo; |
|
40 |
operand[1] = hi; |
|
41 |
return operand; |
|
42 |
} |
|
43 |
||
44 |
// Buffer for 128-bits masks used by SSE instructions. |
|
45 |
static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) |
|
46 |
||
47 |
// Static initialization during VM startup. |
|
48 |
static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); |
|
49 |
static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); |
|
50 |
static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); |
|
51 |
static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); |
|
52 |
||
53 |
||
54 |
||
55 |
NEEDS_CLEANUP // remove this definitions ? |
|
56 |
const Register IC_Klass = rax; // where the IC klass is cached |
|
57 |
const Register SYNC_header = rax; // synchronization header |
|
58 |
const Register SHIFT_count = rcx; // where count for shift operations must be |
|
59 |
||
60 |
#define __ _masm-> |
|
61 |
||
62 |
||
63 |
static void select_different_registers(Register preserve, |
|
64 |
Register extra, |
|
65 |
Register &tmp1, |
|
66 |
Register &tmp2) { |
|
67 |
if (tmp1 == preserve) { |
|
68 |
assert_different_registers(tmp1, tmp2, extra); |
|
69 |
tmp1 = extra; |
|
70 |
} else if (tmp2 == preserve) { |
|
71 |
assert_different_registers(tmp1, tmp2, extra); |
|
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tmp2 = extra; |
|
73 |
} |
|
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assert_different_registers(preserve, tmp1, tmp2); |
|
75 |
} |
|
76 |
||
77 |
||
78 |
||
79 |
static void select_different_registers(Register preserve, |
|
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Register extra, |
|
81 |
Register &tmp1, |
|
82 |
Register &tmp2, |
|
83 |
Register &tmp3) { |
|
84 |
if (tmp1 == preserve) { |
|
85 |
assert_different_registers(tmp1, tmp2, tmp3, extra); |
|
86 |
tmp1 = extra; |
|
87 |
} else if (tmp2 == preserve) { |
|
88 |
assert_different_registers(tmp1, tmp2, tmp3, extra); |
|
89 |
tmp2 = extra; |
|
90 |
} else if (tmp3 == preserve) { |
|
91 |
assert_different_registers(tmp1, tmp2, tmp3, extra); |
|
92 |
tmp3 = extra; |
|
93 |
} |
|
94 |
assert_different_registers(preserve, tmp1, tmp2, tmp3); |
|
95 |
} |
|
96 |
||
97 |
||
98 |
||
99 |
bool LIR_Assembler::is_small_constant(LIR_Opr opr) { |
|
100 |
if (opr->is_constant()) { |
|
101 |
LIR_Const* constant = opr->as_constant_ptr(); |
|
102 |
switch (constant->type()) { |
|
103 |
case T_INT: { |
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104 |
return true; |
|
105 |
} |
|
106 |
||
107 |
default: |
|
108 |
return false; |
|
109 |
} |
|
110 |
} |
|
111 |
return false; |
|
112 |
} |
|
113 |
||
114 |
||
115 |
LIR_Opr LIR_Assembler::receiverOpr() { |
|
1066 | 116 |
return FrameMap::receiver_opr; |
1 | 117 |
} |
118 |
||
119 |
LIR_Opr LIR_Assembler::incomingReceiverOpr() { |
|
120 |
return receiverOpr(); |
|
121 |
} |
|
122 |
||
123 |
LIR_Opr LIR_Assembler::osrBufferPointer() { |
|
1066 | 124 |
return FrameMap::as_pointer_opr(receiverOpr()->as_register()); |
1 | 125 |
} |
126 |
||
127 |
//--------------fpu register translations----------------------- |
|
128 |
||
129 |
||
130 |
address LIR_Assembler::float_constant(float f) { |
|
131 |
address const_addr = __ float_constant(f); |
|
132 |
if (const_addr == NULL) { |
|
133 |
bailout("const section overflow"); |
|
134 |
return __ code()->consts()->start(); |
|
135 |
} else { |
|
136 |
return const_addr; |
|
137 |
} |
|
138 |
} |
|
139 |
||
140 |
||
141 |
address LIR_Assembler::double_constant(double d) { |
|
142 |
address const_addr = __ double_constant(d); |
|
143 |
if (const_addr == NULL) { |
|
144 |
bailout("const section overflow"); |
|
145 |
return __ code()->consts()->start(); |
|
146 |
} else { |
|
147 |
return const_addr; |
|
148 |
} |
|
149 |
} |
|
150 |
||
151 |
||
152 |
void LIR_Assembler::set_24bit_FPU() { |
|
153 |
__ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); |
|
154 |
} |
|
155 |
||
156 |
void LIR_Assembler::reset_FPU() { |
|
157 |
__ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); |
|
158 |
} |
|
159 |
||
160 |
void LIR_Assembler::fpop() { |
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161 |
__ fpop(); |
|
162 |
} |
|
163 |
||
164 |
void LIR_Assembler::fxch(int i) { |
|
165 |
__ fxch(i); |
|
166 |
} |
|
167 |
||
168 |
void LIR_Assembler::fld(int i) { |
|
169 |
__ fld_s(i); |
|
170 |
} |
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171 |
||
172 |
void LIR_Assembler::ffree(int i) { |
|
173 |
__ ffree(i); |
|
174 |
} |
|
175 |
||
176 |
void LIR_Assembler::breakpoint() { |
|
177 |
__ int3(); |
|
178 |
} |
|
179 |
||
180 |
void LIR_Assembler::push(LIR_Opr opr) { |
|
181 |
if (opr->is_single_cpu()) { |
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182 |
__ push_reg(opr->as_register()); |
|
183 |
} else if (opr->is_double_cpu()) { |
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1066 | 184 |
NOT_LP64(__ push_reg(opr->as_register_hi())); |
1 | 185 |
__ push_reg(opr->as_register_lo()); |
186 |
} else if (opr->is_stack()) { |
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187 |
__ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); |
|
188 |
} else if (opr->is_constant()) { |
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189 |
LIR_Const* const_opr = opr->as_constant_ptr(); |
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190 |
if (const_opr->type() == T_OBJECT) { |
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191 |
__ push_oop(const_opr->as_jobject()); |
|
192 |
} else if (const_opr->type() == T_INT) { |
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193 |
__ push_jint(const_opr->as_jint()); |
|
194 |
} else { |
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195 |
ShouldNotReachHere(); |
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196 |
} |
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197 |
||
198 |
} else { |
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199 |
ShouldNotReachHere(); |
|
200 |
} |
|
201 |
} |
|
202 |
||
203 |
void LIR_Assembler::pop(LIR_Opr opr) { |
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204 |
if (opr->is_single_cpu()) { |
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1066 | 205 |
__ pop_reg(opr->as_register()); |
1 | 206 |
} else { |
207 |
ShouldNotReachHere(); |
|
208 |
} |
|
209 |
} |
|
210 |
||
1066 | 211 |
bool LIR_Assembler::is_literal_address(LIR_Address* addr) { |
212 |
return addr->base()->is_illegal() && addr->index()->is_illegal(); |
|
213 |
} |
|
214 |
||
1 | 215 |
//------------------------------------------- |
1066 | 216 |
|
1 | 217 |
Address LIR_Assembler::as_Address(LIR_Address* addr) { |
1066 | 218 |
return as_Address(addr, rscratch1); |
219 |
} |
|
220 |
||
221 |
Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { |
|
1 | 222 |
if (addr->base()->is_illegal()) { |
223 |
assert(addr->index()->is_illegal(), "must be illegal too"); |
|
1066 | 224 |
AddressLiteral laddr((address)addr->disp(), relocInfo::none); |
225 |
if (! __ reachable(laddr)) { |
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226 |
__ movptr(tmp, laddr.addr()); |
|
227 |
Address res(tmp, 0); |
|
228 |
return res; |
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229 |
} else { |
|
230 |
return __ as_Address(laddr); |
|
231 |
} |
|
1 | 232 |
} |
233 |
||
1066 | 234 |
Register base = addr->base()->as_pointer_register(); |
1 | 235 |
|
236 |
if (addr->index()->is_illegal()) { |
|
237 |
return Address( base, addr->disp()); |
|
1066 | 238 |
} else if (addr->index()->is_cpu_register()) { |
239 |
Register index = addr->index()->as_pointer_register(); |
|
1 | 240 |
return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); |
241 |
} else if (addr->index()->is_constant()) { |
|
1066 | 242 |
intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); |
243 |
assert(Assembler::is_simm32(addr_offset), "must be"); |
|
1 | 244 |
|
245 |
return Address(base, addr_offset); |
|
246 |
} else { |
|
247 |
Unimplemented(); |
|
248 |
return Address(); |
|
249 |
} |
|
250 |
} |
|
251 |
||
252 |
||
253 |
Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { |
|
254 |
Address base = as_Address(addr); |
|
255 |
return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); |
|
256 |
} |
|
257 |
||
258 |
||
259 |
Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { |
|
260 |
return as_Address(addr); |
|
261 |
} |
|
262 |
||
263 |
||
264 |
void LIR_Assembler::osr_entry() { |
|
265 |
offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); |
|
266 |
BlockBegin* osr_entry = compilation()->hir()->osr_entry(); |
|
267 |
ValueStack* entry_state = osr_entry->state(); |
|
268 |
int number_of_locks = entry_state->locks_size(); |
|
269 |
||
270 |
// we jump here if osr happens with the interpreter |
|
271 |
// state set up to continue at the beginning of the |
|
272 |
// loop that triggered osr - in particular, we have |
|
273 |
// the following registers setup: |
|
274 |
// |
|
275 |
// rcx: osr buffer |
|
276 |
// |
|
277 |
||
278 |
// build frame |
|
279 |
ciMethod* m = compilation()->method(); |
|
280 |
__ build_frame(initial_frame_size_in_bytes()); |
|
281 |
||
282 |
// OSR buffer is |
|
283 |
// |
|
284 |
// locals[nlocals-1..0] |
|
285 |
// monitors[0..number_of_locks] |
|
286 |
// |
|
287 |
// locals is a direct copy of the interpreter frame so in the osr buffer |
|
288 |
// so first slot in the local array is the last local from the interpreter |
|
289 |
// and last slot is local[0] (receiver) from the interpreter |
|
290 |
// |
|
291 |
// Similarly with locks. The first lock slot in the osr buffer is the nth lock |
|
292 |
// from the interpreter frame, the nth lock slot in the osr buffer is 0th lock |
|
293 |
// in the interpreter frame (the method lock if a sync method) |
|
294 |
||
295 |
// Initialize monitors in the compiled activation. |
|
296 |
// rcx: pointer to osr buffer |
|
297 |
// |
|
298 |
// All other registers are dead at this point and the locals will be |
|
299 |
// copied into place by code emitted in the IR. |
|
300 |
||
1066 | 301 |
Register OSR_buf = osrBufferPointer()->as_pointer_register(); |
1 | 302 |
{ assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); |
303 |
int monitor_offset = BytesPerWord * method()->max_locals() + |
|
4430 | 304 |
(2 * BytesPerWord) * (number_of_locks - 1); |
305 |
// SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in |
|
306 |
// the OSR buffer using 2 word entries: first the lock and then |
|
307 |
// the oop. |
|
1 | 308 |
for (int i = 0; i < number_of_locks; i++) { |
4430 | 309 |
int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); |
1 | 310 |
#ifdef ASSERT |
311 |
// verify the interpreter's monitor has a non-null object |
|
312 |
{ |
|
313 |
Label L; |
|
4430 | 314 |
__ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD); |
1 | 315 |
__ jcc(Assembler::notZero, L); |
316 |
__ stop("locked object is NULL"); |
|
317 |
__ bind(L); |
|
318 |
} |
|
319 |
#endif |
|
4430 | 320 |
__ movptr(rbx, Address(OSR_buf, slot_offset + 0)); |
1066 | 321 |
__ movptr(frame_map()->address_for_monitor_lock(i), rbx); |
4430 | 322 |
__ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); |
1066 | 323 |
__ movptr(frame_map()->address_for_monitor_object(i), rbx); |
1 | 324 |
} |
325 |
} |
|
326 |
} |
|
327 |
||
328 |
||
329 |
// inline cache check; done before the frame is built. |
|
330 |
int LIR_Assembler::check_icache() { |
|
331 |
Register receiver = FrameMap::receiver_opr->as_register(); |
|
332 |
Register ic_klass = IC_Klass; |
|
1066 | 333 |
const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); |
1 | 334 |
|
335 |
if (!VerifyOops) { |
|
336 |
// insert some nops so that the verified entry point is aligned on CodeEntryAlignment |
|
1066 | 337 |
while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) { |
1 | 338 |
__ nop(); |
339 |
} |
|
340 |
} |
|
341 |
int offset = __ offset(); |
|
342 |
__ inline_cache_check(receiver, IC_Klass); |
|
343 |
assert(__ offset() % CodeEntryAlignment == 0 || VerifyOops, "alignment must be correct"); |
|
344 |
if (VerifyOops) { |
|
345 |
// force alignment after the cache check. |
|
346 |
// It's been verified to be aligned if !VerifyOops |
|
347 |
__ align(CodeEntryAlignment); |
|
348 |
} |
|
349 |
return offset; |
|
350 |
} |
|
351 |
||
352 |
||
353 |
void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { |
|
354 |
jobject o = NULL; |
|
355 |
PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); |
|
356 |
__ movoop(reg, o); |
|
357 |
patching_epilog(patch, lir_patch_normal, reg, info); |
|
358 |
} |
|
359 |
||
360 |
||
361 |
void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register new_hdr, int monitor_no, Register exception) { |
|
362 |
if (exception->is_valid()) { |
|
363 |
// preserve exception |
|
364 |
// note: the monitor_exit runtime call is a leaf routine |
|
365 |
// and cannot block => no GC can happen |
|
366 |
// The slow case (MonitorAccessStub) uses the first two stack slots |
|
367 |
// ([esp+0] and [esp+4]), therefore we store the exception at [esp+8] |
|
1066 | 368 |
__ movptr (Address(rsp, 2*wordSize), exception); |
1 | 369 |
} |
370 |
||
371 |
Register obj_reg = obj_opr->as_register(); |
|
372 |
Register lock_reg = lock_opr->as_register(); |
|
373 |
||
374 |
// setup registers (lock_reg must be rax, for lock_object) |
|
375 |
assert(obj_reg != SYNC_header && lock_reg != SYNC_header, "rax, must be available here"); |
|
376 |
Register hdr = lock_reg; |
|
377 |
assert(new_hdr == SYNC_header, "wrong register"); |
|
378 |
lock_reg = new_hdr; |
|
379 |
// compute pointer to BasicLock |
|
380 |
Address lock_addr = frame_map()->address_for_monitor_lock(monitor_no); |
|
1066 | 381 |
__ lea(lock_reg, lock_addr); |
1 | 382 |
// unlock object |
383 |
MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, true, monitor_no); |
|
384 |
// _slow_case_stubs->append(slow_case); |
|
385 |
// temporary fix: must be created after exceptionhandler, therefore as call stub |
|
386 |
_slow_case_stubs->append(slow_case); |
|
387 |
if (UseFastLocking) { |
|
388 |
// try inlined fast unlocking first, revert to slow locking if it fails |
|
389 |
// note: lock_reg points to the displaced header since the displaced header offset is 0! |
|
390 |
assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); |
|
391 |
__ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry()); |
|
392 |
} else { |
|
393 |
// always do slow unlocking |
|
394 |
// note: the slow unlocking code could be inlined here, however if we use |
|
395 |
// slow unlocking, speed doesn't matter anyway and this solution is |
|
396 |
// simpler and requires less duplicated code - additionally, the |
|
397 |
// slow unlocking code is the same in either case which simplifies |
|
398 |
// debugging |
|
399 |
__ jmp(*slow_case->entry()); |
|
400 |
} |
|
401 |
// done |
|
402 |
__ bind(*slow_case->continuation()); |
|
403 |
||
404 |
if (exception->is_valid()) { |
|
405 |
// restore exception |
|
1066 | 406 |
__ movptr (exception, Address(rsp, 2 * wordSize)); |
1 | 407 |
} |
408 |
} |
|
409 |
||
410 |
// This specifies the rsp decrement needed to build the frame |
|
411 |
int LIR_Assembler::initial_frame_size_in_bytes() { |
|
412 |
// if rounding, must let FrameMap know! |
|
1066 | 413 |
|
414 |
// The frame_map records size in slots (32bit word) |
|
415 |
||
416 |
// subtract two words to account for return address and link |
|
417 |
return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; |
|
1 | 418 |
} |
419 |
||
420 |
||
4752 | 421 |
int LIR_Assembler::emit_exception_handler() { |
1 | 422 |
// if the last instruction is a call (typically to do a throw which |
423 |
// is coming at the end after block reordering) the return address |
|
424 |
// must still point into the code area in order to avoid assertion |
|
425 |
// failures when searching for the corresponding bci => add a nop |
|
426 |
// (was bug 5/14/1999 - gri) |
|
427 |
__ nop(); |
|
428 |
||
429 |
// generate code for exception handler |
|
430 |
address handler_base = __ start_a_stub(exception_handler_size); |
|
431 |
if (handler_base == NULL) { |
|
432 |
// not enough space left for the handler |
|
433 |
bailout("exception handler overflow"); |
|
4752 | 434 |
return -1; |
1 | 435 |
} |
4752 | 436 |
|
1 | 437 |
int offset = code_offset(); |
438 |
||
5046 | 439 |
// the exception oop and pc are in rax, and rdx |
1 | 440 |
// no other registers need to be preserved, so invalidate them |
5046 | 441 |
__ invalidate_registers(false, true, true, false, true, true); |
1 | 442 |
|
443 |
// check that there is really an exception |
|
444 |
__ verify_not_null_oop(rax); |
|
445 |
||
5046 | 446 |
// search an exception handler (rax: exception oop, rdx: throwing pc) |
447 |
__ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_nofpu_id))); |
|
448 |
||
449 |
__ stop("should not reach here"); |
|
450 |
||
1 | 451 |
assert(code_offset() - offset <= exception_handler_size, "overflow"); |
452 |
__ end_a_stub(); |
|
4752 | 453 |
|
454 |
return offset; |
|
1 | 455 |
} |
456 |
||
4752 | 457 |
|
5334
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|
458 |
// Emit the code to remove the frame from the stack in the exception |
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|
459 |
// unwind path. |
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|
460 |
int LIR_Assembler::emit_unwind_handler() { |
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|
461 |
#ifndef PRODUCT |
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|
462 |
if (CommentedAssembly) { |
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|
463 |
_masm->block_comment("Unwind handler"); |
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|
464 |
} |
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|
465 |
#endif |
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changeset
|
466 |
|
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|
467 |
int offset = code_offset(); |
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changeset
|
468 |
|
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changeset
|
469 |
// Fetch the exception from TLS and clear out exception related thread state |
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|
470 |
__ get_thread(rsi); |
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|
471 |
__ movptr(rax, Address(rsi, JavaThread::exception_oop_offset())); |
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|
472 |
__ movptr(Address(rsi, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD); |
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|
473 |
__ movptr(Address(rsi, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD); |
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changeset
|
474 |
|
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|
475 |
__ bind(_unwind_handler_entry); |
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|
476 |
__ verify_not_null_oop(rax); |
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|
477 |
if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
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|
478 |
__ mov(rsi, rax); // Preserve the exception |
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|
479 |
} |
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changeset
|
480 |
|
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changeset
|
481 |
// Preform needed unlocking |
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|
482 |
MonitorExitStub* stub = NULL; |
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changeset
|
483 |
if (method()->is_synchronized()) { |
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|
484 |
monitor_address(0, FrameMap::rax_opr); |
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|
485 |
stub = new MonitorExitStub(FrameMap::rax_opr, true, 0); |
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|
486 |
__ unlock_object(rdi, rbx, rax, *stub->entry()); |
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|
487 |
__ bind(*stub->continuation()); |
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changeset
|
488 |
} |
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changeset
|
489 |
|
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changeset
|
490 |
if (compilation()->env()->dtrace_method_probes()) { |
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|
491 |
__ movoop(Address(rsp, 0), method()->constant_encoding()); |
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|
492 |
__ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); |
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changeset
|
493 |
} |
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diff
changeset
|
494 |
|
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changeset
|
495 |
if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
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changeset
|
496 |
__ mov(rax, rsi); // Restore the exception |
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changeset
|
497 |
} |
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changeset
|
498 |
|
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|
499 |
// remove the activation and dispatch to the unwind handler |
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|
500 |
__ remove_frame(initial_frame_size_in_bytes()); |
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|
501 |
__ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); |
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|
502 |
|
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|
503 |
// Emit the slow path assembly |
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|
504 |
if (stub != NULL) { |
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changeset
|
505 |
stub->emit_code(this); |
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changeset
|
506 |
} |
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changeset
|
507 |
|
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changeset
|
508 |
return offset; |
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5253
diff
changeset
|
509 |
} |
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changeset
|
510 |
|
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changeset
|
511 |
|
4752 | 512 |
int LIR_Assembler::emit_deopt_handler() { |
1 | 513 |
// if the last instruction is a call (typically to do a throw which |
514 |
// is coming at the end after block reordering) the return address |
|
515 |
// must still point into the code area in order to avoid assertion |
|
516 |
// failures when searching for the corresponding bci => add a nop |
|
517 |
// (was bug 5/14/1999 - gri) |
|
518 |
__ nop(); |
|
519 |
||
520 |
// generate code for exception handler |
|
521 |
address handler_base = __ start_a_stub(deopt_handler_size); |
|
522 |
if (handler_base == NULL) { |
|
523 |
// not enough space left for the handler |
|
524 |
bailout("deopt handler overflow"); |
|
4752 | 525 |
return -1; |
1 | 526 |
} |
4752 | 527 |
|
1 | 528 |
int offset = code_offset(); |
529 |
InternalAddress here(__ pc()); |
|
5046 | 530 |
|
1 | 531 |
__ pushptr(here.addr()); |
532 |
__ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); |
|
5046 | 533 |
|
1 | 534 |
assert(code_offset() - offset <= deopt_handler_size, "overflow"); |
535 |
__ end_a_stub(); |
|
536 |
||
4752 | 537 |
return offset; |
1 | 538 |
} |
539 |
||
540 |
||
541 |
// This is the fast version of java.lang.String.compare; it has not |
|
542 |
// OSR-entry and therefore, we generate a slow version for OSR's |
|
543 |
void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) { |
|
1066 | 544 |
__ movptr (rbx, rcx); // receiver is in rcx |
545 |
__ movptr (rax, arg1->as_register()); |
|
1 | 546 |
|
547 |
// Get addresses of first characters from both Strings |
|
1066 | 548 |
__ movptr (rsi, Address(rax, java_lang_String::value_offset_in_bytes())); |
549 |
__ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes())); |
|
550 |
__ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); |
|
1 | 551 |
|
552 |
||
553 |
// rbx, may be NULL |
|
554 |
add_debug_info_for_null_check_here(info); |
|
1066 | 555 |
__ movptr (rdi, Address(rbx, java_lang_String::value_offset_in_bytes())); |
556 |
__ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes())); |
|
557 |
__ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); |
|
1 | 558 |
|
559 |
// compute minimum length (in rax) and difference of lengths (on top of stack) |
|
560 |
if (VM_Version::supports_cmov()) { |
|
1066 | 561 |
__ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); |
562 |
__ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes())); |
|
563 |
__ mov (rcx, rbx); |
|
564 |
__ subptr (rbx, rax); // subtract lengths |
|
565 |
__ push (rbx); // result |
|
566 |
__ cmov (Assembler::lessEqual, rax, rcx); |
|
1 | 567 |
} else { |
568 |
Label L; |
|
1066 | 569 |
__ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); |
570 |
__ movl (rcx, Address(rax, java_lang_String::count_offset_in_bytes())); |
|
571 |
__ mov (rax, rbx); |
|
572 |
__ subptr (rbx, rcx); |
|
573 |
__ push (rbx); |
|
574 |
__ jcc (Assembler::lessEqual, L); |
|
575 |
__ mov (rax, rcx); |
|
1 | 576 |
__ bind (L); |
577 |
} |
|
578 |
// is minimum length 0? |
|
579 |
Label noLoop, haveResult; |
|
1066 | 580 |
__ testptr (rax, rax); |
1 | 581 |
__ jcc (Assembler::zero, noLoop); |
582 |
||
583 |
// compare first characters |
|
2148
09c7f703773b
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jrose
parents:
1888
diff
changeset
|
584 |
__ load_unsigned_short(rcx, Address(rdi, 0)); |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1888
diff
changeset
|
585 |
__ load_unsigned_short(rbx, Address(rsi, 0)); |
1 | 586 |
__ subl(rcx, rbx); |
587 |
__ jcc(Assembler::notZero, haveResult); |
|
588 |
// starting loop |
|
589 |
__ decrement(rax); // we already tested index: skip one |
|
590 |
__ jcc(Assembler::zero, noLoop); |
|
591 |
||
592 |
// set rsi.edi to the end of the arrays (arrays have same length) |
|
593 |
// negate the index |
|
594 |
||
1066 | 595 |
__ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR))); |
596 |
__ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR))); |
|
597 |
__ negptr(rax); |
|
1 | 598 |
|
599 |
// compare the strings in a loop |
|
600 |
||
601 |
Label loop; |
|
602 |
__ align(wordSize); |
|
603 |
__ bind(loop); |
|
2148
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1888
diff
changeset
|
604 |
__ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0)); |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1888
diff
changeset
|
605 |
__ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0)); |
1 | 606 |
__ subl(rcx, rbx); |
607 |
__ jcc(Assembler::notZero, haveResult); |
|
608 |
__ increment(rax); |
|
609 |
__ jcc(Assembler::notZero, loop); |
|
610 |
||
611 |
// strings are equal up to min length |
|
612 |
||
613 |
__ bind(noLoop); |
|
1066 | 614 |
__ pop(rax); |
1 | 615 |
return_op(LIR_OprFact::illegalOpr); |
616 |
||
617 |
__ bind(haveResult); |
|
618 |
// leave instruction is going to discard the TOS value |
|
1066 | 619 |
__ mov (rax, rcx); // result of call is in rax, |
1 | 620 |
} |
621 |
||
622 |
||
623 |
void LIR_Assembler::return_op(LIR_Opr result) { |
|
624 |
assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); |
|
625 |
if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { |
|
626 |
assert(result->fpu() == 0, "result must already be on TOS"); |
|
627 |
} |
|
628 |
||
629 |
// Pop the stack before the safepoint code |
|
5046 | 630 |
__ remove_frame(initial_frame_size_in_bytes()); |
1 | 631 |
|
632 |
bool result_is_oop = result->is_valid() ? result->is_oop() : false; |
|
633 |
||
634 |
// Note: we do not need to round double result; float result has the right precision |
|
635 |
// the poll sets the condition code, but no data registers |
|
636 |
AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), |
|
637 |
relocInfo::poll_return_type); |
|
1066 | 638 |
|
639 |
// NOTE: the requires that the polling page be reachable else the reloc |
|
640 |
// goes to the movq that loads the address and not the faulting instruction |
|
641 |
// which breaks the signal handler code |
|
642 |
||
1 | 643 |
__ test32(rax, polling_page); |
644 |
||
645 |
__ ret(0); |
|
646 |
} |
|
647 |
||
648 |
||
649 |
int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { |
|
650 |
AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), |
|
651 |
relocInfo::poll_type); |
|
652 |
||
653 |
if (info != NULL) { |
|
654 |
add_debug_info_for_branch(info); |
|
655 |
} else { |
|
656 |
ShouldNotReachHere(); |
|
657 |
} |
|
658 |
||
659 |
int offset = __ offset(); |
|
1066 | 660 |
|
661 |
// NOTE: the requires that the polling page be reachable else the reloc |
|
662 |
// goes to the movq that loads the address and not the faulting instruction |
|
663 |
// which breaks the signal handler code |
|
664 |
||
1 | 665 |
__ test32(rax, polling_page); |
666 |
return offset; |
|
667 |
} |
|
668 |
||
669 |
||
670 |
void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { |
|
1066 | 671 |
if (from_reg != to_reg) __ mov(to_reg, from_reg); |
1 | 672 |
} |
673 |
||
674 |
void LIR_Assembler::swap_reg(Register a, Register b) { |
|
1066 | 675 |
__ xchgptr(a, b); |
1 | 676 |
} |
677 |
||
678 |
||
679 |
void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { |
|
680 |
assert(src->is_constant(), "should not call otherwise"); |
|
681 |
assert(dest->is_register(), "should not call otherwise"); |
|
682 |
LIR_Const* c = src->as_constant_ptr(); |
|
683 |
||
684 |
switch (c->type()) { |
|
5048
c31b6243f37e
6932496: c1: deoptimization of jsr subroutine fails on sparcv9
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parents:
5046
diff
changeset
|
685 |
case T_INT: |
c31b6243f37e
6932496: c1: deoptimization of jsr subroutine fails on sparcv9
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parents:
5046
diff
changeset
|
686 |
case T_ADDRESS: { |
1 | 687 |
assert(patch_code == lir_patch_none, "no patching handled here"); |
688 |
__ movl(dest->as_register(), c->as_jint()); |
|
689 |
break; |
|
690 |
} |
|
691 |
||
692 |
case T_LONG: { |
|
693 |
assert(patch_code == lir_patch_none, "no patching handled here"); |
|
1066 | 694 |
#ifdef _LP64 |
695 |
__ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); |
|
696 |
#else |
|
697 |
__ movptr(dest->as_register_lo(), c->as_jint_lo()); |
|
698 |
__ movptr(dest->as_register_hi(), c->as_jint_hi()); |
|
699 |
#endif // _LP64 |
|
1 | 700 |
break; |
701 |
} |
|
702 |
||
703 |
case T_OBJECT: { |
|
704 |
if (patch_code != lir_patch_none) { |
|
705 |
jobject2reg_with_patching(dest->as_register(), info); |
|
706 |
} else { |
|
707 |
__ movoop(dest->as_register(), c->as_jobject()); |
|
708 |
} |
|
709 |
break; |
|
710 |
} |
|
711 |
||
712 |
case T_FLOAT: { |
|
713 |
if (dest->is_single_xmm()) { |
|
714 |
if (c->is_zero_float()) { |
|
715 |
__ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); |
|
716 |
} else { |
|
717 |
__ movflt(dest->as_xmm_float_reg(), |
|
718 |
InternalAddress(float_constant(c->as_jfloat()))); |
|
719 |
} |
|
720 |
} else { |
|
721 |
assert(dest->is_single_fpu(), "must be"); |
|
722 |
assert(dest->fpu_regnr() == 0, "dest must be TOS"); |
|
723 |
if (c->is_zero_float()) { |
|
724 |
__ fldz(); |
|
725 |
} else if (c->is_one_float()) { |
|
726 |
__ fld1(); |
|
727 |
} else { |
|
728 |
__ fld_s (InternalAddress(float_constant(c->as_jfloat()))); |
|
729 |
} |
|
730 |
} |
|
731 |
break; |
|
732 |
} |
|
733 |
||
734 |
case T_DOUBLE: { |
|
735 |
if (dest->is_double_xmm()) { |
|
736 |
if (c->is_zero_double()) { |
|
737 |
__ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); |
|
738 |
} else { |
|
739 |
__ movdbl(dest->as_xmm_double_reg(), |
|
740 |
InternalAddress(double_constant(c->as_jdouble()))); |
|
741 |
} |
|
742 |
} else { |
|
743 |
assert(dest->is_double_fpu(), "must be"); |
|
744 |
assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); |
|
745 |
if (c->is_zero_double()) { |
|
746 |
__ fldz(); |
|
747 |
} else if (c->is_one_double()) { |
|
748 |
__ fld1(); |
|
749 |
} else { |
|
750 |
__ fld_d (InternalAddress(double_constant(c->as_jdouble()))); |
|
751 |
} |
|
752 |
} |
|
753 |
break; |
|
754 |
} |
|
755 |
||
756 |
default: |
|
757 |
ShouldNotReachHere(); |
|
758 |
} |
|
759 |
} |
|
760 |
||
761 |
void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { |
|
762 |
assert(src->is_constant(), "should not call otherwise"); |
|
763 |
assert(dest->is_stack(), "should not call otherwise"); |
|
764 |
LIR_Const* c = src->as_constant_ptr(); |
|
765 |
||
766 |
switch (c->type()) { |
|
767 |
case T_INT: // fall through |
|
768 |
case T_FLOAT: |
|
5048
c31b6243f37e
6932496: c1: deoptimization of jsr subroutine fails on sparcv9
roland
parents:
5046
diff
changeset
|
769 |
case T_ADDRESS: |
1 | 770 |
__ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); |
771 |
break; |
|
772 |
||
773 |
case T_OBJECT: |
|
774 |
__ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); |
|
775 |
break; |
|
776 |
||
777 |
case T_LONG: // fall through |
|
778 |
case T_DOUBLE: |
|
1066 | 779 |
#ifdef _LP64 |
780 |
__ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), |
|
781 |
lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); |
|
782 |
#else |
|
783 |
__ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), |
|
784 |
lo_word_offset_in_bytes), c->as_jint_lo_bits()); |
|
785 |
__ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), |
|
786 |
hi_word_offset_in_bytes), c->as_jint_hi_bits()); |
|
787 |
#endif // _LP64 |
|
1 | 788 |
break; |
789 |
||
790 |
default: |
|
791 |
ShouldNotReachHere(); |
|
792 |
} |
|
793 |
} |
|
794 |
||
795 |
void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) { |
|
796 |
assert(src->is_constant(), "should not call otherwise"); |
|
797 |
assert(dest->is_address(), "should not call otherwise"); |
|
798 |
LIR_Const* c = src->as_constant_ptr(); |
|
799 |
LIR_Address* addr = dest->as_address_ptr(); |
|
800 |
||
1066 | 801 |
int null_check_here = code_offset(); |
1 | 802 |
switch (type) { |
803 |
case T_INT: // fall through |
|
804 |
case T_FLOAT: |
|
5048
c31b6243f37e
6932496: c1: deoptimization of jsr subroutine fails on sparcv9
roland
parents:
5046
diff
changeset
|
805 |
case T_ADDRESS: |
1 | 806 |
__ movl(as_Address(addr), c->as_jint_bits()); |
807 |
break; |
|
808 |
||
809 |
case T_OBJECT: // fall through |
|
810 |
case T_ARRAY: |
|
811 |
if (c->as_jobject() == NULL) { |
|
1888
bbf498fb4354
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
1125
diff
changeset
|
812 |
__ movptr(as_Address(addr), NULL_WORD); |
1 | 813 |
} else { |
1066 | 814 |
if (is_literal_address(addr)) { |
815 |
ShouldNotReachHere(); |
|
816 |
__ movoop(as_Address(addr, noreg), c->as_jobject()); |
|
817 |
} else { |
|
4430 | 818 |
#ifdef _LP64 |
819 |
__ movoop(rscratch1, c->as_jobject()); |
|
820 |
null_check_here = code_offset(); |
|
821 |
__ movptr(as_Address_lo(addr), rscratch1); |
|
822 |
#else |
|
1066 | 823 |
__ movoop(as_Address(addr), c->as_jobject()); |
4430 | 824 |
#endif |
1066 | 825 |
} |
1 | 826 |
} |
827 |
break; |
|
828 |
||
829 |
case T_LONG: // fall through |
|
830 |
case T_DOUBLE: |
|
1066 | 831 |
#ifdef _LP64 |
832 |
if (is_literal_address(addr)) { |
|
833 |
ShouldNotReachHere(); |
|
834 |
__ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); |
|
835 |
} else { |
|
836 |
__ movptr(r10, (intptr_t)c->as_jlong_bits()); |
|
837 |
null_check_here = code_offset(); |
|
838 |
__ movptr(as_Address_lo(addr), r10); |
|
839 |
} |
|
840 |
#else |
|
841 |
// Always reachable in 32bit so this doesn't produce useless move literal |
|
842 |
__ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); |
|
843 |
__ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); |
|
844 |
#endif // _LP64 |
|
1 | 845 |
break; |
846 |
||
847 |
case T_BOOLEAN: // fall through |
|
848 |
case T_BYTE: |
|
849 |
__ movb(as_Address(addr), c->as_jint() & 0xFF); |
|
850 |
break; |
|
851 |
||
852 |
case T_CHAR: // fall through |
|
853 |
case T_SHORT: |
|
854 |
__ movw(as_Address(addr), c->as_jint() & 0xFFFF); |
|
855 |
break; |
|
856 |
||
857 |
default: |
|
858 |
ShouldNotReachHere(); |
|
859 |
}; |
|
1066 | 860 |
|
861 |
if (info != NULL) { |
|
862 |
add_debug_info_for_null_check(null_check_here, info); |
|
863 |
} |
|
1 | 864 |
} |
865 |
||
866 |
||
867 |
void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { |
|
868 |
assert(src->is_register(), "should not call otherwise"); |
|
869 |
assert(dest->is_register(), "should not call otherwise"); |
|
870 |
||
871 |
// move between cpu-registers |
|
872 |
if (dest->is_single_cpu()) { |
|
1066 | 873 |
#ifdef _LP64 |
874 |
if (src->type() == T_LONG) { |
|
875 |
// Can do LONG -> OBJECT |
|
876 |
move_regs(src->as_register_lo(), dest->as_register()); |
|
877 |
return; |
|
878 |
} |
|
879 |
#endif |
|
1 | 880 |
assert(src->is_single_cpu(), "must match"); |
881 |
if (src->type() == T_OBJECT) { |
|
882 |
__ verify_oop(src->as_register()); |
|
883 |
} |
|
884 |
move_regs(src->as_register(), dest->as_register()); |
|
885 |
||
886 |
} else if (dest->is_double_cpu()) { |
|
1066 | 887 |
#ifdef _LP64 |
888 |
if (src->type() == T_OBJECT || src->type() == T_ARRAY) { |
|
889 |
// Surprising to me but we can see move of a long to t_object |
|
890 |
__ verify_oop(src->as_register()); |
|
891 |
move_regs(src->as_register(), dest->as_register_lo()); |
|
892 |
return; |
|
893 |
} |
|
894 |
#endif |
|
1 | 895 |
assert(src->is_double_cpu(), "must match"); |
896 |
Register f_lo = src->as_register_lo(); |
|
897 |
Register f_hi = src->as_register_hi(); |
|
898 |
Register t_lo = dest->as_register_lo(); |
|
899 |
Register t_hi = dest->as_register_hi(); |
|
1066 | 900 |
#ifdef _LP64 |
901 |
assert(f_hi == f_lo, "must be same"); |
|
902 |
assert(t_hi == t_lo, "must be same"); |
|
903 |
move_regs(f_lo, t_lo); |
|
904 |
#else |
|
1 | 905 |
assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); |
906 |
||
1066 | 907 |
|
1 | 908 |
if (f_lo == t_hi && f_hi == t_lo) { |
909 |
swap_reg(f_lo, f_hi); |
|
910 |
} else if (f_hi == t_lo) { |
|
911 |
assert(f_lo != t_hi, "overwriting register"); |
|
912 |
move_regs(f_hi, t_hi); |
|
913 |
move_regs(f_lo, t_lo); |
|
914 |
} else { |
|
915 |
assert(f_hi != t_lo, "overwriting register"); |
|
916 |
move_regs(f_lo, t_lo); |
|
917 |
move_regs(f_hi, t_hi); |
|
918 |
} |
|
1066 | 919 |
#endif // LP64 |
1 | 920 |
|
921 |
// special moves from fpu-register to xmm-register |
|
922 |
// necessary for method results |
|
923 |
} else if (src->is_single_xmm() && !dest->is_single_xmm()) { |
|
924 |
__ movflt(Address(rsp, 0), src->as_xmm_float_reg()); |
|
925 |
__ fld_s(Address(rsp, 0)); |
|
926 |
} else if (src->is_double_xmm() && !dest->is_double_xmm()) { |
|
927 |
__ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); |
|
928 |
__ fld_d(Address(rsp, 0)); |
|
929 |
} else if (dest->is_single_xmm() && !src->is_single_xmm()) { |
|
930 |
__ fstp_s(Address(rsp, 0)); |
|
931 |
__ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); |
|
932 |
} else if (dest->is_double_xmm() && !src->is_double_xmm()) { |
|
933 |
__ fstp_d(Address(rsp, 0)); |
|
934 |
__ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); |
|
935 |
||
936 |
// move between xmm-registers |
|
937 |
} else if (dest->is_single_xmm()) { |
|
938 |
assert(src->is_single_xmm(), "must match"); |
|
939 |
__ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); |
|
940 |
} else if (dest->is_double_xmm()) { |
|
941 |
assert(src->is_double_xmm(), "must match"); |
|
942 |
__ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); |
|
943 |
||
944 |
// move between fpu-registers (no instruction necessary because of fpu-stack) |
|
945 |
} else if (dest->is_single_fpu() || dest->is_double_fpu()) { |
|
946 |
assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); |
|
947 |
assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); |
|
948 |
} else { |
|
949 |
ShouldNotReachHere(); |
|
950 |
} |
|
951 |
} |
|
952 |
||
953 |
void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { |
|
954 |
assert(src->is_register(), "should not call otherwise"); |
|
955 |
assert(dest->is_stack(), "should not call otherwise"); |
|
956 |
||
957 |
if (src->is_single_cpu()) { |
|
958 |
Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); |
|
959 |
if (type == T_OBJECT || type == T_ARRAY) { |
|
960 |
__ verify_oop(src->as_register()); |
|
1066 | 961 |
__ movptr (dst, src->as_register()); |
962 |
} else { |
|
963 |
__ movl (dst, src->as_register()); |
|
1 | 964 |
} |
965 |
||
966 |
} else if (src->is_double_cpu()) { |
|
967 |
Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); |
|
968 |
Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); |
|
1066 | 969 |
__ movptr (dstLO, src->as_register_lo()); |
970 |
NOT_LP64(__ movptr (dstHI, src->as_register_hi())); |
|
1 | 971 |
|
972 |
} else if (src->is_single_xmm()) { |
|
973 |
Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); |
|
974 |
__ movflt(dst_addr, src->as_xmm_float_reg()); |
|
975 |
||
976 |
} else if (src->is_double_xmm()) { |
|
977 |
Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); |
|
978 |
__ movdbl(dst_addr, src->as_xmm_double_reg()); |
|
979 |
||
980 |
} else if (src->is_single_fpu()) { |
|
981 |
assert(src->fpu_regnr() == 0, "argument must be on TOS"); |
|
982 |
Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); |
|
983 |
if (pop_fpu_stack) __ fstp_s (dst_addr); |
|
984 |
else __ fst_s (dst_addr); |
|
985 |
||
986 |
} else if (src->is_double_fpu()) { |
|
987 |
assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); |
|
988 |
Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); |
|
989 |
if (pop_fpu_stack) __ fstp_d (dst_addr); |
|
990 |
else __ fst_d (dst_addr); |
|
991 |
||
992 |
} else { |
|
993 |
ShouldNotReachHere(); |
|
994 |
} |
|
995 |
} |
|
996 |
||
997 |
||
998 |
void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool /* unaligned */) { |
|
999 |
LIR_Address* to_addr = dest->as_address_ptr(); |
|
1000 |
PatchingStub* patch = NULL; |
|
1001 |
||
1002 |
if (type == T_ARRAY || type == T_OBJECT) { |
|
1003 |
__ verify_oop(src->as_register()); |
|
1004 |
} |
|
1005 |
if (patch_code != lir_patch_none) { |
|
1006 |
patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
|
1066 | 1007 |
Address toa = as_Address(to_addr); |
1008 |
assert(toa.disp() != 0, "must have"); |
|
1 | 1009 |
} |
1010 |
if (info != NULL) { |
|
1011 |
add_debug_info_for_null_check_here(info); |
|
1012 |
} |
|
1013 |
||
1014 |
switch (type) { |
|
1015 |
case T_FLOAT: { |
|
1016 |
if (src->is_single_xmm()) { |
|
1017 |
__ movflt(as_Address(to_addr), src->as_xmm_float_reg()); |
|
1018 |
} else { |
|
1019 |
assert(src->is_single_fpu(), "must be"); |
|
1020 |
assert(src->fpu_regnr() == 0, "argument must be on TOS"); |
|
1021 |
if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); |
|
1022 |
else __ fst_s (as_Address(to_addr)); |
|
1023 |
} |
|
1024 |
break; |
|
1025 |
} |
|
1026 |
||
1027 |
case T_DOUBLE: { |
|
1028 |
if (src->is_double_xmm()) { |
|
1029 |
__ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); |
|
1030 |
} else { |
|
1031 |
assert(src->is_double_fpu(), "must be"); |
|
1032 |
assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); |
|
1033 |
if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); |
|
1034 |
else __ fst_d (as_Address(to_addr)); |
|
1035 |
} |
|
1036 |
break; |
|
1037 |
} |
|
1038 |
||
1039 |
case T_ADDRESS: // fall through |
|
1040 |
case T_ARRAY: // fall through |
|
1041 |
case T_OBJECT: // fall through |
|
1066 | 1042 |
#ifdef _LP64 |
1043 |
__ movptr(as_Address(to_addr), src->as_register()); |
|
1044 |
break; |
|
1045 |
#endif // _LP64 |
|
1 | 1046 |
case T_INT: |
1047 |
__ movl(as_Address(to_addr), src->as_register()); |
|
1048 |
break; |
|
1049 |
||
1050 |
case T_LONG: { |
|
1051 |
Register from_lo = src->as_register_lo(); |
|
1052 |
Register from_hi = src->as_register_hi(); |
|
1066 | 1053 |
#ifdef _LP64 |
1054 |
__ movptr(as_Address_lo(to_addr), from_lo); |
|
1055 |
#else |
|
1 | 1056 |
Register base = to_addr->base()->as_register(); |
1057 |
Register index = noreg; |
|
1058 |
if (to_addr->index()->is_register()) { |
|
1059 |
index = to_addr->index()->as_register(); |
|
1060 |
} |
|
1061 |
if (base == from_lo || index == from_lo) { |
|
1062 |
assert(base != from_hi, "can't be"); |
|
1063 |
assert(index == noreg || (index != base && index != from_hi), "can't handle this"); |
|
1064 |
__ movl(as_Address_hi(to_addr), from_hi); |
|
1065 |
if (patch != NULL) { |
|
1066 |
patching_epilog(patch, lir_patch_high, base, info); |
|
1067 |
patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
|
1068 |
patch_code = lir_patch_low; |
|
1069 |
} |
|
1070 |
__ movl(as_Address_lo(to_addr), from_lo); |
|
1071 |
} else { |
|
1072 |
assert(index == noreg || (index != base && index != from_lo), "can't handle this"); |
|
1073 |
__ movl(as_Address_lo(to_addr), from_lo); |
|
1074 |
if (patch != NULL) { |
|
1075 |
patching_epilog(patch, lir_patch_low, base, info); |
|
1076 |
patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
|
1077 |
patch_code = lir_patch_high; |
|
1078 |
} |
|
1079 |
__ movl(as_Address_hi(to_addr), from_hi); |
|
1080 |
} |
|
1066 | 1081 |
#endif // _LP64 |
1 | 1082 |
break; |
1083 |
} |
|
1084 |
||
1085 |
case T_BYTE: // fall through |
|
1086 |
case T_BOOLEAN: { |
|
1087 |
Register src_reg = src->as_register(); |
|
1088 |
Address dst_addr = as_Address(to_addr); |
|
1089 |
assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); |
|
1090 |
__ movb(dst_addr, src_reg); |
|
1091 |
break; |
|
1092 |
} |
|
1093 |
||
1094 |
case T_CHAR: // fall through |
|
1095 |
case T_SHORT: |
|
1096 |
__ movw(as_Address(to_addr), src->as_register()); |
|
1097 |
break; |
|
1098 |
||
1099 |
default: |
|
1100 |
ShouldNotReachHere(); |
|
1101 |
} |
|
1102 |
||
1103 |
if (patch_code != lir_patch_none) { |
|
1104 |
patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); |
|
1105 |
} |
|
1106 |
} |
|
1107 |
||
1108 |
||
1109 |
void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { |
|
1110 |
assert(src->is_stack(), "should not call otherwise"); |
|
1111 |
assert(dest->is_register(), "should not call otherwise"); |
|
1112 |
||
1113 |
if (dest->is_single_cpu()) { |
|
1114 |
if (type == T_ARRAY || type == T_OBJECT) { |
|
1066 | 1115 |
__ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); |
1 | 1116 |
__ verify_oop(dest->as_register()); |
1066 | 1117 |
} else { |
1118 |
__ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); |
|
1 | 1119 |
} |
1120 |
||
1121 |
} else if (dest->is_double_cpu()) { |
|
1122 |
Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); |
|
1123 |
Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); |
|
1066 | 1124 |
__ movptr(dest->as_register_lo(), src_addr_LO); |
1125 |
NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); |
|
1 | 1126 |
|
1127 |
} else if (dest->is_single_xmm()) { |
|
1128 |
Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); |
|
1129 |
__ movflt(dest->as_xmm_float_reg(), src_addr); |
|
1130 |
||
1131 |
} else if (dest->is_double_xmm()) { |
|
1132 |
Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); |
|
1133 |
__ movdbl(dest->as_xmm_double_reg(), src_addr); |
|
1134 |
||
1135 |
} else if (dest->is_single_fpu()) { |
|
1136 |
assert(dest->fpu_regnr() == 0, "dest must be TOS"); |
|
1137 |
Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); |
|
1138 |
__ fld_s(src_addr); |
|
1139 |
||
1140 |
} else if (dest->is_double_fpu()) { |
|
1141 |
assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); |
|
1142 |
Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); |
|
1143 |
__ fld_d(src_addr); |
|
1144 |
||
1145 |
} else { |
|
1146 |
ShouldNotReachHere(); |
|
1147 |
} |
|
1148 |
} |
|
1149 |
||
1150 |
||
1151 |
void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { |
|
1152 |
if (src->is_single_stack()) { |
|
1066 | 1153 |
if (type == T_OBJECT || type == T_ARRAY) { |
1154 |
__ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); |
|
1155 |
__ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); |
|
1156 |
} else { |
|
4430 | 1157 |
#ifndef _LP64 |
1066 | 1158 |
__ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); |
1159 |
__ popl (frame_map()->address_for_slot(dest->single_stack_ix())); |
|
4430 | 1160 |
#else |
1161 |
//no pushl on 64bits |
|
1162 |
__ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); |
|
1163 |
__ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); |
|
1164 |
#endif |
|
1066 | 1165 |
} |
1 | 1166 |
|
1167 |
} else if (src->is_double_stack()) { |
|
1066 | 1168 |
#ifdef _LP64 |
1169 |
__ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); |
|
1170 |
__ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); |
|
1171 |
#else |
|
1 | 1172 |
__ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); |
1066 | 1173 |
// push and pop the part at src + wordSize, adding wordSize for the previous push |
1125
0e9a5f36b566
6746320: Hotspot regression test for 6512111 fails in -Xmixed mode
never
parents:
1066
diff
changeset
|
1174 |
__ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); |
0e9a5f36b566
6746320: Hotspot regression test for 6512111 fails in -Xmixed mode
never
parents:
1066
diff
changeset
|
1175 |
__ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); |
1 | 1176 |
__ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); |
1066 | 1177 |
#endif // _LP64 |
1 | 1178 |
|
1179 |
} else { |
|
1180 |
ShouldNotReachHere(); |
|
1181 |
} |
|
1182 |
} |
|
1183 |
||
1184 |
||
1185 |
void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool /* unaligned */) { |
|
1186 |
assert(src->is_address(), "should not call otherwise"); |
|
1187 |
assert(dest->is_register(), "should not call otherwise"); |
|
1188 |
||
1189 |
LIR_Address* addr = src->as_address_ptr(); |
|
1190 |
Address from_addr = as_Address(addr); |
|
1191 |
||
1192 |
switch (type) { |
|
1193 |
case T_BOOLEAN: // fall through |
|
1194 |
case T_BYTE: // fall through |
|
1195 |
case T_CHAR: // fall through |
|
1196 |
case T_SHORT: |
|
1197 |
if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { |
|
1198 |
// on pre P6 processors we may get partial register stalls |
|
1199 |
// so blow away the value of to_rinfo before loading a |
|
1200 |
// partial word into it. Do it here so that it precedes |
|
1201 |
// the potential patch point below. |
|
1066 | 1202 |
__ xorptr(dest->as_register(), dest->as_register()); |
1 | 1203 |
} |
1204 |
break; |
|
1205 |
} |
|
1206 |
||
1207 |
PatchingStub* patch = NULL; |
|
1208 |
if (patch_code != lir_patch_none) { |
|
1209 |
patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
|
1066 | 1210 |
assert(from_addr.disp() != 0, "must have"); |
1 | 1211 |
} |
1212 |
if (info != NULL) { |
|
1213 |
add_debug_info_for_null_check_here(info); |
|
1214 |
} |
|
1215 |
||
1216 |
switch (type) { |
|
1217 |
case T_FLOAT: { |
|
1218 |
if (dest->is_single_xmm()) { |
|
1219 |
__ movflt(dest->as_xmm_float_reg(), from_addr); |
|
1220 |
} else { |
|
1221 |
assert(dest->is_single_fpu(), "must be"); |
|
1222 |
assert(dest->fpu_regnr() == 0, "dest must be TOS"); |
|
1223 |
__ fld_s(from_addr); |
|
1224 |
} |
|
1225 |
break; |
|
1226 |
} |
|
1227 |
||
1228 |
case T_DOUBLE: { |
|
1229 |
if (dest->is_double_xmm()) { |
|
1230 |
__ movdbl(dest->as_xmm_double_reg(), from_addr); |
|
1231 |
} else { |
|
1232 |
assert(dest->is_double_fpu(), "must be"); |
|
1233 |
assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); |
|
1234 |
__ fld_d(from_addr); |
|
1235 |
} |
|
1236 |
break; |
|
1237 |
} |
|
1238 |
||
1239 |
case T_ADDRESS: // fall through |
|
1240 |
case T_OBJECT: // fall through |
|
1241 |
case T_ARRAY: // fall through |
|
1066 | 1242 |
#ifdef _LP64 |
1243 |
__ movptr(dest->as_register(), from_addr); |
|
1244 |
break; |
|
1245 |
#endif // _L64 |
|
1 | 1246 |
case T_INT: |
5354
30df1bf62cca
6946892: c1 shouldn't sign-extend to upper 32bits on x64
iveresov
parents:
5334
diff
changeset
|
1247 |
__ movl(dest->as_register(), from_addr); |
1 | 1248 |
break; |
1249 |
||
1250 |
case T_LONG: { |
|
1251 |
Register to_lo = dest->as_register_lo(); |
|
1252 |
Register to_hi = dest->as_register_hi(); |
|
1066 | 1253 |
#ifdef _LP64 |
1254 |
__ movptr(to_lo, as_Address_lo(addr)); |
|
1255 |
#else |
|
1 | 1256 |
Register base = addr->base()->as_register(); |
1257 |
Register index = noreg; |
|
1258 |
if (addr->index()->is_register()) { |
|
1259 |
index = addr->index()->as_register(); |
|
1260 |
} |
|
1261 |
if ((base == to_lo && index == to_hi) || |
|
1262 |
(base == to_hi && index == to_lo)) { |
|
1263 |
// addresses with 2 registers are only formed as a result of |
|
1264 |
// array access so this code will never have to deal with |
|
1265 |
// patches or null checks. |
|
1266 |
assert(info == NULL && patch == NULL, "must be"); |
|
1066 | 1267 |
__ lea(to_hi, as_Address(addr)); |
1 | 1268 |
__ movl(to_lo, Address(to_hi, 0)); |
1269 |
__ movl(to_hi, Address(to_hi, BytesPerWord)); |
|
1270 |
} else if (base == to_lo || index == to_lo) { |
|
1271 |
assert(base != to_hi, "can't be"); |
|
1272 |
assert(index == noreg || (index != base && index != to_hi), "can't handle this"); |
|
1273 |
__ movl(to_hi, as_Address_hi(addr)); |
|
1274 |
if (patch != NULL) { |
|
1275 |
patching_epilog(patch, lir_patch_high, base, info); |
|
1276 |
patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
|
1277 |
patch_code = lir_patch_low; |
|
1278 |
} |
|
1279 |
__ movl(to_lo, as_Address_lo(addr)); |
|
1280 |
} else { |
|
1281 |
assert(index == noreg || (index != base && index != to_lo), "can't handle this"); |
|
1282 |
__ movl(to_lo, as_Address_lo(addr)); |
|
1283 |
if (patch != NULL) { |
|
1284 |
patching_epilog(patch, lir_patch_low, base, info); |
|
1285 |
patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
|
1286 |
patch_code = lir_patch_high; |
|
1287 |
} |
|
1288 |
__ movl(to_hi, as_Address_hi(addr)); |
|
1289 |
} |
|
1066 | 1290 |
#endif // _LP64 |
1 | 1291 |
break; |
1292 |
} |
|
1293 |
||
1294 |
case T_BOOLEAN: // fall through |
|
1295 |
case T_BYTE: { |
|
1296 |
Register dest_reg = dest->as_register(); |
|
1297 |
assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); |
|
1298 |
if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { |
|
1066 | 1299 |
__ movsbl(dest_reg, from_addr); |
1 | 1300 |
} else { |
1301 |
__ movb(dest_reg, from_addr); |
|
1302 |
__ shll(dest_reg, 24); |
|
1303 |
__ sarl(dest_reg, 24); |
|
1304 |
} |
|
1305 |
break; |
|
1306 |
} |
|
1307 |
||
1308 |
case T_CHAR: { |
|
1309 |
Register dest_reg = dest->as_register(); |
|
1310 |
assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); |
|
1311 |
if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { |
|
1066 | 1312 |
__ movzwl(dest_reg, from_addr); |
1 | 1313 |
} else { |
1314 |
__ movw(dest_reg, from_addr); |
|
1315 |
} |
|
1316 |
break; |
|
1317 |
} |
|
1318 |
||
1319 |
case T_SHORT: { |
|
1320 |
Register dest_reg = dest->as_register(); |
|
1321 |
if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { |
|
1066 | 1322 |
__ movswl(dest_reg, from_addr); |
1 | 1323 |
} else { |
1324 |
__ movw(dest_reg, from_addr); |
|
1325 |
__ shll(dest_reg, 16); |
|
1326 |
__ sarl(dest_reg, 16); |
|
1327 |
} |
|
1328 |
break; |
|
1329 |
} |
|
1330 |
||
1331 |
default: |
|
1332 |
ShouldNotReachHere(); |
|
1333 |
} |
|
1334 |
||
1335 |
if (patch != NULL) { |
|
1336 |
patching_epilog(patch, patch_code, addr->base()->as_register(), info); |
|
1337 |
} |
|
1338 |
||
1339 |
if (type == T_ARRAY || type == T_OBJECT) { |
|
1340 |
__ verify_oop(dest->as_register()); |
|
1341 |
} |
|
1342 |
} |
|
1343 |
||
1344 |
||
1345 |
void LIR_Assembler::prefetchr(LIR_Opr src) { |
|
1346 |
LIR_Address* addr = src->as_address_ptr(); |
|
1347 |
Address from_addr = as_Address(addr); |
|
1348 |
||
1349 |
if (VM_Version::supports_sse()) { |
|
1350 |
switch (ReadPrefetchInstr) { |
|
1351 |
case 0: |
|
1352 |
__ prefetchnta(from_addr); break; |
|
1353 |
case 1: |
|
1354 |
__ prefetcht0(from_addr); break; |
|
1355 |
case 2: |
|
1356 |
__ prefetcht2(from_addr); break; |
|
1357 |
default: |
|
1358 |
ShouldNotReachHere(); break; |
|
1359 |
} |
|
1360 |
} else if (VM_Version::supports_3dnow()) { |
|
1361 |
__ prefetchr(from_addr); |
|
1362 |
} |
|
1363 |
} |
|
1364 |
||
1365 |
||
1366 |
void LIR_Assembler::prefetchw(LIR_Opr src) { |
|
1367 |
LIR_Address* addr = src->as_address_ptr(); |
|
1368 |
Address from_addr = as_Address(addr); |
|
1369 |
||
1370 |
if (VM_Version::supports_sse()) { |
|
1371 |
switch (AllocatePrefetchInstr) { |
|
1372 |
case 0: |
|
1373 |
__ prefetchnta(from_addr); break; |
|
1374 |
case 1: |
|
1375 |
__ prefetcht0(from_addr); break; |
|
1376 |
case 2: |
|
1377 |
__ prefetcht2(from_addr); break; |
|
1378 |
case 3: |
|
1379 |
__ prefetchw(from_addr); break; |
|
1380 |
default: |
|
1381 |
ShouldNotReachHere(); break; |
|
1382 |
} |
|
1383 |
} else if (VM_Version::supports_3dnow()) { |
|
1384 |
__ prefetchw(from_addr); |
|
1385 |
} |
|
1386 |
} |
|
1387 |
||
1388 |
||
1389 |
NEEDS_CLEANUP; // This could be static? |
|
1390 |
Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { |
|
202
dc13bf0e5d5d
6633953: type2aelembytes{T_ADDRESS} should be 8 bytes in 64 bit VM
kvn
parents:
1
diff
changeset
|
1391 |
int elem_size = type2aelembytes(type); |
1 | 1392 |
switch (elem_size) { |
1393 |
case 1: return Address::times_1; |
|
1394 |
case 2: return Address::times_2; |
|
1395 |
case 4: return Address::times_4; |
|
1396 |
case 8: return Address::times_8; |
|
1397 |
} |
|
1398 |
ShouldNotReachHere(); |
|
1399 |
return Address::no_scale; |
|
1400 |
} |
|
1401 |
||
1402 |
||
1403 |
void LIR_Assembler::emit_op3(LIR_Op3* op) { |
|
1404 |
switch (op->code()) { |
|
1405 |
case lir_idiv: |
|
1406 |
case lir_irem: |
|
1407 |
arithmetic_idiv(op->code(), |
|
1408 |
op->in_opr1(), |
|
1409 |
op->in_opr2(), |
|
1410 |
op->in_opr3(), |
|
1411 |
op->result_opr(), |
|
1412 |
op->info()); |
|
1413 |
break; |
|
1414 |
default: ShouldNotReachHere(); break; |
|
1415 |
} |
|
1416 |
} |
|
1417 |
||
1418 |
void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { |
|
1419 |
#ifdef ASSERT |
|
1420 |
assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); |
|
1421 |
if (op->block() != NULL) _branch_target_blocks.append(op->block()); |
|
1422 |
if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); |
|
1423 |
#endif |
|
1424 |
||
1425 |
if (op->cond() == lir_cond_always) { |
|
1426 |
if (op->info() != NULL) add_debug_info_for_branch(op->info()); |
|
1427 |
__ jmp (*(op->label())); |
|
1428 |
} else { |
|
1429 |
Assembler::Condition acond = Assembler::zero; |
|
1430 |
if (op->code() == lir_cond_float_branch) { |
|
1431 |
assert(op->ublock() != NULL, "must have unordered successor"); |
|
1432 |
__ jcc(Assembler::parity, *(op->ublock()->label())); |
|
1433 |
switch(op->cond()) { |
|
1434 |
case lir_cond_equal: acond = Assembler::equal; break; |
|
1435 |
case lir_cond_notEqual: acond = Assembler::notEqual; break; |
|
1436 |
case lir_cond_less: acond = Assembler::below; break; |
|
1437 |
case lir_cond_lessEqual: acond = Assembler::belowEqual; break; |
|
1438 |
case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; |
|
1439 |
case lir_cond_greater: acond = Assembler::above; break; |
|
1440 |
default: ShouldNotReachHere(); |
|
1441 |
} |
|
1442 |
} else { |
|
1443 |
switch (op->cond()) { |
|
1444 |
case lir_cond_equal: acond = Assembler::equal; break; |
|
1445 |
case lir_cond_notEqual: acond = Assembler::notEqual; break; |
|
1446 |
case lir_cond_less: acond = Assembler::less; break; |
|
1447 |
case lir_cond_lessEqual: acond = Assembler::lessEqual; break; |
|
1448 |
case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; |
|
1449 |
case lir_cond_greater: acond = Assembler::greater; break; |
|
1450 |
case lir_cond_belowEqual: acond = Assembler::belowEqual; break; |
|
1451 |
case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; |
|
1452 |
default: ShouldNotReachHere(); |
|
1453 |
} |
|
1454 |
} |
|
1455 |
__ jcc(acond,*(op->label())); |
|
1456 |
} |
|
1457 |
} |
|
1458 |
||
1459 |
void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { |
|
1460 |
LIR_Opr src = op->in_opr(); |
|
1461 |
LIR_Opr dest = op->result_opr(); |
|
1462 |
||
1463 |
switch (op->bytecode()) { |
|
1464 |
case Bytecodes::_i2l: |
|
1066 | 1465 |
#ifdef _LP64 |
1466 |
__ movl2ptr(dest->as_register_lo(), src->as_register()); |
|
1467 |
#else |
|
1 | 1468 |
move_regs(src->as_register(), dest->as_register_lo()); |
1469 |
move_regs(src->as_register(), dest->as_register_hi()); |
|
1470 |
__ sarl(dest->as_register_hi(), 31); |
|
1066 | 1471 |
#endif // LP64 |
1 | 1472 |
break; |
1473 |
||
1474 |
case Bytecodes::_l2i: |
|
1475 |
move_regs(src->as_register_lo(), dest->as_register()); |
|
1476 |
break; |
|
1477 |
||
1478 |
case Bytecodes::_i2b: |
|
1479 |
move_regs(src->as_register(), dest->as_register()); |
|
1480 |
__ sign_extend_byte(dest->as_register()); |
|
1481 |
break; |
|
1482 |
||
1483 |
case Bytecodes::_i2c: |
|
1484 |
move_regs(src->as_register(), dest->as_register()); |
|
1485 |
__ andl(dest->as_register(), 0xFFFF); |
|
1486 |
break; |
|
1487 |
||
1488 |
case Bytecodes::_i2s: |
|
1489 |
move_regs(src->as_register(), dest->as_register()); |
|
1490 |
__ sign_extend_short(dest->as_register()); |
|
1491 |
break; |
|
1492 |
||
1493 |
||
1494 |
case Bytecodes::_f2d: |
|
1495 |
case Bytecodes::_d2f: |
|
1496 |
if (dest->is_single_xmm()) { |
|
1497 |
__ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); |
|
1498 |
} else if (dest->is_double_xmm()) { |
|
1499 |
__ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); |
|
1500 |
} else { |
|
1501 |
assert(src->fpu() == dest->fpu(), "register must be equal"); |
|
1502 |
// do nothing (float result is rounded later through spilling) |
|
1503 |
} |
|
1504 |
break; |
|
1505 |
||
1506 |
case Bytecodes::_i2f: |
|
1507 |
case Bytecodes::_i2d: |
|
1508 |
if (dest->is_single_xmm()) { |
|
1066 | 1509 |
__ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); |
1 | 1510 |
} else if (dest->is_double_xmm()) { |
1066 | 1511 |
__ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); |
1 | 1512 |
} else { |
1513 |
assert(dest->fpu() == 0, "result must be on TOS"); |
|
1514 |
__ movl(Address(rsp, 0), src->as_register()); |
|
1515 |
__ fild_s(Address(rsp, 0)); |
|
1516 |
} |
|
1517 |
break; |
|
1518 |
||
1519 |
case Bytecodes::_f2i: |
|
1520 |
case Bytecodes::_d2i: |
|
1521 |
if (src->is_single_xmm()) { |
|
1066 | 1522 |
__ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); |
1 | 1523 |
} else if (src->is_double_xmm()) { |
1066 | 1524 |
__ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); |
1 | 1525 |
} else { |
1526 |
assert(src->fpu() == 0, "input must be on TOS"); |
|
1527 |
__ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); |
|
1528 |
__ fist_s(Address(rsp, 0)); |
|
1529 |
__ movl(dest->as_register(), Address(rsp, 0)); |
|
1530 |
__ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); |
|
1531 |
} |
|
1532 |
||
1533 |
// IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub |
|
1534 |
assert(op->stub() != NULL, "stub required"); |
|
1535 |
__ cmpl(dest->as_register(), 0x80000000); |
|
1536 |
__ jcc(Assembler::equal, *op->stub()->entry()); |
|
1537 |
__ bind(*op->stub()->continuation()); |
|
1538 |
break; |
|
1539 |
||
1540 |
case Bytecodes::_l2f: |
|
1541 |
case Bytecodes::_l2d: |
|
1542 |
assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); |
|
1543 |
assert(dest->fpu() == 0, "result must be on TOS"); |
|
1544 |
||
1066 | 1545 |
__ movptr(Address(rsp, 0), src->as_register_lo()); |
1546 |
NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); |
|
1 | 1547 |
__ fild_d(Address(rsp, 0)); |
1548 |
// float result is rounded later through spilling |
|
1549 |
break; |
|
1550 |
||
1551 |
case Bytecodes::_f2l: |
|
1552 |
case Bytecodes::_d2l: |
|
1553 |
assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); |
|
1554 |
assert(src->fpu() == 0, "input must be on TOS"); |
|
1066 | 1555 |
assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); |
1 | 1556 |
|
1557 |
// instruction sequence too long to inline it here |
|
1558 |
{ |
|
1559 |
__ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); |
|
1560 |
} |
|
1561 |
break; |
|
1562 |
||
1563 |
default: ShouldNotReachHere(); |
|
1564 |
} |
|
1565 |
} |
|
1566 |
||
1567 |
void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { |
|
1568 |
if (op->init_check()) { |
|
1569 |
__ cmpl(Address(op->klass()->as_register(), |
|
1570 |
instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc)), |
|
1571 |
instanceKlass::fully_initialized); |
|
1572 |
add_debug_info_for_null_check_here(op->stub()->info()); |
|
1573 |
__ jcc(Assembler::notEqual, *op->stub()->entry()); |
|
1574 |
} |
|
1575 |
__ allocate_object(op->obj()->as_register(), |
|
1576 |
op->tmp1()->as_register(), |
|
1577 |
op->tmp2()->as_register(), |
|
1578 |
op->header_size(), |
|
1579 |
op->object_size(), |
|
1580 |
op->klass()->as_register(), |
|
1581 |
*op->stub()->entry()); |
|
1582 |
__ bind(*op->stub()->continuation()); |
|
1583 |
} |
|
1584 |
||
1585 |
void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { |
|
1586 |
if (UseSlowPath || |
|
1587 |
(!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || |
|
1588 |
(!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { |
|
1589 |
__ jmp(*op->stub()->entry()); |
|
1590 |
} else { |
|
1591 |
Register len = op->len()->as_register(); |
|
1592 |
Register tmp1 = op->tmp1()->as_register(); |
|
1593 |
Register tmp2 = op->tmp2()->as_register(); |
|
1594 |
Register tmp3 = op->tmp3()->as_register(); |
|
1595 |
if (len == tmp1) { |
|
1596 |
tmp1 = tmp3; |
|
1597 |
} else if (len == tmp2) { |
|
1598 |
tmp2 = tmp3; |
|
1599 |
} else if (len == tmp3) { |
|
1600 |
// everything is ok |
|
1601 |
} else { |
|
1066 | 1602 |
__ mov(tmp3, len); |
1 | 1603 |
} |
1604 |
__ allocate_array(op->obj()->as_register(), |
|
1605 |
len, |
|
1606 |
tmp1, |
|
1607 |
tmp2, |
|
1608 |
arrayOopDesc::header_size(op->type()), |
|
1609 |
array_element_size(op->type()), |
|
1610 |
op->klass()->as_register(), |
|
1611 |
*op->stub()->entry()); |
|
1612 |
} |
|
1613 |
__ bind(*op->stub()->continuation()); |
|
1614 |
} |
|
1615 |
||
6453 | 1616 |
void LIR_Assembler::type_profile_helper(Register mdo, |
1617 |
ciMethodData *md, ciProfileData *data, |
|
1618 |
Register recv, Label* update_done) { |
|
1619 |
uint i; |
|
1620 |
for (i = 0; i < ReceiverTypeData::row_limit(); i++) { |
|
1621 |
Label next_test; |
|
1622 |
// See if the receiver is receiver[n]. |
|
1623 |
__ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); |
|
1624 |
__ jccb(Assembler::notEqual, next_test); |
|
1625 |
Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); |
|
1626 |
__ addptr(data_addr, DataLayout::counter_increment); |
|
1627 |
__ jmpb(*update_done); |
|
1628 |
__ bind(next_test); |
|
1629 |
} |
|
1630 |
||
1631 |
// Didn't find receiver; find next empty slot and fill it in |
|
1632 |
for (i = 0; i < ReceiverTypeData::row_limit(); i++) { |
|
1633 |
Label next_test; |
|
1634 |
Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); |
|
1635 |
__ cmpptr(recv_addr, (intptr_t)NULL_WORD); |
|
1636 |
__ jccb(Assembler::notEqual, next_test); |
|
1637 |
__ movptr(recv_addr, recv); |
|
1638 |
__ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment); |
|
1639 |
__ jmpb(*update_done); |
|
1640 |
__ bind(next_test); |
|
1641 |
} |
|
1642 |
} |
|
1643 |
||
1644 |
void LIR_Assembler::emit_checkcast(LIR_OpTypeCheck *op) { |
|
1645 |
assert(op->code() == lir_checkcast, "Invalid operation"); |
|
1646 |
// we always need a stub for the failure case. |
|
1647 |
CodeStub* stub = op->stub(); |
|
1648 |
Register obj = op->object()->as_register(); |
|
1649 |
Register k_RInfo = op->tmp1()->as_register(); |
|
1650 |
Register klass_RInfo = op->tmp2()->as_register(); |
|
1651 |
Register dst = op->result_opr()->as_register(); |
|
1652 |
ciKlass* k = op->klass(); |
|
1653 |
Register Rtmp1 = noreg; |
|
1654 |
||
1655 |
// check if it needs to be profiled |
|
1656 |
ciMethodData* md; |
|
1657 |
ciProfileData* data; |
|
1658 |
||
1659 |
if (op->should_profile()) { |
|
1660 |
ciMethod* method = op->profiled_method(); |
|
1661 |
assert(method != NULL, "Should have method"); |
|
1662 |
int bci = op->profiled_bci(); |
|
1663 |
md = method->method_data(); |
|
1664 |
if (md == NULL) { |
|
1665 |
bailout("out of memory building methodDataOop"); |
|
1666 |
return; |
|
1667 |
} |
|
1668 |
data = md->bci_to_data(bci); |
|
1669 |
assert(data != NULL, "need data for checkcast"); |
|
1670 |
assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for checkcast"); |
|
1671 |
} |
|
1672 |
Label profile_cast_failure; |
|
1673 |
||
1674 |
Label done, done_null; |
|
1675 |
// Where to go in case of cast failure |
|
1676 |
Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); |
|
1677 |
||
1678 |
if (obj == k_RInfo) { |
|
1679 |
k_RInfo = dst; |
|
1680 |
} else if (obj == klass_RInfo) { |
|
1681 |
klass_RInfo = dst; |
|
1682 |
} |
|
1683 |
if (k->is_loaded()) { |
|
1684 |
select_different_registers(obj, dst, k_RInfo, klass_RInfo); |
|
1685 |
} else { |
|
1686 |
Rtmp1 = op->tmp3()->as_register(); |
|
1687 |
select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); |
|
1688 |
} |
|
1689 |
||
1690 |
assert_different_registers(obj, k_RInfo, klass_RInfo); |
|
1691 |
if (!k->is_loaded()) { |
|
1692 |
jobject2reg_with_patching(k_RInfo, op->info_for_patch()); |
|
1693 |
} else { |
|
1694 |
#ifdef _LP64 |
|
1695 |
__ movoop(k_RInfo, k->constant_encoding()); |
|
1696 |
#endif // _LP64 |
|
1697 |
} |
|
1698 |
assert(obj != k_RInfo, "must be different"); |
|
1699 |
||
1700 |
__ cmpptr(obj, (int32_t)NULL_WORD); |
|
1701 |
if (op->should_profile()) { |
|
1702 |
Label profile_done; |
|
1703 |
__ jccb(Assembler::notEqual, profile_done); |
|
1704 |
// Object is null; update methodDataOop |
|
1705 |
Register mdo = klass_RInfo; |
|
1706 |
__ movoop(mdo, md->constant_encoding()); |
|
1707 |
Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); |
|
1708 |
int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); |
|
1709 |
__ orl(data_addr, header_bits); |
|
1710 |
__ jmp(done_null); |
|
1711 |
__ bind(profile_done); |
|
1712 |
} else { |
|
1713 |
__ jcc(Assembler::equal, done_null); |
|
1714 |
} |
|
1715 |
__ verify_oop(obj); |
|
1716 |
||
1717 |
if (op->fast_check()) { |
|
1718 |
// get object classo |
|
1719 |
// not a safepoint as obj null check happens earlier |
|
1720 |
if (k->is_loaded()) { |
|
1721 |
#ifdef _LP64 |
|
1722 |
__ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); |
|
1723 |
#else |
|
1724 |
__ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); |
|
1725 |
#endif // _LP64 |
|
1726 |
} else { |
|
1727 |
__ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); |
|
1728 |
} |
|
1729 |
__ jcc(Assembler::notEqual, *failure_target); |
|
1730 |
} else { |
|
1731 |
// get object class |
|
1732 |
// not a safepoint as obj null check happens earlier |
|
1733 |
__ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); |
|
1734 |
if (k->is_loaded()) { |
|
1735 |
// See if we get an immediate positive hit |
|
1736 |
#ifdef _LP64 |
|
1737 |
__ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); |
|
1738 |
#else |
|
1739 |
__ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); |
|
1740 |
#endif // _LP64 |
|
1741 |
if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) { |
|
1742 |
__ jcc(Assembler::notEqual, *failure_target); |
|
1743 |
} else { |
|
1744 |
// See if we get an immediate positive hit |
|
1745 |
__ jcc(Assembler::equal, done); |
|
1746 |
// check for self |
|
1747 |
#ifdef _LP64 |
|
1748 |
__ cmpptr(klass_RInfo, k_RInfo); |
|
1749 |
#else |
|
1750 |
__ cmpoop(klass_RInfo, k->constant_encoding()); |
|
1751 |
#endif // _LP64 |
|
1752 |
__ jcc(Assembler::equal, done); |
|
1753 |
||
1754 |
__ push(klass_RInfo); |
|
1755 |
#ifdef _LP64 |
|
1756 |
__ push(k_RInfo); |
|
1757 |
#else |
|
1758 |
__ pushoop(k->constant_encoding()); |
|
1759 |
#endif // _LP64 |
|
1760 |
__ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
|
1761 |
__ pop(klass_RInfo); |
|
1762 |
__ pop(klass_RInfo); |
|
1763 |
// result is a boolean |
|
1764 |
__ cmpl(klass_RInfo, 0); |
|
1765 |
__ jcc(Assembler::equal, *failure_target); |
|
1766 |
} |
|
1767 |
} else { |
|
1768 |
// perform the fast part of the checking logic |
|
1769 |
__ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, &done, failure_target, NULL); |
|
1770 |
// call out-of-line instance of __ check_klass_subtype_slow_path(...): |
|
1771 |
__ push(klass_RInfo); |
|
1772 |
__ push(k_RInfo); |
|
1773 |
__ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
|
1774 |
__ pop(klass_RInfo); |
|
1775 |
__ pop(k_RInfo); |
|
1776 |
// result is a boolean |
|
1777 |
__ cmpl(k_RInfo, 0); |
|
1778 |
__ jcc(Assembler::equal, *failure_target); |
|
1779 |
} |
|
1780 |
} |
|
1781 |
__ bind(done); |
|
1782 |
||
1783 |
if (op->should_profile()) { |
|
1784 |
Register mdo = klass_RInfo, recv = k_RInfo; |
|
1785 |
__ movoop(mdo, md->constant_encoding()); |
|
1786 |
__ movptr(recv, Address(obj, oopDesc::klass_offset_in_bytes())); |
|
1787 |
Label update_done; |
|
1788 |
type_profile_helper(mdo, md, data, recv, &update_done); |
|
1789 |
__ jmpb(update_done); |
|
1790 |
||
1791 |
__ bind(profile_cast_failure); |
|
1792 |
__ movoop(mdo, md->constant_encoding()); |
|
1793 |
Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); |
|
1794 |
__ subptr(counter_addr, DataLayout::counter_increment); |
|
1795 |
__ jmp(*stub->entry()); |
|
1796 |
||
1797 |
__ bind(update_done); |
|
1798 |
} |
|
1799 |
__ bind(done_null); |
|
1800 |
if (dst != obj) { |
|
1801 |
__ mov(dst, obj); |
|
1802 |
} |
|
1803 |
} |
|
1 | 1804 |
|
1805 |
void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { |
|
1806 |
LIR_Code code = op->code(); |
|
1807 |
if (code == lir_store_check) { |
|
1808 |
Register value = op->object()->as_register(); |
|
1809 |
Register array = op->array()->as_register(); |
|
1810 |
Register k_RInfo = op->tmp1()->as_register(); |
|
1811 |
Register klass_RInfo = op->tmp2()->as_register(); |
|
1812 |
Register Rtmp1 = op->tmp3()->as_register(); |
|
1813 |
||
1814 |
CodeStub* stub = op->stub(); |
|
1815 |
Label done; |
|
1066 | 1816 |
__ cmpptr(value, (int32_t)NULL_WORD); |
1 | 1817 |
__ jcc(Assembler::equal, done); |
1818 |
add_debug_info_for_null_check_here(op->info_for_exception()); |
|
1066 | 1819 |
__ movptr(k_RInfo, Address(array, oopDesc::klass_offset_in_bytes())); |
1820 |
__ movptr(klass_RInfo, Address(value, oopDesc::klass_offset_in_bytes())); |
|
1 | 1821 |
|
1822 |
// get instance klass |
|
1066 | 1823 |
__ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc))); |
2256
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2148
diff
changeset
|
1824 |
// perform the fast part of the checking logic |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2148
diff
changeset
|
1825 |
__ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, &done, stub->entry(), NULL); |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2148
diff
changeset
|
1826 |
// call out-of-line instance of __ check_klass_subtype_slow_path(...): |
1066 | 1827 |
__ push(klass_RInfo); |
1828 |
__ push(k_RInfo); |
|
1 | 1829 |
__ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
1066 | 1830 |
__ pop(klass_RInfo); |
1831 |
__ pop(k_RInfo); |
|
1832 |
// result is a boolean |
|
1 | 1833 |
__ cmpl(k_RInfo, 0); |
1834 |
__ jcc(Assembler::equal, *stub->entry()); |
|
1835 |
__ bind(done); |
|
1836 |
} else if (code == lir_instanceof) { |
|
1837 |
Register obj = op->object()->as_register(); |
|
1838 |
Register k_RInfo = op->tmp1()->as_register(); |
|
1839 |
Register klass_RInfo = op->tmp2()->as_register(); |
|
1840 |
Register dst = op->result_opr()->as_register(); |
|
1841 |
ciKlass* k = op->klass(); |
|
1842 |
||
1843 |
Label done; |
|
1844 |
Label zero; |
|
1845 |
Label one; |
|
1846 |
if (obj == k_RInfo) { |
|
1847 |
k_RInfo = klass_RInfo; |
|
1848 |
klass_RInfo = obj; |
|
1849 |
} |
|
1850 |
// patching may screw with our temporaries on sparc, |
|
1851 |
// so let's do it before loading the class |
|
1852 |
if (!k->is_loaded()) { |
|
1853 |
jobject2reg_with_patching(k_RInfo, op->info_for_patch()); |
|
1066 | 1854 |
} else { |
3908
24b55ad4c228
6863023: need non-perm oops in code cache for JSR 292
jrose
parents:
2867
diff
changeset
|
1855 |
LP64_ONLY(__ movoop(k_RInfo, k->constant_encoding())); |
1 | 1856 |
} |
1857 |
assert(obj != k_RInfo, "must be different"); |
|
1858 |
||
1859 |
__ verify_oop(obj); |
|
1860 |
if (op->fast_check()) { |
|
1066 | 1861 |
__ cmpptr(obj, (int32_t)NULL_WORD); |
1 | 1862 |
__ jcc(Assembler::equal, zero); |
1863 |
// get object class |
|
1864 |
// not a safepoint as obj null check happens earlier |
|
1066 | 1865 |
if (LP64_ONLY(false &&) k->is_loaded()) { |
3908
24b55ad4c228
6863023: need non-perm oops in code cache for JSR 292
jrose
parents:
2867
diff
changeset
|
1866 |
NOT_LP64(__ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding())); |
1 | 1867 |
k_RInfo = noreg; |
1868 |
} else { |
|
1066 | 1869 |
__ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); |
1 | 1870 |
|
1871 |
} |
|
1872 |
__ jcc(Assembler::equal, one); |
|
1873 |
} else { |
|
1874 |
// get object class |
|
1875 |
// not a safepoint as obj null check happens earlier |
|
1066 | 1876 |
__ cmpptr(obj, (int32_t)NULL_WORD); |
1 | 1877 |
__ jcc(Assembler::equal, zero); |
1066 | 1878 |
__ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); |
1879 |
||
1880 |
#ifndef _LP64 |
|
1 | 1881 |
if (k->is_loaded()) { |
1882 |
// See if we get an immediate positive hit |
|
3908
24b55ad4c228
6863023: need non-perm oops in code cache for JSR 292
jrose
parents:
2867
diff
changeset
|
1883 |
__ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); |
1 | 1884 |
__ jcc(Assembler::equal, one); |
1885 |
if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() == k->super_check_offset()) { |
|
1886 |
// check for self |
|
3908
24b55ad4c228
6863023: need non-perm oops in code cache for JSR 292
jrose
parents:
2867
diff
changeset
|
1887 |
__ cmpoop(klass_RInfo, k->constant_encoding()); |
1 | 1888 |
__ jcc(Assembler::equal, one); |
1066 | 1889 |
__ push(klass_RInfo); |
3908
24b55ad4c228
6863023: need non-perm oops in code cache for JSR 292
jrose
parents:
2867
diff
changeset
|
1890 |
__ pushoop(k->constant_encoding()); |
1 | 1891 |
__ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
1066 | 1892 |
__ pop(klass_RInfo); |
1893 |
__ pop(dst); |
|
1 | 1894 |
__ jmp(done); |
1895 |
} |
|
2256
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2148
diff
changeset
|
1896 |
} |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2148
diff
changeset
|
1897 |
else // next block is unconditional if LP64: |
1066 | 1898 |
#endif // LP64 |
2256
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2148
diff
changeset
|
1899 |
{ |
1 | 1900 |
assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers"); |
1901 |
||
2256
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2148
diff
changeset
|
1902 |
// perform the fast part of the checking logic |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2148
diff
changeset
|
1903 |
__ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, dst, &one, &zero, NULL); |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2148
diff
changeset
|
1904 |
// call out-of-line instance of __ check_klass_subtype_slow_path(...): |
1066 | 1905 |
__ push(klass_RInfo); |
1906 |
__ push(k_RInfo); |
|
1 | 1907 |
__ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
1066 | 1908 |
__ pop(klass_RInfo); |
1909 |
__ pop(dst); |
|
1 | 1910 |
__ jmp(done); |
1911 |
} |
|
1912 |
} |
|
1913 |
__ bind(zero); |
|
1066 | 1914 |
__ xorptr(dst, dst); |
1 | 1915 |
__ jmp(done); |
1916 |
__ bind(one); |
|
1066 | 1917 |
__ movptr(dst, 1); |
1 | 1918 |
__ bind(done); |
1919 |
} else { |
|
1920 |
ShouldNotReachHere(); |
|
1921 |
} |
|
1922 |
||
1923 |
} |
|
1924 |
||
1925 |
||
1926 |
void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { |
|
1066 | 1927 |
if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { |
1 | 1928 |
assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); |
1929 |
assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); |
|
1930 |
assert(op->new_value()->as_register_lo() == rbx, "wrong register"); |
|
1931 |
assert(op->new_value()->as_register_hi() == rcx, "wrong register"); |
|
1932 |
Register addr = op->addr()->as_register(); |
|
1933 |
if (os::is_MP()) { |
|
1934 |
__ lock(); |
|
1935 |
} |
|
1066 | 1936 |
NOT_LP64(__ cmpxchg8(Address(addr, 0))); |
1937 |
||
1938 |
} else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { |
|
1939 |
NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) |
|
1940 |
Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); |
|
1 | 1941 |
Register newval = op->new_value()->as_register(); |
1942 |
Register cmpval = op->cmp_value()->as_register(); |
|
1943 |
assert(cmpval == rax, "wrong register"); |
|
1944 |
assert(newval != NULL, "new val must be register"); |
|
1945 |
assert(cmpval != newval, "cmp and new values must be in different registers"); |
|
1946 |
assert(cmpval != addr, "cmp and addr must be in different registers"); |
|
1947 |
assert(newval != addr, "new value and addr must be in different registers"); |
|
1948 |
if (os::is_MP()) { |
|
1949 |
__ lock(); |
|
1950 |
} |
|
1066 | 1951 |
if ( op->code() == lir_cas_obj) { |
1952 |
__ cmpxchgptr(newval, Address(addr, 0)); |
|
1953 |
} else if (op->code() == lir_cas_int) { |
|
1954 |
__ cmpxchgl(newval, Address(addr, 0)); |
|
1955 |
} else { |
|
1956 |
LP64_ONLY(__ cmpxchgq(newval, Address(addr, 0))); |
|
1957 |
} |
|
1958 |
#ifdef _LP64 |
|
1959 |
} else if (op->code() == lir_cas_long) { |
|
1960 |
Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); |
|
1961 |
Register newval = op->new_value()->as_register_lo(); |
|
1962 |
Register cmpval = op->cmp_value()->as_register_lo(); |
|
1963 |
assert(cmpval == rax, "wrong register"); |
|
1964 |
assert(newval != NULL, "new val must be register"); |
|
1965 |
assert(cmpval != newval, "cmp and new values must be in different registers"); |
|
1966 |
assert(cmpval != addr, "cmp and addr must be in different registers"); |
|
1967 |
assert(newval != addr, "new value and addr must be in different registers"); |
|
1968 |
if (os::is_MP()) { |
|
1969 |
__ lock(); |
|
1970 |
} |
|
1971 |
__ cmpxchgq(newval, Address(addr, 0)); |
|
1972 |
#endif // _LP64 |
|
1 | 1973 |
} else { |
1974 |
Unimplemented(); |
|
1975 |
} |
|
1976 |
} |
|
1977 |
||
1978 |
void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) { |
|
1979 |
Assembler::Condition acond, ncond; |
|
1980 |
switch (condition) { |
|
1981 |
case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; |
|
1982 |
case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; |
|
1983 |
case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; |
|
1984 |
case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; |
|
1985 |
case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; |
|
1986 |
case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; |
|
1987 |
case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; |
|
1988 |
case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; |
|
1989 |
default: ShouldNotReachHere(); |
|
1990 |
} |
|
1991 |
||
1992 |
if (opr1->is_cpu_register()) { |
|
1993 |
reg2reg(opr1, result); |
|
1994 |
} else if (opr1->is_stack()) { |
|
1995 |
stack2reg(opr1, result, result->type()); |
|
1996 |
} else if (opr1->is_constant()) { |
|
1997 |
const2reg(opr1, result, lir_patch_none, NULL); |
|
1998 |
} else { |
|
1999 |
ShouldNotReachHere(); |
|
2000 |
} |
|
2001 |
||
2002 |
if (VM_Version::supports_cmov() && !opr2->is_constant()) { |
|
2003 |
// optimized version that does not require a branch |
|
2004 |
if (opr2->is_single_cpu()) { |
|
2005 |
assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); |
|
1066 | 2006 |
__ cmov(ncond, result->as_register(), opr2->as_register()); |
1 | 2007 |
} else if (opr2->is_double_cpu()) { |
2008 |
assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); |
|
2009 |
assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); |
|
1066 | 2010 |
__ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); |
2011 |
NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) |
|
1 | 2012 |
} else if (opr2->is_single_stack()) { |
2013 |
__ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); |
|
2014 |
} else if (opr2->is_double_stack()) { |
|
1066 | 2015 |
__ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); |
2016 |
NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) |
|
1 | 2017 |
} else { |
2018 |
ShouldNotReachHere(); |
|
2019 |
} |
|
2020 |
||
2021 |
} else { |
|
2022 |
Label skip; |
|
2023 |
__ jcc (acond, skip); |
|
2024 |
if (opr2->is_cpu_register()) { |
|
2025 |
reg2reg(opr2, result); |
|
2026 |
} else if (opr2->is_stack()) { |
|
2027 |
stack2reg(opr2, result, result->type()); |
|
2028 |
} else if (opr2->is_constant()) { |
|
2029 |
const2reg(opr2, result, lir_patch_none, NULL); |
|
2030 |
} else { |
|
2031 |
ShouldNotReachHere(); |
|
2032 |
} |
|
2033 |
__ bind(skip); |
|
2034 |
} |
|
2035 |
} |
|
2036 |
||
2037 |
||
2038 |
void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { |
|
2039 |
assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); |
|
2040 |
||
2041 |
if (left->is_single_cpu()) { |
|
2042 |
assert(left == dest, "left and dest must be equal"); |
|
2043 |
Register lreg = left->as_register(); |
|
2044 |
||
2045 |
if (right->is_single_cpu()) { |
|
2046 |
// cpu register - cpu register |
|
2047 |
Register rreg = right->as_register(); |
|
2048 |
switch (code) { |
|
2049 |
case lir_add: __ addl (lreg, rreg); break; |
|
2050 |
case lir_sub: __ subl (lreg, rreg); break; |
|
2051 |
case lir_mul: __ imull(lreg, rreg); break; |
|
2052 |
default: ShouldNotReachHere(); |
|
2053 |
} |
|
2054 |
||
2055 |
} else if (right->is_stack()) { |
|
2056 |
// cpu register - stack |
|
2057 |
Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); |
|
2058 |
switch (code) { |
|
2059 |
case lir_add: __ addl(lreg, raddr); break; |
|
2060 |
case lir_sub: __ subl(lreg, raddr); break; |
|
2061 |
default: ShouldNotReachHere(); |
|
2062 |
} |
|
2063 |
||
2064 |
} else if (right->is_constant()) { |
|
2065 |
// cpu register - constant |
|
2066 |
jint c = right->as_constant_ptr()->as_jint(); |
|
2067 |
switch (code) { |
|
2068 |
case lir_add: { |
|
2069 |
__ increment(lreg, c); |
|
2070 |
break; |
|
2071 |
} |
|
2072 |
case lir_sub: { |
|
2073 |
__ decrement(lreg, c); |
|
2074 |
break; |
|
2075 |
} |
|
2076 |
default: ShouldNotReachHere(); |
|
2077 |
} |
|
2078 |
||
2079 |
} else { |
|
2080 |
ShouldNotReachHere(); |
|
2081 |
} |
|
2082 |
||
2083 |
} else if (left->is_double_cpu()) { |
|
2084 |
assert(left == dest, "left and dest must be equal"); |
|
2085 |
Register lreg_lo = left->as_register_lo(); |
|
2086 |
Register lreg_hi = left->as_register_hi(); |
|
2087 |
||
2088 |
if (right->is_double_cpu()) { |
|
2089 |
// cpu register - cpu register |
|
2090 |
Register rreg_lo = right->as_register_lo(); |
|
2091 |
Register rreg_hi = right->as_register_hi(); |
|
1066 | 2092 |
NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); |
2093 |
LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); |
|
1 | 2094 |
switch (code) { |
2095 |
case lir_add: |
|
1066 | 2096 |
__ addptr(lreg_lo, rreg_lo); |
2097 |
NOT_LP64(__ adcl(lreg_hi, rreg_hi)); |
|
1 | 2098 |
break; |
2099 |
case lir_sub: |
|
1066 | 2100 |
__ subptr(lreg_lo, rreg_lo); |
2101 |
NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); |
|
1 | 2102 |
break; |
2103 |
case lir_mul: |
|
1066 | 2104 |
#ifdef _LP64 |
2105 |
__ imulq(lreg_lo, rreg_lo); |
|
2106 |
#else |
|
1 | 2107 |
assert(lreg_lo == rax && lreg_hi == rdx, "must be"); |
2108 |
__ imull(lreg_hi, rreg_lo); |
|
2109 |
__ imull(rreg_hi, lreg_lo); |
|
2110 |
__ addl (rreg_hi, lreg_hi); |
|
2111 |
__ mull (rreg_lo); |
|
2112 |
__ addl (lreg_hi, rreg_hi); |
|
1066 | 2113 |
#endif // _LP64 |
1 | 2114 |
break; |
2115 |
default: |
|
2116 |
ShouldNotReachHere(); |
|
2117 |
} |
|
2118 |
||
2119 |
} else if (right->is_constant()) { |
|
2120 |
// cpu register - constant |
|
1066 | 2121 |
#ifdef _LP64 |
2122 |
jlong c = right->as_constant_ptr()->as_jlong_bits(); |
|
2123 |
__ movptr(r10, (intptr_t) c); |
|
2124 |
switch (code) { |
|
2125 |
case lir_add: |
|
2126 |
__ addptr(lreg_lo, r10); |
|
2127 |
break; |
|
2128 |
case lir_sub: |
|
2129 |
__ subptr(lreg_lo, r10); |
|
2130 |
break; |
|
2131 |
default: |
|
2132 |
ShouldNotReachHere(); |
|
2133 |
} |
|
2134 |
#else |
|
1 | 2135 |
jint c_lo = right->as_constant_ptr()->as_jint_lo(); |
2136 |
jint c_hi = right->as_constant_ptr()->as_jint_hi(); |
|
2137 |
switch (code) { |
|
2138 |
case lir_add: |
|
1066 | 2139 |
__ addptr(lreg_lo, c_lo); |
1 | 2140 |
__ adcl(lreg_hi, c_hi); |
2141 |
break; |
|
2142 |
case lir_sub: |
|
1066 | 2143 |
__ subptr(lreg_lo, c_lo); |
1 | 2144 |
__ sbbl(lreg_hi, c_hi); |
2145 |
break; |
|
2146 |
default: |
|
2147 |
ShouldNotReachHere(); |
|
2148 |
} |
|
1066 | 2149 |
#endif // _LP64 |
1 | 2150 |
|
2151 |
} else { |
|
2152 |
ShouldNotReachHere(); |
|
2153 |
} |
|
2154 |
||
2155 |
} else if (left->is_single_xmm()) { |
|
2156 |
assert(left == dest, "left and dest must be equal"); |
|
2157 |
XMMRegister lreg = left->as_xmm_float_reg(); |
|
2158 |
||
2159 |
if (right->is_single_xmm()) { |
|
2160 |
XMMRegister rreg = right->as_xmm_float_reg(); |
|
2161 |
switch (code) { |
|
2162 |
case lir_add: __ addss(lreg, rreg); break; |
|
2163 |
case lir_sub: __ subss(lreg, rreg); break; |
|
2164 |
case lir_mul_strictfp: // fall through |
|
2165 |
case lir_mul: __ mulss(lreg, rreg); break; |
|
2166 |
case lir_div_strictfp: // fall through |
|
2167 |
case lir_div: __ divss(lreg, rreg); break; |
|
2168 |
default: ShouldNotReachHere(); |
|
2169 |
} |
|
2170 |
} else { |
|
2171 |
Address raddr; |
|
2172 |
if (right->is_single_stack()) { |
|
2173 |
raddr = frame_map()->address_for_slot(right->single_stack_ix()); |
|
2174 |
} else if (right->is_constant()) { |
|
2175 |
// hack for now |
|
2176 |
raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); |
|
2177 |
} else { |
|
2178 |
ShouldNotReachHere(); |
|
2179 |
} |
|
2180 |
switch (code) { |
|
2181 |
case lir_add: __ addss(lreg, raddr); break; |
|
2182 |
case lir_sub: __ subss(lreg, raddr); break; |
|
2183 |
case lir_mul_strictfp: // fall through |
|
2184 |
case lir_mul: __ mulss(lreg, raddr); break; |
|
2185 |
case lir_div_strictfp: // fall through |
|
2186 |
case lir_div: __ divss(lreg, raddr); break; |
|
2187 |
default: ShouldNotReachHere(); |
|
2188 |
} |
|
2189 |
} |
|
2190 |
||
2191 |
} else if (left->is_double_xmm()) { |
|
2192 |
assert(left == dest, "left and dest must be equal"); |
|
2193 |
||
2194 |
XMMRegister lreg = left->as_xmm_double_reg(); |
|
2195 |
if (right->is_double_xmm()) { |
|
2196 |
XMMRegister rreg = right->as_xmm_double_reg(); |
|
2197 |
switch (code) { |
|
2198 |
case lir_add: __ addsd(lreg, rreg); break; |
|
2199 |
case lir_sub: __ subsd(lreg, rreg); break; |
|
2200 |
case lir_mul_strictfp: // fall through |
|
2201 |
case lir_mul: __ mulsd(lreg, rreg); break; |
|
2202 |
case lir_div_strictfp: // fall through |
|
2203 |
case lir_div: __ divsd(lreg, rreg); break; |
|
2204 |
default: ShouldNotReachHere(); |
|
2205 |
} |
|
2206 |
} else { |
|
2207 |
Address raddr; |
|
2208 |
if (right->is_double_stack()) { |
|
2209 |
raddr = frame_map()->address_for_slot(right->double_stack_ix()); |
|
2210 |
} else if (right->is_constant()) { |
|
2211 |
// hack for now |
|
2212 |
raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); |
|
2213 |
} else { |
|
2214 |
ShouldNotReachHere(); |
|
2215 |
} |
|
2216 |
switch (code) { |
|
2217 |
case lir_add: __ addsd(lreg, raddr); break; |
|
2218 |
case lir_sub: __ subsd(lreg, raddr); break; |
|
2219 |
case lir_mul_strictfp: // fall through |
|
2220 |
case lir_mul: __ mulsd(lreg, raddr); break; |
|
2221 |
case lir_div_strictfp: // fall through |
|
2222 |
case lir_div: __ divsd(lreg, raddr); break; |
|
2223 |
default: ShouldNotReachHere(); |
|
2224 |
} |
|
2225 |
} |
|
2226 |
||
2227 |
} else if (left->is_single_fpu()) { |
|
2228 |
assert(dest->is_single_fpu(), "fpu stack allocation required"); |
|
2229 |
||
2230 |
if (right->is_single_fpu()) { |
|
2231 |
arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); |
|
2232 |
||
2233 |
} else { |
|
2234 |
assert(left->fpu_regnr() == 0, "left must be on TOS"); |
|
2235 |
assert(dest->fpu_regnr() == 0, "dest must be on TOS"); |
|
2236 |
||
2237 |
Address raddr; |
|
2238 |
if (right->is_single_stack()) { |
|
2239 |
raddr = frame_map()->address_for_slot(right->single_stack_ix()); |
|
2240 |
} else if (right->is_constant()) { |
|
2241 |
address const_addr = float_constant(right->as_jfloat()); |
|
2242 |
assert(const_addr != NULL, "incorrect float/double constant maintainance"); |
|
2243 |
// hack for now |
|
2244 |
raddr = __ as_Address(InternalAddress(const_addr)); |
|
2245 |
} else { |
|
2246 |
ShouldNotReachHere(); |
|
2247 |
} |
|
2248 |
||
2249 |
switch (code) { |
|
2250 |
case lir_add: __ fadd_s(raddr); break; |
|
2251 |
case lir_sub: __ fsub_s(raddr); break; |
|
2252 |
case lir_mul_strictfp: // fall through |
|
2253 |
case lir_mul: __ fmul_s(raddr); break; |
|
2254 |
case lir_div_strictfp: // fall through |
|
2255 |
case lir_div: __ fdiv_s(raddr); break; |
|
2256 |
default: ShouldNotReachHere(); |
|
2257 |
} |
|
2258 |
} |
|
2259 |
||
2260 |
} else if (left->is_double_fpu()) { |
|
2261 |
assert(dest->is_double_fpu(), "fpu stack allocation required"); |
|
2262 |
||
2263 |
if (code == lir_mul_strictfp || code == lir_div_strictfp) { |
|
2264 |
// Double values require special handling for strictfp mul/div on x86 |
|
2265 |
__ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); |
|
2266 |
__ fmulp(left->fpu_regnrLo() + 1); |
|
2267 |
} |
|
2268 |
||
2269 |
if (right->is_double_fpu()) { |
|
2270 |
arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); |
|
2271 |
||
2272 |
} else { |
|
2273 |
assert(left->fpu_regnrLo() == 0, "left must be on TOS"); |
|
2274 |
assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); |
|
2275 |
||
2276 |
Address raddr; |
|
2277 |
if (right->is_double_stack()) { |
|
2278 |
raddr = frame_map()->address_for_slot(right->double_stack_ix()); |
|
2279 |
} else if (right->is_constant()) { |
|
2280 |
// hack for now |
|
2281 |
raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); |
|
2282 |
} else { |
|
2283 |
ShouldNotReachHere(); |
|
2284 |
} |
|
2285 |
||
2286 |
switch (code) { |
|
2287 |
case lir_add: __ fadd_d(raddr); break; |
|
2288 |
case lir_sub: __ fsub_d(raddr); break; |
|
2289 |
case lir_mul_strictfp: // fall through |
|
2290 |
case lir_mul: __ fmul_d(raddr); break; |
|
2291 |
case lir_div_strictfp: // fall through |
|
2292 |
case lir_div: __ fdiv_d(raddr); break; |
|
2293 |
default: ShouldNotReachHere(); |
|
2294 |
} |
|
2295 |
} |
|
2296 |
||
2297 |
if (code == lir_mul_strictfp || code == lir_div_strictfp) { |
|
2298 |
// Double values require special handling for strictfp mul/div on x86 |
|
2299 |
__ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); |
|
2300 |
__ fmulp(dest->fpu_regnrLo() + 1); |
|
2301 |
} |
|
2302 |
||
2303 |
} else if (left->is_single_stack() || left->is_address()) { |
|
2304 |
assert(left == dest, "left and dest must be equal"); |
|
2305 |
||
2306 |
Address laddr; |
|
2307 |
if (left->is_single_stack()) { |
|
2308 |
laddr = frame_map()->address_for_slot(left->single_stack_ix()); |
|
2309 |
} else if (left->is_address()) { |
|
2310 |
laddr = as_Address(left->as_address_ptr()); |
|
2311 |
} else { |
|
2312 |
ShouldNotReachHere(); |
|
2313 |
} |
|
2314 |
||
2315 |
if (right->is_single_cpu()) { |
|
2316 |
Register rreg = right->as_register(); |
|
2317 |
switch (code) { |
|
2318 |
case lir_add: __ addl(laddr, rreg); break; |
|
2319 |
case lir_sub: __ subl(laddr, rreg); break; |
|
2320 |
default: ShouldNotReachHere(); |
|
2321 |
} |
|
2322 |
} else if (right->is_constant()) { |
|
2323 |
jint c = right->as_constant_ptr()->as_jint(); |
|
2324 |
switch (code) { |
|
2325 |
case lir_add: { |
|
1066 | 2326 |
__ incrementl(laddr, c); |
1 | 2327 |
break; |
2328 |
} |
|
2329 |
case lir_sub: { |
|
1066 | 2330 |
__ decrementl(laddr, c); |
1 | 2331 |
break; |
2332 |
} |
|
2333 |
default: ShouldNotReachHere(); |
|
2334 |
} |
|
2335 |
} else { |
|
2336 |
ShouldNotReachHere(); |
|
2337 |
} |
|
2338 |
||
2339 |
} else { |
|
2340 |
ShouldNotReachHere(); |
|
2341 |
} |
|
2342 |
} |
|
2343 |
||
2344 |
void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { |
|
2345 |
assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); |
|
2346 |
assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); |
|
2347 |
assert(left_index == 0 || right_index == 0, "either must be on top of stack"); |
|
2348 |
||
2349 |
bool left_is_tos = (left_index == 0); |
|
2350 |
bool dest_is_tos = (dest_index == 0); |
|
2351 |
int non_tos_index = (left_is_tos ? right_index : left_index); |
|
2352 |
||
2353 |
switch (code) { |
|
2354 |
case lir_add: |
|
2355 |
if (pop_fpu_stack) __ faddp(non_tos_index); |
|
2356 |
else if (dest_is_tos) __ fadd (non_tos_index); |
|
2357 |
else __ fadda(non_tos_index); |
|
2358 |
break; |
|
2359 |
||
2360 |
case lir_sub: |
|
2361 |
if (left_is_tos) { |
|
2362 |
if (pop_fpu_stack) __ fsubrp(non_tos_index); |
|
2363 |
else if (dest_is_tos) __ fsub (non_tos_index); |
|
2364 |
else __ fsubra(non_tos_index); |
|
2365 |
} else { |
|
2366 |
if (pop_fpu_stack) __ fsubp (non_tos_index); |
|
2367 |
else if (dest_is_tos) __ fsubr (non_tos_index); |
|
2368 |
else __ fsuba (non_tos_index); |
|
2369 |
} |
|
2370 |
break; |
|
2371 |
||
2372 |
case lir_mul_strictfp: // fall through |
|
2373 |
case lir_mul: |
|
2374 |
if (pop_fpu_stack) __ fmulp(non_tos_index); |
|
2375 |
else if (dest_is_tos) __ fmul (non_tos_index); |
|
2376 |
else __ fmula(non_tos_index); |
|
2377 |
break; |
|
2378 |
||
2379 |
case lir_div_strictfp: // fall through |
|
2380 |
case lir_div: |
|
2381 |
if (left_is_tos) { |
|
2382 |
if (pop_fpu_stack) __ fdivrp(non_tos_index); |
|
2383 |
else if (dest_is_tos) __ fdiv (non_tos_index); |
|
2384 |
else __ fdivra(non_tos_index); |
|
2385 |
} else { |
|
2386 |
if (pop_fpu_stack) __ fdivp (non_tos_index); |
|
2387 |
else if (dest_is_tos) __ fdivr (non_tos_index); |
|
2388 |
else __ fdiva (non_tos_index); |
|
2389 |
} |
|
2390 |
break; |
|
2391 |
||
2392 |
case lir_rem: |
|
2393 |
assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); |
|
2394 |
__ fremr(noreg); |
|
2395 |
break; |
|
2396 |
||
2397 |
default: |
|
2398 |
ShouldNotReachHere(); |
|
2399 |
} |
|
2400 |
} |
|
2401 |
||
2402 |
||
2403 |
void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { |
|
2404 |
if (value->is_double_xmm()) { |
|
2405 |
switch(code) { |
|
2406 |
case lir_abs : |
|
2407 |
{ |
|
2408 |
if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { |
|
2409 |
__ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); |
|
2410 |
} |
|
2411 |
__ andpd(dest->as_xmm_double_reg(), |
|
2412 |
ExternalAddress((address)double_signmask_pool)); |
|
2413 |
} |
|
2414 |
break; |
|
2415 |
||
2416 |
case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; |
|
2417 |
// all other intrinsics are not available in the SSE instruction set, so FPU is used |
|
2418 |
default : ShouldNotReachHere(); |
|
2419 |
} |
|
2420 |
||
2421 |
} else if (value->is_double_fpu()) { |
|
2422 |
assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); |
|
2423 |
switch(code) { |
|
2424 |
case lir_log : __ flog() ; break; |
|
2425 |
case lir_log10 : __ flog10() ; break; |
|
2426 |
case lir_abs : __ fabs() ; break; |
|
2427 |
case lir_sqrt : __ fsqrt(); break; |
|
2428 |
case lir_sin : |
|
2429 |
// Should consider not saving rbx, if not necessary |
|
2430 |
__ trigfunc('s', op->as_Op2()->fpu_stack_size()); |
|
2431 |
break; |
|
2432 |
case lir_cos : |
|
2433 |
// Should consider not saving rbx, if not necessary |
|
2434 |
assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots"); |
|
2435 |
__ trigfunc('c', op->as_Op2()->fpu_stack_size()); |
|
2436 |
break; |
|
2437 |
case lir_tan : |
|
2438 |
// Should consider not saving rbx, if not necessary |
|
2439 |
__ trigfunc('t', op->as_Op2()->fpu_stack_size()); |
|
2440 |
break; |
|
2441 |
default : ShouldNotReachHere(); |
|
2442 |
} |
|
2443 |
} else { |
|
2444 |
Unimplemented(); |
|
2445 |
} |
|
2446 |
} |
|
2447 |
||
2448 |
void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { |
|
2449 |
// assert(left->destroys_register(), "check"); |
|
2450 |
if (left->is_single_cpu()) { |
|
2451 |
Register reg = left->as_register(); |
|
2452 |
if (right->is_constant()) { |
|
2453 |
int val = right->as_constant_ptr()->as_jint(); |
|
2454 |
switch (code) { |
|
2455 |
case lir_logic_and: __ andl (reg, val); break; |
|
2456 |
case lir_logic_or: __ orl (reg, val); break; |
|
2457 |
case lir_logic_xor: __ xorl (reg, val); break; |
|
2458 |
default: ShouldNotReachHere(); |
|
2459 |
} |
|
2460 |
} else if (right->is_stack()) { |
|
2461 |
// added support for stack operands |
|
2462 |
Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); |
|
2463 |
switch (code) { |
|
2464 |
case lir_logic_and: __ andl (reg, raddr); break; |
|
2465 |
case lir_logic_or: __ orl (reg, raddr); break; |
|
2466 |
case lir_logic_xor: __ xorl (reg, raddr); break; |
|
2467 |
default: ShouldNotReachHere(); |
|
2468 |
} |
|
2469 |
} else { |
|
2470 |
Register rright = right->as_register(); |
|
2471 |
switch (code) { |
|
1066 | 2472 |
case lir_logic_and: __ andptr (reg, rright); break; |
2473 |
case lir_logic_or : __ orptr (reg, rright); break; |
|
2474 |
case lir_logic_xor: __ xorptr (reg, rright); break; |
|
1 | 2475 |
default: ShouldNotReachHere(); |
2476 |
} |
|
2477 |
} |
|
2478 |
move_regs(reg, dst->as_register()); |
|
2479 |
} else { |
|
2480 |
Register l_lo = left->as_register_lo(); |
|
2481 |
Register l_hi = left->as_register_hi(); |
|
2482 |
if (right->is_constant()) { |
|
1066 | 2483 |
#ifdef _LP64 |
2484 |
__ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); |
|
2485 |
switch (code) { |
|
2486 |
case lir_logic_and: |
|
2487 |
__ andq(l_lo, rscratch1); |
|
2488 |
break; |
|
2489 |
case lir_logic_or: |
|
2490 |
__ orq(l_lo, rscratch1); |
|
2491 |
break; |
|
2492 |
case lir_logic_xor: |
|
2493 |
__ xorq(l_lo, rscratch1); |
|
2494 |
break; |
|
2495 |
default: ShouldNotReachHere(); |
|
2496 |
} |
|
2497 |
#else |
|
1 | 2498 |
int r_lo = right->as_constant_ptr()->as_jint_lo(); |
2499 |
int r_hi = right->as_constant_ptr()->as_jint_hi(); |
|
2500 |
switch (code) { |
|
2501 |
case lir_logic_and: |
|
2502 |
__ andl(l_lo, r_lo); |
|
2503 |
__ andl(l_hi, r_hi); |
|
2504 |
break; |
|
2505 |
case lir_logic_or: |
|
2506 |
__ orl(l_lo, r_lo); |
|
2507 |
__ orl(l_hi, r_hi); |
|
2508 |
break; |
|
2509 |
case lir_logic_xor: |
|
2510 |
__ xorl(l_lo, r_lo); |
|
2511 |
__ xorl(l_hi, r_hi); |
|
2512 |
break; |
|
2513 |
default: ShouldNotReachHere(); |
|
2514 |
} |
|
1066 | 2515 |
#endif // _LP64 |
1 | 2516 |
} else { |
5695 | 2517 |
#ifdef _LP64 |
2518 |
Register r_lo; |
|
2519 |
if (right->type() == T_OBJECT || right->type() == T_ARRAY) { |
|
2520 |
r_lo = right->as_register(); |
|
2521 |
} else { |
|
2522 |
r_lo = right->as_register_lo(); |
|
2523 |
} |
|
2524 |
#else |
|
1 | 2525 |
Register r_lo = right->as_register_lo(); |
2526 |
Register r_hi = right->as_register_hi(); |
|
2527 |
assert(l_lo != r_hi, "overwriting registers"); |
|
5695 | 2528 |
#endif |
1 | 2529 |
switch (code) { |
2530 |
case lir_logic_and: |
|
1066 | 2531 |
__ andptr(l_lo, r_lo); |
2532 |
NOT_LP64(__ andptr(l_hi, r_hi);) |
|
1 | 2533 |
break; |
2534 |
case lir_logic_or: |
|
1066 | 2535 |
__ orptr(l_lo, r_lo); |
2536 |
NOT_LP64(__ orptr(l_hi, r_hi);) |
|
1 | 2537 |
break; |
2538 |
case lir_logic_xor: |
|
1066 | 2539 |
__ xorptr(l_lo, r_lo); |
2540 |
NOT_LP64(__ xorptr(l_hi, r_hi);) |
|
1 | 2541 |
break; |
2542 |
default: ShouldNotReachHere(); |
|
2543 |
} |
|
2544 |
} |
|
2545 |
||
2546 |
Register dst_lo = dst->as_register_lo(); |
|
2547 |
Register dst_hi = dst->as_register_hi(); |
|
2548 |
||
1066 | 2549 |
#ifdef _LP64 |
2550 |
move_regs(l_lo, dst_lo); |
|
2551 |
#else |
|
1 | 2552 |
if (dst_lo == l_hi) { |
2553 |
assert(dst_hi != l_lo, "overwriting registers"); |
|
2554 |
move_regs(l_hi, dst_hi); |
|
2555 |
move_regs(l_lo, dst_lo); |
|
2556 |
} else { |
|
2557 |
assert(dst_lo != l_hi, "overwriting registers"); |
|
2558 |
move_regs(l_lo, dst_lo); |
|
2559 |
move_regs(l_hi, dst_hi); |
|
2560 |
} |
|
1066 | 2561 |
#endif // _LP64 |
1 | 2562 |
} |
2563 |
} |
|
2564 |
||
2565 |
||
2566 |
// we assume that rax, and rdx can be overwritten |
|
2567 |
void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { |
|
2568 |
||
2569 |
assert(left->is_single_cpu(), "left must be register"); |
|
2570 |
assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); |
|
2571 |
assert(result->is_single_cpu(), "result must be register"); |
|
2572 |
||
2573 |
// assert(left->destroys_register(), "check"); |
|
2574 |
// assert(right->destroys_register(), "check"); |
|
2575 |
||
2576 |
Register lreg = left->as_register(); |
|
2577 |
Register dreg = result->as_register(); |
|
2578 |
||
2579 |
if (right->is_constant()) { |
|
2580 |
int divisor = right->as_constant_ptr()->as_jint(); |
|
2581 |
assert(divisor > 0 && is_power_of_2(divisor), "must be"); |
|
2582 |
if (code == lir_idiv) { |
|
2583 |
assert(lreg == rax, "must be rax,"); |
|
2584 |
assert(temp->as_register() == rdx, "tmp register must be rdx"); |
|
2585 |
__ cdql(); // sign extend into rdx:rax |
|
2586 |
if (divisor == 2) { |
|
2587 |
__ subl(lreg, rdx); |
|
2588 |
} else { |
|
2589 |
__ andl(rdx, divisor - 1); |
|
2590 |
__ addl(lreg, rdx); |
|
2591 |
} |
|
2592 |
__ sarl(lreg, log2_intptr(divisor)); |
|
2593 |
move_regs(lreg, dreg); |
|
2594 |
} else if (code == lir_irem) { |
|
2595 |
Label done; |
|
1066 | 2596 |
__ mov(dreg, lreg); |
1 | 2597 |
__ andl(dreg, 0x80000000 | (divisor - 1)); |
2598 |
__ jcc(Assembler::positive, done); |
|
2599 |
__ decrement(dreg); |
|
2600 |
__ orl(dreg, ~(divisor - 1)); |
|
2601 |
__ increment(dreg); |
|
2602 |
__ bind(done); |
|
2603 |
} else { |
|
2604 |
ShouldNotReachHere(); |
|
2605 |
} |
|
2606 |
} else { |
|
2607 |
Register rreg = right->as_register(); |
|
2608 |
assert(lreg == rax, "left register must be rax,"); |
|
2609 |
assert(rreg != rdx, "right register must not be rdx"); |
|
2610 |
assert(temp->as_register() == rdx, "tmp register must be rdx"); |
|
2611 |
||
2612 |
move_regs(lreg, rax); |
|
2613 |
||
2614 |
int idivl_offset = __ corrected_idivl(rreg); |
|
2615 |
add_debug_info_for_div0(idivl_offset, info); |
|
2616 |
if (code == lir_irem) { |
|
2617 |
move_regs(rdx, dreg); // result is in rdx |
|
2618 |
} else { |
|
2619 |
move_regs(rax, dreg); |
|
2620 |
} |
|
2621 |
} |
|
2622 |
} |
|
2623 |
||
2624 |
||
2625 |
void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { |
|
2626 |
if (opr1->is_single_cpu()) { |
|
2627 |
Register reg1 = opr1->as_register(); |
|
2628 |
if (opr2->is_single_cpu()) { |
|
2629 |
// cpu register - cpu register |
|
1066 | 2630 |
if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { |
2631 |
__ cmpptr(reg1, opr2->as_register()); |
|
2632 |
} else { |
|
2633 |
assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); |
|
2634 |
__ cmpl(reg1, opr2->as_register()); |
|
2635 |
} |
|
1 | 2636 |
} else if (opr2->is_stack()) { |
2637 |
// cpu register - stack |
|
1066 | 2638 |
if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { |
2639 |
__ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); |
|
2640 |
} else { |
|
2641 |
__ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); |
|
2642 |
} |
|
1 | 2643 |
} else if (opr2->is_constant()) { |
2644 |
// cpu register - constant |
|
2645 |
LIR_Const* c = opr2->as_constant_ptr(); |
|
2646 |
if (c->type() == T_INT) { |
|
2647 |
__ cmpl(reg1, c->as_jint()); |
|
1066 | 2648 |
} else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
2649 |
// In 64bit oops are single register |
|
1 | 2650 |
jobject o = c->as_jobject(); |
2651 |
if (o == NULL) { |
|
1066 | 2652 |
__ cmpptr(reg1, (int32_t)NULL_WORD); |
1 | 2653 |
} else { |
1066 | 2654 |
#ifdef _LP64 |
2655 |
__ movoop(rscratch1, o); |
|
2656 |
__ cmpptr(reg1, rscratch1); |
|
2657 |
#else |
|
1 | 2658 |
__ cmpoop(reg1, c->as_jobject()); |
1066 | 2659 |
#endif // _LP64 |
1 | 2660 |
} |
2661 |
} else { |
|
2662 |
ShouldNotReachHere(); |
|
2663 |
} |
|
2664 |
// cpu register - address |
|
2665 |
} else if (opr2->is_address()) { |
|
2666 |
if (op->info() != NULL) { |
|
2667 |
add_debug_info_for_null_check_here(op->info()); |
|
2668 |
} |
|
2669 |
__ cmpl(reg1, as_Address(opr2->as_address_ptr())); |
|
2670 |
} else { |
|
2671 |
ShouldNotReachHere(); |
|
2672 |
} |
|
2673 |
||
2674 |
} else if(opr1->is_double_cpu()) { |
|
2675 |
Register xlo = opr1->as_register_lo(); |
|
2676 |
Register xhi = opr1->as_register_hi(); |
|
2677 |
if (opr2->is_double_cpu()) { |
|
1066 | 2678 |
#ifdef _LP64 |
2679 |
__ cmpptr(xlo, opr2->as_register_lo()); |
|
2680 |
#else |
|
1 | 2681 |
// cpu register - cpu register |
2682 |
Register ylo = opr2->as_register_lo(); |
|
2683 |
Register yhi = opr2->as_register_hi(); |
|
2684 |
__ subl(xlo, ylo); |
|
2685 |
__ sbbl(xhi, yhi); |
|
2686 |
if (condition == lir_cond_equal || condition == lir_cond_notEqual) { |
|
2687 |
__ orl(xhi, xlo); |
|
2688 |
} |
|
1066 | 2689 |
#endif // _LP64 |
1 | 2690 |
} else if (opr2->is_constant()) { |
2691 |
// cpu register - constant 0 |
|
2692 |
assert(opr2->as_jlong() == (jlong)0, "only handles zero"); |
|
1066 | 2693 |
#ifdef _LP64 |
2694 |
__ cmpptr(xlo, (int32_t)opr2->as_jlong()); |
|
2695 |
#else |
|
1 | 2696 |
assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); |
2697 |
__ orl(xhi, xlo); |
|
1066 | 2698 |
#endif // _LP64 |
1 | 2699 |
} else { |
2700 |
ShouldNotReachHere(); |
|
2701 |
} |
|
2702 |
||
2703 |
} else if (opr1->is_single_xmm()) { |
|
2704 |
XMMRegister reg1 = opr1->as_xmm_float_reg(); |
|
2705 |
if (opr2->is_single_xmm()) { |
|
2706 |
// xmm register - xmm register |
|
2707 |
__ ucomiss(reg1, opr2->as_xmm_float_reg()); |
|
2708 |
} else if (opr2->is_stack()) { |
|
2709 |
// xmm register - stack |
|
2710 |
__ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); |
|
2711 |
} else if (opr2->is_constant()) { |
|
2712 |
// xmm register - constant |
|
2713 |
__ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); |
|
2714 |
} else if (opr2->is_address()) { |
|
2715 |
// xmm register - address |
|
2716 |
if (op->info() != NULL) { |
|
2717 |
add_debug_info_for_null_check_here(op->info()); |
|
2718 |
} |
|
2719 |
__ ucomiss(reg1, as_Address(opr2->as_address_ptr())); |
|
2720 |
} else { |
|
2721 |
ShouldNotReachHere(); |
|
2722 |
} |
|
2723 |
||
2724 |
} else if (opr1->is_double_xmm()) { |
|
2725 |
XMMRegister reg1 = opr1->as_xmm_double_reg(); |
|
2726 |
if (opr2->is_double_xmm()) { |
|
2727 |
// xmm register - xmm register |
|
2728 |
__ ucomisd(reg1, opr2->as_xmm_double_reg()); |
|
2729 |
} else if (opr2->is_stack()) { |
|
2730 |
// xmm register - stack |
|
2731 |
__ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); |
|
2732 |
} else if (opr2->is_constant()) { |
|
2733 |
// xmm register - constant |
|
2734 |
__ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); |
|
2735 |
} else if (opr2->is_address()) { |
|
2736 |
// xmm register - address |
|
2737 |
if (op->info() != NULL) { |
|
2738 |
add_debug_info_for_null_check_here(op->info()); |
|
2739 |
} |
|
2740 |
__ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); |
|
2741 |
} else { |
|
2742 |
ShouldNotReachHere(); |
|
2743 |
} |
|
2744 |
||
2745 |
} else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { |
|
2746 |
assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); |
|
2747 |
assert(opr2->is_fpu_register(), "both must be registers"); |
|
2748 |
__ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); |
|
2749 |
||
2750 |
} else if (opr1->is_address() && opr2->is_constant()) { |
|
1066 | 2751 |
LIR_Const* c = opr2->as_constant_ptr(); |
2752 |
#ifdef _LP64 |
|
2753 |
if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
|
2754 |
assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); |
|
2755 |
__ movoop(rscratch1, c->as_jobject()); |
|
2756 |
} |
|
2757 |
#endif // LP64 |
|
1 | 2758 |
if (op->info() != NULL) { |
2759 |
add_debug_info_for_null_check_here(op->info()); |
|
2760 |
} |
|
2761 |
// special case: address - constant |
|
2762 |
LIR_Address* addr = opr1->as_address_ptr(); |
|
2763 |
if (c->type() == T_INT) { |
|
2764 |
__ cmpl(as_Address(addr), c->as_jint()); |
|
1066 | 2765 |
} else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
2766 |
#ifdef _LP64 |
|
2767 |
// %%% Make this explode if addr isn't reachable until we figure out a |
|
2768 |
// better strategy by giving noreg as the temp for as_Address |
|
2769 |
__ cmpptr(rscratch1, as_Address(addr, noreg)); |
|
2770 |
#else |
|
1 | 2771 |
__ cmpoop(as_Address(addr), c->as_jobject()); |
1066 | 2772 |
#endif // _LP64 |
1 | 2773 |
} else { |
2774 |
ShouldNotReachHere(); |
|
2775 |
} |
|
2776 |
||
2777 |
} else { |
|
2778 |
ShouldNotReachHere(); |
|
2779 |
} |
|
2780 |
} |
|
2781 |
||
2782 |
void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { |
|
2783 |
if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { |
|
2784 |
if (left->is_single_xmm()) { |
|
2785 |
assert(right->is_single_xmm(), "must match"); |
|
2786 |
__ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); |
|
2787 |
} else if (left->is_double_xmm()) { |
|
2788 |
assert(right->is_double_xmm(), "must match"); |
|
2789 |
__ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); |
|
2790 |
||
2791 |
} else { |
|
2792 |
assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); |
|
2793 |
assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); |
|
2794 |
||
2795 |
assert(left->fpu() == 0, "left must be on TOS"); |
|
2796 |
__ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), |
|
2797 |
op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); |
|
2798 |
} |
|
2799 |
} else { |
|
2800 |
assert(code == lir_cmp_l2i, "check"); |
|
1066 | 2801 |
#ifdef _LP64 |
5253 | 2802 |
Label done; |
2803 |
Register dest = dst->as_register(); |
|
2804 |
__ cmpptr(left->as_register_lo(), right->as_register_lo()); |
|
2805 |
__ movl(dest, -1); |
|
2806 |
__ jccb(Assembler::less, done); |
|
2807 |
__ set_byte_if_not_zero(dest); |
|
2808 |
__ movzbl(dest, dest); |
|
2809 |
__ bind(done); |
|
1066 | 2810 |
#else |
1 | 2811 |
__ lcmp2int(left->as_register_hi(), |
2812 |
left->as_register_lo(), |
|
2813 |
right->as_register_hi(), |
|
2814 |
right->as_register_lo()); |
|
2815 |
move_regs(left->as_register_hi(), dst->as_register()); |
|
1066 | 2816 |
#endif // _LP64 |
1 | 2817 |
} |
2818 |
} |
|
2819 |
||
2820 |
||
2821 |
void LIR_Assembler::align_call(LIR_Code code) { |
|
2822 |
if (os::is_MP()) { |
|
2823 |
// make sure that the displacement word of the call ends up word aligned |
|
2824 |
int offset = __ offset(); |
|
2825 |
switch (code) { |
|
2826 |
case lir_static_call: |
|
2827 |
case lir_optvirtual_call: |
|
5046 | 2828 |
case lir_dynamic_call: |
1 | 2829 |
offset += NativeCall::displacement_offset; |
2830 |
break; |
|
2831 |
case lir_icvirtual_call: |
|
2832 |
offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; |
|
2833 |
break; |
|
2834 |
case lir_virtual_call: // currently, sparc-specific for niagara |
|
2835 |
default: ShouldNotReachHere(); |
|
2836 |
} |
|
2837 |
while (offset++ % BytesPerWord != 0) { |
|
2838 |
__ nop(); |
|
2839 |
} |
|
2840 |
} |
|
2841 |
} |
|
2842 |
||
2843 |
||
5046 | 2844 |
void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { |
1 | 2845 |
assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, |
2846 |
"must be aligned"); |
|
5046 | 2847 |
__ call(AddressLiteral(op->addr(), rtype)); |
5687 | 2848 |
add_call_info(code_offset(), op->info()); |
1 | 2849 |
} |
2850 |
||
2851 |
||
5046 | 2852 |
void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { |
1 | 2853 |
RelocationHolder rh = virtual_call_Relocation::spec(pc()); |
2854 |
__ movoop(IC_Klass, (jobject)Universe::non_oop_word()); |
|
2855 |
assert(!os::is_MP() || |
|
2856 |
(__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, |
|
2857 |
"must be aligned"); |
|
5046 | 2858 |
__ call(AddressLiteral(op->addr(), rh)); |
5687 | 2859 |
add_call_info(code_offset(), op->info()); |
1 | 2860 |
} |
2861 |
||
2862 |
||
2863 |
/* Currently, vtable-dispatch is only enabled for sparc platforms */ |
|
5046 | 2864 |
void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { |
1 | 2865 |
ShouldNotReachHere(); |
2866 |
} |
|
2867 |
||
5046 | 2868 |
|
1 | 2869 |
void LIR_Assembler::emit_static_call_stub() { |
2870 |
address call_pc = __ pc(); |
|
2871 |
address stub = __ start_a_stub(call_stub_size); |
|
2872 |
if (stub == NULL) { |
|
2873 |
bailout("static call stub overflow"); |
|
2874 |
return; |
|
2875 |
} |
|
2876 |
||
2877 |
int start = __ offset(); |
|
2878 |
if (os::is_MP()) { |
|
2879 |
// make sure that the displacement word of the call ends up word aligned |
|
2880 |
int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset; |
|
2881 |
while (offset++ % BytesPerWord != 0) { |
|
2882 |
__ nop(); |
|
2883 |
} |
|
2884 |
} |
|
2885 |
__ relocate(static_stub_Relocation::spec(call_pc)); |
|
2886 |
__ movoop(rbx, (jobject)NULL); |
|
2887 |
// must be set to -1 at code generation time |
|
2888 |
assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); |
|
1066 | 2889 |
// On 64bit this will die since it will take a movq & jmp, must be only a jmp |
2890 |
__ jump(RuntimeAddress(__ pc())); |
|
1 | 2891 |
|
5402
c51fd0c1d005
6888953: some calls to function-like macros are missing semicolons
jcoomes
parents:
5334
diff
changeset
|
2892 |
assert(__ offset() - start <= call_stub_size, "stub too big"); |
1 | 2893 |
__ end_a_stub(); |
2894 |
} |
|
2895 |
||
2896 |
||
5334
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5253
diff
changeset
|
2897 |
void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { |
1 | 2898 |
assert(exceptionOop->as_register() == rax, "must match"); |
5334
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5253
diff
changeset
|
2899 |
assert(exceptionPC->as_register() == rdx, "must match"); |
1 | 2900 |
|
2901 |
// exception object is not added to oop map by LinearScan |
|
2902 |
// (LinearScan assumes that no oops are in fixed registers) |
|
2903 |
info->add_register_oop(exceptionOop); |
|
2904 |
Runtime1::StubID unwind_id; |
|
2905 |
||
5334
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5253
diff
changeset
|
2906 |
// get current pc information |
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5253
diff
changeset
|
2907 |
// pc is only needed if the method has an exception handler, the unwind code does not need it. |
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5253
diff
changeset
|
2908 |
int pc_for_athrow_offset = __ offset(); |
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5253
diff
changeset
|
2909 |
InternalAddress pc_for_athrow(__ pc()); |
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5253
diff
changeset
|
2910 |
__ lea(exceptionPC->as_register(), pc_for_athrow); |
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5253
diff
changeset
|
2911 |
add_call_info(pc_for_athrow_offset, info); // for exception handler |
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5253
diff
changeset
|
2912 |
|
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5253
diff
changeset
|
2913 |
__ verify_not_null_oop(rax); |
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5253
diff
changeset
|
2914 |
// search an exception handler (rax: exception oop, rdx: throwing pc) |
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
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parents:
5253
diff
changeset
|
2915 |
if (compilation()->has_fpu_code()) { |
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5253
diff
changeset
|
2916 |
unwind_id = Runtime1::handle_exception_id; |
1 | 2917 |
} else { |
5334
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5253
diff
changeset
|
2918 |
unwind_id = Runtime1::handle_exception_nofpu_id; |
1 | 2919 |
} |
5334
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5253
diff
changeset
|
2920 |
__ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); |
1 | 2921 |
|
2922 |
// enough room for two byte trap |
|
2923 |
__ nop(); |
|
2924 |
} |
|
2925 |
||
2926 |
||
5334
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5253
diff
changeset
|
2927 |
void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { |
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5253
diff
changeset
|
2928 |
assert(exceptionOop->as_register() == rax, "must match"); |
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5253
diff
changeset
|
2929 |
|
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5253
diff
changeset
|
2930 |
__ jmp(_unwind_handler_entry); |
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5253
diff
changeset
|
2931 |
} |
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5253
diff
changeset
|
2932 |
|
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5253
diff
changeset
|
2933 |
|
1 | 2934 |
void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { |
2935 |
||
2936 |
// optimized version for linear scan: |
|
2937 |
// * count must be already in ECX (guaranteed by LinearScan) |
|
2938 |
// * left and dest must be equal |
|
2939 |
// * tmp must be unused |
|
2940 |
assert(count->as_register() == SHIFT_count, "count must be in ECX"); |
|
2941 |
assert(left == dest, "left and dest must be equal"); |
|
2942 |
assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); |
|
2943 |
||
2944 |
if (left->is_single_cpu()) { |
|
2945 |
Register value = left->as_register(); |
|
2946 |
assert(value != SHIFT_count, "left cannot be ECX"); |
|
2947 |
||
2948 |
switch (code) { |
|
2949 |
case lir_shl: __ shll(value); break; |
|
2950 |
case lir_shr: __ sarl(value); break; |
|
2951 |
case lir_ushr: __ shrl(value); break; |
|
2952 |
default: ShouldNotReachHere(); |
|
2953 |
} |
|
2954 |
} else if (left->is_double_cpu()) { |
|
2955 |
Register lo = left->as_register_lo(); |
|
2956 |
Register hi = left->as_register_hi(); |
|
2957 |
assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); |
|
1066 | 2958 |
#ifdef _LP64 |
2959 |
switch (code) { |
|
2960 |
case lir_shl: __ shlptr(lo); break; |
|
2961 |
case lir_shr: __ sarptr(lo); break; |
|
2962 |
case lir_ushr: __ shrptr(lo); break; |
|
2963 |
default: ShouldNotReachHere(); |
|
2964 |
} |
|
2965 |
#else |
|
1 | 2966 |
|
2967 |
switch (code) { |
|
2968 |
case lir_shl: __ lshl(hi, lo); break; |
|
2969 |
case lir_shr: __ lshr(hi, lo, true); break; |
|
2970 |
case lir_ushr: __ lshr(hi, lo, false); break; |
|
2971 |
default: ShouldNotReachHere(); |
|
2972 |
} |
|
1066 | 2973 |
#endif // LP64 |
1 | 2974 |
} else { |
2975 |
ShouldNotReachHere(); |
|
2976 |
} |
|
2977 |
} |
|
2978 |
||
2979 |
||
2980 |
void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { |
|
2981 |
if (dest->is_single_cpu()) { |
|
2982 |
// first move left into dest so that left is not destroyed by the shift |
|
2983 |
Register value = dest->as_register(); |
|
2984 |
count = count & 0x1F; // Java spec |
|
2985 |
||
2986 |
move_regs(left->as_register(), value); |
|
2987 |
switch (code) { |
|
2988 |
case lir_shl: __ shll(value, count); break; |
|
2989 |
case lir_shr: __ sarl(value, count); break; |
|
2990 |
case lir_ushr: __ shrl(value, count); break; |
|
2991 |
default: ShouldNotReachHere(); |
|
2992 |
} |
|
2993 |
} else if (dest->is_double_cpu()) { |
|
1066 | 2994 |
#ifndef _LP64 |
1 | 2995 |
Unimplemented(); |
1066 | 2996 |
#else |
2997 |
// first move left into dest so that left is not destroyed by the shift |
|
2998 |
Register value = dest->as_register_lo(); |
|
2999 |
count = count & 0x1F; // Java spec |
|
3000 |
||
3001 |
move_regs(left->as_register_lo(), value); |
|
3002 |
switch (code) { |
|
3003 |
case lir_shl: __ shlptr(value, count); break; |
|
3004 |
case lir_shr: __ sarptr(value, count); break; |
|
3005 |
case lir_ushr: __ shrptr(value, count); break; |
|
3006 |
default: ShouldNotReachHere(); |
|
3007 |
} |
|
3008 |
#endif // _LP64 |
|
1 | 3009 |
} else { |
3010 |
ShouldNotReachHere(); |
|
3011 |
} |
|
3012 |
} |
|
3013 |
||
3014 |
||
3015 |
void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { |
|
3016 |
assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); |
|
3017 |
int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; |
|
3018 |
assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); |
|
1066 | 3019 |
__ movptr (Address(rsp, offset_from_rsp_in_bytes), r); |
1 | 3020 |
} |
3021 |
||
3022 |
||
3023 |
void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { |
|
3024 |
assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); |
|
3025 |
int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; |
|
3026 |
assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); |
|
1066 | 3027 |
__ movptr (Address(rsp, offset_from_rsp_in_bytes), c); |
1 | 3028 |
} |
3029 |
||
3030 |
||
3031 |
void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { |
|
3032 |
assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); |
|
3033 |
int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; |
|
3034 |
assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); |
|
3035 |
__ movoop (Address(rsp, offset_from_rsp_in_bytes), o); |
|
3036 |
} |
|
3037 |
||
3038 |
||
3039 |
// This code replaces a call to arraycopy; no exception may |
|
3040 |
// be thrown in this code, they must be thrown in the System.arraycopy |
|
3041 |
// activation frame; we could save some checks if this would not be the case |
|
3042 |
void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { |
|
3043 |
ciArrayKlass* default_type = op->expected_type(); |
|
3044 |
Register src = op->src()->as_register(); |
|
3045 |
Register dst = op->dst()->as_register(); |
|
3046 |
Register src_pos = op->src_pos()->as_register(); |
|
3047 |
Register dst_pos = op->dst_pos()->as_register(); |
|
3048 |
Register length = op->length()->as_register(); |
|
3049 |
Register tmp = op->tmp()->as_register(); |
|
3050 |
||
3051 |
CodeStub* stub = op->stub(); |
|
3052 |
int flags = op->flags(); |
|
3053 |
BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; |
|
3054 |
if (basic_type == T_ARRAY) basic_type = T_OBJECT; |
|
3055 |
||
3056 |
// if we don't know anything or it's an object array, just go through the generic arraycopy |
|
3057 |
if (default_type == NULL) { |
|
3058 |
Label done; |
|
3059 |
// save outgoing arguments on stack in case call to System.arraycopy is needed |
|
3060 |
// HACK ALERT. This code used to push the parameters in a hardwired fashion |
|
3061 |
// for interpreter calling conventions. Now we have to do it in new style conventions. |
|
3062 |
// For the moment until C1 gets the new register allocator I just force all the |
|
3063 |
// args to the right place (except the register args) and then on the back side |
|
3064 |
// reload the register args properly if we go slow path. Yuck |
|
3065 |
||
3066 |
// These are proper for the calling convention |
|
3067 |
||
3068 |
store_parameter(length, 2); |
|
3069 |
store_parameter(dst_pos, 1); |
|
3070 |
store_parameter(dst, 0); |
|
3071 |
||
3072 |
// these are just temporary placements until we need to reload |
|
3073 |
store_parameter(src_pos, 3); |
|
3074 |
store_parameter(src, 4); |
|
1066 | 3075 |
NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) |
3076 |
||
3077 |
address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); |
|
1 | 3078 |
|
3079 |
// pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint |
|
1066 | 3080 |
#ifdef _LP64 |
3081 |
// The arguments are in java calling convention so we can trivially shift them to C |
|
3082 |
// convention |
|
3083 |
assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); |
|
3084 |
__ mov(c_rarg0, j_rarg0); |
|
3085 |
assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); |
|
3086 |
__ mov(c_rarg1, j_rarg1); |
|
3087 |
assert_different_registers(c_rarg2, j_rarg3, j_rarg4); |
|
3088 |
__ mov(c_rarg2, j_rarg2); |
|
3089 |
assert_different_registers(c_rarg3, j_rarg4); |
|
3090 |
__ mov(c_rarg3, j_rarg3); |
|
3091 |
#ifdef _WIN64 |
|
3092 |
// Allocate abi space for args but be sure to keep stack aligned |
|
3093 |
__ subptr(rsp, 6*wordSize); |
|
3094 |
store_parameter(j_rarg4, 4); |
|
3095 |
__ call(RuntimeAddress(entry)); |
|
3096 |
__ addptr(rsp, 6*wordSize); |
|
3097 |
#else |
|
3098 |
__ mov(c_rarg4, j_rarg4); |
|
3099 |
__ call(RuntimeAddress(entry)); |
|
3100 |
#endif // _WIN64 |
|
3101 |
#else |
|
3102 |
__ push(length); |
|
3103 |
__ push(dst_pos); |
|
3104 |
__ push(dst); |
|
3105 |
__ push(src_pos); |
|
3106 |
__ push(src); |
|
1 | 3107 |
__ call_VM_leaf(entry, 5); // removes pushed parameter from the stack |
3108 |
||
1066 | 3109 |
#endif // _LP64 |
3110 |
||
1 | 3111 |
__ cmpl(rax, 0); |
3112 |
__ jcc(Assembler::equal, *stub->continuation()); |
|
3113 |
||
3114 |
// Reload values from the stack so they are where the stub |
|
3115 |
// expects them. |
|
1066 | 3116 |
__ movptr (dst, Address(rsp, 0*BytesPerWord)); |
3117 |
__ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); |
|
3118 |
__ movptr (length, Address(rsp, 2*BytesPerWord)); |
|
3119 |
__ movptr (src_pos, Address(rsp, 3*BytesPerWord)); |
|
3120 |
__ movptr (src, Address(rsp, 4*BytesPerWord)); |
|
1 | 3121 |
__ jmp(*stub->entry()); |
3122 |
||
3123 |
__ bind(*stub->continuation()); |
|
3124 |
return; |
|
3125 |
} |
|
3126 |
||
3127 |
assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); |
|
3128 |
||
202
dc13bf0e5d5d
6633953: type2aelembytes{T_ADDRESS} should be 8 bytes in 64 bit VM
kvn
parents:
1
diff
changeset
|
3129 |
int elem_size = type2aelembytes(basic_type); |
1 | 3130 |
int shift_amount; |
3131 |
Address::ScaleFactor scale; |
|
3132 |
||
3133 |
switch (elem_size) { |
|
3134 |
case 1 : |
|
3135 |
shift_amount = 0; |
|
3136 |
scale = Address::times_1; |
|
3137 |
break; |
|
3138 |
case 2 : |
|
3139 |
shift_amount = 1; |
|
3140 |
scale = Address::times_2; |
|
3141 |
break; |
|
3142 |
case 4 : |
|
3143 |
shift_amount = 2; |
|
3144 |
scale = Address::times_4; |
|
3145 |
break; |
|
3146 |
case 8 : |
|
3147 |
shift_amount = 3; |
|
3148 |
scale = Address::times_8; |
|
3149 |
break; |
|
3150 |
default: |
|
3151 |
ShouldNotReachHere(); |
|
3152 |
} |
|
3153 |
||
3154 |
Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); |
|
3155 |
Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); |
|
3156 |
Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); |
|
3157 |
Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); |
|
3158 |
||
1066 | 3159 |
// length and pos's are all sign extended at this point on 64bit |
3160 |
||
1 | 3161 |
// test for NULL |
3162 |
if (flags & LIR_OpArrayCopy::src_null_check) { |
|
1066 | 3163 |
__ testptr(src, src); |
1 | 3164 |
__ jcc(Assembler::zero, *stub->entry()); |
3165 |
} |
|
3166 |
if (flags & LIR_OpArrayCopy::dst_null_check) { |
|
1066 | 3167 |
__ testptr(dst, dst); |
1 | 3168 |
__ jcc(Assembler::zero, *stub->entry()); |
3169 |
} |
|
3170 |
||
3171 |
// check if negative |
|
3172 |
if (flags & LIR_OpArrayCopy::src_pos_positive_check) { |
|
3173 |
__ testl(src_pos, src_pos); |
|
3174 |
__ jcc(Assembler::less, *stub->entry()); |
|
3175 |
} |
|
3176 |
if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { |
|
3177 |
__ testl(dst_pos, dst_pos); |
|
3178 |
__ jcc(Assembler::less, *stub->entry()); |
|
3179 |
} |
|
3180 |
if (flags & LIR_OpArrayCopy::length_positive_check) { |
|
3181 |
__ testl(length, length); |
|
3182 |
__ jcc(Assembler::less, *stub->entry()); |
|
3183 |
} |
|
3184 |
||
3185 |
if (flags & LIR_OpArrayCopy::src_range_check) { |
|
1066 | 3186 |
__ lea(tmp, Address(src_pos, length, Address::times_1, 0)); |
1 | 3187 |
__ cmpl(tmp, src_length_addr); |
3188 |
__ jcc(Assembler::above, *stub->entry()); |
|
3189 |
} |
|
3190 |
if (flags & LIR_OpArrayCopy::dst_range_check) { |
|
1066 | 3191 |
__ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); |
1 | 3192 |
__ cmpl(tmp, dst_length_addr); |
3193 |
__ jcc(Assembler::above, *stub->entry()); |
|
3194 |
} |
|
3195 |
||
3196 |
if (flags & LIR_OpArrayCopy::type_check) { |
|
1066 | 3197 |
__ movptr(tmp, src_klass_addr); |
3198 |
__ cmpptr(tmp, dst_klass_addr); |
|
1 | 3199 |
__ jcc(Assembler::notEqual, *stub->entry()); |
3200 |
} |
|
3201 |
||
3202 |
#ifdef ASSERT |
|
3203 |
if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { |
|
3204 |
// Sanity check the known type with the incoming class. For the |
|
3205 |
// primitive case the types must match exactly with src.klass and |
|
3206 |
// dst.klass each exactly matching the default type. For the |
|
3207 |
// object array case, if no type check is needed then either the |
|
3208 |
// dst type is exactly the expected type and the src type is a |
|
3209 |
// subtype which we can't check or src is the same array as dst |
|
3210 |
// but not necessarily exactly of type default_type. |
|
3211 |
Label known_ok, halt; |
|
3908
24b55ad4c228
6863023: need non-perm oops in code cache for JSR 292
jrose
parents:
2867
diff
changeset
|
3212 |
__ movoop(tmp, default_type->constant_encoding()); |
1 | 3213 |
if (basic_type != T_OBJECT) { |
1066 | 3214 |
__ cmpptr(tmp, dst_klass_addr); |
1 | 3215 |
__ jcc(Assembler::notEqual, halt); |
1066 | 3216 |
__ cmpptr(tmp, src_klass_addr); |
1 | 3217 |
__ jcc(Assembler::equal, known_ok); |
3218 |
} else { |
|
1066 | 3219 |
__ cmpptr(tmp, dst_klass_addr); |
1 | 3220 |
__ jcc(Assembler::equal, known_ok); |
1066 | 3221 |
__ cmpptr(src, dst); |
1 | 3222 |
__ jcc(Assembler::equal, known_ok); |
3223 |
} |
|
3224 |
__ bind(halt); |
|
3225 |
__ stop("incorrect type information in arraycopy"); |
|
3226 |
__ bind(known_ok); |
|
3227 |
} |
|
3228 |
#endif |
|
3229 |
||
1066 | 3230 |
if (shift_amount > 0 && basic_type != T_OBJECT) { |
3231 |
__ shlptr(length, shift_amount); |
|
3232 |
} |
|
3233 |
||
3234 |
#ifdef _LP64 |
|
3235 |
assert_different_registers(c_rarg0, dst, dst_pos, length); |
|
4430 | 3236 |
__ movl2ptr(src_pos, src_pos); //higher 32bits must be null |
1066 | 3237 |
__ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
3238 |
assert_different_registers(c_rarg1, length); |
|
4430 | 3239 |
__ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null |
1066 | 3240 |
__ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
3241 |
__ mov(c_rarg2, length); |
|
3242 |
||
3243 |
#else |
|
3244 |
__ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
|
1 | 3245 |
store_parameter(tmp, 0); |
1066 | 3246 |
__ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
1 | 3247 |
store_parameter(tmp, 1); |
3248 |
store_parameter(length, 2); |
|
1066 | 3249 |
#endif // _LP64 |
1 | 3250 |
if (basic_type == T_OBJECT) { |
3251 |
__ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy), 0); |
|
3252 |
} else { |
|
3253 |
__ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy), 0); |
|
3254 |
} |
|
3255 |
||
3256 |
__ bind(*stub->continuation()); |
|
3257 |
} |
|
3258 |
||
3259 |
||
3260 |
void LIR_Assembler::emit_lock(LIR_OpLock* op) { |
|
3261 |
Register obj = op->obj_opr()->as_register(); // may not be an oop |
|
3262 |
Register hdr = op->hdr_opr()->as_register(); |
|
3263 |
Register lock = op->lock_opr()->as_register(); |
|
3264 |
if (!UseFastLocking) { |
|
3265 |
__ jmp(*op->stub()->entry()); |
|
3266 |
} else if (op->code() == lir_lock) { |
|
3267 |
Register scratch = noreg; |
|
3268 |
if (UseBiasedLocking) { |
|
3269 |
scratch = op->scratch_opr()->as_register(); |
|
3270 |
} |
|
3271 |
assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); |
|
3272 |
// add debug info for NullPointerException only if one is possible |
|
3273 |
int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); |
|
3274 |
if (op->info() != NULL) { |
|
3275 |
add_debug_info_for_null_check(null_check_offset, op->info()); |
|
3276 |
} |
|
3277 |
// done |
|
3278 |
} else if (op->code() == lir_unlock) { |
|
3279 |
assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); |
|
3280 |
__ unlock_object(hdr, obj, lock, *op->stub()->entry()); |
|
3281 |
} else { |
|
3282 |
Unimplemented(); |
|
3283 |
} |
|
3284 |
__ bind(*op->stub()->continuation()); |
|
3285 |
} |
|
3286 |
||
3287 |
||
3288 |
void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { |
|
3289 |
ciMethod* method = op->profiled_method(); |
|
3290 |
int bci = op->profiled_bci(); |
|
3291 |
||
3292 |
// Update counter for all call types |
|
3293 |
ciMethodData* md = method->method_data(); |
|
3294 |
if (md == NULL) { |
|
3295 |
bailout("out of memory building methodDataOop"); |
|
3296 |
return; |
|
3297 |
} |
|
3298 |
ciProfileData* data = md->bci_to_data(bci); |
|
3299 |
assert(data->is_CounterData(), "need CounterData for calls"); |
|
3300 |
assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); |
|
3301 |
Register mdo = op->mdo()->as_register(); |
|
3908
24b55ad4c228
6863023: need non-perm oops in code cache for JSR 292
jrose
parents:
2867
diff
changeset
|
3302 |
__ movoop(mdo, md->constant_encoding()); |
1 | 3303 |
Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); |
3304 |
Bytecodes::Code bc = method->java_code_at_bci(bci); |
|
3305 |
// Perform additional virtual call profiling for invokevirtual and |
|
3306 |
// invokeinterface bytecodes |
|
3307 |
if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && |
|
6453 | 3308 |
C1ProfileVirtualCalls) { |
1 | 3309 |
assert(op->recv()->is_single_cpu(), "recv must be allocated"); |
3310 |
Register recv = op->recv()->as_register(); |
|
3311 |
assert_different_registers(mdo, recv); |
|
3312 |
assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); |
|
3313 |
ciKlass* known_klass = op->known_holder(); |
|
6453 | 3314 |
if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { |
1 | 3315 |
// We know the type that will be seen at this call site; we can |
3316 |
// statically update the methodDataOop rather than needing to do |
|
3317 |
// dynamic tests on the receiver type |
|
3318 |
||
3319 |
// NOTE: we should probably put a lock around this search to |
|
3320 |
// avoid collisions by concurrent compilations |
|
3321 |
ciVirtualCallData* vc_data = (ciVirtualCallData*) data; |
|
3322 |
uint i; |
|
3323 |
for (i = 0; i < VirtualCallData::row_limit(); i++) { |
|
3324 |
ciKlass* receiver = vc_data->receiver(i); |
|
3325 |
if (known_klass->equals(receiver)) { |
|
3326 |
Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); |
|
6453 | 3327 |
__ addptr(data_addr, DataLayout::counter_increment); |
1 | 3328 |
return; |
3329 |
} |
|
3330 |
} |
|
3331 |
||
3332 |
// Receiver type not found in profile data; select an empty slot |
|
3333 |
||
3334 |
// Note that this is less efficient than it should be because it |
|
3335 |
// always does a write to the receiver part of the |
|
3336 |
// VirtualCallData rather than just the first time |
|
3337 |
for (i = 0; i < VirtualCallData::row_limit(); i++) { |
|
3338 |
ciKlass* receiver = vc_data->receiver(i); |
|
3339 |
if (receiver == NULL) { |
|
3340 |
Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); |
|
3908
24b55ad4c228
6863023: need non-perm oops in code cache for JSR 292
jrose
parents:
2867
diff
changeset
|
3341 |
__ movoop(recv_addr, known_klass->constant_encoding()); |
1 | 3342 |
Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); |
6453 | 3343 |
__ addptr(data_addr, DataLayout::counter_increment); |
1 | 3344 |
return; |
3345 |
} |
|
3346 |
} |
|
3347 |
} else { |
|
1066 | 3348 |
__ movptr(recv, Address(recv, oopDesc::klass_offset_in_bytes())); |
1 | 3349 |
Label update_done; |
6453 | 3350 |
type_profile_helper(mdo, md, data, recv, &update_done); |
4754
8aef16f24e16
6614597: Performance variability in jvm2008 xml.validation
kvn
parents:
4752
diff
changeset
|
3351 |
// Receiver did not match any saved receiver and there is no empty row for it. |
4892
e977b527544a
6923002: assert(false,"this call site should not be polymorphic")
kvn
parents:
4754
diff
changeset
|
3352 |
// Increment total counter to indicate polymorphic case. |
6453 | 3353 |
__ addptr(counter_addr, DataLayout::counter_increment); |
1 | 3354 |
|
3355 |
__ bind(update_done); |
|
3356 |
} |
|
4754
8aef16f24e16
6614597: Performance variability in jvm2008 xml.validation
kvn
parents:
4752
diff
changeset
|
3357 |
} else { |
8aef16f24e16
6614597: Performance variability in jvm2008 xml.validation
kvn
parents:
4752
diff
changeset
|
3358 |
// Static call |
6453 | 3359 |
__ addptr(counter_addr, DataLayout::counter_increment); |
1 | 3360 |
} |
3361 |
} |
|
3362 |
||
3363 |
void LIR_Assembler::emit_delay(LIR_OpDelay*) { |
|
3364 |
Unimplemented(); |
|
3365 |
} |
|
3366 |
||
3367 |
||
3368 |
void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { |
|
1066 | 3369 |
__ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); |
1 | 3370 |
} |
3371 |
||
3372 |
||
3373 |
void LIR_Assembler::align_backward_branch_target() { |
|
3374 |
__ align(BytesPerWord); |
|
3375 |
} |
|
3376 |
||
3377 |
||
3378 |
void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { |
|
3379 |
if (left->is_single_cpu()) { |
|
3380 |
__ negl(left->as_register()); |
|
3381 |
move_regs(left->as_register(), dest->as_register()); |
|
3382 |
||
3383 |
} else if (left->is_double_cpu()) { |
|
3384 |
Register lo = left->as_register_lo(); |
|
1066 | 3385 |
#ifdef _LP64 |
3386 |
Register dst = dest->as_register_lo(); |
|
3387 |
__ movptr(dst, lo); |
|
3388 |
__ negptr(dst); |
|
3389 |
#else |
|
1 | 3390 |
Register hi = left->as_register_hi(); |
3391 |
__ lneg(hi, lo); |
|
3392 |
if (dest->as_register_lo() == hi) { |
|
3393 |
assert(dest->as_register_hi() != lo, "destroying register"); |
|
3394 |
move_regs(hi, dest->as_register_hi()); |
|
3395 |
move_regs(lo, dest->as_register_lo()); |
|
3396 |
} else { |
|
3397 |
move_regs(lo, dest->as_register_lo()); |
|
3398 |
move_regs(hi, dest->as_register_hi()); |
|
3399 |
} |
|
1066 | 3400 |
#endif // _LP64 |
1 | 3401 |
|
3402 |
} else if (dest->is_single_xmm()) { |
|
3403 |
if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { |
|
3404 |
__ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); |
|
3405 |
} |
|
3406 |
__ xorps(dest->as_xmm_float_reg(), |
|
3407 |
ExternalAddress((address)float_signflip_pool)); |
|
3408 |
||
3409 |
} else if (dest->is_double_xmm()) { |
|
3410 |
if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { |
|
3411 |
__ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); |
|
3412 |
} |
|
3413 |
__ xorpd(dest->as_xmm_double_reg(), |
|
3414 |
ExternalAddress((address)double_signflip_pool)); |
|
3415 |
||
3416 |
} else if (left->is_single_fpu() || left->is_double_fpu()) { |
|
3417 |
assert(left->fpu() == 0, "arg must be on TOS"); |
|
3418 |
assert(dest->fpu() == 0, "dest must be TOS"); |
|
3419 |
__ fchs(); |
|
3420 |
||
3421 |
} else { |
|
3422 |
ShouldNotReachHere(); |
|
3423 |
} |
|
3424 |
} |
|
3425 |
||
3426 |
||
3427 |
void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) { |
|
3428 |
assert(addr->is_address() && dest->is_register(), "check"); |
|
1066 | 3429 |
Register reg; |
3430 |
reg = dest->as_pointer_register(); |
|
3431 |
__ lea(reg, as_Address(addr->as_address_ptr())); |
|
1 | 3432 |
} |
3433 |
||
3434 |
||
3435 |
||
3436 |
void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { |
|
3437 |
assert(!tmp->is_valid(), "don't need temporary"); |
|
3438 |
__ call(RuntimeAddress(dest)); |
|
3439 |
if (info != NULL) { |
|
3440 |
add_call_info_here(info); |
|
3441 |
} |
|
3442 |
} |
|
3443 |
||
3444 |
||
3445 |
void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { |
|
3446 |
assert(type == T_LONG, "only for volatile long fields"); |
|
3447 |
||
3448 |
if (info != NULL) { |
|
3449 |
add_debug_info_for_null_check_here(info); |
|
3450 |
} |
|
3451 |
||
3452 |
if (src->is_double_xmm()) { |
|
3453 |
if (dest->is_double_cpu()) { |
|
1066 | 3454 |
#ifdef _LP64 |
3455 |
__ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); |
|
3456 |
#else |
|
3457 |
__ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); |
|
1 | 3458 |
__ psrlq(src->as_xmm_double_reg(), 32); |
1066 | 3459 |
__ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); |
3460 |
#endif // _LP64 |
|
1 | 3461 |
} else if (dest->is_double_stack()) { |
3462 |
__ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); |
|
3463 |
} else if (dest->is_address()) { |
|
3464 |
__ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); |
|
3465 |
} else { |
|
3466 |
ShouldNotReachHere(); |
|
3467 |
} |
|
3468 |
||
3469 |
} else if (dest->is_double_xmm()) { |
|
3470 |
if (src->is_double_stack()) { |
|
3471 |
__ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); |
|
3472 |
} else if (src->is_address()) { |
|
3473 |
__ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); |
|
3474 |
} else { |
|
3475 |
ShouldNotReachHere(); |
|
3476 |
} |
|
3477 |
||
3478 |
} else if (src->is_double_fpu()) { |
|
3479 |
assert(src->fpu_regnrLo() == 0, "must be TOS"); |
|
3480 |
if (dest->is_double_stack()) { |
|
3481 |
__ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); |
|
3482 |
} else if (dest->is_address()) { |
|
3483 |
__ fistp_d(as_Address(dest->as_address_ptr())); |
|
3484 |
} else { |
|
3485 |
ShouldNotReachHere(); |
|
3486 |
} |
|
3487 |
||
3488 |
} else if (dest->is_double_fpu()) { |
|
3489 |
assert(dest->fpu_regnrLo() == 0, "must be TOS"); |
|
3490 |
if (src->is_double_stack()) { |
|
3491 |
__ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); |
|
3492 |
} else if (src->is_address()) { |
|
3493 |
__ fild_d(as_Address(src->as_address_ptr())); |
|
3494 |
} else { |
|
3495 |
ShouldNotReachHere(); |
|
3496 |
} |
|
3497 |
} else { |
|
3498 |
ShouldNotReachHere(); |
|
3499 |
} |
|
3500 |
} |
|
3501 |
||
3502 |
||
3503 |
void LIR_Assembler::membar() { |
|
1066 | 3504 |
// QQQ sparc TSO uses this, |
3505 |
__ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); |
|
1 | 3506 |
} |
3507 |
||
3508 |
void LIR_Assembler::membar_acquire() { |
|
3509 |
// No x86 machines currently require load fences |
|
3510 |
// __ load_fence(); |
|
3511 |
} |
|
3512 |
||
3513 |
void LIR_Assembler::membar_release() { |
|
3514 |
// No x86 machines currently require store fences |
|
3515 |
// __ store_fence(); |
|
3516 |
} |
|
3517 |
||
3518 |
void LIR_Assembler::get_thread(LIR_Opr result_reg) { |
|
3519 |
assert(result_reg->is_register(), "check"); |
|
1066 | 3520 |
#ifdef _LP64 |
3521 |
// __ get_thread(result_reg->as_register_lo()); |
|
3522 |
__ mov(result_reg->as_register(), r15_thread); |
|
3523 |
#else |
|
1 | 3524 |
__ get_thread(result_reg->as_register()); |
1066 | 3525 |
#endif // _LP64 |
1 | 3526 |
} |
3527 |
||
3528 |
||
3529 |
void LIR_Assembler::peephole(LIR_List*) { |
|
3530 |
// do nothing for now |
|
3531 |
} |
|
3532 |
||
3533 |
||
3534 |
#undef __ |