//

// Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.

// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

//

// This code is free software; you can redistribute it and/or modify it

// under the terms of the GNU General Public License version 2 only, as

// published by the Free Software Foundation.

//

// This code is distributed in the hope that it will be useful, but WITHOUT

// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

// version 2 for more details (a copy is included in the LICENSE file that

// accompanied this code).

//

// You should have received a copy of the GNU General Public License version

// 2 along with this work; if not, write to the Free Software Foundation,

// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

//

// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

// or visit www.oracle.com if you need additional information or have any

// questions.

//

//

// X86 Architecture Description File

//----------REGISTER DEFINITION BLOCK------------------------------------------

// This information is used by the matcher and the register allocator to

// describe individual registers and classes of registers within the target

// archtecture.

register %{

//----------Architecture Description Register Definitions----------------------

// General Registers

// "reg_def"  name ( register save type, C convention save type,

//                   ideal register type, encoding );

// Register Save Types:

//

// NS  = No-Save:       The register allocator assumes that these registers

//                      can be used without saving upon entry to the method, &

//                      that they do not need to be saved at call sites.

//

// SOC = Save-On-Call:  The register allocator assumes that these registers

//                      can be used without saving upon entry to the method,

//                      but that they must be saved at call sites.

//

// SOE = Save-On-Entry: The register allocator assumes that these registers

//                      must be saved before using them upon entry to the

//                      method, but they do not need to be saved at call

//                      sites.

//

// AS  = Always-Save:   The register allocator assumes that these registers

//                      must be saved before using them upon entry to the

//                      method, & that they must be saved at call sites.

//

// Ideal Register Type is used to determine how to save & restore a

// register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get

// spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.

//

// The encoding number is the actual bit-pattern placed into the opcodes.

// General Registers

// Previously set EBX, ESI, and EDI as save-on-entry for java code

// Turn off SOE in java-code due to frequent use of uncommon-traps.

// Now that allocator is better, turn on ESI and EDI as SOE registers.

reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());

reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());

reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());

reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());

// now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code

reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());

reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());

reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());

reg_def ESP( NS,  NS, Op_RegI, 4, rsp->as_VMReg());

// Float registers.  We treat TOS/FPR0 special.  It is invisible to the

// allocator, and only shows up in the encodings.

reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());

reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());

// Ok so here's the trick FPR1 is really st(0) except in the midst

// of emission of assembly for a machnode. During the emission the fpu stack

// is pushed making FPR1 == st(1) temporarily. However at any safepoint

// the stack will not have this element so FPR1 == st(0) from the

// oopMap viewpoint. This same weirdness with numbering causes

// instruction encoding to have to play games with the register

// encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation

// where it does flt->flt moves to see an example

//

reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());

reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());

reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());

reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());

reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());

reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());

reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());

reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());

reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());

reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());

reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());

reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());

reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());

reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());

// Specify priority of register selection within phases of register

// allocation.  Highest priority is first.  A useful heuristic is to

// give registers a low priority when they are required by machine

// instructions, like EAX and EDX.  Registers which are used as

// pairs must fall on an even boundary (witness the FPR#L's in this list).

// For the Intel integer registers, the equivalent Long pairs are

// EDX:EAX, EBX:ECX, and EDI:EBP.

alloc_class chunk0( ECX,   EBX,   EBP,   EDI,   EAX,   EDX,   ESI, ESP,

                    FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,

                    FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,

                    FPR6L, FPR6H, FPR7L, FPR7H );

//----------Architecture Description Register Classes--------------------------

// Several register classes are automatically defined based upon information in

// this architecture description.

// 1) reg_class inline_cache_reg           ( /* as def'd in frame section */ )

// 2) reg_class compiler_method_oop_reg    ( /* as def'd in frame section */ )

// 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )

// 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )

//

// Class for all registers

reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);

// Class for general registers

reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);

// Class for general registers which may be used for implicit null checks on win95

// Also safe for use by tailjump. We don't want to allocate in rbp,

reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);

// Class of "X" registers

reg_class int_x_reg(EBX, ECX, EDX, EAX);

// Class of registers that can appear in an address with no offset.

// EBP and ESP require an extra instruction byte for zero offset.

// Used in fast-unlock

reg_class p_reg(EDX, EDI, ESI, EBX);

// Class for general registers not including ECX

reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);

// Class for general registers not including EAX

reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);

// Class for general registers not including EAX or EBX.

reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);

// Class of EAX (for multiply and divide operations)

reg_class eax_reg(EAX);

// Class of EBX (for atomic add)

reg_class ebx_reg(EBX);

// Class of ECX (for shift and JCXZ operations and cmpLTMask)

reg_class ecx_reg(ECX);

// Class of EDX (for multiply and divide operations)

reg_class edx_reg(EDX);

// Class of EDI (for synchronization)

reg_class edi_reg(EDI);

// Class of ESI (for synchronization)

reg_class esi_reg(ESI);

// Singleton class for interpreter's stack pointer

reg_class ebp_reg(EBP);

// Singleton class for stack pointer

reg_class sp_reg(ESP);

// Singleton class for instruction pointer

// reg_class ip_reg(EIP);

// Class of integer register pairs

reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );

// Class of integer register pairs that aligns with calling convention

reg_class eadx_reg( EAX,EDX );

reg_class ebcx_reg( ECX,EBX );

// Not AX or DX, used in divides

reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );

// Floating point registers.  Notice FPR0 is not a choice.

// FPR0 is not ever allocated; we use clever encodings to fake

// a 2-address instructions out of Intels FP stack.

reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );

reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,

                      FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,

                      FPR7L,FPR7H );

reg_class fp_flt_reg0( FPR1L );

reg_class fp_dbl_reg0( FPR1L,FPR1H );

reg_class fp_dbl_reg1( FPR2L,FPR2H );

reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,

                          FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );

%}

//----------SOURCE BLOCK-------------------------------------------------------

// This is a block of C++ code which provides values, functions, and

// definitions necessary in the rest of the architecture description

source_hpp %{

// Must be visible to the DFA in dfa_x86_32.cpp

extern bool is_operand_hi32_zero(Node* n);

%}

source %{

#define   RELOC_IMM32    Assembler::imm_operand

#define   RELOC_DISP32   Assembler::disp32_operand

#define __ _masm.

// How to find the high register of a Long pair, given the low register

#define   HIGH_FROM_LOW(x) ((x)+2)

// These masks are used to provide 128-bit aligned bitmasks to the XMM

// instructions, to allow sign-masking or sign-bit flipping.  They allow

// fast versions of NegF/NegD and AbsF/AbsD.

// Note: 'double' and 'long long' have 32-bits alignment on x86.

static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {

  // Use the expression (adr)&(~0xF) to provide 128-bits aligned address

  // of 128-bits operands for SSE instructions.

  jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));

  // Store the value to a 128-bits operand.

  operand[0] = lo;

  operand[1] = hi;

  return operand;

}

// Buffer for 128-bits masks used by SSE instructions.

static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)

// Static initialization during VM startup.

static jlong *float_signmask_pool  = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));

static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));

static jlong *float_signflip_pool  = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));

static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));

// Offset hacking within calls.

static int pre_call_FPU_size() {

  if (Compile::current()->in_24_bit_fp_mode())

    return 6; // fldcw

  return 0;

}

static int preserve_SP_size() {

  return 2;  // op, rm(reg/reg)

}

// !!!!! Special hack to get all type of calls to specify the byte offset

//       from the start of the call to the point where the return address

//       will point.

int MachCallStaticJavaNode::ret_addr_offset() {

  int offset = 5 + pre_call_FPU_size();  // 5 bytes from start of call to where return address points

  if (_method_handle_invoke)

    offset += preserve_SP_size();

  return offset;

}

int MachCallDynamicJavaNode::ret_addr_offset() {

  return 10 + pre_call_FPU_size();  // 10 bytes from start of call to where return address points

}

static int sizeof_FFree_Float_Stack_All = -1;

int MachCallRuntimeNode::ret_addr_offset() {

  assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");

  return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size();

}

// Indicate if the safepoint node needs the polling page as an input.

// Since x86 does have absolute addressing, it doesn't.

bool SafePointNode::needs_polling_address_input() {

  return false;

}

//

// Compute padding required for nodes which need alignment

//

// The address of the call instruction needs to be 4-byte aligned to

// ensure that it does not span a cache line so that it can be patched.

int CallStaticJavaDirectNode::compute_padding(int current_offset) const {

  current_offset += pre_call_FPU_size();  // skip fldcw, if any

  current_offset += 1;      // skip call opcode byte

  return round_to(current_offset, alignment_required()) - current_offset;

}

// The address of the call instruction needs to be 4-byte aligned to

// ensure that it does not span a cache line so that it can be patched.

int CallStaticJavaHandleNode::compute_padding(int current_offset) const {

  current_offset += pre_call_FPU_size();  // skip fldcw, if any

  current_offset += preserve_SP_size();   // skip mov rbp, rsp

  current_offset += 1;      // skip call opcode byte

  return round_to(current_offset, alignment_required()) - current_offset;

}

// The address of the call instruction needs to be 4-byte aligned to

// ensure that it does not span a cache line so that it can be patched.

int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {

  current_offset += pre_call_FPU_size();  // skip fldcw, if any

  current_offset += 5;      // skip MOV instruction

  current_offset += 1;      // skip call opcode byte

  return round_to(current_offset, alignment_required()) - current_offset;

}

// EMIT_RM()

void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {

  unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);

  cbuf.insts()->emit_int8(c);

}

// EMIT_CC()

void emit_cc(CodeBuffer &cbuf, int f1, int f2) {

  unsigned char c = (unsigned char)( f1 | f2 );

  cbuf.insts()->emit_int8(c);

}

// EMIT_OPCODE()

void emit_opcode(CodeBuffer &cbuf, int code) {

  cbuf.insts()->emit_int8((unsigned char) code);

}

// EMIT_OPCODE() w/ relocation information

void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {

  cbuf.relocate(cbuf.insts_mark() + offset, reloc);

  emit_opcode(cbuf, code);

}

// EMIT_D8()

void emit_d8(CodeBuffer &cbuf, int d8) {

  cbuf.insts()->emit_int8((unsigned char) d8);

}

// EMIT_D16()

void emit_d16(CodeBuffer &cbuf, int d16) {

  cbuf.insts()->emit_int16(d16);

}

// EMIT_D32()

void emit_d32(CodeBuffer &cbuf, int d32) {

  cbuf.insts()->emit_int32(d32);

}

// emit 32 bit value and construct relocation entry from relocInfo::relocType

void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,

        int format) {

  cbuf.relocate(cbuf.insts_mark(), reloc, format);

  cbuf.insts()->emit_int32(d32);

}

// emit 32 bit value and construct relocation entry from RelocationHolder

void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,

        int format) {

#ifdef ASSERT

  if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {

    assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");

  }

#endif

  cbuf.relocate(cbuf.insts_mark(), rspec, format);

  cbuf.insts()->emit_int32(d32);

}

// Access stack slot for load or store

void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {

  emit_opcode( cbuf, opcode );               // (e.g., FILD   [ESP+src])

  if( -128 <= disp && disp <= 127 ) {

    emit_rm( cbuf, 0x01, rm_field, ESP_enc );  // R/M byte

    emit_rm( cbuf, 0x00, ESP_enc, ESP_enc);    // SIB byte

    emit_d8 (cbuf, disp);     // Displacement  // R/M byte

  } else {

    emit_rm( cbuf, 0x02, rm_field, ESP_enc );  // R/M byte

    emit_rm( cbuf, 0x00, ESP_enc, ESP_enc);    // SIB byte

    emit_d32(cbuf, disp);     // Displacement  // R/M byte

  }

}

   // rRegI ereg, memory mem) %{    // emit_reg_mem

void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) {

  // There is no index & no scale, use form without SIB byte

  if ((index == 0x4) &&

      (scale == 0) && (base != ESP_enc)) {

    // If no displacement, mode is 0x0; unless base is [EBP]

    if ( (displace == 0) && (base != EBP_enc) ) {

      emit_rm(cbuf, 0x0, reg_encoding, base);

    }

    else {                    // If 8-bit displacement, mode 0x1

      if ((displace >= -128) && (displace <= 127)

          && (disp_reloc == relocInfo::none) ) {

        emit_rm(cbuf, 0x1, reg_encoding, base);

        emit_d8(cbuf, displace);

      }

      else {                  // If 32-bit displacement

        if (base == -1) { // Special flag for absolute address

          emit_rm(cbuf, 0x0, reg_encoding, 0x5);

          // (manual lies; no SIB needed here)

          if ( disp_reloc != relocInfo::none ) {

            emit_d32_reloc(cbuf, displace, disp_reloc, 1);

          } else {

            emit_d32      (cbuf, displace);

          }

        }

        else {                // Normal base + offset

          emit_rm(cbuf, 0x2, reg_encoding, base);

          if ( disp_reloc != relocInfo::none ) {

            emit_d32_reloc(cbuf, displace, disp_reloc, 1);

          } else {

            emit_d32      (cbuf, displace);

          }

        }

      }

    }

  }

  else {                      // Else, encode with the SIB byte

    // If no displacement, mode is 0x0; unless base is [EBP]

    if (displace == 0 && (base != EBP_enc)) {  // If no displacement

      emit_rm(cbuf, 0x0, reg_encoding, 0x4);

      emit_rm(cbuf, scale, index, base);

    }

    else {                    // If 8-bit displacement, mode 0x1

      if ((displace >= -128) && (displace <= 127)

          && (disp_reloc == relocInfo::none) ) {

        emit_rm(cbuf, 0x1, reg_encoding, 0x4);

        emit_rm(cbuf, scale, index, base);

        emit_d8(cbuf, displace);

      }

      else {                  // If 32-bit displacement

        if (base == 0x04 ) {

          emit_rm(cbuf, 0x2, reg_encoding, 0x4);

          emit_rm(cbuf, scale, index, 0x04);

        } else {

          emit_rm(cbuf, 0x2, reg_encoding, 0x4);

          emit_rm(cbuf, scale, index, base);

        }

        if ( disp_reloc != relocInfo::none ) {

          emit_d32_reloc(cbuf, displace, disp_reloc, 1);

        } else {

          emit_d32      (cbuf, displace);

        }

      }

    }

  }

}

void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {

  if( dst_encoding == src_encoding ) {

    // reg-reg copy, use an empty encoding

  } else {

    emit_opcode( cbuf, 0x8B );

    emit_rm(cbuf, 0x3, dst_encoding, src_encoding );

  }

}

void emit_cmpfp_fixup(MacroAssembler& _masm) {

  Label exit;

  __ jccb(Assembler::noParity, exit);

  __ pushf();

  //

  // comiss/ucomiss instructions set ZF,PF,CF flags and

  // zero OF,AF,SF for NaN values.

  // Fixup flags by zeroing ZF,PF so that compare of NaN

  // values returns 'less than' result (CF is set).

  // Leave the rest of flags unchanged.

  //

  //    7 6 5 4 3 2 1 0

  //   |S|Z|r|A|r|P|r|C|  (r - reserved bit)

  //    0 0 1 0 1 0 1 1   (0x2B)

  //

  __ andl(Address(rsp, 0), 0xffffff2b);

  __ popf();

  __ bind(exit);

}

void emit_cmpfp3(MacroAssembler& _masm, Register dst) {

  Label done;

  __ movl(dst, -1);

  __ jcc(Assembler::parity, done);

  __ jcc(Assembler::below, done);

  __ setb(Assembler::notEqual, dst);

  __ movzbl(dst, dst);

  __ bind(done);

}

//=============================================================================

const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;

int Compile::ConstantTable::calculate_table_base_offset() const {

  return 0;  // absolute addressing, no offset

}

void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {

  // Empty encoding

}

uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {

  return 0;

}

#ifndef PRODUCT

void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {

  st->print("# MachConstantBaseNode (empty encoding)");

}

#endif

//=============================================================================

#ifndef PRODUCT

void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {

  Compile* C = ra_->C;

  int framesize = C->frame_slots() << LogBytesPerInt;

  assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");

  // Remove wordSize for return addr which is already pushed.

  framesize -= wordSize;

  if (C->need_stack_bang(framesize)) {

    framesize -= wordSize;

    st->print("# stack bang");

    st->print("\n\t");

    st->print("PUSH   EBP\t# Save EBP");

    if (framesize) {