/*

 * Copyright (c) 2003, 2014, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

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 */

#ifndef OS_CPU_LINUX_X86_VM_ORDERACCESS_LINUX_X86_INLINE_HPP

#define OS_CPU_LINUX_X86_VM_ORDERACCESS_LINUX_X86_INLINE_HPP

#include "runtime/atomic.inline.hpp"

#include "runtime/orderAccess.hpp"

#include "runtime/os.hpp"

// Implementation of class OrderAccess.

// A compiler barrier, forcing the C++ compiler to invalidate all memory assumptions

static inline void compiler_barrier() {

  __asm__ volatile ("" : : : "memory");

}

inline void OrderAccess::loadload()   { acquire(); }

inline void OrderAccess::storestore() { release(); }

inline void OrderAccess::loadstore()  { acquire(); }

inline void OrderAccess::storeload()  { fence(); }

inline void OrderAccess::acquire() {

  volatile intptr_t local_dummy;

#ifdef AMD64

  __asm__ volatile ("movq 0(%%rsp), %0" : "=r" (local_dummy) : : "memory");

#else

  __asm__ volatile ("movl 0(%%esp),%0" : "=r" (local_dummy) : : "memory");

#endif // AMD64

}

inline void OrderAccess::release() {

  compiler_barrier();

}

inline void OrderAccess::fence() {

  if (os::is_MP()) {

    // always use locked addl since mfence is sometimes expensive

#ifdef AMD64

    __asm__ volatile ("lock; addl $0,0(%%rsp)" : : : "cc", "memory");

#else

    __asm__ volatile ("lock; addl $0,0(%%esp)" : : : "cc", "memory");

#endif

  }

}

inline jbyte    OrderAccess::load_acquire(volatile jbyte*   p) { jbyte   v = *p; compiler_barrier(); return v; }

inline jshort   OrderAccess::load_acquire(volatile jshort*  p) { jshort  v = *p; compiler_barrier(); return v; }

inline jint     OrderAccess::load_acquire(volatile jint*    p) { jint    v = *p; compiler_barrier(); return v; }

inline jlong    OrderAccess::load_acquire(volatile jlong*   p) { jlong   v = Atomic::load(p); compiler_barrier(); return v; }

inline jubyte   OrderAccess::load_acquire(volatile jubyte*  p) { jubyte  v = *p; compiler_barrier(); return v; }

inline jushort  OrderAccess::load_acquire(volatile jushort* p) { jushort v = *p; compiler_barrier(); return v; }

inline juint    OrderAccess::load_acquire(volatile juint*   p) { juint   v = *p; compiler_barrier(); return v; }

inline julong   OrderAccess::load_acquire(volatile julong*  p) { julong  v = Atomic::load((volatile jlong*)p); compiler_barrier(); return v; }

inline jfloat   OrderAccess::load_acquire(volatile jfloat*  p) { jfloat  v = *p; compiler_barrier(); return v; }

inline jdouble  OrderAccess::load_acquire(volatile jdouble* p) { jdouble v = jdouble_cast(Atomic::load((volatile jlong*)p)); compiler_barrier(); return v; }

inline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t*   p) { intptr_t v = *p; compiler_barrier(); return v; }

inline void*    OrderAccess::load_ptr_acquire(volatile void*       p) { void*    v = *(void* volatile *)p; compiler_barrier(); return v; }

inline void*    OrderAccess::load_ptr_acquire(const volatile void* p) { void*    v = *(void* const volatile *)p; compiler_barrier(); return v; }

inline void     OrderAccess::release_store(volatile jbyte*   p, jbyte   v) { compiler_barrier(); *p = v; }

inline void     OrderAccess::release_store(volatile jshort*  p, jshort  v) { compiler_barrier(); *p = v; }

inline void     OrderAccess::release_store(volatile jint*    p, jint    v) { compiler_barrier(); *p = v; }

inline void     OrderAccess::release_store(volatile jlong*   p, jlong   v) { compiler_barrier(); Atomic::store(v, p); }

inline void     OrderAccess::release_store(volatile jubyte*  p, jubyte  v) { compiler_barrier(); *p = v; }

inline void     OrderAccess::release_store(volatile jushort* p, jushort v) { compiler_barrier(); *p = v; }

inline void     OrderAccess::release_store(volatile juint*   p, juint   v) { compiler_barrier(); *p = v; }

inline void     OrderAccess::release_store(volatile julong*  p, julong  v) { compiler_barrier(); Atomic::store((jlong)v, (volatile jlong*)p); }

inline void     OrderAccess::release_store(volatile jfloat*  p, jfloat  v) { compiler_barrier(); *p = v; }

inline void     OrderAccess::release_store(volatile jdouble* p, jdouble v) { release_store((volatile jlong *)p, jlong_cast(v)); }

inline void     OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { compiler_barrier(); *p = v; }

inline void     OrderAccess::release_store_ptr(volatile void*     p, void*    v) { compiler_barrier(); *(void* volatile *)p = v; }

inline void     OrderAccess::store_fence(jbyte*  p, jbyte  v) {

  __asm__ volatile (  "xchgb (%2),%0"

                    : "=q" (v)

                    : "0" (v), "r" (p)

                    : "memory");

}

inline void     OrderAccess::store_fence(jshort* p, jshort v) {

  __asm__ volatile (  "xchgw (%2),%0"

                    : "=r" (v)

                    : "0" (v), "r" (p)

                    : "memory");

}

inline void     OrderAccess::store_fence(jint*   p, jint   v) {

  __asm__ volatile (  "xchgl (%2),%0"

                    : "=r" (v)

                    : "0" (v), "r" (p)

                    : "memory");

}

inline void     OrderAccess::store_fence(jlong*   p, jlong   v) {

#ifdef AMD64

  __asm__ __volatile__ ("xchgq (%2), %0"

                        : "=r" (v)

                        : "0" (v), "r" (p)

                        : "memory");

#else

  *p = v; fence();

#endif // AMD64

}

// AMD64 copied the bodies for the the signed version. 32bit did this. As long as the

// compiler does the inlining this is simpler.

inline void     OrderAccess::store_fence(jubyte*  p, jubyte  v) { store_fence((jbyte*)p,  (jbyte)v);  }

inline void     OrderAccess::store_fence(jushort* p, jushort v) { store_fence((jshort*)p, (jshort)v); }

inline void     OrderAccess::store_fence(juint*   p, juint   v) { store_fence((jint*)p,   (jint)v);   }

inline void     OrderAccess::store_fence(julong*  p, julong  v) { store_fence((jlong*)p,  (jlong)v);  }

inline void     OrderAccess::store_fence(jfloat*  p, jfloat  v) { *p = v; fence(); }

inline void     OrderAccess::store_fence(jdouble* p, jdouble v) { store_fence((jlong*)p, jlong_cast(v)); }

inline void     OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) {

#ifdef AMD64

  __asm__ __volatile__ ("xchgq (%2), %0"

                        : "=r" (v)

                        : "0" (v), "r" (p)

                        : "memory");

#else

  store_fence((jint*)p, (jint)v);

#endif // AMD64

}

inline void     OrderAccess::store_ptr_fence(void**    p, void*    v) {

#ifdef AMD64

  __asm__ __volatile__ ("xchgq (%2), %0"

                        : "=r" (v)

                        : "0" (v), "r" (p)

                        : "memory");

#else

  store_fence((jint*)p, (jint)v);

#endif // AMD64

}

// Must duplicate definitions instead of calling store_fence because we don't want to cast away volatile.

inline void     OrderAccess::release_store_fence(volatile jbyte*  p, jbyte  v) {

  __asm__ volatile (  "xchgb (%2),%0"

                    : "=q" (v)

                    : "0" (v), "r" (p)

                    : "memory");

}

inline void     OrderAccess::release_store_fence(volatile jshort* p, jshort v) {

  __asm__ volatile (  "xchgw (%2),%0"

                    : "=r" (v)

                    : "0" (v), "r" (p)

                    : "memory");

}

inline void     OrderAccess::release_store_fence(volatile jint*   p, jint   v) {

  __asm__ volatile (  "xchgl (%2),%0"

                    : "=r" (v)

                    : "0" (v), "r" (p)

                    : "memory");

}

inline void     OrderAccess::release_store_fence(volatile jlong*   p, jlong   v) {

#ifdef AMD64

  __asm__ __volatile__ (  "xchgq (%2), %0"

                          : "=r" (v)

                          : "0" (v), "r" (p)

                          : "memory");

#else

  release_store(p, v); fence();

#endif // AMD64

}

inline void     OrderAccess::release_store_fence(volatile jubyte*  p, jubyte  v) { release_store_fence((volatile jbyte*)p,  (jbyte)v);  }

inline void     OrderAccess::release_store_fence(volatile jushort* p, jushort v) { release_store_fence((volatile jshort*)p, (jshort)v); }

inline void     OrderAccess::release_store_fence(volatile juint*   p, juint   v) { release_store_fence((volatile jint*)p,   (jint)v);   }

inline void     OrderAccess::release_store_fence(volatile julong*  p, julong  v) { release_store_fence((volatile jlong*)p,  (jlong)v);  }

inline void     OrderAccess::release_store_fence(volatile jfloat*  p, jfloat  v) { *p = v; fence(); }

inline void     OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { release_store_fence((volatile jlong*)p, jlong_cast(v)); }

inline void     OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) {

#ifdef AMD64

  __asm__ __volatile__ (  "xchgq (%2), %0"

                          : "=r" (v)

                          : "0" (v), "r" (p)

                          : "memory");

#else

  release_store_fence((volatile jint*)p, (jint)v);

#endif // AMD64

}

inline void     OrderAccess::release_store_ptr_fence(volatile void*     p, void*    v) {

#ifdef AMD64

  __asm__ __volatile__ (  "xchgq (%2), %0"

                          : "=r" (v)

                          : "0" (v), "r" (p)

                          : "memory");

#else

  release_store_fence((volatile jint*)p, (jint)v);

#endif // AMD64

}

#endif // OS_CPU_LINUX_X86_VM_ORDERACCESS_LINUX_X86_INLINE_HPP