src/hotspot/cpu/arm/relocInfo_arm.cpp
author coleenp
Wed, 06 Jun 2018 10:45:40 -0400
changeset 50429 83aec1d357d4
parent 49849 2aa32bb6f3dc
child 52351 0ecb4e520110
permissions -rw-r--r--
8204301: Make OrderAccess functions available to hpp rather than inline.hpp files Summary: move orderAccess.inline.hpp into orderAccess.hpp and remove os.hpp inclusion and conditional os::is_MP() for fence on x86 platforms Reviewed-by: dholmes, hseigel
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/*
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 * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#include "precompiled.hpp"
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#include "asm/assembler.inline.hpp"
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#include "assembler_arm.inline.hpp"
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#include "code/relocInfo.hpp"
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#include "nativeInst_arm.hpp"
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#include "oops/compressedOops.inline.hpp"
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#include "oops/oop.hpp"
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#include "runtime/orderAccess.hpp"
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#include "runtime/safepoint.hpp"
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void Relocation::pd_set_data_value(address x, intptr_t o, bool verify_only) {
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  NativeMovConstReg* ni = nativeMovConstReg_at(addr());
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#if defined(AARCH64) && defined(COMPILER2)
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  if (ni->is_movz()) {
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    assert(type() == relocInfo::oop_type, "!");
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    if (verify_only) {
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      uintptr_t d = ni->data();
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      guarantee((d >> 32) == 0, "not narrow oop");
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      narrowOop no = d;
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      oop o = CompressedOops::decode(no);
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      guarantee(cast_from_oop<intptr_t>(o) == (intptr_t)x, "instructions must match");
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    } else {
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      ni->set_data((intptr_t)x);
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    }
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    return;
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  }
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#endif
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  if (verify_only) {
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    guarantee(ni->data() == (intptr_t)(x + o), "instructions must match");
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  } else {
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    ni->set_data((intptr_t)(x + o));
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  }
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}
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address Relocation::pd_call_destination(address orig_addr) {
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  address pc = addr();
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  int adj = 0;
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  if (orig_addr != NULL) {
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    // We just moved this call instruction from orig_addr to addr().
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    // This means that, when relative, its target will appear to have grown by addr() - orig_addr.
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    adj = orig_addr - pc;
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  }
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  RawNativeInstruction* ni = rawNativeInstruction_at(pc);
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#if (!defined(AARCH64))
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  if (NOT_AARCH64(ni->is_add_lr()) AARCH64_ONLY(ni->is_adr_aligned_lr())) {
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    // On arm32, skip the optional 'add LR, PC, #offset'
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    // (Allowing the jump support code to handle fat_call)
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    pc = ni->next_raw_instruction_address();
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    ni = nativeInstruction_at(pc);
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  }
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#endif
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  if (AARCH64_ONLY(ni->is_call()) NOT_AARCH64(ni->is_bl())) {
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    // For arm32, fat_call are handled by is_jump for the new 'ni',
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    // requiring only to support is_bl.
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    //
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    // For AARCH64, skipping a leading adr is not sufficient
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    // to reduce calls to a simple bl.
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    return rawNativeCall_at(pc)->destination(adj);
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  }
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  if (ni->is_jump()) {
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    return rawNativeJump_at(pc)->jump_destination(adj);
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  }
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  ShouldNotReachHere();
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  return NULL;
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}
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void Relocation::pd_set_call_destination(address x) {
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  address pc = addr();
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  NativeInstruction* ni = nativeInstruction_at(pc);
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#if (!defined(AARCH64))
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  if (NOT_AARCH64(ni->is_add_lr()) AARCH64_ONLY(ni->is_adr_aligned_lr())) {
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    // On arm32, skip the optional 'add LR, PC, #offset'
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    // (Allowing the jump support code to handle fat_call)
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    pc = ni->next_raw_instruction_address();
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    ni = nativeInstruction_at(pc);
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  }
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#endif
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  if (AARCH64_ONLY(ni->is_call()) NOT_AARCH64(ni->is_bl())) {
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    // For arm32, fat_call are handled by is_jump for the new 'ni',
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    // requiring only to support is_bl.
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    //
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    // For AARCH64, skipping a leading adr is not sufficient
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    // to reduce calls to a simple bl.
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    rawNativeCall_at(pc)->set_destination(x);
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    return;
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  }
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  if (ni->is_jump()) { // raw jump
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    rawNativeJump_at(pc)->set_jump_destination(x);
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    return;
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  }
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  ShouldNotReachHere();
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}
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address* Relocation::pd_address_in_code() {
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  return (address*)addr();
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}
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address Relocation::pd_get_address_from_code() {
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  return *pd_address_in_code();
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}
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void poll_Relocation::fix_relocation_after_move(const CodeBuffer* src, CodeBuffer* dest) {
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}
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void metadata_Relocation::pd_fix_value(address x) {
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  assert(! addr_in_const(), "Do not use");
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#ifdef AARCH64
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#ifdef COMPILER2
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  NativeMovConstReg* ni = nativeMovConstReg_at(addr());
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  if (ni->is_mov_slow()) {
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    return;
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  }
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#endif
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  set_value(x);
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#else
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  if (!VM_Version::supports_movw()) {
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    set_value(x);
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#ifdef ASSERT
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  } else {
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    // the movw/movt data should be correct
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    NativeMovConstReg* ni = nativeMovConstReg_at(addr());
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    assert(ni->is_movw(), "not a movw");
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    // The following assert should be correct but the shared code
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    // currently 'fixes' the metadata instructions before the
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    // metadata_table is copied in the new method (see
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    // JDK-8042845). This means that 'x' (which comes from the table)
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    // does not match the value inlined in the code (which is
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    // correct). Failure can be temporarily ignored since the code is
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    // correct and the table is copied shortly afterward.
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    //
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    // assert(ni->data() == (int)x, "metadata relocation mismatch");
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#endif
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  }
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#endif // !AARCH64
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}