author | coleenp |
Wed, 06 Jun 2018 10:45:40 -0400 | |
changeset 50429 | 83aec1d357d4 |
parent 49849 | 2aa32bb6f3dc |
child 52351 | 0ecb4e520110 |
permissions | -rw-r--r-- |
42664 | 1 |
/* |
50429
83aec1d357d4
8204301: Make OrderAccess functions available to hpp rather than inline.hpp files
coleenp
parents:
49849
diff
changeset
|
2 |
* Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved. |
42664 | 3 |
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 |
* |
|
5 |
* This code is free software; you can redistribute it and/or modify it |
|
6 |
* under the terms of the GNU General Public License version 2 only, as |
|
7 |
* published by the Free Software Foundation. |
|
8 |
* |
|
9 |
* This code is distributed in the hope that it will be useful, but WITHOUT |
|
10 |
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
|
11 |
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
|
12 |
* version 2 for more details (a copy is included in the LICENSE file that |
|
13 |
* accompanied this code). |
|
14 |
* |
|
15 |
* You should have received a copy of the GNU General Public License version |
|
16 |
* 2 along with this work; if not, write to the Free Software Foundation, |
|
17 |
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
|
18 |
* |
|
19 |
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
20 |
* or visit www.oracle.com if you need additional information or have any |
|
21 |
* questions. |
|
22 |
* |
|
23 |
*/ |
|
24 |
||
25 |
#include "precompiled.hpp" |
|
26 |
#include "asm/assembler.inline.hpp" |
|
27 |
#include "assembler_arm.inline.hpp" |
|
28 |
#include "code/relocInfo.hpp" |
|
29 |
#include "nativeInst_arm.hpp" |
|
49592
77fb0be7d19f
8199946: Move load/store and encode/decode out of oopDesc
stefank
parents:
47216
diff
changeset
|
30 |
#include "oops/compressedOops.inline.hpp" |
77fb0be7d19f
8199946: Move load/store and encode/decode out of oopDesc
stefank
parents:
47216
diff
changeset
|
31 |
#include "oops/oop.hpp" |
50429
83aec1d357d4
8204301: Make OrderAccess functions available to hpp rather than inline.hpp files
coleenp
parents:
49849
diff
changeset
|
32 |
#include "runtime/orderAccess.hpp" |
42664 | 33 |
#include "runtime/safepoint.hpp" |
34 |
||
35 |
void Relocation::pd_set_data_value(address x, intptr_t o, bool verify_only) { |
|
36 |
||
37 |
NativeMovConstReg* ni = nativeMovConstReg_at(addr()); |
|
38 |
#if defined(AARCH64) && defined(COMPILER2) |
|
39 |
if (ni->is_movz()) { |
|
40 |
assert(type() == relocInfo::oop_type, "!"); |
|
41 |
if (verify_only) { |
|
42 |
uintptr_t d = ni->data(); |
|
43 |
guarantee((d >> 32) == 0, "not narrow oop"); |
|
44 |
narrowOop no = d; |
|
49592
77fb0be7d19f
8199946: Move load/store and encode/decode out of oopDesc
stefank
parents:
47216
diff
changeset
|
45 |
oop o = CompressedOops::decode(no); |
42664 | 46 |
guarantee(cast_from_oop<intptr_t>(o) == (intptr_t)x, "instructions must match"); |
47 |
} else { |
|
48 |
ni->set_data((intptr_t)x); |
|
49 |
} |
|
50 |
return; |
|
51 |
} |
|
52 |
#endif |
|
53 |
if (verify_only) { |
|
54 |
guarantee(ni->data() == (intptr_t)(x + o), "instructions must match"); |
|
55 |
} else { |
|
56 |
ni->set_data((intptr_t)(x + o)); |
|
57 |
} |
|
58 |
} |
|
59 |
||
60 |
address Relocation::pd_call_destination(address orig_addr) { |
|
61 |
address pc = addr(); |
|
62 |
||
63 |
int adj = 0; |
|
64 |
if (orig_addr != NULL) { |
|
65 |
// We just moved this call instruction from orig_addr to addr(). |
|
66 |
// This means that, when relative, its target will appear to have grown by addr() - orig_addr. |
|
67 |
adj = orig_addr - pc; |
|
68 |
} |
|
69 |
||
70 |
RawNativeInstruction* ni = rawNativeInstruction_at(pc); |
|
71 |
||
72 |
#if (!defined(AARCH64)) |
|
73 |
if (NOT_AARCH64(ni->is_add_lr()) AARCH64_ONLY(ni->is_adr_aligned_lr())) { |
|
74 |
// On arm32, skip the optional 'add LR, PC, #offset' |
|
75 |
// (Allowing the jump support code to handle fat_call) |
|
76 |
pc = ni->next_raw_instruction_address(); |
|
77 |
ni = nativeInstruction_at(pc); |
|
78 |
} |
|
79 |
#endif |
|
80 |
||
81 |
if (AARCH64_ONLY(ni->is_call()) NOT_AARCH64(ni->is_bl())) { |
|
82 |
// For arm32, fat_call are handled by is_jump for the new 'ni', |
|
83 |
// requiring only to support is_bl. |
|
84 |
// |
|
85 |
// For AARCH64, skipping a leading adr is not sufficient |
|
86 |
// to reduce calls to a simple bl. |
|
87 |
return rawNativeCall_at(pc)->destination(adj); |
|
88 |
} |
|
89 |
||
90 |
if (ni->is_jump()) { |
|
91 |
return rawNativeJump_at(pc)->jump_destination(adj); |
|
92 |
} |
|
93 |
ShouldNotReachHere(); |
|
94 |
return NULL; |
|
95 |
} |
|
96 |
||
97 |
void Relocation::pd_set_call_destination(address x) { |
|
98 |
address pc = addr(); |
|
99 |
NativeInstruction* ni = nativeInstruction_at(pc); |
|
100 |
||
101 |
#if (!defined(AARCH64)) |
|
102 |
if (NOT_AARCH64(ni->is_add_lr()) AARCH64_ONLY(ni->is_adr_aligned_lr())) { |
|
103 |
// On arm32, skip the optional 'add LR, PC, #offset' |
|
104 |
// (Allowing the jump support code to handle fat_call) |
|
105 |
pc = ni->next_raw_instruction_address(); |
|
106 |
ni = nativeInstruction_at(pc); |
|
107 |
} |
|
108 |
#endif |
|
109 |
||
110 |
if (AARCH64_ONLY(ni->is_call()) NOT_AARCH64(ni->is_bl())) { |
|
111 |
// For arm32, fat_call are handled by is_jump for the new 'ni', |
|
112 |
// requiring only to support is_bl. |
|
113 |
// |
|
114 |
// For AARCH64, skipping a leading adr is not sufficient |
|
115 |
// to reduce calls to a simple bl. |
|
116 |
rawNativeCall_at(pc)->set_destination(x); |
|
117 |
return; |
|
118 |
} |
|
119 |
||
120 |
if (ni->is_jump()) { // raw jump |
|
121 |
rawNativeJump_at(pc)->set_jump_destination(x); |
|
122 |
return; |
|
123 |
} |
|
124 |
ShouldNotReachHere(); |
|
125 |
} |
|
126 |
||
127 |
||
128 |
address* Relocation::pd_address_in_code() { |
|
129 |
return (address*)addr(); |
|
130 |
} |
|
131 |
||
132 |
address Relocation::pd_get_address_from_code() { |
|
133 |
return *pd_address_in_code(); |
|
134 |
} |
|
135 |
||
136 |
void poll_Relocation::fix_relocation_after_move(const CodeBuffer* src, CodeBuffer* dest) { |
|
137 |
} |
|
138 |
||
139 |
void metadata_Relocation::pd_fix_value(address x) { |
|
140 |
assert(! addr_in_const(), "Do not use"); |
|
141 |
#ifdef AARCH64 |
|
142 |
#ifdef COMPILER2 |
|
143 |
NativeMovConstReg* ni = nativeMovConstReg_at(addr()); |
|
45429
e41531cfe73e
8181093: assert(si->is_ldr_literal()) failed on arm64 test nsk/jdi/.../returnValue004
bobv
parents:
42664
diff
changeset
|
144 |
if (ni->is_mov_slow()) { |
42664 | 145 |
return; |
146 |
} |
|
147 |
#endif |
|
148 |
set_value(x); |
|
149 |
#else |
|
150 |
if (!VM_Version::supports_movw()) { |
|
151 |
set_value(x); |
|
152 |
#ifdef ASSERT |
|
153 |
} else { |
|
154 |
// the movw/movt data should be correct |
|
155 |
NativeMovConstReg* ni = nativeMovConstReg_at(addr()); |
|
156 |
assert(ni->is_movw(), "not a movw"); |
|
157 |
// The following assert should be correct but the shared code |
|
158 |
// currently 'fixes' the metadata instructions before the |
|
159 |
// metadata_table is copied in the new method (see |
|
160 |
// JDK-8042845). This means that 'x' (which comes from the table) |
|
161 |
// does not match the value inlined in the code (which is |
|
162 |
// correct). Failure can be temporarily ignored since the code is |
|
163 |
// correct and the table is copied shortly afterward. |
|
164 |
// |
|
165 |
// assert(ni->data() == (int)x, "metadata relocation mismatch"); |
|
166 |
#endif |
|
167 |
} |
|
168 |
#endif // !AARCH64 |
|
169 |
} |