/*

 * Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved.

 * Copyright (c) 2016, 2017, SAP SE. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#include "precompiled.hpp"

#include "c1/c1_Compilation.hpp"

#include "c1/c1_FrameMap.hpp"

#include "c1/c1_Instruction.hpp"

#include "c1/c1_LIRAssembler.hpp"

#include "c1/c1_LIRGenerator.hpp"

#include "c1/c1_Runtime1.hpp"

#include "c1/c1_ValueStack.hpp"

#include "ci/ciArray.hpp"

#include "ci/ciObjArrayKlass.hpp"

#include "ci/ciTypeArrayKlass.hpp"

#include "runtime/sharedRuntime.hpp"

#include "runtime/stubRoutines.hpp"

#include "vmreg_s390.inline.hpp"

#ifdef ASSERT

#define __ gen()->lir(__FILE__, __LINE__)->

#else

#define __ gen()->lir()->

#endif

void LIRItem::load_byte_item() {

  // Byte loads use same registers as other loads.

  load_item();

}

void LIRItem::load_nonconstant(int bits) {

  LIR_Opr r = value()->operand();

  if (_gen->can_inline_as_constant(value(), bits)) {

    if (!r->is_constant()) {

      r = LIR_OprFact::value_type(value()->type());

    }

    _result = r;

  } else {

    load_item();

  }

}

//--------------------------------------------------------------

//               LIRGenerator

//--------------------------------------------------------------

LIR_Opr LIRGenerator::exceptionOopOpr() { return FrameMap::as_oop_opr(Z_EXC_OOP); }

LIR_Opr LIRGenerator::exceptionPcOpr()  { return FrameMap::as_opr(Z_EXC_PC); }

LIR_Opr LIRGenerator::divInOpr()        { return FrameMap::Z_R11_opr; }

LIR_Opr LIRGenerator::divOutOpr()       { return FrameMap::Z_R11_opr; }

LIR_Opr LIRGenerator::remOutOpr()       { return FrameMap::Z_R10_opr; }

LIR_Opr LIRGenerator::ldivInOpr()       { return FrameMap::Z_R11_long_opr; }

LIR_Opr LIRGenerator::ldivOutOpr()      { return FrameMap::Z_R11_long_opr; }

LIR_Opr LIRGenerator::lremOutOpr()      { return FrameMap::Z_R10_long_opr; }

LIR_Opr LIRGenerator::syncLockOpr()     { return new_register(T_INT); }

LIR_Opr LIRGenerator::syncTempOpr()     { return FrameMap::Z_R13_opr; }

LIR_Opr LIRGenerator::getThreadTemp()   { return LIR_OprFact::illegalOpr; }

LIR_Opr LIRGenerator::result_register_for (ValueType* type, bool callee) {

  LIR_Opr opr;

  switch (type->tag()) {

    case intTag:    opr = FrameMap::Z_R2_opr;        break;

    case objectTag: opr = FrameMap::Z_R2_oop_opr;    break;

    case longTag:   opr = FrameMap::Z_R2_long_opr;   break;

    case floatTag:  opr = FrameMap::Z_F0_opr;        break;

    case doubleTag: opr = FrameMap::Z_F0_double_opr; break;

    case addressTag:

    default: ShouldNotReachHere(); return LIR_OprFact::illegalOpr;

  }

  assert(opr->type_field() == as_OprType(as_BasicType(type)), "type mismatch");

  return opr;

}

LIR_Opr LIRGenerator::rlock_byte(BasicType type) {

  return new_register(T_INT);

}

//--------- Loading items into registers. --------------------------------

// z/Architecture cannot inline all constants.

bool LIRGenerator::can_store_as_constant(Value v, BasicType type) const {

  if (v->type()->as_IntConstant() != NULL) {

    return Immediate::is_simm16(v->type()->as_IntConstant()->value());

  } else if (v->type()->as_LongConstant() != NULL) {

    return Immediate::is_simm16(v->type()->as_LongConstant()->value());

  } else if (v->type()->as_ObjectConstant() != NULL) {

    return v->type()->as_ObjectConstant()->value()->is_null_object();

  } else {

    return false;

  }

}

bool LIRGenerator::can_inline_as_constant(Value i, int bits) const {

  if (i->type()->as_IntConstant() != NULL) {

    return Assembler::is_simm(i->type()->as_IntConstant()->value(), bits);

  } else if (i->type()->as_LongConstant() != NULL) {

    return Assembler::is_simm(i->type()->as_LongConstant()->value(), bits);

  } else {

    return can_store_as_constant(i, as_BasicType(i->type()));

  }

}

bool LIRGenerator::can_inline_as_constant(LIR_Const* c) const {

  if (c->type() == T_INT) {

    return Immediate::is_simm20(c->as_jint());

  } else   if (c->type() == T_LONG) {

    return Immediate::is_simm20(c->as_jlong());

  }

  return false;

}

LIR_Opr LIRGenerator::safepoint_poll_register() {

  return new_register(longType);

}

LIR_Address* LIRGenerator::generate_address(LIR_Opr base, LIR_Opr index,

                                            int shift, int disp, BasicType type) {

  assert(base->is_register(), "must be");

  if (index->is_constant()) {

    intx large_disp = disp;

    LIR_Const *constant = index->as_constant_ptr();

    if (constant->type() == T_LONG) {

      large_disp += constant->as_jlong() << shift;

    } else {

      large_disp += (intx)(constant->as_jint()) << shift;

    }

    if (Displacement::is_validDisp(large_disp)) {

      return new LIR_Address(base, large_disp, type);

    }

    // Index is illegal so replace it with the displacement loaded into a register.

    index = new_pointer_register();

    __ move(LIR_OprFact::intptrConst(large_disp), index);

    return new LIR_Address(base, index, type);

  } else {

    if (shift > 0) {

      LIR_Opr tmp = new_pointer_register();

      __ shift_left(index, shift, tmp);

      index = tmp;

    }

    return new LIR_Address(base, index, disp, type);

  }

}

LIR_Address* LIRGenerator::emit_array_address(LIR_Opr array_opr, LIR_Opr index_opr,

                                              BasicType type) {

  int elem_size = type2aelembytes(type);

  int shift = exact_log2(elem_size);

  int offset_in_bytes = arrayOopDesc::base_offset_in_bytes(type);

  LIR_Address* addr;

  if (index_opr->is_constant()) {

    addr = new LIR_Address(array_opr,

                           offset_in_bytes + (intx)(index_opr->as_jint()) * elem_size, type);

  } else {

    if (index_opr->type() == T_INT) {

      LIR_Opr tmp = new_register(T_LONG);

      __ convert(Bytecodes::_i2l, index_opr, tmp);

      index_opr = tmp;

    }

    if (shift > 0) {

      __ shift_left(index_opr, shift, index_opr);

    }

    addr = new LIR_Address(array_opr,

                           index_opr,

                           offset_in_bytes, type);

  }

  return addr;

}

LIR_Opr LIRGenerator::load_immediate(int x, BasicType type) {

  LIR_Opr r = LIR_OprFact::illegalOpr;

  if (type == T_LONG) {

    r = LIR_OprFact::longConst(x);

  } else if (type == T_INT) {

    r = LIR_OprFact::intConst(x);

  } else {

    ShouldNotReachHere();

  }

  return r;

}

void LIRGenerator::increment_counter(address counter, BasicType type, int step) {

  LIR_Opr pointer = new_pointer_register();

  __ move(LIR_OprFact::intptrConst(counter), pointer);

  LIR_Address* addr = new LIR_Address(pointer, type);

  increment_counter(addr, step);

}

void LIRGenerator::increment_counter(LIR_Address* addr, int step) {

  __ add((LIR_Opr)addr, LIR_OprFact::intConst(step), (LIR_Opr)addr);

}

void LIRGenerator::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {

  LIR_Opr scratch = FrameMap::Z_R1_opr;

  __ load(new LIR_Address(base, disp, T_INT), scratch, info);

  __ cmp(condition, scratch, c);

}

void LIRGenerator::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, int disp, BasicType type, CodeEmitInfo* info) {

  __ cmp_reg_mem(condition, reg, new LIR_Address(base, disp, type), info);

}

bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, int c, LIR_Opr result, LIR_Opr tmp) {

  if (tmp->is_valid()) {

    if (is_power_of_2(c + 1)) {

      __ move(left, tmp);

      __ sub(left, tmp, result);

      return true;

    } else if (is_power_of_2(c - 1)) {

      __ move(left, tmp);

      __ add(left, tmp, result);

      return true;

    }

  }

  return false;

}

void LIRGenerator::store_stack_parameter (LIR_Opr item, ByteSize offset_from_sp) {

  BasicType type = item->type();

  __ store(item, new LIR_Address(FrameMap::Z_SP_opr, in_bytes(offset_from_sp), type));

}

//----------------------------------------------------------------------

//             visitor functions

//----------------------------------------------------------------------

void LIRGenerator::array_store_check(LIR_Opr value, LIR_Opr array, CodeEmitInfo* store_check_info, ciMethod* profiled_method, int profiled_bci) {

  LIR_Opr tmp1 = new_register(objectType);

  LIR_Opr tmp2 = new_register(objectType);

  LIR_Opr tmp3 = LIR_OprFact::illegalOpr;

  __ store_check(value, array, tmp1, tmp2, tmp3, store_check_info, profiled_method, profiled_bci);

}

void LIRGenerator::do_MonitorEnter(MonitorEnter* x) {

  assert(x->is_pinned(),"");

  LIRItem obj(x->obj(), this);

  obj.load_item();

  set_no_result(x);

  // "lock" stores the address of the monitor stack slot, so this is not an oop.

  LIR_Opr lock = new_register(T_INT);

  CodeEmitInfo* info_for_exception = NULL;

  if (x->needs_null_check()) {

    info_for_exception = state_for (x);

  }

  // This CodeEmitInfo must not have the xhandlers because here the

  // object is already locked (xhandlers expect object to be unlocked).

  CodeEmitInfo* info = state_for (x, x->state(), true);

  monitor_enter(obj.result(), lock, syncTempOpr(), LIR_OprFact::illegalOpr,

                x->monitor_no(), info_for_exception, info);

}

void LIRGenerator::do_MonitorExit(MonitorExit* x) {

  assert(x->is_pinned(),"");

  LIRItem obj(x->obj(), this);

  obj.dont_load_item();

  LIR_Opr lock = new_register(T_INT);

  LIR_Opr obj_temp = new_register(T_INT);

  set_no_result(x);

  monitor_exit(obj_temp, lock, syncTempOpr(), LIR_OprFact::illegalOpr, x->monitor_no());

}

// _ineg, _lneg, _fneg, _dneg

void LIRGenerator::do_NegateOp(NegateOp* x) {

  LIRItem value(x->x(), this);

  value.load_item();

  LIR_Opr reg = rlock_result(x);

  __ negate(value.result(), reg);

}

// for _fadd, _fmul, _fsub, _fdiv, _frem

//     _dadd, _dmul, _dsub, _ddiv, _drem

void LIRGenerator::do_ArithmeticOp_FPU(ArithmeticOp* x) {

  LIRItem left(x->x(),  this);

  LIRItem right(x->y(), this);

  LIRItem* left_arg  = &left;

  LIRItem* right_arg = &right;

  assert(!left.is_stack(), "can't both be memory operands");

  left.load_item();

  if (right.is_register() || right.is_constant()) {

    right.load_item();

  } else {

    right.dont_load_item();

  }

  if ((x->op() == Bytecodes::_frem) || (x->op() == Bytecodes::_drem)) {

    address entry;

    switch (x->op()) {

    case Bytecodes::_frem:

      entry = CAST_FROM_FN_PTR(address, SharedRuntime::frem);

      break;

    case Bytecodes::_drem:

      entry = CAST_FROM_FN_PTR(address, SharedRuntime::drem);

      break;

    default:

      ShouldNotReachHere();

    }

    LIR_Opr result = call_runtime(x->x(), x->y(), entry, x->type(), NULL);

    set_result(x, result);

  } else {

    LIR_Opr reg = rlock(x);

    LIR_Opr tmp = LIR_OprFact::illegalOpr;

    arithmetic_op_fpu(x->op(), reg, left.result(), right.result(), x->is_strictfp(), tmp);

    set_result(x, reg);

  }

}

// for _ladd, _lmul, _lsub, _ldiv, _lrem

void LIRGenerator::do_ArithmeticOp_Long(ArithmeticOp* x) {

  if (x->op() == Bytecodes::_ldiv || x->op() == Bytecodes::_lrem) {

    // Use shifts if divisior is a power of 2 otherwise use DSGR instruction.

    // Instruction: DSGR R1, R2

    // input : R1+1: dividend   (R1, R1+1 designate a register pair, R1 must be even)

    //         R2:   divisor

    //

    // output: R1+1: quotient

    //         R1:   remainder

    //

    // Register selection: R1:   Z_R10

    //                     R1+1: Z_R11

    //                     R2:   to be chosen by register allocator (linear scan)

    // R1, and R1+1 will be destroyed.

    LIRItem right(x->y(), this);

    LIRItem left(x->x() , this);   // Visit left second, so that the is_register test is valid.

    // Call state_for before load_item_force because state_for may

    // force the evaluation of other instructions that are needed for

    // correct debug info. Otherwise the live range of the fix

    // register might be too long.

    CodeEmitInfo* info = state_for (x);

    LIR_Opr result = rlock_result(x);

    LIR_Opr result_reg = result;

    LIR_Opr tmp = LIR_OprFact::illegalOpr;

    LIR_Opr divisor_opr = right.result();

    if (divisor_opr->is_constant() && is_power_of_2(divisor_opr->as_jlong())) {

      left.load_item();

      right.dont_load_item();

    } else {

      left.load_item_force(ldivInOpr());

      right.load_item();

      // DSGR instruction needs register pair.

      if (x->op() == Bytecodes::_ldiv) {

        result_reg = ldivOutOpr();

        tmp        = lremOutOpr();

      } else {

        result_reg = lremOutOpr();

        tmp        = ldivOutOpr();

      }

    }

    if (!ImplicitDiv0Checks) {

      __ cmp(lir_cond_equal, right.result(), LIR_OprFact::longConst(0));

      __ branch(lir_cond_equal, T_LONG, new DivByZeroStub(info));

      // Idiv/irem cannot trap (passing info would generate an assertion).

      info = NULL;

    }

    if (x->op() == Bytecodes::_lrem) {

      __ irem(left.result(), right.result(), result_reg, tmp, info);

    } else if (x->op() == Bytecodes::_ldiv) {

      __ idiv(left.result(), right.result(), result_reg, tmp, info);

    } else {

      ShouldNotReachHere();

    }

    if (result_reg != result) {

      __ move(result_reg, result);

    }

  } else {

    LIRItem left(x->x(), this);

    LIRItem right(x->y(), this);

    left.load_item();

    right.load_nonconstant(32);

    rlock_result(x);

    arithmetic_op_long(x->op(), x->operand(), left.result(), right.result(), NULL);

  }

}

// for: _iadd, _imul, _isub, _idiv, _irem

void LIRGenerator::do_ArithmeticOp_Int(ArithmeticOp* x) {

  if (x->op() == Bytecodes::_idiv || x->op() == Bytecodes::_irem) {

    // Use shifts if divisior is a power of 2 otherwise use DSGFR instruction.

    // Instruction: DSGFR R1, R2

    // input : R1+1: dividend   (R1, R1+1 designate a register pair, R1 must be even)

    //         R2:   divisor

    //

    // output: R1+1: quotient

    //         R1:   remainder

    //

    // Register selection: R1:   Z_R10

    //                     R1+1: Z_R11

    //                     R2:   To be chosen by register allocator (linear scan).

    // R1, and R1+1 will be destroyed.

    LIRItem right(x->y(), this);

    LIRItem left(x->x() , this);   // Visit left second, so that the is_register test is valid.

    // Call state_for before load_item_force because state_for may

    // force the evaluation of other instructions that are needed for

    // correct debug info. Otherwise the live range of the fix

    // register might be too long.

    CodeEmitInfo* info = state_for (x);

    LIR_Opr result = rlock_result(x);

    LIR_Opr result_reg = result;

    LIR_Opr tmp = LIR_OprFact::illegalOpr;

    LIR_Opr divisor_opr = right.result();

    if (divisor_opr->is_constant() && is_power_of_2(divisor_opr->as_jint())) {

      left.load_item();

      right.dont_load_item();

    } else {

      left.load_item_force(divInOpr());

      right.load_item();

      // DSGFR instruction needs register pair.

      if (x->op() == Bytecodes::_idiv) {

        result_reg = divOutOpr();

        tmp        = remOutOpr();

      } else {

        result_reg = remOutOpr();

        tmp        = divOutOpr();

      }

    }

    if (!ImplicitDiv0Checks) {

      __ cmp(lir_cond_equal, right.result(), LIR_OprFact::intConst(0));

      __ branch(lir_cond_equal, T_INT, new DivByZeroStub(info));

      // Idiv/irem cannot trap (passing info would generate an assertion).

      info = NULL;

    }

    if (x->op() == Bytecodes::_irem) {

      __ irem(left.result(), right.result(), result_reg, tmp, info);

    } else if (x->op() == Bytecodes::_idiv) {

      __ idiv(left.result(), right.result(), result_reg, tmp, info);

    } else {

      ShouldNotReachHere();

    }

    if (result_reg != result) {

      __ move(result_reg, result);

    }

  } else {

    LIRItem left(x->x(),  this);

    LIRItem right(x->y(), this);

    LIRItem* left_arg = &left;

    LIRItem* right_arg = &right;

    if (x->is_commutative() && left.is_stack() && right.is_register()) {

      // swap them if left is real stack (or cached) and right is real register(not cached)

      left_arg = &right;

      right_arg = &left;

    }

    left_arg->load_item();

    // Do not need to load right, as we can handle stack and constants.

    if (x->op() == Bytecodes::_imul) {

      bool use_tmp = false;

      if (right_arg->is_constant()) {

        int iconst = right_arg->get_jint_constant();

        if (is_power_of_2(iconst - 1) || is_power_of_2(iconst + 1)) {

          use_tmp = true;

        }

      }

      right_arg->dont_load_item();

      LIR_Opr tmp = LIR_OprFact::illegalOpr;

      if (use_tmp) {

        tmp = new_register(T_INT);

      }

      rlock_result(x);

      arithmetic_op_int(x->op(), x->operand(), left_arg->result(), right_arg->result(), tmp);

    } else {

      right_arg->dont_load_item();

      rlock_result(x);

      LIR_Opr tmp = LIR_OprFact::illegalOpr;

      arithmetic_op_int(x->op(), x->operand(), left_arg->result(), right_arg->result(), tmp);

    }

  }

}

void LIRGenerator::do_ArithmeticOp(ArithmeticOp* x) {

  // If an operand with use count 1 is the left operand, then it is

  // likely that no move for 2-operand-LIR-form is necessary.

  if (x->is_commutative() && x->y()->as_Constant() == NULL && x->x()->use_count() > x->y()->use_count()) {

    x->swap_operands();

  }

  ValueTag tag = x->type()->tag();

  assert(x->x()->type()->tag() == tag && x->y()->type()->tag() == tag, "wrong parameters");

  switch (tag) {