hotspot/src/share/vm/opto/chaitin.cpp
author jwilhelm
Thu, 06 Jul 2017 01:50:26 +0200
changeset 46630 75aa3e39d02c
parent 46625 edefffab74e2
permissions -rw-r--r--
8182299: Enable disabled clang warnings, build on OSX 10 + Xcode 8 8182656: Make the required changes in GC code to build on OSX 10 + Xcode 8 8182657: Make the required changes in Runtime code to build on OSX 10 + Xcode 8 8182658: Make the required changes in Compiler code to build on OSX 10 + Xcode 8 Reviewed-by: jwilhelm, ehelin, phh Contributed-by: phh <hohensee@amazon.com>, jwilhelm <jesper.wilhelmsson@oracle.com>
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/*
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 * Copyright (c) 2000, 2017, Oracle and/or its affiliates. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#include "precompiled.hpp"
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#include "compiler/compileLog.hpp"
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#include "compiler/oopMap.hpp"
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#include "memory/allocation.inline.hpp"
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#include "memory/resourceArea.hpp"
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#include "opto/addnode.hpp"
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#include "opto/block.hpp"
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#include "opto/callnode.hpp"
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#include "opto/cfgnode.hpp"
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#include "opto/chaitin.hpp"
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#include "opto/coalesce.hpp"
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#include "opto/connode.hpp"
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#include "opto/idealGraphPrinter.hpp"
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#include "opto/indexSet.hpp"
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#include "opto/machnode.hpp"
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#include "opto/memnode.hpp"
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#include "opto/movenode.hpp"
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#include "opto/opcodes.hpp"
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#include "opto/rootnode.hpp"
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#include "utilities/align.hpp"
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#ifndef PRODUCT
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void LRG::dump() const {
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  ttyLocker ttyl;
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  tty->print("%d ",num_regs());
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  _mask.dump();
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  if( _msize_valid ) {
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    if( mask_size() == compute_mask_size() ) tty->print(", #%d ",_mask_size);
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    else tty->print(", #!!!_%d_vs_%d ",_mask_size,_mask.Size());
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  } else {
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    tty->print(", #?(%d) ",_mask.Size());
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  }
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  tty->print("EffDeg: ");
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  if( _degree_valid ) tty->print( "%d ", _eff_degree );
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  else tty->print("? ");
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  if( is_multidef() ) {
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    tty->print("MultiDef ");
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    if (_defs != NULL) {
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      tty->print("(");
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      for (int i = 0; i < _defs->length(); i++) {
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        tty->print("N%d ", _defs->at(i)->_idx);
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      }
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      tty->print(") ");
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    }
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  }
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  else if( _def == 0 ) tty->print("Dead ");
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  else tty->print("Def: N%d ",_def->_idx);
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  tty->print("Cost:%4.2g Area:%4.2g Score:%4.2g ",_cost,_area, score());
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  // Flags
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  if( _is_oop ) tty->print("Oop ");
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  if( _is_float ) tty->print("Float ");
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  if( _is_vector ) tty->print("Vector ");
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  if( _was_spilled1 ) tty->print("Spilled ");
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  if( _was_spilled2 ) tty->print("Spilled2 ");
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  if( _direct_conflict ) tty->print("Direct_conflict ");
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  if( _fat_proj ) tty->print("Fat ");
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  if( _was_lo ) tty->print("Lo ");
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  if( _has_copy ) tty->print("Copy ");
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  if( _at_risk ) tty->print("Risk ");
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  if( _must_spill ) tty->print("Must_spill ");
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  if( _is_bound ) tty->print("Bound ");
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  if( _msize_valid ) {
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    if( _degree_valid && lo_degree() ) tty->print("Trivial ");
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  }
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  tty->cr();
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}
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#endif
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// Compute score from cost and area.  Low score is best to spill.
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static double raw_score( double cost, double area ) {
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  return cost - (area*RegisterCostAreaRatio) * 1.52588e-5;
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}
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double LRG::score() const {
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  // Scale _area by RegisterCostAreaRatio/64K then subtract from cost.
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  // Bigger area lowers score, encourages spilling this live range.
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  // Bigger cost raise score, prevents spilling this live range.
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  // (Note: 1/65536 is the magic constant below; I dont trust the C optimizer
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  // to turn a divide by a constant into a multiply by the reciprical).
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  double score = raw_score( _cost, _area);
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  // Account for area.  Basically, LRGs covering large areas are better
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  // to spill because more other LRGs get freed up.
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  if( _area == 0.0 )            // No area?  Then no progress to spill
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    return 1e35;
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  if( _was_spilled2 )           // If spilled once before, we are unlikely
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    return score + 1e30;        // to make progress again.
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  if( _cost >= _area*3.0 )      // Tiny area relative to cost
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    return score + 1e17;        // Probably no progress to spill
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  if( (_cost+_cost) >= _area*3.0 ) // Small area relative to cost
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    return score + 1e10;        // Likely no progress to spill
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  return score;
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}
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#define NUMBUCKS 3
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// Straight out of Tarjan's union-find algorithm
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uint LiveRangeMap::find_compress(uint lrg) {
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  uint cur = lrg;
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  uint next = _uf_map.at(cur);
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  while (next != cur) { // Scan chain of equivalences
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    assert( next < cur, "always union smaller");
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    cur = next; // until find a fixed-point
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    next = _uf_map.at(cur);
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  }
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  // Core of union-find algorithm: update chain of
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  // equivalences to be equal to the root.
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  while (lrg != next) {
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    uint tmp = _uf_map.at(lrg);
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    _uf_map.at_put(lrg, next);
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    lrg = tmp;
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  }
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  return lrg;
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}
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// Reset the Union-Find map to identity
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void LiveRangeMap::reset_uf_map(uint max_lrg_id) {
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  _max_lrg_id= max_lrg_id;
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  // Force the Union-Find mapping to be at least this large
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  _uf_map.at_put_grow(_max_lrg_id, 0);
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  // Initialize it to be the ID mapping.
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  for (uint i = 0; i < _max_lrg_id; ++i) {
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    _uf_map.at_put(i, i);
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  }
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}
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// Make all Nodes map directly to their final live range; no need for
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// the Union-Find mapping after this call.
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void LiveRangeMap::compress_uf_map_for_nodes() {
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  // For all Nodes, compress mapping
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  uint unique = _names.length();
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  for (uint i = 0; i < unique; ++i) {
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    uint lrg = _names.at(i);
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    uint compressed_lrg = find(lrg);
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    if (lrg != compressed_lrg) {
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      _names.at_put(i, compressed_lrg);
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    }
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  }
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}
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// Like Find above, but no path compress, so bad asymptotic behavior
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uint LiveRangeMap::find_const(uint lrg) const {
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  if (!lrg) {
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    return lrg; // Ignore the zero LRG
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  }
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  // Off the end?  This happens during debugging dumps when you got
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  // brand new live ranges but have not told the allocator yet.
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  if (lrg >= _max_lrg_id) {
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    return lrg;
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  }
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  uint next = _uf_map.at(lrg);
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  while (next != lrg) { // Scan chain of equivalences
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    assert(next < lrg, "always union smaller");
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    lrg = next; // until find a fixed-point
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    next = _uf_map.at(lrg);
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  }
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  return next;
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}
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PhaseChaitin::PhaseChaitin(uint unique, PhaseCFG &cfg, Matcher &matcher, bool scheduling_info_generated)
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  : PhaseRegAlloc(unique, cfg, matcher,
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#ifndef PRODUCT
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       print_chaitin_statistics
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#else
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       NULL
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#endif
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       )
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  , _lrg_map(Thread::current()->resource_area(), unique)
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  , _live(0)
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  , _spilled_once(Thread::current()->resource_area())
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  , _spilled_twice(Thread::current()->resource_area())
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  , _lo_degree(0), _lo_stk_degree(0), _hi_degree(0), _simplified(0)
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  , _oldphi(unique)
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  , _scheduling_info_generated(scheduling_info_generated)
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  , _sched_int_pressure(0, INTPRESSURE)
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  , _sched_float_pressure(0, FLOATPRESSURE)
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  , _scratch_int_pressure(0, INTPRESSURE)
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  , _scratch_float_pressure(0, FLOATPRESSURE)
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#ifndef PRODUCT
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  , _trace_spilling(C->directive()->TraceSpillingOption)
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#endif
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{
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  Compile::TracePhase tp("ctorChaitin", &timers[_t_ctorChaitin]);
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  _high_frequency_lrg = MIN2(double(OPTO_LRG_HIGH_FREQ), _cfg.get_outer_loop_frequency());
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  // Build a list of basic blocks, sorted by frequency
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  _blks = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks());
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  // Experiment with sorting strategies to speed compilation
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  double  cutoff = BLOCK_FREQUENCY(1.0); // Cutoff for high frequency bucket
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  Block **buckets[NUMBUCKS];             // Array of buckets
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  uint    buckcnt[NUMBUCKS];             // Array of bucket counters
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  double  buckval[NUMBUCKS];             // Array of bucket value cutoffs
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  for (uint i = 0; i < NUMBUCKS; i++) {
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    buckets[i] = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks());
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    buckcnt[i] = 0;
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    // Bump by three orders of magnitude each time
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    cutoff *= 0.001;
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    buckval[i] = cutoff;
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    for (uint j = 0; j < _cfg.number_of_blocks(); j++) {
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      buckets[i][j] = NULL;
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    }
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  }
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  // Sort blocks into buckets
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  for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
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    for (uint j = 0; j < NUMBUCKS; j++) {
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      if ((j == NUMBUCKS - 1) || (_cfg.get_block(i)->_freq > buckval[j])) {
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        // Assign block to end of list for appropriate bucket
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        buckets[j][buckcnt[j]++] = _cfg.get_block(i);
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        break; // kick out of inner loop
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      }
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    }
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  }
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  // Dump buckets into final block array
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  uint blkcnt = 0;
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  for (uint i = 0; i < NUMBUCKS; i++) {
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    for (uint j = 0; j < buckcnt[i]; j++) {
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      _blks[blkcnt++] = buckets[i][j];
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    }
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  }
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  assert(blkcnt == _cfg.number_of_blocks(), "Block array not totally filled");
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}
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// union 2 sets together.
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void PhaseChaitin::Union( const Node *src_n, const Node *dst_n ) {
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  uint src = _lrg_map.find(src_n);
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  uint dst = _lrg_map.find(dst_n);
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  assert(src, "");
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  assert(dst, "");
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  assert(src < _lrg_map.max_lrg_id(), "oob");
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  assert(dst < _lrg_map.max_lrg_id(), "oob");
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  assert(src < dst, "always union smaller");
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  _lrg_map.uf_map(dst, src);
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}
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void PhaseChaitin::new_lrg(const Node *x, uint lrg) {
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  // Make the Node->LRG mapping
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  _lrg_map.extend(x->_idx,lrg);
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  // Make the Union-Find mapping an identity function
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  _lrg_map.uf_extend(lrg, lrg);
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}
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int PhaseChaitin::clone_projs(Block* b, uint idx, Node* orig, Node* copy, uint& max_lrg_id) {
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  assert(b->find_node(copy) == (idx - 1), "incorrect insert index for copy kill projections");
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  DEBUG_ONLY( Block* borig = _cfg.get_block_for_node(orig); )
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  int found_projs = 0;
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  uint cnt = orig->outcnt();
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  for (uint i = 0; i < cnt; i++) {
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    Node* proj = orig->raw_out(i);
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    if (proj->is_MachProj()) {
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      assert(proj->outcnt() == 0, "only kill projections are expected here");
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      assert(_cfg.get_block_for_node(proj) == borig, "incorrect block for kill projections");
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      found_projs++;
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      // Copy kill projections after the cloned node
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      Node* kills = proj->clone();
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      kills->set_req(0, copy);
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      b->insert_node(kills, idx++);
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      _cfg.map_node_to_block(kills, b);
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      new_lrg(kills, max_lrg_id++);
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    }
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  }
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  return found_projs;
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}
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// Renumber the live ranges to compact them.  Makes the IFG smaller.
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void PhaseChaitin::compact() {
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  Compile::TracePhase tp("chaitinCompact", &timers[_t_chaitinCompact]);
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  // Current the _uf_map contains a series of short chains which are headed
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  // by a self-cycle.  All the chains run from big numbers to little numbers.
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  // The Find() call chases the chains & shortens them for the next Find call.
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  // We are going to change this structure slightly.  Numbers above a moving
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  // wave 'i' are unchanged.  Numbers below 'j' point directly to their
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   312
  // compacted live range with no further chaining.  There are no chains or
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   313
  // cycles below 'i', so the Find call no longer works.
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   314
  uint j=1;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   315
  uint i;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   316
  for (i = 1; i < _lrg_map.max_lrg_id(); i++) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   317
    uint lr = _lrg_map.uf_live_range_id(i);
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   318
    // Ignore unallocated live ranges
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   319
    if (!lr) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   320
      continue;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   321
    }
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   322
    assert(lr <= i, "");
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   323
    _lrg_map.uf_map(i, ( lr == i ) ? j++ : _lrg_map.uf_live_range_id(lr));
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   324
  }
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   325
  // Now change the Node->LR mapping to reflect the compacted names
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   326
  uint unique = _lrg_map.size();
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   327
  for (i = 0; i < unique; i++) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   328
    uint lrg_id = _lrg_map.live_range_id(i);
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   329
    _lrg_map.map(i, _lrg_map.uf_live_range_id(lrg_id));
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   330
  }
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   331
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   332
  // Reset the Union-Find mapping
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   333
  _lrg_map.reset_uf_map(j);
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   334
}
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   335
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   336
void PhaseChaitin::Register_Allocate() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   337
489c9b5090e2 Initial load
duke
parents:
diff changeset
   338
  // Above the OLD FP (and in registers) are the incoming arguments.  Stack
489c9b5090e2 Initial load
duke
parents:
diff changeset
   339
  // slots in this area are called "arg_slots".  Above the NEW FP (and in
489c9b5090e2 Initial load
duke
parents:
diff changeset
   340
  // registers) is the outgoing argument area; above that is the spill/temp
489c9b5090e2 Initial load
duke
parents:
diff changeset
   341
  // area.  These are all "frame_slots".  Arg_slots start at the zero
489c9b5090e2 Initial load
duke
parents:
diff changeset
   342
  // stack_slots and count up to the known arg_size.  Frame_slots start at
489c9b5090e2 Initial load
duke
parents:
diff changeset
   343
  // the stack_slot #arg_size and go up.  After allocation I map stack
489c9b5090e2 Initial load
duke
parents:
diff changeset
   344
  // slots to actual offsets.  Stack-slots in the arg_slot area are biased
489c9b5090e2 Initial load
duke
parents:
diff changeset
   345
  // by the frame_size; stack-slots in the frame_slot area are biased by 0.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   346
489c9b5090e2 Initial load
duke
parents:
diff changeset
   347
  _trip_cnt = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   348
  _alternate = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   349
  _matcher._allocation_started = true;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   350
13520
a1ba7784ef54 7148109: C2 compiler consumes too much heap resources
kvn
parents: 13491
diff changeset
   351
  ResourceArea split_arena;     // Arena for Split local resources
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   352
  ResourceArea live_arena;      // Arena for liveness & IFG info
489c9b5090e2 Initial load
duke
parents:
diff changeset
   353
  ResourceMark rm(&live_arena);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   354
489c9b5090e2 Initial load
duke
parents:
diff changeset
   355
  // Need live-ness for the IFG; need the IFG for coalescing.  If the
489c9b5090e2 Initial load
duke
parents:
diff changeset
   356
  // liveness is JUST for coalescing, then I can get some mileage by renaming
489c9b5090e2 Initial load
duke
parents:
diff changeset
   357
  // all copy-related live ranges low and then using the max copy-related
489c9b5090e2 Initial load
duke
parents:
diff changeset
   358
  // live range as a cut-off for LIVE and the IFG.  In other words, I can
489c9b5090e2 Initial load
duke
parents:
diff changeset
   359
  // build a subset of LIVE and IFG just for copies.
33065
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   360
  PhaseLive live(_cfg, _lrg_map.names(), &live_arena, false);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   361
489c9b5090e2 Initial load
duke
parents:
diff changeset
   362
  // Need IFG for coalescing and coloring
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   363
  PhaseIFG ifg(&live_arena);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   364
  _ifg = &ifg;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   365
489c9b5090e2 Initial load
duke
parents:
diff changeset
   366
  // Come out of SSA world to the Named world.  Assign (virtual) registers to
489c9b5090e2 Initial load
duke
parents:
diff changeset
   367
  // Nodes.  Use the same register for all inputs and the output of PhiNodes
489c9b5090e2 Initial load
duke
parents:
diff changeset
   368
  // - effectively ending SSA form.  This requires either coalescing live
489c9b5090e2 Initial load
duke
parents:
diff changeset
   369
  // ranges or inserting copies.  For the moment, we insert "virtual copies"
489c9b5090e2 Initial load
duke
parents:
diff changeset
   370
  // - we pretend there is a copy prior to each Phi in predecessor blocks.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   371
  // We will attempt to coalesce such "virtual copies" before we manifest
489c9b5090e2 Initial load
duke
parents:
diff changeset
   372
  // them for real.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   373
  de_ssa();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   374
2030
39d55e4534b4 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents: 2014
diff changeset
   375
#ifdef ASSERT
39d55e4534b4 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents: 2014
diff changeset
   376
  // Veify the graph before RA.
39d55e4534b4 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents: 2014
diff changeset
   377
  verify(&live_arena);
39d55e4534b4 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents: 2014
diff changeset
   378
#endif
39d55e4534b4 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents: 2014
diff changeset
   379
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   380
  {
26913
9ad70cd32368 8058968: Compiler time traces should be improved
shade
parents: 25930
diff changeset
   381
    Compile::TracePhase tp("computeLive", &timers[_t_computeLive]);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   382
    _live = NULL;                 // Mark live as being not available
489c9b5090e2 Initial load
duke
parents:
diff changeset
   383
    rm.reset_to_mark();           // Reclaim working storage
489c9b5090e2 Initial load
duke
parents:
diff changeset
   384
    IndexSet::reset_memory(C, &live_arena);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   385
    ifg.init(_lrg_map.max_lrg_id()); // Empty IFG
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   386
    gather_lrg_masks( false );    // Collect LRG masks
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   387
    live.compute(_lrg_map.max_lrg_id()); // Compute liveness
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   388
    _live = &live;                // Mark LIVE as being available
489c9b5090e2 Initial load
duke
parents:
diff changeset
   389
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   390
489c9b5090e2 Initial load
duke
parents:
diff changeset
   391
  // Base pointers are currently "used" by instructions which define new
489c9b5090e2 Initial load
duke
parents:
diff changeset
   392
  // derived pointers.  This makes base pointers live up to the where the
489c9b5090e2 Initial load
duke
parents:
diff changeset
   393
  // derived pointer is made, but not beyond.  Really, they need to be live
489c9b5090e2 Initial load
duke
parents:
diff changeset
   394
  // across any GC point where the derived value is live.  So this code looks
489c9b5090e2 Initial load
duke
parents:
diff changeset
   395
  // at all the GC points, and "stretches" the live range of any base pointer
489c9b5090e2 Initial load
duke
parents:
diff changeset
   396
  // to the GC point.
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   397
  if (stretch_base_pointer_live_ranges(&live_arena)) {
26913
9ad70cd32368 8058968: Compiler time traces should be improved
shade
parents: 25930
diff changeset
   398
    Compile::TracePhase tp("computeLive (sbplr)", &timers[_t_computeLive]);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   399
    // Since some live range stretched, I need to recompute live
489c9b5090e2 Initial load
duke
parents:
diff changeset
   400
    _live = NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   401
    rm.reset_to_mark();         // Reclaim working storage
489c9b5090e2 Initial load
duke
parents:
diff changeset
   402
    IndexSet::reset_memory(C, &live_arena);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   403
    ifg.init(_lrg_map.max_lrg_id());
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   404
    gather_lrg_masks(false);
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   405
    live.compute(_lrg_map.max_lrg_id());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   406
    _live = &live;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   407
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   408
  // Create the interference graph using virtual copies
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   409
  build_ifg_virtual();  // Include stack slots this time
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   410
26913
9ad70cd32368 8058968: Compiler time traces should be improved
shade
parents: 25930
diff changeset
   411
  // The IFG is/was triangular.  I am 'squaring it up' so Union can run
9ad70cd32368 8058968: Compiler time traces should be improved
shade
parents: 25930
diff changeset
   412
  // faster.  Union requires a 'for all' operation which is slow on the
9ad70cd32368 8058968: Compiler time traces should be improved
shade
parents: 25930
diff changeset
   413
  // triangular adjacency matrix (quick reminder: the IFG is 'sparse' -
9ad70cd32368 8058968: Compiler time traces should be improved
shade
parents: 25930
diff changeset
   414
  // meaning I can visit all the Nodes neighbors less than a Node in time
9ad70cd32368 8058968: Compiler time traces should be improved
shade
parents: 25930
diff changeset
   415
  // O(# of neighbors), but I have to visit all the Nodes greater than a
9ad70cd32368 8058968: Compiler time traces should be improved
shade
parents: 25930
diff changeset
   416
  // given Node and search them for an instance, i.e., time O(#MaxLRG)).
9ad70cd32368 8058968: Compiler time traces should be improved
shade
parents: 25930
diff changeset
   417
  _ifg->SquareUp();
9ad70cd32368 8058968: Compiler time traces should be improved
shade
parents: 25930
diff changeset
   418
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   419
  // Aggressive (but pessimistic) copy coalescing.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   420
  // This pass works on virtual copies.  Any virtual copies which are not
489c9b5090e2 Initial load
duke
parents:
diff changeset
   421
  // coalesced get manifested as actual copies
489c9b5090e2 Initial load
duke
parents:
diff changeset
   422
  {
26913
9ad70cd32368 8058968: Compiler time traces should be improved
shade
parents: 25930
diff changeset
   423
    Compile::TracePhase tp("chaitinCoalesce1", &timers[_t_chaitinCoalesce1]);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   424
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   425
    PhaseAggressiveCoalesce coalesce(*this);
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   426
    coalesce.coalesce_driver();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   427
    // Insert un-coalesced copies.  Visit all Phis.  Where inputs to a Phi do
489c9b5090e2 Initial load
duke
parents:
diff changeset
   428
    // not match the Phi itself, insert a copy.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   429
    coalesce.insert_copies(_matcher);
18099
45973b036c3e 8014959: assert(Compile::current()->live_nodes() < (uint)MaxNodeLimit) failed: Live Node limit exceeded limit
drchase
parents: 17013
diff changeset
   430
    if (C->failing()) {
45973b036c3e 8014959: assert(Compile::current()->live_nodes() < (uint)MaxNodeLimit) failed: Live Node limit exceeded limit
drchase
parents: 17013
diff changeset
   431
      return;
45973b036c3e 8014959: assert(Compile::current()->live_nodes() < (uint)MaxNodeLimit) failed: Live Node limit exceeded limit
drchase
parents: 17013
diff changeset
   432
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   433
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   434
489c9b5090e2 Initial load
duke
parents:
diff changeset
   435
  // After aggressive coalesce, attempt a first cut at coloring.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   436
  // To color, we need the IFG and for that we need LIVE.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   437
  {
26913
9ad70cd32368 8058968: Compiler time traces should be improved
shade
parents: 25930
diff changeset
   438
    Compile::TracePhase tp("computeLive", &timers[_t_computeLive]);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   439
    _live = NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   440
    rm.reset_to_mark();           // Reclaim working storage
489c9b5090e2 Initial load
duke
parents:
diff changeset
   441
    IndexSet::reset_memory(C, &live_arena);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   442
    ifg.init(_lrg_map.max_lrg_id());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   443
    gather_lrg_masks( true );
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   444
    live.compute(_lrg_map.max_lrg_id());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   445
    _live = &live;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   446
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   447
489c9b5090e2 Initial load
duke
parents:
diff changeset
   448
  // Build physical interference graph
489c9b5090e2 Initial load
duke
parents:
diff changeset
   449
  uint must_spill = 0;
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   450
  must_spill = build_ifg_physical(&live_arena);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   451
  // If we have a guaranteed spill, might as well spill now
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   452
  if (must_spill) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   453
    if(!_lrg_map.max_lrg_id()) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   454
      return;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   455
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   456
    // Bail out if unique gets too large (ie - unique > MaxNodeLimit)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   457
    C->check_node_count(10*must_spill, "out of nodes before split");
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   458
    if (C->failing()) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   459
      return;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   460
    }
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   461
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   462
    uint new_max_lrg_id = Split(_lrg_map.max_lrg_id(), &split_arena);  // Split spilling LRG everywhere
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   463
    _lrg_map.set_max_lrg_id(new_max_lrg_id);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   464
    // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   465
    // or we failed to split
489c9b5090e2 Initial load
duke
parents:
diff changeset
   466
    C->check_node_count(2*NodeLimitFudgeFactor, "out of nodes after physical split");
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   467
    if (C->failing()) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   468
      return;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   469
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   470
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   471
    NOT_PRODUCT(C->verify_graph_edges();)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   472
489c9b5090e2 Initial load
duke
parents:
diff changeset
   473
    compact();                  // Compact LRGs; return new lower max lrg
489c9b5090e2 Initial load
duke
parents:
diff changeset
   474
489c9b5090e2 Initial load
duke
parents:
diff changeset
   475
    {
26913
9ad70cd32368 8058968: Compiler time traces should be improved
shade
parents: 25930
diff changeset
   476
      Compile::TracePhase tp("computeLive", &timers[_t_computeLive]);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   477
      _live = NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   478
      rm.reset_to_mark();         // Reclaim working storage
489c9b5090e2 Initial load
duke
parents:
diff changeset
   479
      IndexSet::reset_memory(C, &live_arena);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   480
      ifg.init(_lrg_map.max_lrg_id()); // Build a new interference graph
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   481
      gather_lrg_masks( true );   // Collect intersect mask
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   482
      live.compute(_lrg_map.max_lrg_id()); // Compute LIVE
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   483
      _live = &live;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   484
    }
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   485
    build_ifg_physical(&live_arena);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   486
    _ifg->SquareUp();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   487
    _ifg->Compute_Effective_Degree();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   488
    // Only do conservative coalescing if requested
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   489
    if (OptoCoalesce) {
26913
9ad70cd32368 8058968: Compiler time traces should be improved
shade
parents: 25930
diff changeset
   490
      Compile::TracePhase tp("chaitinCoalesce2", &timers[_t_chaitinCoalesce2]);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   491
      // Conservative (and pessimistic) copy coalescing of those spills
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   492
      PhaseConservativeCoalesce coalesce(*this);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   493
      // If max live ranges greater than cutoff, don't color the stack.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   494
      // This cutoff can be larger than below since it is only done once.
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   495
      coalesce.coalesce_driver();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   496
    }
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   497
    _lrg_map.compress_uf_map_for_nodes();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   498
489c9b5090e2 Initial load
duke
parents:
diff changeset
   499
#ifdef ASSERT
2030
39d55e4534b4 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents: 2014
diff changeset
   500
    verify(&live_arena, true);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   501
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   502
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   503
    ifg.SquareUp();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   504
    ifg.Compute_Effective_Degree();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   505
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   506
    set_was_low();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   507
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   508
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   509
489c9b5090e2 Initial load
duke
parents:
diff changeset
   510
  // Prepare for Simplify & Select
489c9b5090e2 Initial load
duke
parents:
diff changeset
   511
  cache_lrg_info();           // Count degree of LRGs
489c9b5090e2 Initial load
duke
parents:
diff changeset
   512
489c9b5090e2 Initial load
duke
parents:
diff changeset
   513
  // Simplify the InterFerence Graph by removing LRGs of low degree.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   514
  // LRGs of low degree are trivially colorable.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   515
  Simplify();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   516
489c9b5090e2 Initial load
duke
parents:
diff changeset
   517
  // Select colors by re-inserting LRGs back into the IFG in reverse order.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   518
  // Return whether or not something spills.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   519
  uint spills = Select( );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   520
489c9b5090e2 Initial load
duke
parents:
diff changeset
   521
  // If we spill, split and recycle the entire thing
489c9b5090e2 Initial load
duke
parents:
diff changeset
   522
  while( spills ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   523
    if( _trip_cnt++ > 24 ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   524
      DEBUG_ONLY( dump_for_spill_split_recycle(); )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   525
      if( _trip_cnt > 27 ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   526
        C->record_method_not_compilable("failed spill-split-recycle sanity check");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   527
        return;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   528
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   529
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   530
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   531
    if (!_lrg_map.max_lrg_id()) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   532
      return;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   533
    }
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   534
    uint new_max_lrg_id = Split(_lrg_map.max_lrg_id(), &split_arena);  // Split spilling LRG everywhere
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   535
    _lrg_map.set_max_lrg_id(new_max_lrg_id);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   536
    // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor)
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   537
    C->check_node_count(2 * NodeLimitFudgeFactor, "out of nodes after split");
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   538
    if (C->failing()) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   539
      return;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   540
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   541
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   542
    compact(); // Compact LRGs; return new lower max lrg
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   543
489c9b5090e2 Initial load
duke
parents:
diff changeset
   544
    // Nuke the live-ness and interference graph and LiveRanGe info
489c9b5090e2 Initial load
duke
parents:
diff changeset
   545
    {
26913
9ad70cd32368 8058968: Compiler time traces should be improved
shade
parents: 25930
diff changeset
   546
      Compile::TracePhase tp("computeLive", &timers[_t_computeLive]);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   547
      _live = NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   548
      rm.reset_to_mark();         // Reclaim working storage
489c9b5090e2 Initial load
duke
parents:
diff changeset
   549
      IndexSet::reset_memory(C, &live_arena);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   550
      ifg.init(_lrg_map.max_lrg_id());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   551
489c9b5090e2 Initial load
duke
parents:
diff changeset
   552
      // Create LiveRanGe array.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   553
      // Intersect register masks for all USEs and DEFs
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   554
      gather_lrg_masks(true);
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   555
      live.compute(_lrg_map.max_lrg_id());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   556
      _live = &live;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   557
    }
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   558
    must_spill = build_ifg_physical(&live_arena);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   559
    _ifg->SquareUp();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   560
    _ifg->Compute_Effective_Degree();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   561
489c9b5090e2 Initial load
duke
parents:
diff changeset
   562
    // Only do conservative coalescing if requested
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   563
    if (OptoCoalesce) {
26913
9ad70cd32368 8058968: Compiler time traces should be improved
shade
parents: 25930
diff changeset
   564
      Compile::TracePhase tp("chaitinCoalesce3", &timers[_t_chaitinCoalesce3]);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   565
      // Conservative (and pessimistic) copy coalescing
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   566
      PhaseConservativeCoalesce coalesce(*this);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   567
      // Check for few live ranges determines how aggressive coalesce is.
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   568
      coalesce.coalesce_driver();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   569
    }
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   570
    _lrg_map.compress_uf_map_for_nodes();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   571
#ifdef ASSERT
2030
39d55e4534b4 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents: 2014
diff changeset
   572
    verify(&live_arena, true);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   573
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   574
    cache_lrg_info();           // Count degree of LRGs
489c9b5090e2 Initial load
duke
parents:
diff changeset
   575
489c9b5090e2 Initial load
duke
parents:
diff changeset
   576
    // Simplify the InterFerence Graph by removing LRGs of low degree.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   577
    // LRGs of low degree are trivially colorable.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   578
    Simplify();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   579
489c9b5090e2 Initial load
duke
parents:
diff changeset
   580
    // Select colors by re-inserting LRGs back into the IFG in reverse order.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   581
    // Return whether or not something spills.
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   582
    spills = Select();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   583
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   584
489c9b5090e2 Initial load
duke
parents:
diff changeset
   585
  // Count number of Simplify-Select trips per coloring success.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   586
  _allocator_attempts += _trip_cnt + 1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   587
  _allocator_successes += 1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   588
489c9b5090e2 Initial load
duke
parents:
diff changeset
   589
  // Peephole remove copies
489c9b5090e2 Initial load
duke
parents:
diff changeset
   590
  post_allocate_copy_removal();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   591
28648
102bdbb42723 8068881: SIGBUS in C2 compiled method weblogic.wsee.jaxws.framework.jaxrpc.EnvironmentFactory$SimulatedWsdlDefinitions.<init>
iveresov
parents: 26913
diff changeset
   592
  // Merge multidefs if multiple defs representing the same value are used in a single block.
102bdbb42723 8068881: SIGBUS in C2 compiled method weblogic.wsee.jaxws.framework.jaxrpc.EnvironmentFactory$SimulatedWsdlDefinitions.<init>
iveresov
parents: 26913
diff changeset
   593
  merge_multidefs();
102bdbb42723 8068881: SIGBUS in C2 compiled method weblogic.wsee.jaxws.framework.jaxrpc.EnvironmentFactory$SimulatedWsdlDefinitions.<init>
iveresov
parents: 26913
diff changeset
   594
2030
39d55e4534b4 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents: 2014
diff changeset
   595
#ifdef ASSERT
39d55e4534b4 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents: 2014
diff changeset
   596
  // Veify the graph after RA.
39d55e4534b4 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents: 2014
diff changeset
   597
  verify(&live_arena);
39d55e4534b4 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents: 2014
diff changeset
   598
#endif
39d55e4534b4 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents: 2014
diff changeset
   599
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   600
  // max_reg is past the largest *register* used.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   601
  // Convert that to a frame_slot number.
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   602
  if (_max_reg <= _matcher._new_SP) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   603
    _framesize = C->out_preserve_stack_slots();
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   604
  }
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   605
  else {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   606
    _framesize = _max_reg -_matcher._new_SP;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   607
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   608
  assert((int)(_matcher._new_SP+_framesize) >= (int)_matcher._out_arg_limit, "framesize must be large enough");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   609
489c9b5090e2 Initial load
duke
parents:
diff changeset
   610
  // This frame must preserve the required fp alignment
46620
750c6edff33b 8178500: Replace usages of round_to and round_down with align_up and align_down
stefank
parents: 46378
diff changeset
   611
  _framesize = align_up(_framesize, Matcher::stack_alignment_in_slots());
29580
a67a581cfe11 8073315: Enable gcc -Wtype-limits and fix upcoming issues.
goetz
parents: 29474
diff changeset
   612
  assert(_framesize <= 1000000, "sanity check");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   613
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   614
  _total_framesize += _framesize;
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   615
  if ((int)_framesize > _max_framesize) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   616
    _max_framesize = _framesize;
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   617
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   618
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   619
489c9b5090e2 Initial load
duke
parents:
diff changeset
   620
  // Convert CISC spills
489c9b5090e2 Initial load
duke
parents:
diff changeset
   621
  fixup_spills();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   622
489c9b5090e2 Initial load
duke
parents:
diff changeset
   623
  // Log regalloc results
489c9b5090e2 Initial load
duke
parents:
diff changeset
   624
  CompileLog* log = Compile::current()->log();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   625
  if (log != NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   626
    log->elem("regalloc attempts='%d' success='%d'", _trip_cnt, !C->failing());
489c9b5090e2 Initial load
duke
parents:
diff changeset
   627
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   628
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   629
  if (C->failing()) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   630
    return;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   631
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   632
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   633
  NOT_PRODUCT(C->verify_graph_edges();)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   634
489c9b5090e2 Initial load
duke
parents:
diff changeset
   635
  // Move important info out of the live_arena to longer lasting storage.
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   636
  alloc_node_regs(_lrg_map.size());
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   637
  for (uint i=0; i < _lrg_map.size(); i++) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   638
    if (_lrg_map.live_range_id(i)) { // Live range associated with Node?
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   639
      LRG &lrg = lrgs(_lrg_map.live_range_id(i));
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   640
      if (!lrg.alive()) {
13491
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
   641
        set_bad(i);
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   642
      } else if (lrg.num_regs() == 1) {
13491
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
   643
        set1(i, lrg.reg());
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
   644
      } else {                  // Must be a register-set
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
   645
        if (!lrg._fat_proj) {   // Must be aligned adjacent register set
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   646
          // Live ranges record the highest register in their mask.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   647
          // We want the low register for the AD file writer's convenience.
13491
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
   648
          OptoReg::Name hi = lrg.reg(); // Get hi register
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
   649
          OptoReg::Name lo = OptoReg::add(hi, (1-lrg.num_regs())); // Find lo
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
   650
          // We have to use pair [lo,lo+1] even for wide vectors because
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
   651
          // the rest of code generation works only with pairs. It is safe
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
   652
          // since for registers encoding only 'lo' is used.
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
   653
          // Second reg from pair is used in ScheduleAndBundle on SPARC where
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
   654
          // vector max size is 8 which corresponds to registers pair.
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
   655
          // It is also used in BuildOopMaps but oop operations are not
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
   656
          // vectorized.
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
   657
          set2(i, lo);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   658
        } else {                // Misaligned; extract 2 bits
489c9b5090e2 Initial load
duke
parents:
diff changeset
   659
          OptoReg::Name hi = lrg.reg(); // Get hi register
489c9b5090e2 Initial load
duke
parents:
diff changeset
   660
          lrg.Remove(hi);       // Yank from mask
489c9b5090e2 Initial load
duke
parents:
diff changeset
   661
          int lo = lrg.mask().find_first_elem(); // Find lo
13491
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
   662
          set_pair(i, hi, lo);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   663
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   664
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   665
      if( lrg._is_oop ) _node_oops.set(i);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   666
    } else {
13491
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
   667
      set_bad(i);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   668
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   669
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   670
489c9b5090e2 Initial load
duke
parents:
diff changeset
   671
  // Done!
489c9b5090e2 Initial load
duke
parents:
diff changeset
   672
  _live = NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   673
  _ifg = NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   674
  C->set_indexSet_arena(NULL);  // ResourceArea is at end of scope
489c9b5090e2 Initial load
duke
parents:
diff changeset
   675
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   676
489c9b5090e2 Initial load
duke
parents:
diff changeset
   677
void PhaseChaitin::de_ssa() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   678
  // Set initial Names for all Nodes.  Most Nodes get the virtual register
489c9b5090e2 Initial load
duke
parents:
diff changeset
   679
  // number.  A few get the ZERO live range number.  These do not
489c9b5090e2 Initial load
duke
parents:
diff changeset
   680
  // get allocated, but instead rely on correct scheduling to ensure that
489c9b5090e2 Initial load
duke
parents:
diff changeset
   681
  // only one instance is simultaneously live at a time.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   682
  uint lr_counter = 1;
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   683
  for( uint i = 0; i < _cfg.number_of_blocks(); i++ ) {
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   684
    Block* block = _cfg.get_block(i);
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   685
    uint cnt = block->number_of_nodes();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   686
489c9b5090e2 Initial load
duke
parents:
diff changeset
   687
    // Handle all the normal Nodes in the block
489c9b5090e2 Initial load
duke
parents:
diff changeset
   688
    for( uint j = 0; j < cnt; j++ ) {
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   689
      Node *n = block->get_node(j);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   690
      // Pre-color to the zero live range, or pick virtual register
489c9b5090e2 Initial load
duke
parents:
diff changeset
   691
      const RegMask &rm = n->out_RegMask();
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   692
      _lrg_map.map(n->_idx, rm.is_NotEmpty() ? lr_counter++ : 0);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   693
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   694
  }
20007
b67e71448544 8024646: Remove LRG_List container, replace it with GrowableArray
adlertz
parents: 19717
diff changeset
   695
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   696
  // Reset the Union-Find mapping to be identity
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   697
  _lrg_map.reset_uf_map(lr_counter);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   698
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   699
33065
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   700
void PhaseChaitin::mark_ssa() {
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   701
  // Use ssa names to populate the live range maps or if no mask
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   702
  // is available, use the 0 entry.
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   703
  uint max_idx = 0;
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   704
  for ( uint i = 0; i < _cfg.number_of_blocks(); i++ ) {
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   705
    Block* block = _cfg.get_block(i);
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   706
    uint cnt = block->number_of_nodes();
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   707
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   708
    // Handle all the normal Nodes in the block
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   709
    for ( uint j = 0; j < cnt; j++ ) {
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   710
      Node *n = block->get_node(j);
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   711
      // Pre-color to the zero live range, or pick virtual register
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   712
      const RegMask &rm = n->out_RegMask();
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   713
      _lrg_map.map(n->_idx, rm.is_NotEmpty() ? n->_idx : 0);
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   714
      max_idx = (n->_idx > max_idx) ? n->_idx : max_idx;
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   715
    }
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   716
  }
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   717
  _lrg_map.set_max_lrg_id(max_idx+1);
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   718
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   719
  // Reset the Union-Find mapping to be identity
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   720
  _lrg_map.reset_uf_map(max_idx+1);
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   721
}
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   722
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   723
489c9b5090e2 Initial load
duke
parents:
diff changeset
   724
// Gather LiveRanGe information, including register masks.  Modification of
489c9b5090e2 Initial load
duke
parents:
diff changeset
   725
// cisc spillable in_RegMasks should not be done before AggressiveCoalesce.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   726
void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   727
489c9b5090e2 Initial load
duke
parents:
diff changeset
   728
  // Nail down the frame pointer live range
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   729
  uint fp_lrg = _lrg_map.live_range_id(_cfg.get_root_node()->in(1)->in(TypeFunc::FramePtr));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   730
  lrgs(fp_lrg)._cost += 1e12;   // Cost is infinite
489c9b5090e2 Initial load
duke
parents:
diff changeset
   731
489c9b5090e2 Initial load
duke
parents:
diff changeset
   732
  // For all blocks
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   733
  for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   734
    Block* block = _cfg.get_block(i);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   735
489c9b5090e2 Initial load
duke
parents:
diff changeset
   736
    // For all instructions
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   737
    for (uint j = 1; j < block->number_of_nodes(); j++) {
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   738
      Node* n = block->get_node(j);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   739
      uint input_edge_start =1; // Skip control most nodes
33065
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   740
      bool is_machine_node = false;
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   741
      if (n->is_Mach()) {
33065
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   742
        is_machine_node = true;
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   743
        input_edge_start = n->as_Mach()->oper_input_base();
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   744
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   745
      uint idx = n->is_Copy();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   746
489c9b5090e2 Initial load
duke
parents:
diff changeset
   747
      // Get virtual register number, same as LiveRanGe index
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   748
      uint vreg = _lrg_map.live_range_id(n);
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   749
      LRG& lrg = lrgs(vreg);
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   750
      if (vreg) {              // No vreg means un-allocable (e.g. memory)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   751
489c9b5090e2 Initial load
duke
parents:
diff changeset
   752
        // Collect has-copy bit
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   753
        if (idx) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   754
          lrg._has_copy = 1;
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   755
          uint clidx = _lrg_map.live_range_id(n->in(idx));
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   756
          LRG& copy_src = lrgs(clidx);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   757
          copy_src._has_copy = 1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   758
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   759
489c9b5090e2 Initial load
duke
parents:
diff changeset
   760
        // Check for float-vs-int live range (used in register-pressure
489c9b5090e2 Initial load
duke
parents:
diff changeset
   761
        // calculations)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   762
        const Type *n_type = n->bottom_type();
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   763
        if (n_type->is_floatingpoint()) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   764
          lrg._is_float = 1;
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   765
        }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   766
489c9b5090e2 Initial load
duke
parents:
diff changeset
   767
        // Check for twice prior spilling.  Once prior spilling might have
489c9b5090e2 Initial load
duke
parents:
diff changeset
   768
        // spilled 'soft', 2nd prior spill should have spilled 'hard' and
489c9b5090e2 Initial load
duke
parents:
diff changeset
   769
        // further spilling is unlikely to make progress.
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   770
        if (_spilled_once.test(n->_idx)) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   771
          lrg._was_spilled1 = 1;
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   772
          if (_spilled_twice.test(n->_idx)) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   773
            lrg._was_spilled2 = 1;
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   774
          }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   775
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   776
489c9b5090e2 Initial load
duke
parents:
diff changeset
   777
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   778
        if (trace_spilling() && lrg._def != NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   779
          // collect defs for MultiDef printing
489c9b5090e2 Initial load
duke
parents:
diff changeset
   780
          if (lrg._defs == NULL) {
6180
53c1bf468c81 6973963: SEGV in ciBlock::start_bci() with EA
kvn
parents: 5547
diff changeset
   781
            lrg._defs = new (_ifg->_arena) GrowableArray<Node*>(_ifg->_arena, 2, 0, NULL);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   782
            lrg._defs->append(lrg._def);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   783
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   784
          lrg._defs->append(n);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   785
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   786
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   787
489c9b5090e2 Initial load
duke
parents:
diff changeset
   788
        // Check for a single def LRG; these can spill nicely
489c9b5090e2 Initial load
duke
parents:
diff changeset
   789
        // via rematerialization.  Flag as NULL for no def found
489c9b5090e2 Initial load
duke
parents:
diff changeset
   790
        // yet, or 'n' for single def or -1 for many defs.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   791
        lrg._def = lrg._def ? NodeSentinel : n;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   792
489c9b5090e2 Initial load
duke
parents:
diff changeset
   793
        // Limit result register mask to acceptable registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
   794
        const RegMask &rm = n->out_RegMask();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   795
        lrg.AND( rm );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   796
46378
4ccca1fdf627 8160748: Inconsistent types for ideal_reg
kbarrett
parents: 37248
diff changeset
   797
        uint ireg = n->ideal_reg();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   798
        assert( !n->bottom_type()->isa_oop_ptr() || ireg == Op_RegP,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   799
                "oops must be in Op_RegP's" );
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   800
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   801
        // Check for vector live range (only if vector register is used).
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   802
        // On SPARC vector uses RegD which could be misaligned so it is not
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   803
        // processes as vector in RA.
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   804
        if (RegMask::is_vector(ireg))
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   805
          lrg._is_vector = 1;
22853
308672304981 8028767: PPC64: (part 121): smaller shared changes needed to build C2
goetz
parents: 20007
diff changeset
   806
        assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD || ireg == Op_RegL,
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   807
               "vector must be in vector registers");
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   808
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   809
        // Check for bound register masks
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   810
        const RegMask &lrgmask = lrg.mask();
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   811
        if (lrgmask.is_bound(ireg)) {
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   812
          lrg._is_bound = 1;
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   813
        }
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   814
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   815
        // Check for maximum frequency value
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   816
        if (lrg._maxfreq < block->_freq) {
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   817
          lrg._maxfreq = block->_freq;
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   818
        }
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   819
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   820
        // Check for oop-iness, or long/double
489c9b5090e2 Initial load
duke
parents:
diff changeset
   821
        // Check for multi-kill projection
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   822
        switch (ireg) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   823
        case MachProjNode::fat_proj:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   824
          // Fat projections have size equal to number of registers killed
489c9b5090e2 Initial load
duke
parents:
diff changeset
   825
          lrg.set_num_regs(rm.Size());
489c9b5090e2 Initial load
duke
parents:
diff changeset
   826
          lrg.set_reg_pressure(lrg.num_regs());
489c9b5090e2 Initial load
duke
parents:
diff changeset
   827
          lrg._fat_proj = 1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   828
          lrg._is_bound = 1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   829
          break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   830
        case Op_RegP:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   831
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
   832
          lrg.set_num_regs(2);  // Size is 2 stack words
489c9b5090e2 Initial load
duke
parents:
diff changeset
   833
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   834
          lrg.set_num_regs(1);  // Size is 1 stack word
489c9b5090e2 Initial load
duke
parents:
diff changeset
   835
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   836
          // Register pressure is tracked relative to the maximum values
489c9b5090e2 Initial load
duke
parents:
diff changeset
   837
          // suggested for that platform, INTPRESSURE and FLOATPRESSURE,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   838
          // and relative to other types which compete for the same regs.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   839
          //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   840
          // The following table contains suggested values based on the
489c9b5090e2 Initial load
duke
parents:
diff changeset
   841
          // architectures as defined in each .ad file.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   842
          // INTPRESSURE and FLOATPRESSURE may be tuned differently for
489c9b5090e2 Initial load
duke
parents:
diff changeset
   843
          // compile-speed or performance.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   844
          // Note1:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   845
          // SPARC and SPARCV9 reg_pressures are at 2 instead of 1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   846
          // since .ad registers are defined as high and low halves.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   847
          // These reg_pressure values remain compatible with the code
489c9b5090e2 Initial load
duke
parents:
diff changeset
   848
          // in is_high_pressure() which relates get_invalid_mask_size(),
489c9b5090e2 Initial load
duke
parents:
diff changeset
   849
          // Block::_reg_pressure and INTPRESSURE, FLOATPRESSURE.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   850
          // Note2:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   851
          // SPARC -d32 has 24 registers available for integral values,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   852
          // but only 10 of these are safe for 64-bit longs.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   853
          // Using set_reg_pressure(2) for both int and long means
489c9b5090e2 Initial load
duke
parents:
diff changeset
   854
          // the allocator will believe it can fit 26 longs into
489c9b5090e2 Initial load
duke
parents:
diff changeset
   855
          // registers.  Using 2 for longs and 1 for ints means the
489c9b5090e2 Initial load
duke
parents:
diff changeset
   856
          // allocator will attempt to put 52 integers into registers.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   857
          // The settings below limit this problem to methods with
489c9b5090e2 Initial load
duke
parents:
diff changeset
   858
          // many long values which are being run on 32-bit SPARC.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   859
          //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   860
          // ------------------- reg_pressure --------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   861
          // Each entry is reg_pressure_per_value,number_of_regs
489c9b5090e2 Initial load
duke
parents:
diff changeset
   862
          //         RegL  RegI  RegFlags   RegF RegD    INTPRESSURE  FLOATPRESSURE
489c9b5090e2 Initial load
duke
parents:
diff changeset
   863
          // IA32     2     1     1          1    1          6           6
489c9b5090e2 Initial load
duke
parents:
diff changeset
   864
          // IA64     1     1     1          1    1         50          41
489c9b5090e2 Initial load
duke
parents:
diff changeset
   865
          // SPARC    2     2     2          2    2         48 (24)     52 (26)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   866
          // SPARCV9  2     2     2          2    2         48 (24)     52 (26)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   867
          // AMD64    1     1     1          1    1         14          15
489c9b5090e2 Initial load
duke
parents:
diff changeset
   868
          // -----------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   869
#if defined(SPARC)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   870
          lrg.set_reg_pressure(2);  // use for v9 as well
489c9b5090e2 Initial load
duke
parents:
diff changeset
   871
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   872
          lrg.set_reg_pressure(1);  // normally one value per register
489c9b5090e2 Initial load
duke
parents:
diff changeset
   873
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   874
          if( n_type->isa_oop_ptr() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   875
            lrg._is_oop = 1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   876
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   877
          break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   878
        case Op_RegL:           // Check for long or double
489c9b5090e2 Initial load
duke
parents:
diff changeset
   879
        case Op_RegD:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   880
          lrg.set_num_regs(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   881
          // Define platform specific register pressure
29474
81a5c5330d08 8072383: resolve conflicts between open and closed ports
dlong
parents: 28648
diff changeset
   882
#if defined(SPARC) || defined(ARM32)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   883
          lrg.set_reg_pressure(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   884
#elif defined(IA32)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   885
          if( ireg == Op_RegL ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   886
            lrg.set_reg_pressure(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   887
          } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   888
            lrg.set_reg_pressure(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   889
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   890
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   891
          lrg.set_reg_pressure(1);  // normally one value per register
489c9b5090e2 Initial load
duke
parents:
diff changeset
   892
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   893
          // If this def of a double forces a mis-aligned double,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   894
          // flag as '_fat_proj' - really flag as allowing misalignment
489c9b5090e2 Initial load
duke
parents:
diff changeset
   895
          // AND changes how we count interferences.  A mis-aligned
489c9b5090e2 Initial load
duke
parents:
diff changeset
   896
          // double can interfere with TWO aligned pairs, or effectively
489c9b5090e2 Initial load
duke
parents:
diff changeset
   897
          // FOUR registers!
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   898
          if (rm.is_misaligned_pair()) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   899
            lrg._fat_proj = 1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   900
            lrg._is_bound = 1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   901
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   902
          break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   903
        case Op_RegF:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   904
        case Op_RegI:
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 1
diff changeset
   905
        case Op_RegN:
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   906
        case Op_RegFlags:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   907
        case 0:                 // not an ideal register
489c9b5090e2 Initial load
duke
parents:
diff changeset
   908
          lrg.set_num_regs(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   909
#ifdef SPARC
489c9b5090e2 Initial load
duke
parents:
diff changeset
   910
          lrg.set_reg_pressure(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   911
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   912
          lrg.set_reg_pressure(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   913
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   914
          break;
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   915
        case Op_VecS:
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   916
          assert(Matcher::vector_size_supported(T_BYTE,4), "sanity");
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   917
          assert(RegMask::num_registers(Op_VecS) == RegMask::SlotsPerVecS, "sanity");
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   918
          lrg.set_num_regs(RegMask::SlotsPerVecS);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   919
          lrg.set_reg_pressure(1);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   920
          break;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   921
        case Op_VecD:
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   922
          assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecD), "sanity");
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   923
          assert(RegMask::num_registers(Op_VecD) == RegMask::SlotsPerVecD, "sanity");
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   924
          assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecD), "vector should be aligned");
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   925
          lrg.set_num_regs(RegMask::SlotsPerVecD);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   926
          lrg.set_reg_pressure(1);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   927
          break;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   928
        case Op_VecX:
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   929
          assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecX), "sanity");
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   930
          assert(RegMask::num_registers(Op_VecX) == RegMask::SlotsPerVecX, "sanity");
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   931
          assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecX), "vector should be aligned");
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   932
          lrg.set_num_regs(RegMask::SlotsPerVecX);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   933
          lrg.set_reg_pressure(1);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   934
          break;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   935
        case Op_VecY:
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   936
          assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecY), "sanity");
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   937
          assert(RegMask::num_registers(Op_VecY) == RegMask::SlotsPerVecY, "sanity");
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   938
          assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecY), "vector should be aligned");
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   939
          lrg.set_num_regs(RegMask::SlotsPerVecY);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   940
          lrg.set_reg_pressure(1);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
   941
          break;
30624
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30239
diff changeset
   942
        case Op_VecZ:
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30239
diff changeset
   943
          assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecZ), "sanity");
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30239
diff changeset
   944
          assert(RegMask::num_registers(Op_VecZ) == RegMask::SlotsPerVecZ, "sanity");
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30239
diff changeset
   945
          assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecZ), "vector should be aligned");
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30239
diff changeset
   946
          lrg.set_num_regs(RegMask::SlotsPerVecZ);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30239
diff changeset
   947
          lrg.set_reg_pressure(1);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30239
diff changeset
   948
          break;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   949
        default:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   950
          ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   951
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   952
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   953
489c9b5090e2 Initial load
duke
parents:
diff changeset
   954
      // Now do the same for inputs
489c9b5090e2 Initial load
duke
parents:
diff changeset
   955
      uint cnt = n->req();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   956
      // Setup for CISC SPILLING
489c9b5090e2 Initial load
duke
parents:
diff changeset
   957
      uint inp = (uint)AdlcVMDeps::Not_cisc_spillable;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   958
      if( UseCISCSpill && after_aggressive ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   959
        inp = n->cisc_operand();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   960
        if( inp != (uint)AdlcVMDeps::Not_cisc_spillable )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   961
          // Convert operand number to edge index number
489c9b5090e2 Initial load
duke
parents:
diff changeset
   962
          inp = n->as_Mach()->operand_index(inp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   963
      }
33065
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   964
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   965
      // Prepare register mask for each input
489c9b5090e2 Initial load
duke
parents:
diff changeset
   966
      for( uint k = input_edge_start; k < cnt; k++ ) {
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   967
        uint vreg = _lrg_map.live_range_id(n->in(k));
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   968
        if (!vreg) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   969
          continue;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   970
        }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   971
489c9b5090e2 Initial load
duke
parents:
diff changeset
   972
        // If this instruction is CISC Spillable, add the flags
489c9b5090e2 Initial load
duke
parents:
diff changeset
   973
        // bit to its appropriate input
489c9b5090e2 Initial load
duke
parents:
diff changeset
   974
        if( UseCISCSpill && after_aggressive && inp == k ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   975
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   976
          if( TraceCISCSpill ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   977
            tty->print("  use_cisc_RegMask: ");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   978
            n->dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   979
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   980
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   981
          n->as_Mach()->use_cisc_RegMask();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   982
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   983
33065
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   984
        if (is_machine_node && _scheduling_info_generated) {
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   985
          MachNode* cur_node = n->as_Mach();
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   986
          // this is cleaned up by register allocation
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   987
          if (k >= cur_node->num_opnds()) continue;
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   988
        }
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
   989
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   990
        LRG &lrg = lrgs(vreg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   991
        // // Testing for floating point code shape
489c9b5090e2 Initial load
duke
parents:
diff changeset
   992
        // Node *test = n->in(k);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   993
        // if( test->is_Mach() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   994
        //   MachNode *m = test->as_Mach();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   995
        //   int  op = m->ideal_Opcode();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   996
        //   if (n->is_Call() && (op == Op_AddF || op == Op_MulF) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   997
        //     int zzz = 1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   998
        //   }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   999
        // }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1000
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1001
        // Limit result register mask to acceptable registers.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1002
        // Do not limit registers from uncommon uses before
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1003
        // AggressiveCoalesce.  This effectively pre-virtual-splits
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1004
        // around uncommon uses of common defs.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1005
        const RegMask &rm = n->in_RegMask(k);
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  1006
        if (!after_aggressive && _cfg.get_block_for_node(n->in(k))->_freq > 1000 * block->_freq) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1007
          // Since we are BEFORE aggressive coalesce, leave the register
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1008
          // mask untrimmed by the call.  This encourages more coalescing.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1009
          // Later, AFTER aggressive, this live range will have to spill
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1010
          // but the spiller handles slow-path calls very nicely.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1011
        } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1012
          lrg.AND( rm );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1013
        }
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1014
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1015
        // Check for bound register masks
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1016
        const RegMask &lrgmask = lrg.mask();
46378
4ccca1fdf627 8160748: Inconsistent types for ideal_reg
kbarrett
parents: 37248
diff changeset
  1017
        uint kreg = n->in(k)->ideal_reg();
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1018
        bool is_vect = RegMask::is_vector(kreg);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1019
        assert(n->in(k)->bottom_type()->isa_vect() == NULL ||
22853
308672304981 8028767: PPC64: (part 121): smaller shared changes needed to build C2
goetz
parents: 20007
diff changeset
  1020
               is_vect || kreg == Op_RegD || kreg == Op_RegL,
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1021
               "vector must be in vector registers");
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1022
        if (lrgmask.is_bound(kreg))
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1023
          lrg._is_bound = 1;
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1024
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1025
        // If this use of a double forces a mis-aligned double,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1026
        // flag as '_fat_proj' - really flag as allowing misalignment
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1027
        // AND changes how we count interferences.  A mis-aligned
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1028
        // double can interfere with TWO aligned pairs, or effectively
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1029
        // FOUR registers!
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1030
#ifdef ASSERT
33065
55892792936f 8134802: LCM register pressure scheduling
mcberg
parents: 32398
diff changeset
  1031
        if (is_vect && !_scheduling_info_generated) {
32398
eed59c1cd49b 8131969: jit/FloatingPoint/gen_math/Loops05 assert(2 <= size && size <= 16) failed: update low bits table
roland
parents: 30624
diff changeset
  1032
          if (lrg.num_regs() != 0) {
eed59c1cd49b 8131969: jit/FloatingPoint/gen_math/Loops05 assert(2 <= size && size <= 16) failed: update low bits table
roland
parents: 30624
diff changeset
  1033
            assert(lrgmask.is_aligned_sets(lrg.num_regs()), "vector should be aligned");
eed59c1cd49b 8131969: jit/FloatingPoint/gen_math/Loops05 assert(2 <= size && size <= 16) failed: update low bits table
roland
parents: 30624
diff changeset
  1034
            assert(!lrg._fat_proj, "sanity");
eed59c1cd49b 8131969: jit/FloatingPoint/gen_math/Loops05 assert(2 <= size && size <= 16) failed: update low bits table
roland
parents: 30624
diff changeset
  1035
            assert(RegMask::num_registers(kreg) == lrg.num_regs(), "sanity");
eed59c1cd49b 8131969: jit/FloatingPoint/gen_math/Loops05 assert(2 <= size && size <= 16) failed: update low bits table
roland
parents: 30624
diff changeset
  1036
          } else {
eed59c1cd49b 8131969: jit/FloatingPoint/gen_math/Loops05 assert(2 <= size && size <= 16) failed: update low bits table
roland
parents: 30624
diff changeset
  1037
            assert(n->is_Phi(), "not all inputs processed only if Phi");
eed59c1cd49b 8131969: jit/FloatingPoint/gen_math/Loops05 assert(2 <= size && size <= 16) failed: update low bits table
roland
parents: 30624
diff changeset
  1038
          }
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1039
        }
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1040
#endif
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1041
        if (!is_vect && lrg.num_regs() == 2 && !lrg._fat_proj && rm.is_misaligned_pair()) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1042
          lrg._fat_proj = 1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1043
          lrg._is_bound = 1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1044
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1045
        // if the LRG is an unaligned pair, we will have to spill
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1046
        // so clear the LRG's register mask if it is not already spilled
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1047
        if (!is_vect && !n->is_SpillCopy() &&
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1048
            (lrg._def == NULL || lrg.is_multidef() || !lrg._def->is_SpillCopy()) &&
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1049
            lrgmask.is_misaligned_pair()) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1050
          lrg.Clear();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1051
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1052
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1053
        // Check for maximum frequency value
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  1054
        if (lrg._maxfreq < block->_freq) {
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  1055
          lrg._maxfreq = block->_freq;
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  1056
        }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1057
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1058
      } // End for all allocated inputs
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1059
    } // end for all instructions
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1060
  } // end for all blocks
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1061
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1062
  // Final per-liverange setup
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1063
  for (uint i2 = 0; i2 < _lrg_map.max_lrg_id(); i2++) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1064
    LRG &lrg = lrgs(i2);
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1065
    assert(!lrg._is_vector || !lrg._fat_proj, "sanity");
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1066
    if (lrg.num_regs() > 1 && !lrg._fat_proj) {
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1067
      lrg.clear_to_sets();
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1068
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1069
    lrg.compute_set_mask_size();
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1070
    if (lrg.not_free()) {      // Handle case where we lose from the start
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1071
      lrg.set_reg(OptoReg::Name(LRG::SPILL_REG));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1072
      lrg._direct_conflict = 1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1073
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1074
    lrg.set_degree(0);          // no neighbors in IFG yet
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1075
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1076
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1077
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1078
// Set the was-lo-degree bit.  Conservative coalescing should not change the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1079
// colorability of the graph.  If any live range was of low-degree before
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1080
// coalescing, it should Simplify.  This call sets the was-lo-degree bit.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1081
// The bit is checked in Simplify.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1082
void PhaseChaitin::set_was_low() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1083
#ifdef ASSERT
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1084
  for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1085
    int size = lrgs(i).num_regs();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1086
    uint old_was_lo = lrgs(i)._was_lo;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1087
    lrgs(i)._was_lo = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1088
    if( lrgs(i).lo_degree() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1089
      lrgs(i)._was_lo = 1;      // Trivially of low degree
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1090
    } else {                    // Else check the Brigg's assertion
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1091
      // Brigg's observation is that the lo-degree neighbors of a
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1092
      // hi-degree live range will not interfere with the color choices
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1093
      // of said hi-degree live range.  The Simplify reverse-stack-coloring
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1094
      // order takes care of the details.  Hence you do not have to count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1095
      // low-degree neighbors when determining if this guy colors.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1096
      int briggs_degree = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1097
      IndexSet *s = _ifg->neighbors(i);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1098
      IndexSetIterator elements(s);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1099
      uint lidx;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1100
      while((lidx = elements.next()) != 0) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1101
        if( !lrgs(lidx).lo_degree() )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1102
          briggs_degree += MAX2(size,lrgs(lidx).num_regs());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1103
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1104
      if( briggs_degree < lrgs(i).degrees_of_freedom() )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1105
        lrgs(i)._was_lo = 1;    // Low degree via the briggs assertion
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1106
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1107
    assert(old_was_lo <= lrgs(i)._was_lo, "_was_lo may not decrease");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1108
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1109
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1110
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1111
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1112
#define REGISTER_CONSTRAINED 16
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1113
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1114
// Compute cost/area ratio, in case we spill.  Build the lo-degree list.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1115
void PhaseChaitin::cache_lrg_info( ) {
26913
9ad70cd32368 8058968: Compiler time traces should be improved
shade
parents: 25930
diff changeset
  1116
  Compile::TracePhase tp("chaitinCacheLRG", &timers[_t_chaitinCacheLRG]);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1117
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1118
  for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1119
    LRG &lrg = lrgs(i);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1120
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1121
    // Check for being of low degree: means we can be trivially colored.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1122
    // Low degree, dead or must-spill guys just get to simplify right away
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1123
    if( lrg.lo_degree() ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1124
       !lrg.alive() ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1125
        lrg._must_spill ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1126
      // Split low degree list into those guys that must get a
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1127
      // register and those that can go to register or stack.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1128
      // The idea is LRGs that can go register or stack color first when
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1129
      // they have a good chance of getting a register.  The register-only
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1130
      // lo-degree live ranges always get a register.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1131
      OptoReg::Name hi_reg = lrg.mask().find_last_elem();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1132
      if( OptoReg::is_stack(hi_reg)) { // Can go to stack?
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1133
        lrg._next = _lo_stk_degree;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1134
        _lo_stk_degree = i;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1135
      } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1136
        lrg._next = _lo_degree;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1137
        _lo_degree = i;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1138
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1139
    } else {                    // Else high degree
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1140
      lrgs(_hi_degree)._prev = i;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1141
      lrg._next = _hi_degree;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1142
      lrg._prev = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1143
      _hi_degree = i;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1144
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1145
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1146
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1147
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1148
// Simplify the IFG by removing LRGs of low degree that have NO copies
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1149
void PhaseChaitin::Pre_Simplify( ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1150
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1151
  // Warm up the lo-degree no-copy list
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1152
  int lo_no_copy = 0;
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1153
  for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1154
    if ((lrgs(i).lo_degree() && !lrgs(i)._has_copy) ||
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1155
        !lrgs(i).alive() ||
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1156
        lrgs(i)._must_spill) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1157
      lrgs(i)._next = lo_no_copy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1158
      lo_no_copy = i;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1159
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1160
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1161
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1162
  while( lo_no_copy ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1163
    uint lo = lo_no_copy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1164
    lo_no_copy = lrgs(lo)._next;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1165
    int size = lrgs(lo).num_regs();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1166
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1167
    // Put the simplified guy on the simplified list.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1168
    lrgs(lo)._next = _simplified;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1169
    _simplified = lo;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1170
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1171
    // Yank this guy from the IFG.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1172
    IndexSet *adj = _ifg->remove_node( lo );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1173
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1174
    // If any neighbors' degrees fall below their number of
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1175
    // allowed registers, then put that neighbor on the low degree
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1176
    // list.  Note that 'degree' can only fall and 'numregs' is
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1177
    // unchanged by this action.  Thus the two are equal at most once,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1178
    // so LRGs hit the lo-degree worklists at most once.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1179
    IndexSetIterator elements(adj);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1180
    uint neighbor;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1181
    while ((neighbor = elements.next()) != 0) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1182
      LRG *n = &lrgs(neighbor);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1183
      assert( _ifg->effective_degree(neighbor) == n->degree(), "" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1184
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1185
      // Check for just becoming of-low-degree
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1186
      if( n->just_lo_degree() && !n->_has_copy ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1187
        assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1188
        // Put on lo-degree list
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1189
        n->_next = lo_no_copy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1190
        lo_no_copy = neighbor;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1191
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1192
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1193
  } // End of while lo-degree no_copy worklist not empty
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1194
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1195
  // No more lo-degree no-copy live ranges to simplify
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1196
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1197
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1198
// Simplify the IFG by removing LRGs of low degree.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1199
void PhaseChaitin::Simplify( ) {
26913
9ad70cd32368 8058968: Compiler time traces should be improved
shade
parents: 25930
diff changeset
  1200
  Compile::TracePhase tp("chaitinSimplify", &timers[_t_chaitinSimplify]);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1201
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1202
  while( 1 ) {                  // Repeat till simplified it all
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1203
    // May want to explore simplifying lo_degree before _lo_stk_degree.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1204
    // This might result in more spills coloring into registers during
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1205
    // Select().
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1206
    while( _lo_degree || _lo_stk_degree ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1207
      // If possible, pull from lo_stk first
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1208
      uint lo;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1209
      if( _lo_degree ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1210
        lo = _lo_degree;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1211
        _lo_degree = lrgs(lo)._next;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1212
      } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1213
        lo = _lo_stk_degree;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1214
        _lo_stk_degree = lrgs(lo)._next;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1215
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1216
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1217
      // Put the simplified guy on the simplified list.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1218
      lrgs(lo)._next = _simplified;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1219
      _simplified = lo;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1220
      // If this guy is "at risk" then mark his current neighbors
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1221
      if( lrgs(lo)._at_risk ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1222
        IndexSetIterator elements(_ifg->neighbors(lo));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1223
        uint datum;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1224
        while ((datum = elements.next()) != 0) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1225
          lrgs(datum)._risk_bias = lo;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1226
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1227
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1228
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1229
      // Yank this guy from the IFG.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1230
      IndexSet *adj = _ifg->remove_node( lo );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1231
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1232
      // If any neighbors' degrees fall below their number of
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1233
      // allowed registers, then put that neighbor on the low degree
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1234
      // list.  Note that 'degree' can only fall and 'numregs' is
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1235
      // unchanged by this action.  Thus the two are equal at most once,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1236
      // so LRGs hit the lo-degree worklist at most once.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1237
      IndexSetIterator elements(adj);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1238
      uint neighbor;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1239
      while ((neighbor = elements.next()) != 0) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1240
        LRG *n = &lrgs(neighbor);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1241
#ifdef ASSERT
2014
5510e7394f2d 6782232: assert("CreateEx must be first instruction in block" )
kvn
parents: 1499
diff changeset
  1242
        if( VerifyOpto || VerifyRegisterAllocator ) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1243
          assert( _ifg->effective_degree(neighbor) == n->degree(), "" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1244
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1245
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1246
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1247
        // Check for just becoming of-low-degree just counting registers.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1248
        // _must_spill live ranges are already on the low degree list.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1249
        if( n->just_lo_degree() && !n->_must_spill ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1250
          assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1251
          // Pull from hi-degree list
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1252
          uint prev = n->_prev;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1253
          uint next = n->_next;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1254
          if( prev ) lrgs(prev)._next = next;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1255
          else _hi_degree = next;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1256
          lrgs(next)._prev = prev;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1257
          n->_next = _lo_degree;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1258
          _lo_degree = neighbor;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1259
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1260
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1261
    } // End of while lo-degree/lo_stk_degree worklist not empty
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1262
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1263
    // Check for got everything: is hi-degree list empty?
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1264
    if( !_hi_degree ) break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1265
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1266
    // Time to pick a potential spill guy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1267
    uint lo_score = _hi_degree;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1268
    double score = lrgs(lo_score).score();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1269
    double area = lrgs(lo_score)._area;
4011
3329fe39ad1a 6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
kvn
parents: 2573
diff changeset
  1270
    double cost = lrgs(lo_score)._cost;
3329fe39ad1a 6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
kvn
parents: 2573
diff changeset
  1271
    bool bound = lrgs(lo_score)._is_bound;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1272
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1273
    // Find cheapest guy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1274
    debug_only( int lo_no_simplify=0; );
4015
fee7000abec2 6889656: assert(lo_lrg->lo_degree() || !lo_no_simplify,"Live range was lo-degree before coalesce
kvn
parents: 4011
diff changeset
  1275
    for( uint i = _hi_degree; i; i = lrgs(i)._next ) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1276
      assert( !(*_ifg->_yanked)[i], "" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1277
      // It's just vaguely possible to move hi-degree to lo-degree without
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1278
      // going through a just-lo-degree stage: If you remove a double from
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1279
      // a float live range it's degree will drop by 2 and you can skip the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1280
      // just-lo-degree stage.  It's very rare (shows up after 5000+ methods
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1281
      // in -Xcomp of Java2Demo).  So just choose this guy to simplify next.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1282
      if( lrgs(i).lo_degree() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1283
        lo_score = i;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1284
        break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1285
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1286
      debug_only( if( lrgs(i)._was_lo ) lo_no_simplify=i; );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1287
      double iscore = lrgs(i).score();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1288
      double iarea = lrgs(i)._area;
4011
3329fe39ad1a 6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
kvn
parents: 2573
diff changeset
  1289
      double icost = lrgs(i)._cost;
3329fe39ad1a 6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
kvn
parents: 2573
diff changeset
  1290
      bool ibound = lrgs(i)._is_bound;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1291
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1292
      // Compare cost/area of i vs cost/area of lo_score.  Smaller cost/area
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1293
      // wins.  Ties happen because all live ranges in question have spilled
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1294
      // a few times before and the spill-score adds a huge number which
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1295
      // washes out the low order bits.  We are choosing the lesser of 2
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1296
      // evils; in this case pick largest area to spill.
4011
3329fe39ad1a 6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
kvn
parents: 2573
diff changeset
  1297
      // Ties also happen when live ranges are defined and used only inside
3329fe39ad1a 6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
kvn
parents: 2573
diff changeset
  1298
      // one block. In which case their area is 0 and score set to max.
3329fe39ad1a 6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
kvn
parents: 2573
diff changeset
  1299
      // In such case choose bound live range over unbound to free registers
3329fe39ad1a 6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
kvn
parents: 2573
diff changeset
  1300
      // or with smaller cost to spill.
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1301
      if( iscore < score ||
4011
3329fe39ad1a 6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
kvn
parents: 2573
diff changeset
  1302
          (iscore == score && iarea > area && lrgs(lo_score)._was_spilled2) ||
3329fe39ad1a 6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
kvn
parents: 2573
diff changeset
  1303
          (iscore == score && iarea == area &&
46630
75aa3e39d02c 8182299: Enable disabled clang warnings, build on OSX 10 + Xcode 8
jwilhelm
parents: 46625
diff changeset
  1304
           ( (ibound && !bound) || (ibound == bound && (icost < cost)) )) ) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1305
        lo_score = i;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1306
        score = iscore;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1307
        area = iarea;
4011
3329fe39ad1a 6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
kvn
parents: 2573
diff changeset
  1308
        cost = icost;
3329fe39ad1a 6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
kvn
parents: 2573
diff changeset
  1309
        bound = ibound;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1310
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1311
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1312
    LRG *lo_lrg = &lrgs(lo_score);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1313
    // The live range we choose for spilling is either hi-degree, or very
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1314
    // rarely it can be low-degree.  If we choose a hi-degree live range
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1315
    // there better not be any lo-degree choices.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1316
    assert( lo_lrg->lo_degree() || !lo_no_simplify, "Live range was lo-degree before coalesce; should simplify" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1317
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1318
    // Pull from hi-degree list
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1319
    uint prev = lo_lrg->_prev;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1320
    uint next = lo_lrg->_next;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1321
    if( prev ) lrgs(prev)._next = next;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1322
    else _hi_degree = next;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1323
    lrgs(next)._prev = prev;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1324
    // Jam him on the lo-degree list, despite his high degree.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1325
    // Maybe he'll get a color, and maybe he'll spill.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1326
    // Only Select() will know.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1327
    lrgs(lo_score)._at_risk = true;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1328
    _lo_degree = lo_score;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1329
    lo_lrg->_next = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1330
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1331
  } // End of while not simplified everything
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1332
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1333
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1334
13491
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1335
// Is 'reg' register legal for 'lrg'?
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1336
static bool is_legal_reg(LRG &lrg, OptoReg::Name reg, int chunk) {
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1337
  if (reg >= chunk && reg < (chunk + RegMask::CHUNK_SIZE) &&
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1338
      lrg.mask().Member(OptoReg::add(reg,-chunk))) {
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1339
    // RA uses OptoReg which represent the highest element of a registers set.
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1340
    // For example, vectorX (128bit) on x86 uses [XMM,XMMb,XMMc,XMMd] set
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1341
    // in which XMMd is used by RA to represent such vectors. A double value
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1342
    // uses [XMM,XMMb] pairs and XMMb is used by RA for it.
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1343
    // The register mask uses largest bits set of overlapping register sets.
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1344
    // On x86 with AVX it uses 8 bits for each XMM registers set.
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1345
    //
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1346
    // The 'lrg' already has cleared-to-set register mask (done in Select()
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1347
    // before calling choose_color()). Passing mask.Member(reg) check above
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1348
    // indicates that the size (num_regs) of 'reg' set is less or equal to
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1349
    // 'lrg' set size.
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1350
    // For set size 1 any register which is member of 'lrg' mask is legal.
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1351
    if (lrg.num_regs()==1)
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1352
      return true;
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1353
    // For larger sets only an aligned register with the same set size is legal.
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1354
    int mask = lrg.num_regs()-1;
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1355
    if ((reg&mask) == mask)
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1356
      return true;
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1357
  }
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1358
  return false;
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1359
}
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1360
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1361
// Choose a color using the biasing heuristic
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1362
OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1363
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1364
  // Check for "at_risk" LRG's
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1365
  uint risk_lrg = _lrg_map.find(lrg._risk_bias);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1366
  if( risk_lrg != 0 ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1367
    // Walk the colored neighbors of the "at_risk" candidate
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1368
    // Choose a color which is both legal and already taken by a neighbor
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1369
    // of the "at_risk" candidate in order to improve the chances of the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1370
    // "at_risk" candidate of coloring
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1371
    IndexSetIterator elements(_ifg->neighbors(risk_lrg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1372
    uint datum;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1373
    while ((datum = elements.next()) != 0) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1374
      OptoReg::Name reg = lrgs(datum).reg();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1375
      // If this LRG's register is legal for us, choose it
13491
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1376
      if (is_legal_reg(lrg, reg, chunk))
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1377
        return reg;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1378
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1379
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1380
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1381
  uint copy_lrg = _lrg_map.find(lrg._copy_bias);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1382
  if( copy_lrg != 0 ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1383
    // If he has a color,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1384
    if( !(*(_ifg->_yanked))[copy_lrg] ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1385
      OptoReg::Name reg = lrgs(copy_lrg).reg();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1386
      //  And it is legal for you,
13491
6def7a824cf7 7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents: 13393
diff changeset
  1387
      if (is_legal_reg(lrg, reg, chunk))
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1388
        return reg;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1389
    } else if( chunk == 0 ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1390
      // Choose a color which is legal for him
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1391
      RegMask tempmask = lrg.mask();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1392
      tempmask.AND(lrgs(copy_lrg).mask());
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1393
      tempmask.clear_to_sets(lrg.num_regs());
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1394
      OptoReg::Name reg = tempmask.find_first_set(lrg.num_regs());
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1395
      if (OptoReg::is_valid(reg))
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1396
        return reg;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1397
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1398
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1399
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1400
  // If no bias info exists, just go with the register selection ordering
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1401
  if (lrg._is_vector || lrg.num_regs() == 2) {
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1402
    // Find an aligned set
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1403
    return OptoReg::add(lrg.mask().find_first_set(lrg.num_regs()),chunk);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1404
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1405
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1406
  // CNC - Fun hack.  Alternate 1st and 2nd selection.  Enables post-allocate
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1407
  // copy removal to remove many more copies, by preventing a just-assigned
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1408
  // register from being repeatedly assigned.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1409
  OptoReg::Name reg = lrg.mask().find_first_elem();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1410
  if( (++_alternate & 1) && OptoReg::is_valid(reg) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1411
    // This 'Remove; find; Insert' idiom is an expensive way to find the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1412
    // SECOND element in the mask.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1413
    lrg.Remove(reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1414
    OptoReg::Name reg2 = lrg.mask().find_first_elem();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1415
    lrg.Insert(reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1416
    if( OptoReg::is_reg(reg2))
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1417
      reg = reg2;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1418
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1419
  return OptoReg::add( reg, chunk );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1420
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1421
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1422
// Choose a color in the current chunk
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1423
OptoReg::Name PhaseChaitin::choose_color( LRG &lrg, int chunk ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1424
  assert( C->in_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP-1)), "must not allocate stack0 (inside preserve area)");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1425
  assert(C->out_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP+0)), "must not allocate stack0 (inside preserve area)");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1426
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1427
  if( lrg.num_regs() == 1 ||    // Common Case
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1428
      !lrg._fat_proj )          // Aligned+adjacent pairs ok
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1429
    // Use a heuristic to "bias" the color choice
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1430
    return bias_color(lrg, chunk);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1431
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1432
  assert(!lrg._is_vector, "should be not vector here" );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1433
  assert( lrg.num_regs() >= 2, "dead live ranges do not color" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1434
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1435
  // Fat-proj case or misaligned double argument.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1436
  assert(lrg.compute_mask_size() == lrg.num_regs() ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1437
         lrg.num_regs() == 2,"fat projs exactly color" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1438
  assert( !chunk, "always color in 1st chunk" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1439
  // Return the highest element in the set.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1440
  return lrg.mask().find_last_elem();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1441
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1442
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1443
// Select colors by re-inserting LRGs back into the IFG.  LRGs are re-inserted
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1444
// in reverse order of removal.  As long as nothing of hi-degree was yanked,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1445
// everything going back is guaranteed a color.  Select that color.  If some
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1446
// hi-degree LRG cannot get a color then we record that we must spill.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1447
uint PhaseChaitin::Select( ) {
26913
9ad70cd32368 8058968: Compiler time traces should be improved
shade
parents: 25930
diff changeset
  1448
  Compile::TracePhase tp("chaitinSelect", &timers[_t_chaitinSelect]);
9ad70cd32368 8058968: Compiler time traces should be improved
shade
parents: 25930
diff changeset
  1449
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1450
  uint spill_reg = LRG::SPILL_REG;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1451
  _max_reg = OptoReg::Name(0);  // Past max register used
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1452
  while( _simplified ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1453
    // Pull next LRG from the simplified list - in reverse order of removal
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1454
    uint lidx = _simplified;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1455
    LRG *lrg = &lrgs(lidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1456
    _simplified = lrg->_next;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1457
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1458
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1459
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1460
    if (trace_spilling()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1461
      ttyLocker ttyl;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1462
      tty->print_cr("L%d selecting degree %d degrees_of_freedom %d", lidx, lrg->degree(),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1463
                    lrg->degrees_of_freedom());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1464
      lrg->dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1465
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1466
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1467
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1468
    // Re-insert into the IFG
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1469
    _ifg->re_insert(lidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1470
    if( !lrg->alive() ) continue;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1471
    // capture allstackedness flag before mask is hacked
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1472
    const int is_allstack = lrg->mask().is_AllStack();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1473
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1474
    // Yeah, yeah, yeah, I know, I know.  I can refactor this
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1475
    // to avoid the GOTO, although the refactored code will not
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1476
    // be much clearer.  We arrive here IFF we have a stack-based
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1477
    // live range that cannot color in the current chunk, and it
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1478
    // has to move into the next free stack chunk.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1479
    int chunk = 0;              // Current chunk is first chunk
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1480
    retry_next_chunk:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1481
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1482
    // Remove neighbor colors
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1483
    IndexSet *s = _ifg->neighbors(lidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1484
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1485
    debug_only(RegMask orig_mask = lrg->mask();)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1486
    IndexSetIterator elements(s);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1487
    uint neighbor;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1488
    while ((neighbor = elements.next()) != 0) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1489
      // Note that neighbor might be a spill_reg.  In this case, exclusion
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1490
      // of its color will be a no-op, since the spill_reg chunk is in outer
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1491
      // space.  Also, if neighbor is in a different chunk, this exclusion
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1492
      // will be a no-op.  (Later on, if lrg runs out of possible colors in
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1493
      // its chunk, a new chunk of color may be tried, in which case
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1494
      // examination of neighbors is started again, at retry_next_chunk.)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1495
      LRG &nlrg = lrgs(neighbor);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1496
      OptoReg::Name nreg = nlrg.reg();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1497
      // Only subtract masks in the same chunk
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1498
      if( nreg >= chunk && nreg < chunk + RegMask::CHUNK_SIZE ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1499
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1500
        uint size = lrg->mask().Size();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1501
        RegMask rm = lrg->mask();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1502
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1503
        lrg->SUBTRACT(nlrg.mask());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1504
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1505
        if (trace_spilling() && lrg->mask().Size() != size) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1506
          ttyLocker ttyl;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1507
          tty->print("L%d ", lidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1508
          rm.dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1509
          tty->print(" intersected L%d ", neighbor);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1510
          nlrg.mask().dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1511
          tty->print(" removed ");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1512
          rm.SUBTRACT(lrg->mask());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1513
          rm.dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1514
          tty->print(" leaving ");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1515
          lrg->mask().dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1516
          tty->cr();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1517
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1518
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1519
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1520
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1521
    //assert(is_allstack == lrg->mask().is_AllStack(), "nbrs must not change AllStackedness");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1522
    // Aligned pairs need aligned masks
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1523
    assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity");
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1524
    if (lrg->num_regs() > 1 && !lrg->_fat_proj) {
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1525
      lrg->clear_to_sets();
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1526
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1527
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1528
    // Check if a color is available and if so pick the color
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1529
    OptoReg::Name reg = choose_color( *lrg, chunk );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1530
#ifdef SPARC
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1531
    debug_only(lrg->compute_set_mask_size());
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1532
    assert(lrg->num_regs() < 2 || lrg->is_bound() || is_even(reg-1), "allocate all doubles aligned");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1533
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1534
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1535
    //---------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1536
    // If we fail to color and the AllStack flag is set, trigger
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1537
    // a chunk-rollover event
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1538
    if(!OptoReg::is_valid(OptoReg::add(reg,-chunk)) && is_allstack) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1539
      // Bump register mask up to next stack chunk
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1540
      chunk += RegMask::CHUNK_SIZE;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1541
      lrg->Set_All();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1542
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1543
      goto retry_next_chunk;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1544
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1545
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1546
    //---------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1547
    // Did we get a color?
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1548
    else if( OptoReg::is_valid(reg)) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1549
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1550
      RegMask avail_rm = lrg->mask();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1551
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1552
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1553
      // Record selected register
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1554
      lrg->set_reg(reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1555
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1556
      if( reg >= _max_reg )     // Compute max register limit
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1557
        _max_reg = OptoReg::add(reg,1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1558
      // Fold reg back into normal space
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1559
      reg = OptoReg::add(reg,-chunk);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1560
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1561
      // If the live range is not bound, then we actually had some choices
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1562
      // to make.  In this case, the mask has more bits in it than the colors
2131
98f9cef66a34 6810672: Comment typos
twisti
parents: 2030
diff changeset
  1563
      // chosen.  Restrict the mask to just what was picked.
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1564
      int n_regs = lrg->num_regs();
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1565
      assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity");
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1566
      if (n_regs == 1 || !lrg->_fat_proj) {
30624
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30239
diff changeset
  1567
        assert(!lrg->_is_vector || n_regs <= RegMask::SlotsPerVecZ, "sanity");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1568
        lrg->Clear();           // Clear the mask
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1569
        lrg->Insert(reg);       // Set regmask to match selected reg
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1570
        // For vectors and pairs, also insert the low bit of the pair
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1571
        for (int i = 1; i < n_regs; i++)
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1572
          lrg->Insert(OptoReg::add(reg,-i));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  1573
        lrg->set_mask_size(n_regs);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1574
      } else {                  // Else fatproj
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1575
        // mask must be equal to fatproj bits, by definition
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1576
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1577
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1578
      if (trace_spilling()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1579
        ttyLocker ttyl;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1580
        tty->print("L%d selected ", lidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1581
        lrg->mask().dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1582
        tty->print(" from ");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1583
        avail_rm.dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1584
        tty->cr();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1585
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1586
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1587
      // Note that reg is the highest-numbered register in the newly-bound mask.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1588
    } // end color available case
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1589
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1590
    //---------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1591
    // Live range is live and no colors available
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1592
    else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1593
      assert( lrg->alive(), "" );
1057
44220ef9a775 6732194: Data corruption dependent on -server/-client/-Xbatch
never
parents: 670
diff changeset
  1594
      assert( !lrg->_fat_proj || lrg->is_multidef() ||
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1595
              lrg->_def->outcnt() > 0, "fat_proj cannot spill");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1596
      assert( !orig_mask.is_AllStack(), "All Stack does not spill" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1597
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1598
      // Assign the special spillreg register
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1599
      lrg->set_reg(OptoReg::Name(spill_reg++));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1600
      // Do not empty the regmask; leave mask_size lying around
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1601
      // for use during Spilling
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1602
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1603
      if( trace_spilling() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1604
        ttyLocker ttyl;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1605
        tty->print("L%d spilling with neighbors: ", lidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1606
        s->dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1607
        debug_only(tty->print(" original mask: "));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1608
        debug_only(orig_mask.dump());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1609
        dump_lrg(lidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1610
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1611
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1612
    } // end spill case
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1613
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1614
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1615
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1616
  return spill_reg-LRG::SPILL_REG;      // Return number of spills
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1617
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1618
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1619
// Copy 'was_spilled'-edness from the source Node to the dst Node.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1620
void PhaseChaitin::copy_was_spilled( Node *src, Node *dst ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1621
  if( _spilled_once.test(src->_idx) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1622
    _spilled_once.set(dst->_idx);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1623
    lrgs(_lrg_map.find(dst))._was_spilled1 = 1;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1624
    if( _spilled_twice.test(src->_idx) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1625
      _spilled_twice.set(dst->_idx);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1626
      lrgs(_lrg_map.find(dst))._was_spilled2 = 1;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1627
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1628
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1629
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1630
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1631
// Set the 'spilled_once' or 'spilled_twice' flag on a node.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1632
void PhaseChaitin::set_was_spilled( Node *n ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1633
  if( _spilled_once.test_set(n->_idx) )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1634
    _spilled_twice.set(n->_idx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1635
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1636
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1637
// Convert Ideal spill instructions into proper FramePtr + offset Loads and
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1638
// Stores.  Use-def chains are NOT preserved, but Node->LRG->reg maps are.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1639
void PhaseChaitin::fixup_spills() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1640
  // This function does only cisc spill work.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1641
  if( !UseCISCSpill ) return;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1642
26913
9ad70cd32368 8058968: Compiler time traces should be improved
shade
parents: 25930
diff changeset
  1643
  Compile::TracePhase tp("fixupSpills", &timers[_t_fixupSpills]);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1644
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1645
  // Grab the Frame Pointer
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  1646
  Node *fp = _cfg.get_root_block()->head()->in(1)->in(TypeFunc::FramePtr);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1647
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1648
  // For all blocks
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  1649
  for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  1650
    Block* block = _cfg.get_block(i);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1651
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1652
    // For all instructions in block
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  1653
    uint last_inst = block->end_idx();
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  1654
    for (uint j = 1; j <= last_inst; j++) {
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
  1655
      Node* n = block->get_node(j);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1656
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1657
      // Dead instruction???
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1658
      assert( n->outcnt() != 0 ||// Nothing dead after post alloc
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1659
              C->top() == n ||  // Or the random TOP node
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1660
              n->is_Proj(),     // Or a fat-proj kill node
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1661
              "No dead instructions after post-alloc" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1662
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1663
      int inp = n->cisc_operand();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1664
      if( inp != AdlcVMDeps::Not_cisc_spillable ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1665
        // Convert operand number to edge index number
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1666
        MachNode *mach = n->as_Mach();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1667
        inp = mach->operand_index(inp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1668
        Node *src = n->in(inp);   // Value to load or store
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1669
        LRG &lrg_cisc = lrgs(_lrg_map.find_const(src));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1670
        OptoReg::Name src_reg = lrg_cisc.reg();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1671
        // Doubles record the HIGH register of an adjacent pair.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1672
        src_reg = OptoReg::add(src_reg,1-lrg_cisc.num_regs());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1673
        if( OptoReg::is_stack(src_reg) ) { // If input is on stack
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1674
          // This is a CISC Spill, get stack offset and construct new node
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1675
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1676
          if( TraceCISCSpill ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1677
            tty->print("    reg-instr:  ");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1678
            n->dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1679
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1680
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1681
          int stk_offset = reg2offset(src_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1682
          // Bailout if we might exceed node limit when spilling this instruction
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1683
          C->check_node_count(0, "out of nodes fixing spills");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1684
          if (C->failing())  return;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1685
          // Transform node
25930
eae8b7490d2c 8054033: Remove unused references to Compile*
thartmann
parents: 24923
diff changeset
  1686
          MachNode *cisc = mach->cisc_version(stk_offset)->as_Mach();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1687
          cisc->set_req(inp,fp);          // Base register is frame pointer
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1688
          if( cisc->oper_input_base() > 1 && mach->oper_input_base() <= 1 ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1689
            assert( cisc->oper_input_base() == 2, "Only adding one edge");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1690
            cisc->ins_req(1,src);         // Requires a memory edge
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1691
          }
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
  1692
          block->map_node(cisc, j);          // Insert into basic block
14623
70c4c1be0a14 7092905: C2: Keep track of the number of dead nodes
bharadwaj
parents: 13895
diff changeset
  1693
          n->subsume_by(cisc, C); // Correct graph
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1694
          //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1695
          ++_used_cisc_instructions;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1696
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1697
          if( TraceCISCSpill ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1698
            tty->print("    cisc-instr: ");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1699
            cisc->dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1700
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1701
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1702
        } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1703
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1704
          if( TraceCISCSpill ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1705
            tty->print("    using reg-instr: ");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1706
            n->dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1707
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1708
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1709
          ++_unused_cisc_instructions;    // input can be on stack
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1710
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1711
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1712
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1713
    } // End of for all instructions
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1714
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1715
  } // End of for all blocks
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1716
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1717
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1718
// Helper to stretch above; recursively discover the base Node for a
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1719
// given derived Node.  Easy for AddP-related machine nodes, but needs
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1720
// to be recursive for derived Phis.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1721
Node *PhaseChaitin::find_base_for_derived( Node **derived_base_map, Node *derived, uint &maxlrg ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1722
  // See if already computed; if so return it
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1723
  if( derived_base_map[derived->_idx] )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1724
    return derived_base_map[derived->_idx];
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1725
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1726
  // See if this happens to be a base.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1727
  // NOTE: we use TypePtr instead of TypeOopPtr because we can have
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1728
  // pointers derived from NULL!  These are always along paths that
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1729
  // can't happen at run-time but the optimizer cannot deduce it so
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1730
  // we have to handle it gracefully.
2573
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2340
diff changeset
  1731
  assert(!derived->bottom_type()->isa_narrowoop() ||
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2340
diff changeset
  1732
          derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1733
  const TypePtr *tj = derived->bottom_type()->isa_ptr();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1734
  // If its an OOP with a non-zero offset, then it is derived.
2573
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2340
diff changeset
  1735
  if( tj == NULL || tj->_offset == 0 ) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1736
    derived_base_map[derived->_idx] = derived;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1737
    return derived;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1738
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1739
  // Derived is NULL+offset?  Base is NULL!
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1740
  if( derived->is_Con() ) {
2573
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2340
diff changeset
  1741
    Node *base = _matcher.mach_null();
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2340
diff changeset
  1742
    assert(base != NULL, "sanity");
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2340
diff changeset
  1743
    if (base->in(0) == NULL) {
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2340
diff changeset
  1744
      // Initialize it once and make it shared:
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2340
diff changeset
  1745
      // set control to _root and place it into Start block
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2340
diff changeset
  1746
      // (where top() node is placed).
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  1747
      base->init_req(0, _cfg.get_root_node());
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 18099
diff changeset
  1748
      Block *startb = _cfg.get_block_for_node(C->top());
22242
07e4f028ec7a 8029446: assert(_cfg.get_block_for_node(proj) == borig) failed: incorrect block for kill projections
adlertz
parents: 20007
diff changeset
  1749
      uint node_pos = startb->find_node(C->top());
07e4f028ec7a 8029446: assert(_cfg.get_block_for_node(proj) == borig) failed: incorrect block for kill projections
adlertz
parents: 20007
diff changeset
  1750
      startb->insert_node(base, node_pos);
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 18099
diff changeset
  1751
      _cfg.map_node_to_block(base, startb);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1752
      assert(_lrg_map.live_range_id(base) == 0, "should not have LRG yet");
22242
07e4f028ec7a 8029446: assert(_cfg.get_block_for_node(proj) == borig) failed: incorrect block for kill projections
adlertz
parents: 20007
diff changeset
  1753
07e4f028ec7a 8029446: assert(_cfg.get_block_for_node(proj) == borig) failed: incorrect block for kill projections
adlertz
parents: 20007
diff changeset
  1754
      // The loadConP0 might have projection nodes depending on architecture
07e4f028ec7a 8029446: assert(_cfg.get_block_for_node(proj) == borig) failed: incorrect block for kill projections
adlertz
parents: 20007
diff changeset
  1755
      // Add the projection nodes to the CFG
07e4f028ec7a 8029446: assert(_cfg.get_block_for_node(proj) == borig) failed: incorrect block for kill projections
adlertz
parents: 20007
diff changeset
  1756
      for (DUIterator_Fast imax, i = base->fast_outs(imax); i < imax; i++) {
07e4f028ec7a 8029446: assert(_cfg.get_block_for_node(proj) == borig) failed: incorrect block for kill projections
adlertz
parents: 20007
diff changeset
  1757
        Node* use = base->fast_out(i);
07e4f028ec7a 8029446: assert(_cfg.get_block_for_node(proj) == borig) failed: incorrect block for kill projections
adlertz
parents: 20007
diff changeset
  1758
        if (use->is_MachProj()) {
07e4f028ec7a 8029446: assert(_cfg.get_block_for_node(proj) == borig) failed: incorrect block for kill projections
adlertz
parents: 20007
diff changeset
  1759
          startb->insert_node(use, ++node_pos);
07e4f028ec7a 8029446: assert(_cfg.get_block_for_node(proj) == borig) failed: incorrect block for kill projections
adlertz
parents: 20007
diff changeset
  1760
          _cfg.map_node_to_block(use, startb);
07e4f028ec7a 8029446: assert(_cfg.get_block_for_node(proj) == borig) failed: incorrect block for kill projections
adlertz
parents: 20007
diff changeset
  1761
          new_lrg(use, maxlrg++);
07e4f028ec7a 8029446: assert(_cfg.get_block_for_node(proj) == borig) failed: incorrect block for kill projections
adlertz
parents: 20007
diff changeset
  1762
        }
07e4f028ec7a 8029446: assert(_cfg.get_block_for_node(proj) == borig) failed: incorrect block for kill projections
adlertz
parents: 20007
diff changeset
  1763
      }
2573
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2340
diff changeset
  1764
    }
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1765
    if (_lrg_map.live_range_id(base) == 0) {
2573
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2340
diff changeset
  1766
      new_lrg(base, maxlrg++);
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2340
diff changeset
  1767
    }
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  1768
    assert(base->in(0) == _cfg.get_root_node() && _cfg.get_block_for_node(base) == _cfg.get_block_for_node(C->top()), "base NULL should be shared");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1769
    derived_base_map[derived->_idx] = base;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1770
    return base;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1771
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1772
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1773
  // Check for AddP-related opcodes
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1774
  if (!derived->is_Phi()) {
33105
294e48b4f704 8080775: Better argument formatting for assert() and friends
david
parents: 32398
diff changeset
  1775
    assert(derived->as_Mach()->ideal_Opcode() == Op_AddP, "but is: %s", derived->Name());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1776
    Node *base = derived->in(AddPNode::Base);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1777
    derived_base_map[derived->_idx] = base;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1778
    return base;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1779
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1780
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1781
  // Recursively find bases for Phis.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1782
  // First check to see if we can avoid a base Phi here.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1783
  Node *base = find_base_for_derived( derived_base_map, derived->in(1),maxlrg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1784
  uint i;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1785
  for( i = 2; i < derived->req(); i++ )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1786
    if( base != find_base_for_derived( derived_base_map,derived->in(i),maxlrg))
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1787
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1788
  // Went to the end without finding any different bases?
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1789
  if( i == derived->req() ) {   // No need for a base Phi here
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1790
    derived_base_map[derived->_idx] = base;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1791
    return base;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1792
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1793
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1794
  // Now we see we need a base-Phi here to merge the bases
2573
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2340
diff changeset
  1795
  const Type *t = base->bottom_type();
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24424
diff changeset
  1796
  base = new PhiNode( derived->in(0), t );
2573
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2340
diff changeset
  1797
  for( i = 1; i < derived->req(); i++ ) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1798
    base->init_req(i, find_base_for_derived(derived_base_map, derived->in(i), maxlrg));
2573
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2340
diff changeset
  1799
    t = t->meet(base->in(i)->bottom_type());
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2340
diff changeset
  1800
  }
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2340
diff changeset
  1801
  base->as_Phi()->set_type(t);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1802
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1803
  // Search the current block for an existing base-Phi
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 18099
diff changeset
  1804
  Block *b = _cfg.get_block_for_node(derived);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1805
  for( i = 1; i <= b->end_idx(); i++ ) {// Search for matching Phi
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
  1806
    Node *phi = b->get_node(i);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1807
    if( !phi->is_Phi() ) {      // Found end of Phis with no match?
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
  1808
      b->insert_node(base,  i); // Must insert created Phi here as base
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 18099
diff changeset
  1809
      _cfg.map_node_to_block(base, b);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1810
      new_lrg(base,maxlrg++);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1811
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1812
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1813
    // See if Phi matches.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1814
    uint j;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1815
    for( j = 1; j < base->req(); j++ )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1816
      if( phi->in(j) != base->in(j) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1817
          !(phi->in(j)->is_Con() && base->in(j)->is_Con()) ) // allow different NULLs
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1818
        break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1819
    if( j == base->req() ) {    // All inputs match?
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1820
      base = phi;               // Then use existing 'phi' and drop 'base'
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1821
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1822
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1823
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1824
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1825
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1826
  // Cache info for later passes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1827
  derived_base_map[derived->_idx] = base;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1828
  return base;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1829
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1830
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1831
// At each Safepoint, insert extra debug edges for each pair of derived value/
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1832
// base pointer that is live across the Safepoint for oopmap building.  The
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1833
// edge pairs get added in after sfpt->jvmtail()->oopoff(), but are in the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1834
// required edge set.
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1835
bool PhaseChaitin::stretch_base_pointer_live_ranges(ResourceArea *a) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1836
  int must_recompute_live = false;
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1837
  uint maxlrg = _lrg_map.max_lrg_id();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1838
  Node **derived_base_map = (Node**)a->Amalloc(sizeof(Node*)*C->unique());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1839
  memset( derived_base_map, 0, sizeof(Node*)*C->unique() );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1840
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1841
  // For all blocks in RPO do...
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  1842
  for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  1843
    Block* block = _cfg.get_block(i);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1844
    // Note use of deep-copy constructor.  I cannot hammer the original
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1845
    // liveout bits, because they are needed by the following coalesce pass.
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  1846
    IndexSet liveout(_live->live(block));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1847
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  1848
    for (uint j = block->end_idx() + 1; j > 1; j--) {
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
  1849
      Node* n = block->get_node(j - 1);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1850
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1851
      // Pre-split compares of loop-phis.  Loop-phis form a cycle we would
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1852
      // like to see in the same register.  Compare uses the loop-phi and so
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1853
      // extends its live range BUT cannot be part of the cycle.  If this
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1854
      // extended live range overlaps with the update of the loop-phi value
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1855
      // we need both alive at the same time -- which requires at least 1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1856
      // copy.  But because Intel has only 2-address registers we end up with
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1857
      // at least 2 copies, one before the loop-phi update instruction and
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1858
      // one after.  Instead we split the input to the compare just after the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1859
      // phi.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1860
      if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_CmpI ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1861
        Node *phi = n->in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1862
        if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) {
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 18099
diff changeset
  1863
          Block *phi_block = _cfg.get_block_for_node(phi);
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  1864
          if (_cfg.get_block_for_node(phi_block->pred(2)) == block) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1865
            const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI];
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24424
diff changeset
  1866
            Node *spill = new MachSpillCopyNode(MachSpillCopyNode::LoopPhiInput, phi, *mask, *mask);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1867
            insert_proj( phi_block, 1, spill, maxlrg++ );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1868
            n->set_req(1,spill);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1869
            must_recompute_live = true;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1870
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1871
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1872
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1873
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1874
      // Get value being defined
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1875
      uint lidx = _lrg_map.live_range_id(n);
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1876
      // Ignore the occasional brand-new live range
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1877
      if (lidx && lidx < _lrg_map.max_lrg_id()) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1878
        // Remove from live-out set
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1879
        liveout.remove(lidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1880
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1881
        // Copies do not define a new value and so do not interfere.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1882
        // Remove the copies source from the liveout set before interfering.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1883
        uint idx = n->is_Copy();
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1884
        if (idx) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1885
          liveout.remove(_lrg_map.live_range_id(n->in(idx)));
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1886
        }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1887
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1888
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1889
      // Found a safepoint?
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1890
      JVMState *jvms = n->jvms();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1891
      if( jvms ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1892
        // Now scan for a live derived pointer
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1893
        IndexSetIterator elements(&liveout);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1894
        uint neighbor;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1895
        while ((neighbor = elements.next()) != 0) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1896
          // Find reaching DEF for base and derived values
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1897
          // This works because we are still in SSA during this call.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1898
          Node *derived = lrgs(neighbor)._def;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1899
          const TypePtr *tj = derived->bottom_type()->isa_ptr();
2573
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2340
diff changeset
  1900
          assert(!derived->bottom_type()->isa_narrowoop() ||
b5002ef26155 6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents: 2340
diff changeset
  1901
                  derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1902
          // If its an OOP with a non-zero offset, then it is derived.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1903
          if( tj && tj->_offset != 0 && tj->isa_oop_ptr() ) {
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1904
            Node *base = find_base_for_derived(derived_base_map, derived, maxlrg);
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1905
            assert(base->_idx < _lrg_map.size(), "");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1906
            // Add reaching DEFs of derived pointer and base pointer as a
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1907
            // pair of inputs
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1908
            n->add_req(derived);
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1909
            n->add_req(base);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1910
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1911
            // See if the base pointer is already live to this point.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1912
            // Since I'm working on the SSA form, live-ness amounts to
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1913
            // reaching def's.  So if I find the base's live range then
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1914
            // I know the base's def reaches here.
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1915
            if ((_lrg_map.live_range_id(base) >= _lrg_map.max_lrg_id() || // (Brand new base (hence not live) or
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1916
                 !liveout.member(_lrg_map.live_range_id(base))) && // not live) AND
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1917
                 (_lrg_map.live_range_id(base) > 0) && // not a constant
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  1918
                 _cfg.get_block_for_node(base) != block) { // base not def'd in blk)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1919
              // Base pointer is not currently live.  Since I stretched
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1920
              // the base pointer to here and it crosses basic-block
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1921
              // boundaries, the global live info is now incorrect.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1922
              // Recompute live.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1923
              must_recompute_live = true;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1924
            } // End of if base pointer is not live to debug info
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1925
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1926
        } // End of scan all live data for derived ptrs crossing GC point
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1927
      } // End of if found a GC point
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1928
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1929
      // Make all inputs live
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1930
      if (!n->is_Phi()) {      // Phi function uses come from prior block
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1931
        for (uint k = 1; k < n->req(); k++) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1932
          uint lidx = _lrg_map.live_range_id(n->in(k));
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1933
          if (lidx < _lrg_map.max_lrg_id()) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1934
            liveout.insert(lidx);
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1935
          }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1936
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1937
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1938
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1939
    } // End of forall instructions in block
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1940
    liveout.clear();  // Free the memory used by liveout.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1941
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1942
  } // End of forall blocks
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1943
  _lrg_map.set_max_lrg_id(maxlrg);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1944
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1945
  // If I created a new live range I need to recompute live
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1946
  if (maxlrg != _ifg->_maxlrg) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1947
    must_recompute_live = true;
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1948
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1949
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1950
  return must_recompute_live != 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1951
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1952
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1953
// Extend the node to LRG mapping
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1954
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1955
void PhaseChaitin::add_reference(const Node *node, const Node *old_node) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1956
  _lrg_map.extend(node->_idx, _lrg_map.live_range_id(old_node));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1957
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1958
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1959
#ifndef PRODUCT
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1960
void PhaseChaitin::dump(const Node *n) const {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1961
  uint r = (n->_idx < _lrg_map.size()) ? _lrg_map.find_const(n) : 0;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1962
  tty->print("L%d",r);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1963
  if (r && n->Opcode() != Op_Phi) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1964
    if( _node_regs ) {          // Got a post-allocation copy of allocation?
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1965
      tty->print("[");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1966
      OptoReg::Name second = get_reg_second(n);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1967
      if( OptoReg::is_valid(second) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1968
        if( OptoReg::is_reg(second) )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1969
          tty->print("%s:",Matcher::regName[second]);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1970
        else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1971
          tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(second));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1972
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1973
      OptoReg::Name first = get_reg_first(n);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1974
      if( OptoReg::is_reg(first) )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1975
        tty->print("%s]",Matcher::regName[first]);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1976
      else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1977
         tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(first));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1978
    } else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1979
    n->out_RegMask().dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1980
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1981
  tty->print("/N%d\t",n->_idx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1982
  tty->print("%s === ", n->Name());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1983
  uint k;
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1984
  for (k = 0; k < n->req(); k++) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1985
    Node *m = n->in(k);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1986
    if (!m) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1987
      tty->print("_ ");
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1988
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1989
    else {
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1990
      uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1991
      tty->print("L%d",r);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1992
      // Data MultiNode's can have projections with no real registers.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1993
      // Don't die while dumping them.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1994
      int op = n->Opcode();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1995
      if( r && op != Op_Phi && op != Op_Proj && op != Op_SCMemProj) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1996
        if( _node_regs ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1997
          tty->print("[");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1998
          OptoReg::Name second = get_reg_second(n->in(k));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1999
          if( OptoReg::is_valid(second) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2000
            if( OptoReg::is_reg(second) )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2001
              tty->print("%s:",Matcher::regName[second]);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2002
            else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2003
              tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2004
                         reg2offset_unchecked(second));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2005
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2006
          OptoReg::Name first = get_reg_first(n->in(k));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2007
          if( OptoReg::is_reg(first) )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2008
            tty->print("%s]",Matcher::regName[first]);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2009
          else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2010
            tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2011
                       reg2offset_unchecked(first));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2012
        } else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2013
          n->in_RegMask(k).dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2014
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2015
      tty->print("/N%d ",m->_idx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2016
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2017
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2018
  if( k < n->len() && n->in(k) ) tty->print("| ");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2019
  for( ; k < n->len(); k++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2020
    Node *m = n->in(k);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2021
    if(!m) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2022
      break;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2023
    }
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2024
    uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2025
    tty->print("L%d",r);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2026
    tty->print("/N%d ",m->_idx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2027
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2028
  if( n->is_Mach() ) n->as_Mach()->dump_spec(tty);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2029
  else n->dump_spec(tty);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2030
  if( _spilled_once.test(n->_idx ) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2031
    tty->print(" Spill_1");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2032
    if( _spilled_twice.test(n->_idx ) )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2033
      tty->print(" Spill_2");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2034
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2035
  tty->print("\n");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2036
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2037
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 18099
diff changeset
  2038
void PhaseChaitin::dump(const Block *b) const {
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 18099
diff changeset
  2039
  b->dump_head(&_cfg);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2040
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2041
  // For all instructions
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
  2042
  for( uint j = 0; j < b->number_of_nodes(); j++ )
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
  2043
    dump(b->get_node(j));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2044
  // Print live-out info at end of block
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2045
  if( _live ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2046
    tty->print("Liveout: ");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2047
    IndexSet *live = _live->live(b);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2048
    IndexSetIterator elements(live);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2049
    tty->print("{");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2050
    uint i;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2051
    while ((i = elements.next()) != 0) {
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2052
      tty->print("L%d ", _lrg_map.find_const(i));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2053
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2054
    tty->print_cr("}");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2055
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2056
  tty->print("\n");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2057
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2058
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2059
void PhaseChaitin::dump() const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2060
  tty->print( "--- Chaitin -- argsize: %d  framesize: %d ---\n",
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2061
              _matcher._new_SP, _framesize );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2062
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2063
  // For all blocks
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  2064
  for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  2065
    dump(_cfg.get_block(i));
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  2066
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2067
  // End of per-block dump
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2068
  tty->print("\n");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2069
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2070
  if (!_ifg) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2071
    tty->print("(No IFG.)\n");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2072
    return;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2073
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2074
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2075
  // Dump LRG array
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2076
  tty->print("--- Live RanGe Array ---\n");
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2077
  for (uint i2 = 1; i2 < _lrg_map.max_lrg_id(); i2++) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2078
    tty->print("L%d: ",i2);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2079
    if (i2 < _ifg->_maxlrg) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2080
      lrgs(i2).dump();
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2081
    }
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2082
    else {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2083
      tty->print_cr("new LRG");
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2084
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2085
  }
24424
2658d7834c6e 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 23528
diff changeset
  2086
  tty->cr();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2087
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2088
  // Dump lo-degree list
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2089
  tty->print("Lo degree: ");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2090
  for(uint i3 = _lo_degree; i3; i3 = lrgs(i3)._next )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2091
    tty->print("L%d ",i3);
24424
2658d7834c6e 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 23528
diff changeset
  2092
  tty->cr();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2093
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2094
  // Dump lo-stk-degree list
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2095
  tty->print("Lo stk degree: ");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2096
  for(uint i4 = _lo_stk_degree; i4; i4 = lrgs(i4)._next )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2097
    tty->print("L%d ",i4);
24424
2658d7834c6e 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 23528
diff changeset
  2098
  tty->cr();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2099
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2100
  // Dump lo-degree list
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2101
  tty->print("Hi degree: ");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2102
  for(uint i5 = _hi_degree; i5; i5 = lrgs(i5)._next )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2103
    tty->print("L%d ",i5);
24424
2658d7834c6e 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 23528
diff changeset
  2104
  tty->cr();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2105
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2106
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2107
void PhaseChaitin::dump_degree_lists() const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2108
  // Dump lo-degree list
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2109
  tty->print("Lo degree: ");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2110
  for( uint i = _lo_degree; i; i = lrgs(i)._next )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2111
    tty->print("L%d ",i);
24424
2658d7834c6e 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 23528
diff changeset
  2112
  tty->cr();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2113
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2114
  // Dump lo-stk-degree list
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2115
  tty->print("Lo stk degree: ");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2116
  for(uint i2 = _lo_stk_degree; i2; i2 = lrgs(i2)._next )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2117
    tty->print("L%d ",i2);
24424
2658d7834c6e 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 23528
diff changeset
  2118
  tty->cr();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2119
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2120
  // Dump lo-degree list
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2121
  tty->print("Hi degree: ");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2122
  for(uint i3 = _hi_degree; i3; i3 = lrgs(i3)._next )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2123
    tty->print("L%d ",i3);
24424
2658d7834c6e 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 23528
diff changeset
  2124
  tty->cr();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2125
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2126
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2127
void PhaseChaitin::dump_simplified() const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2128
  tty->print("Simplified: ");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2129
  for( uint i = _simplified; i; i = lrgs(i)._next )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2130
    tty->print("L%d ",i);
24424
2658d7834c6e 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 23528
diff changeset
  2131
  tty->cr();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2132
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2133
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2134
static char *print_reg( OptoReg::Name reg, const PhaseChaitin *pc, char *buf ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2135
  if ((int)reg < 0)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2136
    sprintf(buf, "<OptoReg::%d>", (int)reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2137
  else if (OptoReg::is_reg(reg))
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2138
    strcpy(buf, Matcher::regName[reg]);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2139
  else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2140
    sprintf(buf,"%s + #%d",OptoReg::regname(OptoReg::c_frame_pointer),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2141
            pc->reg2offset(reg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2142
  return buf+strlen(buf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2143
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2144
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2145
// Dump a register name into a buffer.  Be intelligent if we get called
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2146
// before allocation is complete.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2147
char *PhaseChaitin::dump_register( const Node *n, char *buf  ) const {
30239
dc83236ebb28 8077364: "if( !this )" construct prevents build on Xcode 6.3
sla
parents: 29580
diff changeset
  2148
  if( this == NULL ) {          // Not got anything?
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2149
    sprintf(buf,"N%d",n->_idx); // Then use Node index
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2150
  } else if( _node_regs ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2151
    // Post allocation, use direct mappings, no LRG info available
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2152
    print_reg( get_reg_first(n), this, buf );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2153
  } else {
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2154
    uint lidx = _lrg_map.find_const(n); // Grab LRG number
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2155
    if( !_ifg ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2156
      sprintf(buf,"L%d",lidx);  // No register binding yet
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2157
    } else if( !lidx ) {        // Special, not allocated value
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2158
      strcpy(buf,"Special");
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  2159
    } else {
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  2160
      if (lrgs(lidx)._is_vector) {
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  2161
        if (lrgs(lidx).mask().is_bound_set(lrgs(lidx).num_regs()))
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  2162
          print_reg( lrgs(lidx).reg(), this, buf ); // a bound machine register
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  2163
        else
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  2164
          sprintf(buf,"L%d",lidx); // No register binding yet
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  2165
      } else if( (lrgs(lidx).num_regs() == 1)
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  2166
                 ? lrgs(lidx).mask().is_bound1()
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  2167
                 : lrgs(lidx).mask().is_bound_pair() ) {
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  2168
        // Hah!  We have a bound machine register
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  2169
        print_reg( lrgs(lidx).reg(), this, buf );
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  2170
      } else {
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  2171
        sprintf(buf,"L%d",lidx); // No register binding yet
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11794
diff changeset
  2172
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2173
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2174
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2175
  return buf+strlen(buf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2176
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2177
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2178
void PhaseChaitin::dump_for_spill_split_recycle() const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2179
  if( WizardMode && (PrintCompilation || PrintOpto) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2180
    // Display which live ranges need to be split and the allocator's state
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2181
    tty->print_cr("Graph-Coloring Iteration %d will split the following live ranges", _trip_cnt);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2182
    for (uint bidx = 1; bidx < _lrg_map.max_lrg_id(); bidx++) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2183
      if( lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2184
        tty->print("L%d: ", bidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2185
        lrgs(bidx).dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2186
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2187
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2188
    tty->cr();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2189
    dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2190
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2191
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2192
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2193
void PhaseChaitin::dump_frame() const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2194
  const char *fp = OptoReg::regname(OptoReg::c_frame_pointer);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2195
  const TypeTuple *domain = C->tf()->domain();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2196
  const int        argcnt = domain->cnt() - TypeFunc::Parms;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2197
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2198
  // Incoming arguments in registers dump
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2199
  for( int k = 0; k < argcnt; k++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2200
    OptoReg::Name parmreg = _matcher._parm_regs[k].first();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2201
    if( OptoReg::is_reg(parmreg))  {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2202
      const char *reg_name = OptoReg::regname(parmreg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2203
      tty->print("#r%3.3d %s", parmreg, reg_name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2204
      parmreg = _matcher._parm_regs[k].second();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2205
      if( OptoReg::is_reg(parmreg))  {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2206
        tty->print(":%s", OptoReg::regname(parmreg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2207
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2208
      tty->print("   : parm %d: ", k);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2209
      domain->field_at(k + TypeFunc::Parms)->dump();
24424
2658d7834c6e 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 23528
diff changeset
  2210
      tty->cr();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2211
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2212
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2213
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2214
  // Check for un-owned padding above incoming args
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2215
  OptoReg::Name reg = _matcher._new_SP;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2216
  if( reg > _matcher._in_arg_limit ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2217
    reg = OptoReg::add(reg, -1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2218
    tty->print_cr("#r%3.3d %s+%2d: pad0, owned by CALLER", reg, fp, reg2offset_unchecked(reg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2219
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2220
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2221
  // Incoming argument area dump
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2222
  OptoReg::Name begin_in_arg = OptoReg::add(_matcher._old_SP,C->out_preserve_stack_slots());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2223
  while( reg > begin_in_arg ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2224
    reg = OptoReg::add(reg, -1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2225
    tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2226
    int j;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2227
    for( j = 0; j < argcnt; j++) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2228
      if( _matcher._parm_regs[j].first() == reg ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2229
          _matcher._parm_regs[j].second() == reg ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2230
        tty->print("parm %d: ",j);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2231
        domain->field_at(j + TypeFunc::Parms)->dump();
24424
2658d7834c6e 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 23528
diff changeset
  2232
        tty->cr();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2233
        break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2234
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2235
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2236
    if( j >= argcnt )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2237
      tty->print_cr("HOLE, owned by SELF");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2238
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2239
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2240
  // Old outgoing preserve area
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2241
  while( reg > _matcher._old_SP ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2242
    reg = OptoReg::add(reg, -1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2243
    tty->print_cr("#r%3.3d %s+%2d: old out preserve",reg,fp,reg2offset_unchecked(reg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2244
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2245
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2246
  // Old SP
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2247
  tty->print_cr("# -- Old %s -- Framesize: %d --",fp,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2248
    reg2offset_unchecked(OptoReg::add(_matcher._old_SP,-1)) - reg2offset_unchecked(_matcher._new_SP)+jintSize);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2249
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2250
  // Preserve area dump
11794
72249bf6ab83 7145346: VerifyStackAtCalls is broken
kvn
parents: 8921
diff changeset
  2251
  int fixed_slots = C->fixed_slots();
72249bf6ab83 7145346: VerifyStackAtCalls is broken
kvn
parents: 8921
diff changeset
  2252
  OptoReg::Name begin_in_preserve = OptoReg::add(_matcher._old_SP, -(int)C->in_preserve_stack_slots());
72249bf6ab83 7145346: VerifyStackAtCalls is broken
kvn
parents: 8921
diff changeset
  2253
  OptoReg::Name return_addr = _matcher.return_addr();
72249bf6ab83 7145346: VerifyStackAtCalls is broken
kvn
parents: 8921
diff changeset
  2254
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2255
  reg = OptoReg::add(reg, -1);
11794
72249bf6ab83 7145346: VerifyStackAtCalls is broken
kvn
parents: 8921
diff changeset
  2256
  while (OptoReg::is_stack(reg)) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2257
    tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg));
11794
72249bf6ab83 7145346: VerifyStackAtCalls is broken
kvn
parents: 8921
diff changeset
  2258
    if (return_addr == reg) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2259
      tty->print_cr("return address");
11794
72249bf6ab83 7145346: VerifyStackAtCalls is broken
kvn
parents: 8921
diff changeset
  2260
    } else if (reg >= begin_in_preserve) {
72249bf6ab83 7145346: VerifyStackAtCalls is broken
kvn
parents: 8921
diff changeset
  2261
      // Preserved slots are present on x86
72249bf6ab83 7145346: VerifyStackAtCalls is broken
kvn
parents: 8921
diff changeset
  2262
      if (return_addr == OptoReg::add(reg, VMRegImpl::slots_per_word))
72249bf6ab83 7145346: VerifyStackAtCalls is broken
kvn
parents: 8921
diff changeset
  2263
        tty->print_cr("saved fp register");
72249bf6ab83 7145346: VerifyStackAtCalls is broken
kvn
parents: 8921
diff changeset
  2264
      else if (return_addr == OptoReg::add(reg, 2*VMRegImpl::slots_per_word) &&
72249bf6ab83 7145346: VerifyStackAtCalls is broken
kvn
parents: 8921
diff changeset
  2265
               VerifyStackAtCalls)
72249bf6ab83 7145346: VerifyStackAtCalls is broken
kvn
parents: 8921
diff changeset
  2266
        tty->print_cr("0xBADB100D   +VerifyStackAtCalls");
72249bf6ab83 7145346: VerifyStackAtCalls is broken
kvn
parents: 8921
diff changeset
  2267
      else
72249bf6ab83 7145346: VerifyStackAtCalls is broken
kvn
parents: 8921
diff changeset
  2268
        tty->print_cr("in_preserve");
72249bf6ab83 7145346: VerifyStackAtCalls is broken
kvn
parents: 8921
diff changeset
  2269
    } else if ((int)OptoReg::reg2stack(reg) < fixed_slots) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2270
      tty->print_cr("Fixed slot %d", OptoReg::reg2stack(reg));
11794
72249bf6ab83 7145346: VerifyStackAtCalls is broken
kvn
parents: 8921
diff changeset
  2271
    } else {
72249bf6ab83 7145346: VerifyStackAtCalls is broken
kvn
parents: 8921
diff changeset
  2272
      tty->print_cr("pad2, stack alignment");
72249bf6ab83 7145346: VerifyStackAtCalls is broken
kvn
parents: 8921
diff changeset
  2273
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2274
    reg = OptoReg::add(reg, -1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2275
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2276
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2277
  // Spill area dump
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2278
  reg = OptoReg::add(_matcher._new_SP, _framesize );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2279
  while( reg > _matcher._out_arg_limit ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2280
    reg = OptoReg::add(reg, -1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2281
    tty->print_cr("#r%3.3d %s+%2d: spill",reg,fp,reg2offset_unchecked(reg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2282
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2283
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2284
  // Outgoing argument area dump
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2285
  while( reg > OptoReg::add(_matcher._new_SP, C->out_preserve_stack_slots()) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2286
    reg = OptoReg::add(reg, -1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2287
    tty->print_cr("#r%3.3d %s+%2d: outgoing argument",reg,fp,reg2offset_unchecked(reg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2288
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2289
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2290
  // Outgoing new preserve area
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2291
  while( reg > _matcher._new_SP ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2292
    reg = OptoReg::add(reg, -1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2293
    tty->print_cr("#r%3.3d %s+%2d: new out preserve",reg,fp,reg2offset_unchecked(reg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2294
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2295
  tty->print_cr("#");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2296
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2297
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2298
void PhaseChaitin::dump_bb( uint pre_order ) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2299
  tty->print_cr("---dump of B%d---",pre_order);
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  2300
  for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  2301
    Block* block = _cfg.get_block(i);
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  2302
    if (block->_pre_order == pre_order) {
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  2303
      dump(block);
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  2304
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2305
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2306
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2307
7441
47ea904dba6a 7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents: 7397
diff changeset
  2308
void PhaseChaitin::dump_lrg( uint lidx, bool defs_only ) const {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2309
  tty->print_cr("---dump of L%d---",lidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2310
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2311
  if (_ifg) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2312
    if (lidx >= _lrg_map.max_lrg_id()) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2313
      tty->print("Attempt to print live range index beyond max live range.\n");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2314
      return;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2315
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2316
    tty->print("L%d: ",lidx);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2317
    if (lidx < _ifg->_maxlrg) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2318
      lrgs(lidx).dump();
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2319
    } else {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2320
      tty->print_cr("new LRG");
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2321
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2322
  }
7441
47ea904dba6a 7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents: 7397
diff changeset
  2323
  if( _ifg && lidx < _ifg->_maxlrg) {
47ea904dba6a 7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents: 7397
diff changeset
  2324
    tty->print("Neighbors: %d - ", _ifg->neighbor_cnt(lidx));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2325
    _ifg->neighbors(lidx)->dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2326
    tty->cr();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2327
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2328
  // For all blocks
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  2329
  for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  2330
    Block* block = _cfg.get_block(i);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2331
    int dump_once = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2332
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2333
    // For all instructions
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
  2334
    for( uint j = 0; j < block->number_of_nodes(); j++ ) {
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
  2335
      Node *n = block->get_node(j);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2336
      if (_lrg_map.find_const(n) == lidx) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2337
        if (!dump_once++) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2338
          tty->cr();
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  2339
          block->dump_head(&_cfg);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2340
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2341
        dump(n);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2342
        continue;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2343
      }
7441
47ea904dba6a 7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents: 7397
diff changeset
  2344
      if (!defs_only) {
47ea904dba6a 7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents: 7397
diff changeset
  2345
        uint cnt = n->req();
47ea904dba6a 7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents: 7397
diff changeset
  2346
        for( uint k = 1; k < cnt; k++ ) {
47ea904dba6a 7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents: 7397
diff changeset
  2347
          Node *m = n->in(k);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2348
          if (!m)  {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2349
            continue;  // be robust in the dumper
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2350
          }
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2351
          if (_lrg_map.find_const(m) == lidx) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  2352
            if (!dump_once++) {
7441
47ea904dba6a 7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents: 7397
diff changeset
  2353
              tty->cr();
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  2354
              block->dump_head(&_cfg);
7441
47ea904dba6a 7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents: 7397
diff changeset
  2355
            }
47ea904dba6a 7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents: 7397
diff changeset
  2356
            dump(n);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2357
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2358
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2359
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2360
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2361
  } // End of per-block dump
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2362
  tty->cr();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2363
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2364
#endif // not PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2365
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2366
int PhaseChaitin::_final_loads  = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2367
int PhaseChaitin::_final_stores = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2368
int PhaseChaitin::_final_memoves= 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2369
int PhaseChaitin::_final_copies = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2370
double PhaseChaitin::_final_load_cost  = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2371
double PhaseChaitin::_final_store_cost = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2372
double PhaseChaitin::_final_memove_cost= 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2373
double PhaseChaitin::_final_copy_cost  = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2374
int PhaseChaitin::_conserv_coalesce = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2375
int PhaseChaitin::_conserv_coalesce_pair = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2376
int PhaseChaitin::_conserv_coalesce_trie = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2377
int PhaseChaitin::_conserv_coalesce_quad = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2378
int PhaseChaitin::_post_alloc = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2379
int PhaseChaitin::_lost_opp_pp_coalesce = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2380
int PhaseChaitin::_lost_opp_cflow_coalesce = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2381
int PhaseChaitin::_used_cisc_instructions   = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2382
int PhaseChaitin::_unused_cisc_instructions = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2383
int PhaseChaitin::_allocator_attempts       = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2384
int PhaseChaitin::_allocator_successes      = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2385
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2386
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2387
uint PhaseChaitin::_high_pressure           = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2388
uint PhaseChaitin::_low_pressure            = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2389
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2390
void PhaseChaitin::print_chaitin_statistics() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2391
  tty->print_cr("Inserted %d spill loads, %d spill stores, %d mem-mem moves and %d copies.", _final_loads, _final_stores, _final_memoves, _final_copies);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2392
  tty->print_cr("Total load cost= %6.0f, store cost = %6.0f, mem-mem cost = %5.2f, copy cost = %5.0f.", _final_load_cost, _final_store_cost, _final_memove_cost, _final_copy_cost);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2393
  tty->print_cr("Adjusted spill cost = %7.0f.",
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2394
                _final_load_cost*4.0 + _final_store_cost  * 2.0 +
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2395
                _final_copy_cost*1.0 + _final_memove_cost*12.0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2396
  tty->print("Conservatively coalesced %d copies, %d pairs",
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2397
                _conserv_coalesce, _conserv_coalesce_pair);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2398
  if( _conserv_coalesce_trie || _conserv_coalesce_quad )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2399
    tty->print(", %d tries, %d quads", _conserv_coalesce_trie, _conserv_coalesce_quad);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2400
  tty->print_cr(", %d post alloc.", _post_alloc);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2401
  if( _lost_opp_pp_coalesce || _lost_opp_cflow_coalesce )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2402
    tty->print_cr("Lost coalesce opportunity, %d private-private, and %d cflow interfered.",
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2403
                  _lost_opp_pp_coalesce, _lost_opp_cflow_coalesce );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2404
  if( _used_cisc_instructions || _unused_cisc_instructions )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2405
    tty->print_cr("Used cisc instruction  %d,  remained in register %d",
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2406
                   _used_cisc_instructions, _unused_cisc_instructions);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2407
  if( _allocator_successes != 0 )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2408
    tty->print_cr("Average allocation trips %f", (float)_allocator_attempts/(float)_allocator_successes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2409
  tty->print_cr("High Pressure Blocks = %d, Low Pressure Blocks = %d", _high_pressure, _low_pressure);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2410
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2411
#endif // not PRODUCT