/*

 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#include "precompiled.hpp"

#include "asm/assembler.inline.hpp"

#include "compiler/disassembler.hpp"

#include "gc_interface/collectedHeap.inline.hpp"

#include "interpreter/interpreter.hpp"

#include "memory/cardTableModRefBS.hpp"

#include "memory/resourceArea.hpp"

#include "prims/methodHandles.hpp"

#include "runtime/biasedLocking.hpp"

#include "runtime/interfaceSupport.hpp"

#include "runtime/objectMonitor.hpp"

#include "runtime/os.hpp"

#include "runtime/sharedRuntime.hpp"

#include "runtime/stubRoutines.hpp"

#include "utilities/macros.hpp"

#if INCLUDE_ALL_GCS

#include "gc_implementation/g1/g1CollectedHeap.inline.hpp"

#include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"

#include "gc_implementation/g1/heapRegion.hpp"

#endif // INCLUDE_ALL_GCS

#ifdef PRODUCT

#define BLOCK_COMMENT(str) /* nothing */

#define STOP(error) stop(error)

#else

#define BLOCK_COMMENT(str) block_comment(str)

#define STOP(error) block_comment(error); stop(error)

#endif

// Convert the raw encoding form into the form expected by the

// constructor for Address.

Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {

  assert(scale == 0, "not supported");

  RelocationHolder rspec;

  if (disp_reloc != relocInfo::none) {

    rspec = Relocation::spec_simple(disp_reloc);

  }

  Register rindex = as_Register(index);

  if (rindex != G0) {

    Address madr(as_Register(base), rindex);

    madr._rspec = rspec;

    return madr;

  } else {

    Address madr(as_Register(base), disp);

    madr._rspec = rspec;

    return madr;

  }

}

Address Argument::address_in_frame() const {

  // Warning: In LP64 mode disp will occupy more than 10 bits, but

  //          op codes such as ld or ldx, only access disp() to get

  //          their simm13 argument.

  int disp = ((_number - Argument::n_register_parameters + frame::memory_parameter_word_sp_offset) * BytesPerWord) + STACK_BIAS;

  if (is_in())

    return Address(FP, disp); // In argument.

  else

    return Address(SP, disp); // Out argument.

}

static const char* argumentNames[][2] = {

  {"A0","P0"}, {"A1","P1"}, {"A2","P2"}, {"A3","P3"}, {"A4","P4"},

  {"A5","P5"}, {"A6","P6"}, {"A7","P7"}, {"A8","P8"}, {"A9","P9"},

  {"A(n>9)","P(n>9)"}

};

const char* Argument::name() const {

  int nofArgs = sizeof argumentNames / sizeof argumentNames[0];

  int num = number();

  if (num >= nofArgs)  num = nofArgs - 1;

  return argumentNames[num][is_in() ? 1 : 0];

}

#ifdef ASSERT

// On RISC, there's no benefit to verifying instruction boundaries.

bool AbstractAssembler::pd_check_instruction_mark() { return false; }

#endif

// Patch instruction inst at offset inst_pos to refer to dest_pos

// and return the resulting instruction.

// We should have pcs, not offsets, but since all is relative, it will work out

// OK.

int MacroAssembler::patched_branch(int dest_pos, int inst, int inst_pos) {

  int m; // mask for displacement field

  int v; // new value for displacement field

  const int word_aligned_ones = -4;

  switch (inv_op(inst)) {

  default: ShouldNotReachHere();

  case call_op:    m = wdisp(word_aligned_ones, 0, 30);  v = wdisp(dest_pos, inst_pos, 30); break;

  case branch_op:

    switch (inv_op2(inst)) {

      case fbp_op2:    m = wdisp(  word_aligned_ones, 0, 19);  v = wdisp(  dest_pos, inst_pos, 19); break;

      case bp_op2:     m = wdisp(  word_aligned_ones, 0, 19);  v = wdisp(  dest_pos, inst_pos, 19); break;

      case fb_op2:     m = wdisp(  word_aligned_ones, 0, 22);  v = wdisp(  dest_pos, inst_pos, 22); break;

      case br_op2:     m = wdisp(  word_aligned_ones, 0, 22);  v = wdisp(  dest_pos, inst_pos, 22); break;

      case cb_op2:     m = wdisp(  word_aligned_ones, 0, 22);  v = wdisp(  dest_pos, inst_pos, 22); break;

      case bpr_op2: {

        if (is_cbcond(inst)) {

          m = wdisp10(word_aligned_ones, 0);

          v = wdisp10(dest_pos, inst_pos);

        } else {

          m = wdisp16(word_aligned_ones, 0);

          v = wdisp16(dest_pos, inst_pos);

        }

        break;

      }

      default: ShouldNotReachHere();

    }

  }

  return  inst & ~m  |  v;

}

// Return the offset of the branch destionation of instruction inst

// at offset pos.

// Should have pcs, but since all is relative, it works out.

int MacroAssembler::branch_destination(int inst, int pos) {

  int r;

  switch (inv_op(inst)) {

  default: ShouldNotReachHere();

  case call_op:        r = inv_wdisp(inst, pos, 30);  break;

  case branch_op:

    switch (inv_op2(inst)) {

      case fbp_op2:    r = inv_wdisp(  inst, pos, 19);  break;

      case bp_op2:     r = inv_wdisp(  inst, pos, 19);  break;

      case fb_op2:     r = inv_wdisp(  inst, pos, 22);  break;

      case br_op2:     r = inv_wdisp(  inst, pos, 22);  break;

      case cb_op2:     r = inv_wdisp(  inst, pos, 22);  break;

      case bpr_op2: {

        if (is_cbcond(inst)) {

          r = inv_wdisp10(inst, pos);

        } else {

          r = inv_wdisp16(inst, pos);

        }

        break;

      }

      default: ShouldNotReachHere();

    }

  }

  return r;

}

void MacroAssembler::null_check(Register reg, int offset) {

  if (needs_explicit_null_check((intptr_t)offset)) {

    // provoke OS NULL exception if reg = NULL by

    // accessing M[reg] w/o changing any registers

    ld_ptr(reg, 0, G0);

  }

  else {

    // nothing to do, (later) access of M[reg + offset]

    // will provoke OS NULL exception if reg = NULL

  }

}

// Ring buffer jumps

#ifndef PRODUCT

void MacroAssembler::ret(  bool trace )   { if (trace) {

                                                    mov(I7, O7); // traceable register

                                                    JMP(O7, 2 * BytesPerInstWord);

                                                  } else {

                                                    jmpl( I7, 2 * BytesPerInstWord, G0 );

                                                  }

                                                }

void MacroAssembler::retl( bool trace )  { if (trace) JMP(O7, 2 * BytesPerInstWord);

                                                 else jmpl( O7, 2 * BytesPerInstWord, G0 ); }

#endif /* PRODUCT */

void MacroAssembler::jmp2(Register r1, Register r2, const char* file, int line ) {

  assert_not_delayed();

  // This can only be traceable if r1 & r2 are visible after a window save

  if (TraceJumps) {

#ifndef PRODUCT

    save_frame(0);

    verify_thread();

    ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);

    add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);

    sll(O0, exact_log2(4*sizeof(intptr_t)), O2);

    add(O2, O1, O1);

    add(r1->after_save(), r2->after_save(), O2);

    set((intptr_t)file, O3);

    set(line, O4);

    Label L;

    // get nearby pc, store jmp target

    call(L, relocInfo::none);  // No relocation for call to pc+0x8

    delayed()->st(O2, O1, 0);

    bind(L);

    // store nearby pc

    st(O7, O1, sizeof(intptr_t));

    // store file

    st(O3, O1, 2*sizeof(intptr_t));

    // store line

    st(O4, O1, 3*sizeof(intptr_t));

    add(O0, 1, O0);

    and3(O0, JavaThread::jump_ring_buffer_size  - 1, O0);

    st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));

    restore();

#endif /* PRODUCT */

  }

  jmpl(r1, r2, G0);

}

void MacroAssembler::jmp(Register r1, int offset, const char* file, int line ) {

  assert_not_delayed();

  // This can only be traceable if r1 is visible after a window save

  if (TraceJumps) {

#ifndef PRODUCT

    save_frame(0);

    verify_thread();

    ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);

    add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);

    sll(O0, exact_log2(4*sizeof(intptr_t)), O2);

    add(O2, O1, O1);

    add(r1->after_save(), offset, O2);

    set((intptr_t)file, O3);

    set(line, O4);

    Label L;

    // get nearby pc, store jmp target

    call(L, relocInfo::none);  // No relocation for call to pc+0x8

    delayed()->st(O2, O1, 0);

    bind(L);

    // store nearby pc

    st(O7, O1, sizeof(intptr_t));

    // store file

    st(O3, O1, 2*sizeof(intptr_t));

    // store line

    st(O4, O1, 3*sizeof(intptr_t));

    add(O0, 1, O0);

    and3(O0, JavaThread::jump_ring_buffer_size  - 1, O0);

    st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));

    restore();

#endif /* PRODUCT */

  }

  jmp(r1, offset);

}

// This code sequence is relocatable to any address, even on LP64.

void MacroAssembler::jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line) {

  assert_not_delayed();

  // Force fixed length sethi because NativeJump and NativeFarCall don't handle

  // variable length instruction streams.

  patchable_sethi(addrlit, temp);

  Address a(temp, addrlit.low10() + offset);  // Add the offset to the displacement.

  if (TraceJumps) {

#ifndef PRODUCT

    // Must do the add here so relocation can find the remainder of the

    // value to be relocated.

    add(a.base(), a.disp(), a.base(), addrlit.rspec(offset));

    save_frame(0);

    verify_thread();

    ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);

    add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);

    sll(O0, exact_log2(4*sizeof(intptr_t)), O2);

    add(O2, O1, O1);

    set((intptr_t)file, O3);

    set(line, O4);

    Label L;

    // get nearby pc, store jmp target

    call(L, relocInfo::none);  // No relocation for call to pc+0x8

    delayed()->st(a.base()->after_save(), O1, 0);

    bind(L);

    // store nearby pc

    st(O7, O1, sizeof(intptr_t));

    // store file

    st(O3, O1, 2*sizeof(intptr_t));

    // store line

    st(O4, O1, 3*sizeof(intptr_t));

    add(O0, 1, O0);

    and3(O0, JavaThread::jump_ring_buffer_size  - 1, O0);

    st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));

    restore();

    jmpl(a.base(), G0, d);

#else

    jmpl(a.base(), a.disp(), d);

#endif /* PRODUCT */

  } else {

    jmpl(a.base(), a.disp(), d);

  }

}

void MacroAssembler::jump(const AddressLiteral& addrlit, Register temp, int offset, const char* file, int line) {

  jumpl(addrlit, temp, G0, offset, file, line);

}

// Conditional breakpoint (for assertion checks in assembly code)

void MacroAssembler::breakpoint_trap(Condition c, CC cc) {

  trap(c, cc, G0, ST_RESERVED_FOR_USER_0);

}

// We want to use ST_BREAKPOINT here, but the debugger is confused by it.

void MacroAssembler::breakpoint_trap() {

  trap(ST_RESERVED_FOR_USER_0);

}

// flush windows (except current) using flushw instruction if avail.

void MacroAssembler::flush_windows() {

  if (VM_Version::v9_instructions_work())  flushw();

  else                                     flush_windows_trap();

}

// Write serialization page so VM thread can do a pseudo remote membar

// We use the current thread pointer to calculate a thread specific

// offset to write to within the page. This minimizes bus traffic

// due to cache line collision.

void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) {

  srl(thread, os::get_serialize_page_shift_count(), tmp2);

  if (Assembler::is_simm13(os::vm_page_size())) {

    and3(tmp2, (os::vm_page_size() - sizeof(int)), tmp2);

  }

  else {

    set((os::vm_page_size() - sizeof(int)), tmp1);

    and3(tmp2, tmp1, tmp2);

  }

  set(os::get_memory_serialize_page(), tmp1);

  st(G0, tmp1, tmp2);

}

void MacroAssembler::enter() {

  Unimplemented();

}

void MacroAssembler::leave() {

  Unimplemented();

}

void MacroAssembler::mult(Register s1, Register s2, Register d) {

  if(VM_Version::v9_instructions_work()) {

    mulx (s1, s2, d);

  } else {

    smul (s1, s2, d);

  }

}

void MacroAssembler::mult(Register s1, int simm13a, Register d) {

  if(VM_Version::v9_instructions_work()) {

    mulx (s1, simm13a, d);

  } else {

    smul (s1, simm13a, d);

  }

}

#ifdef ASSERT

void MacroAssembler::read_ccr_v8_assert(Register ccr_save) {

  const Register s1 = G3_scratch;

  const Register s2 = G4_scratch;

  Label get_psr_test;

  // Get the condition codes the V8 way.

  read_ccr_trap(s1);

  mov(ccr_save, s2);

  // This is a test of V8 which has icc but not xcc

  // so mask off the xcc bits

  and3(s2, 0xf, s2);

  // Compare condition codes from the V8 and V9 ways.

  subcc(s2, s1, G0);

  br(Assembler::notEqual, true, Assembler::pt, get_psr_test);

  delayed()->breakpoint_trap();

  bind(get_psr_test);

}

void MacroAssembler::write_ccr_v8_assert(Register ccr_save) {

  const Register s1 = G3_scratch;

  const Register s2 = G4_scratch;

  Label set_psr_test;

  // Write out the saved condition codes the V8 way

  write_ccr_trap(ccr_save, s1, s2);

  // Read back the condition codes using the V9 instruction

  rdccr(s1);

  mov(ccr_save, s2);

  // This is a test of V8 which has icc but not xcc

  // so mask off the xcc bits

  and3(s2, 0xf, s2);

  and3(s1, 0xf, s1);

  // Compare the V8 way with the V9 way.

  subcc(s2, s1, G0);

  br(Assembler::notEqual, true, Assembler::pt, set_psr_test);

  delayed()->breakpoint_trap();

  bind(set_psr_test);

}

#else

#define read_ccr_v8_assert(x)

#define write_ccr_v8_assert(x)

#endif // ASSERT

void MacroAssembler::read_ccr(Register ccr_save) {

  if (VM_Version::v9_instructions_work()) {

    rdccr(ccr_save);

    // Test code sequence used on V8.  Do not move above rdccr.

    read_ccr_v8_assert(ccr_save);

  } else {

    read_ccr_trap(ccr_save);

  }

}

void MacroAssembler::write_ccr(Register ccr_save) {

  if (VM_Version::v9_instructions_work()) {

    // Test code sequence used on V8.  Do not move below wrccr.

    write_ccr_v8_assert(ccr_save);

    wrccr(ccr_save);

  } else {

    const Register temp_reg1 = G3_scratch;

    const Register temp_reg2 = G4_scratch;

    write_ccr_trap(ccr_save, temp_reg1, temp_reg2);

  }

}

// Calls to C land

#ifdef ASSERT

// a hook for debugging

static Thread* reinitialize_thread() {

  return ThreadLocalStorage::thread();

}

#else

#define reinitialize_thread ThreadLocalStorage::thread

#endif

#ifdef ASSERT

address last_get_thread = NULL;

#endif

// call this when G2_thread is not known to be valid

void MacroAssembler::get_thread() {

  save_frame(0);                // to avoid clobbering O0

  mov(G1, L0);                  // avoid clobbering G1

  mov(G5_method, L1);           // avoid clobbering G5

  mov(G3, L2);                  // avoid clobbering G3 also

  mov(G4, L5);                  // avoid clobbering G4

#ifdef ASSERT

  AddressLiteral last_get_thread_addrlit(&last_get_thread);

  set(last_get_thread_addrlit, L3);

  inc(L4, get_pc(L4) + 2 * BytesPerInstWord); // skip getpc() code + inc + st_ptr to point L4 at call

  st_ptr(L4, L3, 0);

#endif

  call(CAST_FROM_FN_PTR(address, reinitialize_thread), relocInfo::runtime_call_type);

  delayed()->nop();

  mov(L0, G1);

  mov(L1, G5_method);

  mov(L2, G3);

  mov(L5, G4);

  restore(O0, 0, G2_thread);

}

static Thread* verify_thread_subroutine(Thread* gthread_value) {

  Thread* correct_value = ThreadLocalStorage::thread();

  guarantee(gthread_value == correct_value, "G2_thread value must be the thread");

  return correct_value;

}

void MacroAssembler::verify_thread() {

  if (VerifyThread) {

    // NOTE: this chops off the heads of the 64-bit O registers.

#ifdef CC_INTERP

    save_frame(0);

#else

    // make sure G2_thread contains the right value

    save_frame_and_mov(0, Lmethod, Lmethod);   // to avoid clobbering O0 (and propagate Lmethod for -Xprof)

    mov(G1, L1);                // avoid clobbering G1

    // G2 saved below

    mov(G3, L3);                // avoid clobbering G3

    mov(G4, L4);                // avoid clobbering G4

    mov(G5_method, L5);         // avoid clobbering G5_method

#endif /* CC_INTERP */

#if defined(COMPILER2) && !defined(_LP64)

    // Save & restore possible 64-bit Long arguments in G-regs

    srlx(G1,32,L0);

    srlx(G4,32,L6);

#endif

    call(CAST_FROM_FN_PTR(address,verify_thread_subroutine), relocInfo::runtime_call_type);

    delayed()->mov(G2_thread, O0);

    mov(L1, G1);                // Restore G1

    // G2 restored below

    mov(L3, G3);                // restore G3

    mov(L4, G4);                // restore G4

    mov(L5, G5_method);         // restore G5_method

#if defined(COMPILER2) && !defined(_LP64)

    // Save & restore possible 64-bit Long arguments in G-regs

    sllx(L0,32,G2);             // Move old high G1 bits high in G2

    srl(G1, 0,G1);              // Clear current high G1 bits

    or3 (G1,G2,G1);             // Recover 64-bit G1

    sllx(L6,32,G2);             // Move old high G4 bits high in G2

    srl(G4, 0,G4);              // Clear current high G4 bits

    or3 (G4,G2,G4);             // Recover 64-bit G4

#endif

    restore(O0, 0, G2_thread);

  }

}

void MacroAssembler::save_thread(const Register thread_cache) {

  verify_thread();