/*

 * Copyright (c) 2002, 2019, Oracle and/or its affiliates. All rights reserved.

 * Copyright (c) 2012, 2018 SAP SE. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#ifndef CPU_PPC_ASSEMBLER_PPC_HPP

#define CPU_PPC_ASSEMBLER_PPC_HPP

#include "asm/register.hpp"

// Address is an abstraction used to represent a memory location

// as used in assembler instructions.

// PPC instructions grok either baseReg + indexReg or baseReg + disp.

class Address {

 private:

  Register _base;         // Base register.

  Register _index;        // Index register.

  intptr_t _disp;         // Displacement.

 public:

  Address(Register b, Register i, address d = 0)

    : _base(b), _index(i), _disp((intptr_t)d) {

    assert(i == noreg || d == 0, "can't have both");

  }

  Address(Register b, address d = 0)

    : _base(b), _index(noreg), _disp((intptr_t)d) {}

  Address(Register b, intptr_t d)

    : _base(b), _index(noreg), _disp(d) {}

  Address(Register b, RegisterOrConstant roc)

    : _base(b), _index(noreg), _disp(0) {

    if (roc.is_constant()) _disp = roc.as_constant(); else _index = roc.as_register();

  }

  Address()

    : _base(noreg), _index(noreg), _disp(0) {}

  // accessors

  Register base()  const { return _base; }

  Register index() const { return _index; }

  int      disp()  const { return (int)_disp; }

  bool     is_const() const { return _base == noreg && _index == noreg; }

};

class AddressLiteral {

 private:

  address          _address;

  RelocationHolder _rspec;

  RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) {

    switch (rtype) {

    case relocInfo::external_word_type:

      return external_word_Relocation::spec(addr);

    case relocInfo::internal_word_type:

      return internal_word_Relocation::spec(addr);

    case relocInfo::opt_virtual_call_type:

      return opt_virtual_call_Relocation::spec();

    case relocInfo::static_call_type:

      return static_call_Relocation::spec();

    case relocInfo::runtime_call_type:

      return runtime_call_Relocation::spec();

    case relocInfo::none:

      return RelocationHolder();

    default:

      ShouldNotReachHere();

      return RelocationHolder();

    }

  }

 protected:

  // creation

  AddressLiteral() : _address(NULL), _rspec(NULL) {}

 public:

  AddressLiteral(address addr, RelocationHolder const& rspec)

    : _address(addr),

      _rspec(rspec) {}

  AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none)

    : _address((address) addr),

      _rspec(rspec_from_rtype(rtype, (address) addr)) {}

  AddressLiteral(oop* addr, relocInfo::relocType rtype = relocInfo::none)

    : _address((address) addr),

      _rspec(rspec_from_rtype(rtype, (address) addr)) {}

  intptr_t value() const { return (intptr_t) _address; }

  const RelocationHolder& rspec() const { return _rspec; }

};

// Argument is an abstraction used to represent an outgoing

// actual argument or an incoming formal parameter, whether

// it resides in memory or in a register, in a manner consistent

// with the PPC Application Binary Interface, or ABI. This is

// often referred to as the native or C calling convention.

class Argument {

 private:

  int _number;  // The number of the argument.

 public:

  enum {

    // Only 8 registers may contain integer parameters.

    n_register_parameters = 8,

    // Can have up to 8 floating registers.

    n_float_register_parameters = 8,

    // PPC C calling conventions.

    // The first eight arguments are passed in int regs if they are int.

    n_int_register_parameters_c = 8,

    // The first thirteen float arguments are passed in float regs.

    n_float_register_parameters_c = 13,

    // Only the first 8 parameters are not placed on the stack. Aix disassembly

    // shows that xlC places all float args after argument 8 on the stack AND

    // in a register. This is not documented, but we follow this convention, too.

    n_regs_not_on_stack_c = 8,

  };

  // creation

  Argument(int number) : _number(number) {}

  int  number() const { return _number; }

  // Locating register-based arguments:

  bool is_register() const { return _number < n_register_parameters; }

  Register as_register() const {

    assert(is_register(), "must be a register argument");

    return as_Register(number() + R3_ARG1->encoding());

  }

};

#if !defined(ABI_ELFv2)

// A ppc64 function descriptor.

struct FunctionDescriptor {

 private:

  address _entry;

  address _toc;

  address _env;

 public:

  inline address entry() const { return _entry; }

  inline address toc()   const { return _toc; }

  inline address env()   const { return _env; }

  inline void set_entry(address entry) { _entry = entry; }

  inline void set_toc(  address toc)   { _toc   = toc; }

  inline void set_env(  address env)   { _env   = env; }

  inline static ByteSize entry_offset() { return byte_offset_of(FunctionDescriptor, _entry); }

  inline static ByteSize toc_offset()   { return byte_offset_of(FunctionDescriptor, _toc); }

  inline static ByteSize env_offset()   { return byte_offset_of(FunctionDescriptor, _env); }

  // Friend functions can be called without loading toc and env.

  enum {

    friend_toc = 0xcafe,

    friend_env = 0xc0de

  };

  inline bool is_friend_function() const {

    return (toc() == (address) friend_toc) && (env() == (address) friend_env);

  }

  // Constructor for stack-allocated instances.

  FunctionDescriptor() {

    _entry = (address) 0xbad;

    _toc   = (address) 0xbad;

    _env   = (address) 0xbad;

  }

};

#endif

// The PPC Assembler: Pure assembler doing NO optimizations on the

// instruction level; i.e., what you write is what you get. The

// Assembler is generating code into a CodeBuffer.

class Assembler : public AbstractAssembler {

 protected:

  // Displacement routines

  static int  patched_branch(int dest_pos, int inst, int inst_pos);

  static int  branch_destination(int inst, int pos);

  friend class AbstractAssembler;

  // Code patchers need various routines like inv_wdisp()

  friend class NativeInstruction;

  friend class NativeGeneralJump;

  friend class Relocation;

 public:

  enum shifts {

    XO_21_29_SHIFT = 2,

    XO_21_30_SHIFT = 1,

    XO_27_29_SHIFT = 2,

    XO_30_31_SHIFT = 0,

    SPR_5_9_SHIFT  = 11u, // SPR_5_9 field in bits 11 -- 15

    SPR_0_4_SHIFT  = 16u, // SPR_0_4 field in bits 16 -- 20

    RS_SHIFT       = 21u, // RS field in bits 21 -- 25

    OPCODE_SHIFT   = 26u, // opcode in bits 26 -- 31

  };

  enum opcdxos_masks {

    XL_FORM_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),

    ADDI_OPCODE_MASK    = (63u << OPCODE_SHIFT),

    ADDIS_OPCODE_MASK   = (63u << OPCODE_SHIFT),

    BXX_OPCODE_MASK     = (63u << OPCODE_SHIFT),

    BCXX_OPCODE_MASK    = (63u << OPCODE_SHIFT),

    // trap instructions

    TDI_OPCODE_MASK     = (63u << OPCODE_SHIFT),

    TWI_OPCODE_MASK     = (63u << OPCODE_SHIFT),

    TD_OPCODE_MASK      = (63u << OPCODE_SHIFT) | (1023u << 1),

    TW_OPCODE_MASK      = (63u << OPCODE_SHIFT) | (1023u << 1),

    LD_OPCODE_MASK      = (63u << OPCODE_SHIFT) | (3u << XO_30_31_SHIFT), // DS-FORM

    STD_OPCODE_MASK     = LD_OPCODE_MASK,

    STDU_OPCODE_MASK    = STD_OPCODE_MASK,

    STDX_OPCODE_MASK    = (63u << OPCODE_SHIFT) | (1023u << 1),

    STDUX_OPCODE_MASK   = STDX_OPCODE_MASK,

    STW_OPCODE_MASK     = (63u << OPCODE_SHIFT),

    STWU_OPCODE_MASK    = STW_OPCODE_MASK,

    STWX_OPCODE_MASK    = (63u << OPCODE_SHIFT) | (1023u << 1),

    STWUX_OPCODE_MASK   = STWX_OPCODE_MASK,

    MTCTR_OPCODE_MASK   = ~(31u << RS_SHIFT),

    ORI_OPCODE_MASK     = (63u << OPCODE_SHIFT),

    ORIS_OPCODE_MASK    = (63u << OPCODE_SHIFT),

    RLDICR_OPCODE_MASK  = (63u << OPCODE_SHIFT) | (7u << XO_27_29_SHIFT)

  };

  enum opcdxos {

    ADD_OPCODE    = (31u << OPCODE_SHIFT | 266u << 1),

    ADDC_OPCODE   = (31u << OPCODE_SHIFT |  10u << 1),

    ADDI_OPCODE   = (14u << OPCODE_SHIFT),

    ADDIS_OPCODE  = (15u << OPCODE_SHIFT),

    ADDIC__OPCODE = (13u << OPCODE_SHIFT),

    ADDE_OPCODE   = (31u << OPCODE_SHIFT | 138u << 1),

    ADDME_OPCODE  = (31u << OPCODE_SHIFT | 234u << 1),

    ADDZE_OPCODE  = (31u << OPCODE_SHIFT | 202u << 1),

    SUBF_OPCODE   = (31u << OPCODE_SHIFT |  40u << 1),

    SUBFC_OPCODE  = (31u << OPCODE_SHIFT |   8u << 1),

    SUBFE_OPCODE  = (31u << OPCODE_SHIFT | 136u << 1),

    SUBFIC_OPCODE = (8u  << OPCODE_SHIFT),

    SUBFME_OPCODE = (31u << OPCODE_SHIFT | 232u << 1),

    SUBFZE_OPCODE = (31u << OPCODE_SHIFT | 200u << 1),

    DIVW_OPCODE   = (31u << OPCODE_SHIFT | 491u << 1),

    MULLW_OPCODE  = (31u << OPCODE_SHIFT | 235u << 1),

    MULHW_OPCODE  = (31u << OPCODE_SHIFT |  75u << 1),

    MULHWU_OPCODE = (31u << OPCODE_SHIFT |  11u << 1),

    MULLI_OPCODE  = (7u  << OPCODE_SHIFT),

    AND_OPCODE    = (31u << OPCODE_SHIFT |  28u << 1),

    ANDI_OPCODE   = (28u << OPCODE_SHIFT),

    ANDIS_OPCODE  = (29u << OPCODE_SHIFT),

    ANDC_OPCODE   = (31u << OPCODE_SHIFT |  60u << 1),

    ORC_OPCODE    = (31u << OPCODE_SHIFT | 412u << 1),

    OR_OPCODE     = (31u << OPCODE_SHIFT | 444u << 1),

    ORI_OPCODE    = (24u << OPCODE_SHIFT),

    ORIS_OPCODE   = (25u << OPCODE_SHIFT),

    XOR_OPCODE    = (31u << OPCODE_SHIFT | 316u << 1),

    XORI_OPCODE   = (26u << OPCODE_SHIFT),

    XORIS_OPCODE  = (27u << OPCODE_SHIFT),

    NEG_OPCODE    = (31u << OPCODE_SHIFT | 104u << 1),

    RLWINM_OPCODE = (21u << OPCODE_SHIFT),

    CLRRWI_OPCODE = RLWINM_OPCODE,

    CLRLWI_OPCODE = RLWINM_OPCODE,

    RLWIMI_OPCODE = (20u << OPCODE_SHIFT),

    SLW_OPCODE    = (31u << OPCODE_SHIFT |  24u << 1),

    SLWI_OPCODE   = RLWINM_OPCODE,

    SRW_OPCODE    = (31u << OPCODE_SHIFT | 536u << 1),

    SRWI_OPCODE   = RLWINM_OPCODE,

    SRAW_OPCODE   = (31u << OPCODE_SHIFT | 792u << 1),

    SRAWI_OPCODE  = (31u << OPCODE_SHIFT | 824u << 1),

    CMP_OPCODE    = (31u << OPCODE_SHIFT |   0u << 1),

    CMPI_OPCODE   = (11u << OPCODE_SHIFT),

    CMPL_OPCODE   = (31u << OPCODE_SHIFT |  32u << 1),

    CMPLI_OPCODE  = (10u << OPCODE_SHIFT),

    CMPRB_OPCODE  = (31u << OPCODE_SHIFT | 192u << 1),

    CMPEQB_OPCODE = (31u << OPCODE_SHIFT | 224u << 1),

    ISEL_OPCODE   = (31u << OPCODE_SHIFT |  15u << 1),

    // Special purpose registers

    MTSPR_OPCODE  = (31u << OPCODE_SHIFT | 467u << 1),

    MFSPR_OPCODE  = (31u << OPCODE_SHIFT | 339u << 1),

    MTXER_OPCODE  = (MTSPR_OPCODE | 1 << SPR_0_4_SHIFT),

    MFXER_OPCODE  = (MFSPR_OPCODE | 1 << SPR_0_4_SHIFT),

    MTDSCR_OPCODE = (MTSPR_OPCODE | 3 << SPR_0_4_SHIFT),

    MFDSCR_OPCODE = (MFSPR_OPCODE | 3 << SPR_0_4_SHIFT),

    MTLR_OPCODE   = (MTSPR_OPCODE | 8 << SPR_0_4_SHIFT),

    MFLR_OPCODE   = (MFSPR_OPCODE | 8 << SPR_0_4_SHIFT),

    MTCTR_OPCODE  = (MTSPR_OPCODE | 9 << SPR_0_4_SHIFT),

    MFCTR_OPCODE  = (MFSPR_OPCODE | 9 << SPR_0_4_SHIFT),

    // Attention: Higher and lower half are inserted in reversed order.

    MTTFHAR_OPCODE   = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),

    MFTFHAR_OPCODE   = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),

    MTTFIAR_OPCODE   = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 1 << SPR_0_4_SHIFT),

    MFTFIAR_OPCODE   = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 1 << SPR_0_4_SHIFT),

    MTTEXASR_OPCODE  = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 2 << SPR_0_4_SHIFT),

    MFTEXASR_OPCODE  = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 2 << SPR_0_4_SHIFT),

    MTTEXASRU_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 3 << SPR_0_4_SHIFT),

    MFTEXASRU_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 3 << SPR_0_4_SHIFT),

    MTVRSAVE_OPCODE  = (MTSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),

    MFVRSAVE_OPCODE  = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),

    MFTB_OPCODE   = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 12 << SPR_0_4_SHIFT),

    MTCRF_OPCODE  = (31u << OPCODE_SHIFT | 144u << 1),

    MFCR_OPCODE   = (31u << OPCODE_SHIFT | 19u << 1),

    MCRF_OPCODE   = (19u << OPCODE_SHIFT | 0u << 1),

    SETB_OPCODE   = (31u << OPCODE_SHIFT | 128u << 1),

    // condition register logic instructions

    CRAND_OPCODE  = (19u << OPCODE_SHIFT | 257u << 1),

    CRNAND_OPCODE = (19u << OPCODE_SHIFT | 225u << 1),

    CROR_OPCODE   = (19u << OPCODE_SHIFT | 449u << 1),

    CRXOR_OPCODE  = (19u << OPCODE_SHIFT | 193u << 1),

    CRNOR_OPCODE  = (19u << OPCODE_SHIFT |  33u << 1),

    CREQV_OPCODE  = (19u << OPCODE_SHIFT | 289u << 1),

    CRANDC_OPCODE = (19u << OPCODE_SHIFT | 129u << 1),

    CRORC_OPCODE  = (19u << OPCODE_SHIFT | 417u << 1),

    BCLR_OPCODE   = (19u << OPCODE_SHIFT | 16u << 1),

    BXX_OPCODE      = (18u << OPCODE_SHIFT),

    BCXX_OPCODE     = (16u << OPCODE_SHIFT),

    // CTR-related opcodes

    BCCTR_OPCODE  = (19u << OPCODE_SHIFT | 528u << 1),

    LWZ_OPCODE   = (32u << OPCODE_SHIFT),

    LWZX_OPCODE  = (31u << OPCODE_SHIFT |  23u << 1),

    LWZU_OPCODE  = (33u << OPCODE_SHIFT),

    LWBRX_OPCODE = (31u << OPCODE_SHIFT |  534 << 1),

    LHA_OPCODE   = (42u << OPCODE_SHIFT),

    LHAX_OPCODE  = (31u << OPCODE_SHIFT | 343u << 1),

    LHAU_OPCODE  = (43u << OPCODE_SHIFT),

    LHZ_OPCODE   = (40u << OPCODE_SHIFT),

    LHZX_OPCODE  = (31u << OPCODE_SHIFT | 279u << 1),

    LHZU_OPCODE  = (41u << OPCODE_SHIFT),

    LHBRX_OPCODE = (31u << OPCODE_SHIFT |  790 << 1),

    LBZ_OPCODE   = (34u << OPCODE_SHIFT),

    LBZX_OPCODE  = (31u << OPCODE_SHIFT |  87u << 1),

    LBZU_OPCODE  = (35u << OPCODE_SHIFT),

    STW_OPCODE   = (36u << OPCODE_SHIFT),

    STWX_OPCODE  = (31u << OPCODE_SHIFT | 151u << 1),

    STWU_OPCODE  = (37u << OPCODE_SHIFT),

    STWUX_OPCODE = (31u << OPCODE_SHIFT | 183u << 1),

    STWBRX_OPCODE = (31u << OPCODE_SHIFT | 662u << 1),

    STH_OPCODE   = (44u << OPCODE_SHIFT),

    STHX_OPCODE  = (31u << OPCODE_SHIFT | 407u << 1),

    STHU_OPCODE  = (45u << OPCODE_SHIFT),

    STHBRX_OPCODE = (31u << OPCODE_SHIFT | 918u << 1),

    STB_OPCODE   = (38u << OPCODE_SHIFT),

    STBX_OPCODE  = (31u << OPCODE_SHIFT | 215u << 1),

    STBU_OPCODE  = (39u << OPCODE_SHIFT),

    EXTSB_OPCODE = (31u << OPCODE_SHIFT | 954u << 1),

    EXTSH_OPCODE = (31u << OPCODE_SHIFT | 922u << 1),

    EXTSW_OPCODE = (31u << OPCODE_SHIFT | 986u << 1),               // X-FORM

    // 32 bit opcode encodings

    LWA_OPCODE    = (58u << OPCODE_SHIFT |   2u << XO_30_31_SHIFT), // DS-FORM

    LWAX_OPCODE   = (31u << OPCODE_SHIFT | 341u << XO_21_30_SHIFT), // X-FORM

    CNTLZW_OPCODE = (31u << OPCODE_SHIFT |  26u << XO_21_30_SHIFT), // X-FORM

    CNTTZW_OPCODE = (31u << OPCODE_SHIFT | 538u << XO_21_30_SHIFT), // X-FORM

    // 64 bit opcode encodings

    LD_OPCODE     = (58u << OPCODE_SHIFT |   0u << XO_30_31_SHIFT), // DS-FORM

    LDU_OPCODE    = (58u << OPCODE_SHIFT |   1u << XO_30_31_SHIFT), // DS-FORM

    LDX_OPCODE    = (31u << OPCODE_SHIFT |  21u << XO_21_30_SHIFT), // X-FORM

    LDBRX_OPCODE  = (31u << OPCODE_SHIFT | 532u << 1),              // X-FORM

    STD_OPCODE    = (62u << OPCODE_SHIFT |   0u << XO_30_31_SHIFT), // DS-FORM

    STDU_OPCODE   = (62u << OPCODE_SHIFT |   1u << XO_30_31_SHIFT), // DS-FORM

    STDUX_OPCODE  = (31u << OPCODE_SHIFT | 181u << 1),              // X-FORM

    STDX_OPCODE   = (31u << OPCODE_SHIFT | 149u << XO_21_30_SHIFT), // X-FORM

    STDBRX_OPCODE = (31u << OPCODE_SHIFT | 660u << 1),              // X-FORM

    RLDICR_OPCODE = (30u << OPCODE_SHIFT |   1u << XO_27_29_SHIFT), // MD-FORM

    RLDICL_OPCODE = (30u << OPCODE_SHIFT |   0u << XO_27_29_SHIFT), // MD-FORM

    RLDIC_OPCODE  = (30u << OPCODE_SHIFT |   2u << XO_27_29_SHIFT), // MD-FORM

    RLDIMI_OPCODE = (30u << OPCODE_SHIFT |   3u << XO_27_29_SHIFT), // MD-FORM

    SRADI_OPCODE  = (31u << OPCODE_SHIFT | 413u << XO_21_29_SHIFT), // XS-FORM

    SLD_OPCODE    = (31u << OPCODE_SHIFT |  27u << 1),              // X-FORM

    SRD_OPCODE    = (31u << OPCODE_SHIFT | 539u << 1),              // X-FORM

    SRAD_OPCODE   = (31u << OPCODE_SHIFT | 794u << 1),              // X-FORM

    MULLD_OPCODE  = (31u << OPCODE_SHIFT | 233u << 1),              // XO-FORM

    MULHD_OPCODE  = (31u << OPCODE_SHIFT |  73u << 1),              // XO-FORM

    MULHDU_OPCODE = (31u << OPCODE_SHIFT |   9u << 1),              // XO-FORM

    DIVD_OPCODE   = (31u << OPCODE_SHIFT | 489u << 1),              // XO-FORM

    CNTLZD_OPCODE = (31u << OPCODE_SHIFT |  58u << XO_21_30_SHIFT), // X-FORM

    CNTTZD_OPCODE = (31u << OPCODE_SHIFT | 570u << XO_21_30_SHIFT), // X-FORM

    NAND_OPCODE   = (31u << OPCODE_SHIFT | 476u << XO_21_30_SHIFT), // X-FORM

    NOR_OPCODE    = (31u << OPCODE_SHIFT | 124u << XO_21_30_SHIFT), // X-FORM

    // opcodes only used for floating arithmetic

    FADD_OPCODE   = (63u << OPCODE_SHIFT |  21u << 1),

    FADDS_OPCODE  = (59u << OPCODE_SHIFT |  21u << 1),

    FCMPU_OPCODE  = (63u << OPCODE_SHIFT |  00u << 1),

    FDIV_OPCODE   = (63u << OPCODE_SHIFT |  18u << 1),

    FDIVS_OPCODE  = (59u << OPCODE_SHIFT |  18u << 1),

    FMR_OPCODE    = (63u << OPCODE_SHIFT |  72u << 1),

    // These are special Power6 opcodes, reused for "lfdepx" and "stfdepx"

    // on Power7.  Do not use.

    // MFFGPR_OPCODE  = (31u << OPCODE_SHIFT | 607u << 1),

    // MFTGPR_OPCODE  = (31u << OPCODE_SHIFT | 735u << 1),

    CMPB_OPCODE    = (31u << OPCODE_SHIFT |  508  << 1),

    POPCNTB_OPCODE = (31u << OPCODE_SHIFT |  122  << 1),

    POPCNTW_OPCODE = (31u << OPCODE_SHIFT |  378  << 1),

    POPCNTD_OPCODE = (31u << OPCODE_SHIFT |  506  << 1),

    FABS_OPCODE    = (63u << OPCODE_SHIFT |  264u << 1),

    FNABS_OPCODE   = (63u << OPCODE_SHIFT |  136u << 1),

    FMUL_OPCODE    = (63u << OPCODE_SHIFT |   25u << 1),

    FMULS_OPCODE   = (59u << OPCODE_SHIFT |   25u << 1),

    FNEG_OPCODE    = (63u << OPCODE_SHIFT |   40u << 1),

    FSUB_OPCODE    = (63u << OPCODE_SHIFT |   20u << 1),

    FSUBS_OPCODE   = (59u << OPCODE_SHIFT |   20u << 1),

    // PPC64-internal FPU conversion opcodes

    FCFID_OPCODE   = (63u << OPCODE_SHIFT |  846u << 1),

    FCFIDS_OPCODE  = (59u << OPCODE_SHIFT |  846u << 1),

    FCTID_OPCODE   = (63u << OPCODE_SHIFT |  814u << 1),

    FCTIDZ_OPCODE  = (63u << OPCODE_SHIFT |  815u << 1),

    FCTIW_OPCODE   = (63u << OPCODE_SHIFT |   14u << 1),

    FCTIWZ_OPCODE  = (63u << OPCODE_SHIFT |   15u << 1),

    FRSP_OPCODE    = (63u << OPCODE_SHIFT |   12u << 1),

    // Fused multiply-accumulate instructions.

    FMADD_OPCODE   = (63u << OPCODE_SHIFT |   29u << 1),

    FMADDS_OPCODE  = (59u << OPCODE_SHIFT |   29u << 1),

    FMSUB_OPCODE   = (63u << OPCODE_SHIFT |   28u << 1),

    FMSUBS_OPCODE  = (59u << OPCODE_SHIFT |   28u << 1),

    FNMADD_OPCODE  = (63u << OPCODE_SHIFT |   31u << 1),

    FNMADDS_OPCODE = (59u << OPCODE_SHIFT |   31u << 1),

    FNMSUB_OPCODE  = (63u << OPCODE_SHIFT |   30u << 1),

    FNMSUBS_OPCODE = (59u << OPCODE_SHIFT |   30u << 1),

    LFD_OPCODE     = (50u << OPCODE_SHIFT |   00u << 1),

    LFDU_OPCODE    = (51u << OPCODE_SHIFT |   00u << 1),

    LFDX_OPCODE    = (31u << OPCODE_SHIFT |  599u << 1),

    LFS_OPCODE     = (48u << OPCODE_SHIFT |   00u << 1),

    LFSU_OPCODE    = (49u << OPCODE_SHIFT |   00u << 1),

    LFSX_OPCODE    = (31u << OPCODE_SHIFT |  535u << 1),

    STFD_OPCODE    = (54u << OPCODE_SHIFT |   00u << 1),

    STFDU_OPCODE   = (55u << OPCODE_SHIFT |   00u << 1),

    STFDX_OPCODE   = (31u << OPCODE_SHIFT |  727u << 1),

    STFS_OPCODE    = (52u << OPCODE_SHIFT |   00u << 1),

    STFSU_OPCODE   = (53u << OPCODE_SHIFT |   00u << 1),

    STFSX_OPCODE   = (31u << OPCODE_SHIFT |  663u << 1),

    FSQRT_OPCODE   = (63u << OPCODE_SHIFT |   22u << 1),            // A-FORM

    FSQRTS_OPCODE  = (59u << OPCODE_SHIFT |   22u << 1),            // A-FORM

    // Vector instruction support for >= Power6

    // Vector Storage Access

    LVEBX_OPCODE   = (31u << OPCODE_SHIFT |    7u << 1),

    LVEHX_OPCODE   = (31u << OPCODE_SHIFT |   39u << 1),

    LVEWX_OPCODE   = (31u << OPCODE_SHIFT |   71u << 1),

    LVX_OPCODE     = (31u << OPCODE_SHIFT |  103u << 1),

    LVXL_OPCODE    = (31u << OPCODE_SHIFT |  359u << 1),

    STVEBX_OPCODE  = (31u << OPCODE_SHIFT |  135u << 1),

    STVEHX_OPCODE  = (31u << OPCODE_SHIFT |  167u << 1),

    STVEWX_OPCODE  = (31u << OPCODE_SHIFT |  199u << 1),

    STVX_OPCODE    = (31u << OPCODE_SHIFT |  231u << 1),

    STVXL_OPCODE   = (31u << OPCODE_SHIFT |  487u << 1),

    LVSL_OPCODE    = (31u << OPCODE_SHIFT |    6u << 1),

    LVSR_OPCODE    = (31u << OPCODE_SHIFT |   38u << 1),

    // Vector-Scalar (VSX) instruction support.