/*

 * Copyright (c) 2003, 2011, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#include "precompiled.hpp"

#include "asm/assembler.hpp"

#include "assembler_sparc.inline.hpp"

#include "code/debugInfoRec.hpp"

#include "code/icBuffer.hpp"

#include "code/vtableStubs.hpp"

#include "interpreter/interpreter.hpp"

#include "oops/compiledICHolderOop.hpp"

#include "prims/jvmtiRedefineClassesTrace.hpp"

#include "runtime/sharedRuntime.hpp"

#include "runtime/vframeArray.hpp"

#include "vmreg_sparc.inline.hpp"

#ifdef COMPILER1

#include "c1/c1_Runtime1.hpp"

#endif

#ifdef COMPILER2

#include "opto/runtime.hpp"

#endif

#ifdef SHARK

#include "compiler/compileBroker.hpp"

#include "shark/sharkCompiler.hpp"

#endif

#define __ masm->

class RegisterSaver {

  // Used for saving volatile registers. This is Gregs, Fregs, I/L/O.

  // The Oregs are problematic. In the 32bit build the compiler can

  // have O registers live with 64 bit quantities. A window save will

  // cut the heads off of the registers. We have to do a very extensive

  // stack dance to save and restore these properly.

  // Note that the Oregs problem only exists if we block at either a polling

  // page exception a compiled code safepoint that was not originally a call

  // or deoptimize following one of these kinds of safepoints.

  // Lots of registers to save.  For all builds, a window save will preserve

  // the %i and %l registers.  For the 32-bit longs-in-two entries and 64-bit

  // builds a window-save will preserve the %o registers.  In the LION build

  // we need to save the 64-bit %o registers which requires we save them

  // before the window-save (as then they become %i registers and get their

  // heads chopped off on interrupt).  We have to save some %g registers here

  // as well.

  enum {

    // This frame's save area.  Includes extra space for the native call:

    // vararg's layout space and the like.  Briefly holds the caller's

    // register save area.

    call_args_area = frame::register_save_words_sp_offset +

                     frame::memory_parameter_word_sp_offset*wordSize,

    // Make sure save locations are always 8 byte aligned.

    // can't use round_to because it doesn't produce compile time constant

    start_of_extra_save_area = ((call_args_area + 7) & ~7),

    g1_offset = start_of_extra_save_area, // g-regs needing saving

    g3_offset = g1_offset+8,

    g4_offset = g3_offset+8,

    g5_offset = g4_offset+8,

    o0_offset = g5_offset+8,

    o1_offset = o0_offset+8,

    o2_offset = o1_offset+8,

    o3_offset = o2_offset+8,

    o4_offset = o3_offset+8,

    o5_offset = o4_offset+8,

    start_of_flags_save_area = o5_offset+8,

    ccr_offset = start_of_flags_save_area,

    fsr_offset = ccr_offset + 8,

    d00_offset = fsr_offset+8,  // Start of float save area

    register_save_size = d00_offset+8*32

  };

  public:

  static int Oexception_offset() { return o0_offset; };

  static int G3_offset() { return g3_offset; };

  static int G5_offset() { return g5_offset; };

  static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words);

  static void restore_live_registers(MacroAssembler* masm);

  // During deoptimization only the result register need to be restored

  // all the other values have already been extracted.

  static void restore_result_registers(MacroAssembler* masm);

};

OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) {

  // Record volatile registers as callee-save values in an OopMap so their save locations will be

  // propagated to the caller frame's RegisterMap during StackFrameStream construction (needed for

  // deoptimization; see compiledVFrame::create_stack_value).  The caller's I, L and O registers

  // are saved in register windows - I's and L's in the caller's frame and O's in the stub frame

  // (as the stub's I's) when the runtime routine called by the stub creates its frame.

  int i;

  // Always make the frame size 16 byte aligned.

  int frame_size = round_to(additional_frame_words + register_save_size, 16);

  // OopMap frame size is in c2 stack slots (sizeof(jint)) not bytes or words

  int frame_size_in_slots = frame_size / sizeof(jint);

  // CodeBlob frame size is in words.

  *total_frame_words = frame_size / wordSize;

  // OopMap* map = new OopMap(*total_frame_words, 0);

  OopMap* map = new OopMap(frame_size_in_slots, 0);

#if !defined(_LP64)

  // Save 64-bit O registers; they will get their heads chopped off on a 'save'.

  __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);

  __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);

  __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);

  __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);

  __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);

  __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);

#endif /* _LP64 */

  __ save(SP, -frame_size, SP);

#ifndef _LP64

  // Reload the 64 bit Oregs. Although they are now Iregs we load them

  // to Oregs here to avoid interrupts cutting off their heads

  __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);

  __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);

  __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);

  __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);

  __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);

  __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);

  __ stx(O0, SP, o0_offset+STACK_BIAS);

  map->set_callee_saved(VMRegImpl::stack2reg((o0_offset + 4)>>2), O0->as_VMReg());

  __ stx(O1, SP, o1_offset+STACK_BIAS);

  map->set_callee_saved(VMRegImpl::stack2reg((o1_offset + 4)>>2), O1->as_VMReg());

  __ stx(O2, SP, o2_offset+STACK_BIAS);

  map->set_callee_saved(VMRegImpl::stack2reg((o2_offset + 4)>>2), O2->as_VMReg());

  __ stx(O3, SP, o3_offset+STACK_BIAS);

  map->set_callee_saved(VMRegImpl::stack2reg((o3_offset + 4)>>2), O3->as_VMReg());

  __ stx(O4, SP, o4_offset+STACK_BIAS);

  map->set_callee_saved(VMRegImpl::stack2reg((o4_offset + 4)>>2), O4->as_VMReg());

  __ stx(O5, SP, o5_offset+STACK_BIAS);

  map->set_callee_saved(VMRegImpl::stack2reg((o5_offset + 4)>>2), O5->as_VMReg());

#endif /* _LP64 */

#ifdef _LP64

  int debug_offset = 0;

#else

  int debug_offset = 4;

#endif

  // Save the G's

  __ stx(G1, SP, g1_offset+STACK_BIAS);

  map->set_callee_saved(VMRegImpl::stack2reg((g1_offset + debug_offset)>>2), G1->as_VMReg());

  __ stx(G3, SP, g3_offset+STACK_BIAS);

  map->set_callee_saved(VMRegImpl::stack2reg((g3_offset + debug_offset)>>2), G3->as_VMReg());

  __ stx(G4, SP, g4_offset+STACK_BIAS);

  map->set_callee_saved(VMRegImpl::stack2reg((g4_offset + debug_offset)>>2), G4->as_VMReg());

  __ stx(G5, SP, g5_offset+STACK_BIAS);

  map->set_callee_saved(VMRegImpl::stack2reg((g5_offset + debug_offset)>>2), G5->as_VMReg());

  // This is really a waste but we'll keep things as they were for now

  if (true) {

#ifndef _LP64

    map->set_callee_saved(VMRegImpl::stack2reg((o0_offset)>>2), O0->as_VMReg()->next());

    map->set_callee_saved(VMRegImpl::stack2reg((o1_offset)>>2), O1->as_VMReg()->next());

    map->set_callee_saved(VMRegImpl::stack2reg((o2_offset)>>2), O2->as_VMReg()->next());

    map->set_callee_saved(VMRegImpl::stack2reg((o3_offset)>>2), O3->as_VMReg()->next());

    map->set_callee_saved(VMRegImpl::stack2reg((o4_offset)>>2), O4->as_VMReg()->next());

    map->set_callee_saved(VMRegImpl::stack2reg((o5_offset)>>2), O5->as_VMReg()->next());

    map->set_callee_saved(VMRegImpl::stack2reg((g1_offset)>>2), G1->as_VMReg()->next());

    map->set_callee_saved(VMRegImpl::stack2reg((g3_offset)>>2), G3->as_VMReg()->next());

    map->set_callee_saved(VMRegImpl::stack2reg((g4_offset)>>2), G4->as_VMReg()->next());

    map->set_callee_saved(VMRegImpl::stack2reg((g5_offset)>>2), G5->as_VMReg()->next());

#endif /* _LP64 */

  }

  // Save the flags

  __ rdccr( G5 );

  __ stx(G5, SP, ccr_offset+STACK_BIAS);

  __ stxfsr(SP, fsr_offset+STACK_BIAS);

  // Save all the FP registers: 32 doubles (32 floats correspond to the 2 halves of the first 16 doubles)

  int offset = d00_offset;

  for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) {

    FloatRegister f = as_FloatRegister(i);

    __ stf(FloatRegisterImpl::D,  f, SP, offset+STACK_BIAS);

    // Record as callee saved both halves of double registers (2 float registers).

    map->set_callee_saved(VMRegImpl::stack2reg(offset>>2), f->as_VMReg());

    map->set_callee_saved(VMRegImpl::stack2reg((offset + sizeof(float))>>2), f->as_VMReg()->next());

    offset += sizeof(double);

  }

  // And we're done.

  return map;

}

// Pop the current frame and restore all the registers that we

// saved.

void RegisterSaver::restore_live_registers(MacroAssembler* masm) {

  // Restore all the FP registers

  for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) {

    __ ldf(FloatRegisterImpl::D, SP, d00_offset+i*sizeof(float)+STACK_BIAS, as_FloatRegister(i));

  }

  __ ldx(SP, ccr_offset+STACK_BIAS, G1);

  __ wrccr (G1) ;

  // Restore the G's

  // Note that G2 (AKA GThread) must be saved and restored separately.

  // TODO-FIXME: save and restore some of the other ASRs, viz., %asi and %gsr.

  __ ldx(SP, g1_offset+STACK_BIAS, G1);

  __ ldx(SP, g3_offset+STACK_BIAS, G3);

  __ ldx(SP, g4_offset+STACK_BIAS, G4);

  __ ldx(SP, g5_offset+STACK_BIAS, G5);

#if !defined(_LP64)

  // Restore the 64-bit O's.

  __ ldx(SP, o0_offset+STACK_BIAS, O0);

  __ ldx(SP, o1_offset+STACK_BIAS, O1);

  __ ldx(SP, o2_offset+STACK_BIAS, O2);

  __ ldx(SP, o3_offset+STACK_BIAS, O3);

  __ ldx(SP, o4_offset+STACK_BIAS, O4);

  __ ldx(SP, o5_offset+STACK_BIAS, O5);

  // And temporarily place them in TLS

  __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);

  __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);

  __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);

  __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);

  __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);

  __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);

#endif /* _LP64 */

  // Restore flags

  __ ldxfsr(SP, fsr_offset+STACK_BIAS);

  __ restore();

#if !defined(_LP64)

  // Now reload the 64bit Oregs after we've restore the window.

  __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);

  __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);

  __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);

  __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);

  __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);

  __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);

#endif /* _LP64 */

}

// Pop the current frame and restore the registers that might be holding

// a result.

void RegisterSaver::restore_result_registers(MacroAssembler* masm) {

#if !defined(_LP64)

  // 32bit build returns longs in G1

  __ ldx(SP, g1_offset+STACK_BIAS, G1);

  // Retrieve the 64-bit O's.

  __ ldx(SP, o0_offset+STACK_BIAS, O0);

  __ ldx(SP, o1_offset+STACK_BIAS, O1);

  // and save to TLS

  __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);

  __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);

#endif /* _LP64 */

  __ ldf(FloatRegisterImpl::D, SP, d00_offset+STACK_BIAS, as_FloatRegister(0));

  __ restore();

#if !defined(_LP64)

  // Now reload the 64bit Oregs after we've restore the window.

  __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);

  __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);

#endif /* _LP64 */

}

// The java_calling_convention describes stack locations as ideal slots on

// a frame with no abi restrictions. Since we must observe abi restrictions

// (like the placement of the register window) the slots must be biased by

// the following value.

static int reg2offset(VMReg r) {

  return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;

}

// ---------------------------------------------------------------------------

// Read the array of BasicTypes from a signature, and compute where the

// arguments should go.  Values in the VMRegPair regs array refer to 4-byte (VMRegImpl::stack_slot_size)

// quantities.  Values less than VMRegImpl::stack0 are registers, those above

// refer to 4-byte stack slots.  All stack slots are based off of the window

// top.  VMRegImpl::stack0 refers to the first slot past the 16-word window,

// and VMRegImpl::stack0+1 refers to the memory word 4-byes higher.  Register

// values 0-63 (up to RegisterImpl::number_of_registers) are the 64-bit

// integer registers.  Values 64-95 are the (32-bit only) float registers.

// Each 32-bit quantity is given its own number, so the integer registers

// (in either 32- or 64-bit builds) use 2 numbers.  For example, there is

// an O0-low and an O0-high.  Essentially, all int register numbers are doubled.

// Register results are passed in O0-O5, for outgoing call arguments.  To

// convert to incoming arguments, convert all O's to I's.  The regs array

// refer to the low and hi 32-bit words of 64-bit registers or stack slots.

// If the regs[].second() field is set to VMRegImpl::Bad(), it means it's unused (a

// 32-bit value was passed).  If both are VMRegImpl::Bad(), it means no value was

// passed (used as a placeholder for the other half of longs and doubles in

// the 64-bit build).  regs[].second() is either VMRegImpl::Bad() or regs[].second() is

// regs[].first()+1 (regs[].first() may be misaligned in the C calling convention).

// Sparc never passes a value in regs[].second() but not regs[].first() (regs[].first()

// == VMRegImpl::Bad() && regs[].second() != VMRegImpl::Bad()) nor unrelated values in the

// same VMRegPair.

// Note: the INPUTS in sig_bt are in units of Java argument words, which are

// either 32-bit or 64-bit depending on the build.  The OUTPUTS are in 32-bit

// units regardless of build.

// ---------------------------------------------------------------------------

// The compiled Java calling convention.  The Java convention always passes

// 64-bit values in adjacent aligned locations (either registers or stack),

// floats in float registers and doubles in aligned float pairs.  Values are

// packed in the registers.  There is no backing varargs store for values in

// registers.  In the 32-bit build, longs are passed in G1 and G4 (cannot be

// passed in I's, because longs in I's get their heads chopped off at

// interrupt).

int SharedRuntime::java_calling_convention(const BasicType *sig_bt,

                                           VMRegPair *regs,

                                           int total_args_passed,

                                           int is_outgoing) {

  assert(F31->as_VMReg()->is_reg(), "overlapping stack/register numbers");

  // Convention is to pack the first 6 int/oop args into the first 6 registers

  // (I0-I5), extras spill to the stack.  Then pack the first 8 float args

  // into F0-F7, extras spill to the stack.  Then pad all register sets to

  // align.  Then put longs and doubles into the same registers as they fit,

  // else spill to the stack.

  const int int_reg_max = SPARC_ARGS_IN_REGS_NUM;

  const int flt_reg_max = 8;

  //

  // Where 32-bit 1-reg longs start being passed

  // In tiered we must pass on stack because c1 can't use a "pair" in a single reg.

  // So make it look like we've filled all the G regs that c2 wants to use.

  Register g_reg = TieredCompilation ? noreg : G1;

  // Count int/oop and float args.  See how many stack slots we'll need and

  // where the longs & doubles will go.

  int int_reg_cnt   = 0;

  int flt_reg_cnt   = 0;

  // int stk_reg_pairs = frame::register_save_words*(wordSize>>2);

  // int stk_reg_pairs = SharedRuntime::out_preserve_stack_slots();

  int stk_reg_pairs = 0;

  for (int i = 0; i < total_args_passed; i++) {

    switch (sig_bt[i]) {

    case T_LONG:                // LP64, longs compete with int args

      assert(sig_bt[i+1] == T_VOID, "");

#ifdef _LP64

      if (int_reg_cnt < int_reg_max) int_reg_cnt++;

#endif

      break;

    case T_OBJECT:

    case T_ARRAY:

    case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address

      if (int_reg_cnt < int_reg_max) int_reg_cnt++;

#ifndef _LP64

      else                            stk_reg_pairs++;

#endif

      break;

    case T_INT:

    case T_SHORT:

    case T_CHAR:

    case T_BYTE:

    case T_BOOLEAN:

      if (int_reg_cnt < int_reg_max) int_reg_cnt++;

      else                            stk_reg_pairs++;

      break;

    case T_FLOAT:

      if (flt_reg_cnt < flt_reg_max) flt_reg_cnt++;

      else                            stk_reg_pairs++;

      break;

    case T_DOUBLE:

      assert(sig_bt[i+1] == T_VOID, "");

      break;

    case T_VOID:

      break;

    default:

      ShouldNotReachHere();

    }

  }

  // This is where the longs/doubles start on the stack.

  stk_reg_pairs = (stk_reg_pairs+1) & ~1; // Round

  int int_reg_pairs = (int_reg_cnt+1) & ~1; // 32-bit 2-reg longs only

  int flt_reg_pairs = (flt_reg_cnt+1) & ~1;

  // int stk_reg = frame::register_save_words*(wordSize>>2);

  // int stk_reg = SharedRuntime::out_preserve_stack_slots();

  int stk_reg = 0;

  int int_reg = 0;

  int flt_reg = 0;

  // Now do the signature layout

  for (int i = 0; i < total_args_passed; i++) {

    switch (sig_bt[i]) {

    case T_INT:

    case T_SHORT:

    case T_CHAR:

    case T_BYTE:

    case T_BOOLEAN:

#ifndef _LP64

    case T_OBJECT:

    case T_ARRAY:

    case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address

#endif // _LP64

      if (int_reg < int_reg_max) {

        Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);

        regs[i].set1(r->as_VMReg());

      } else {

        regs[i].set1(VMRegImpl::stack2reg(stk_reg++));

      }

      break;

#ifdef _LP64

    case T_OBJECT:

    case T_ARRAY:

    case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address

      if (int_reg < int_reg_max) {

        Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);

        regs[i].set2(r->as_VMReg());

      } else {

        regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));

        stk_reg_pairs += 2;

      }

      break;

#endif // _LP64

    case T_LONG:

      assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half");

#ifdef _LP64

        if (int_reg < int_reg_max) {

          Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);

          regs[i].set2(r->as_VMReg());

        } else {

          regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));

          stk_reg_pairs += 2;

        }

#else

#ifdef COMPILER2

        // For 32-bit build, can't pass longs in O-regs because they become

        // I-regs and get trashed.  Use G-regs instead.  G1 and G4 are almost

        // spare and available.  This convention isn't used by the Sparc ABI or

        // anywhere else. If we're tiered then we don't use G-regs because c1

        // can't deal with them as a "pair". (Tiered makes this code think g's are filled)

        // G0: zero

        // G1: 1st Long arg

        // G2: global allocated to TLS

        // G3: used in inline cache check

        // G4: 2nd Long arg

        // G5: used in inline cache check

        // G6: used by OS

        // G7: used by OS

        if (g_reg == G1) {

          regs[i].set2(G1->as_VMReg()); // This long arg in G1

          g_reg = G4;                  // Where the next arg goes

        } else if (g_reg == G4) {

          regs[i].set2(G4->as_VMReg()); // The 2nd long arg in G4

          g_reg = noreg;               // No more longs in registers

        } else {

          regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));

          stk_reg_pairs += 2;

        }

#else // COMPILER2

        if (int_reg_pairs + 1 < int_reg_max) {

          if (is_outgoing) {

            regs[i].set_pair(as_oRegister(int_reg_pairs + 1)->as_VMReg(), as_oRegister(int_reg_pairs)->as_VMReg());

          } else {

            regs[i].set_pair(as_iRegister(int_reg_pairs + 1)->as_VMReg(), as_iRegister(int_reg_pairs)->as_VMReg());

          }

          int_reg_pairs += 2;

        } else {

          regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));

          stk_reg_pairs += 2;

        }

#endif // COMPILER2

#endif // _LP64

      break;