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/*
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* Copyright (c) 2009, 2019, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*/
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package org.graalvm.compiler.asm.amd64;
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import static org.graalvm.compiler.asm.amd64.AMD64AsmOptions.UseIncDec;
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import static org.graalvm.compiler.asm.amd64.AMD64AsmOptions.UseXmmLoadAndClearUpper;
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import static org.graalvm.compiler.asm.amd64.AMD64AsmOptions.UseXmmRegToRegMoveAll;
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import org.graalvm.compiler.asm.amd64.AVXKind.AVXSize;
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import org.graalvm.compiler.core.common.NumUtil;
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import jdk.vm.ci.amd64.AMD64;
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import jdk.vm.ci.amd64.AMD64Kind;
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import jdk.vm.ci.code.Register;
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import jdk.vm.ci.code.TargetDescription;
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/**
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* This class implements commonly used X86 code patterns.
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*/
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public class AMD64MacroAssembler extends AMD64Assembler {
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public AMD64MacroAssembler(TargetDescription target) {
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super(target);
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}
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public final void decrementq(Register reg, int value) {
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if (value == Integer.MIN_VALUE) {
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subq(reg, value);
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return;
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}
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if (value < 0) {
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incrementq(reg, -value);
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return;
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}
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if (value == 0) {
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return;
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}
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if (value == 1 && UseIncDec) {
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decq(reg);
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} else {
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subq(reg, value);
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}
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}
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public final void decrementq(AMD64Address dst, int value) {
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if (value == Integer.MIN_VALUE) {
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subq(dst, value);
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return;
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}
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if (value < 0) {
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incrementq(dst, -value);
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return;
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}
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if (value == 0) {
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return;
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}
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if (value == 1 && UseIncDec) {
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decq(dst);
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} else {
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subq(dst, value);
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}
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}
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public void incrementq(Register reg, int value) {
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if (value == Integer.MIN_VALUE) {
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addq(reg, value);
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return;
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}
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if (value < 0) {
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decrementq(reg, -value);
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return;
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}
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if (value == 0) {
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return;
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}
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if (value == 1 && UseIncDec) {
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incq(reg);
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} else {
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addq(reg, value);
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}
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}
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public final void incrementq(AMD64Address dst, int value) {
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if (value == Integer.MIN_VALUE) {
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addq(dst, value);
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return;
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}
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if (value < 0) {
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decrementq(dst, -value);
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return;
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}
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if (value == 0) {
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return;
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}
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if (value == 1 && UseIncDec) {
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incq(dst);
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} else {
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addq(dst, value);
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}
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}
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public final void movptr(Register dst, AMD64Address src) {
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movq(dst, src);
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}
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public final void movptr(AMD64Address dst, Register src) {
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movq(dst, src);
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}
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public final void movptr(AMD64Address dst, int src) {
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movslq(dst, src);
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}
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public final void cmpptr(Register src1, Register src2) {
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cmpq(src1, src2);
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}
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public final void cmpptr(Register src1, AMD64Address src2) {
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cmpq(src1, src2);
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}
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public final void decrementl(Register reg) {
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decrementl(reg, 1);
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}
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public final void decrementl(Register reg, int value) {
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if (value == Integer.MIN_VALUE) {
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subl(reg, value);
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return;
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}
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if (value < 0) {
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incrementl(reg, -value);
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return;
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}
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if (value == 0) {
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return;
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}
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if (value == 1 && UseIncDec) {
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decl(reg);
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} else {
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subl(reg, value);
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}
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}
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public final void decrementl(AMD64Address dst, int value) {
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if (value == Integer.MIN_VALUE) {
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subl(dst, value);
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return;
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}
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if (value < 0) {
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incrementl(dst, -value);
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return;
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}
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if (value == 0) {
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return;
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}
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if (value == 1 && UseIncDec) {
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decl(dst);
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} else {
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subl(dst, value);
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}
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}
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public final void incrementl(Register reg, int value) {
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if (value == Integer.MIN_VALUE) {
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addl(reg, value);
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return;
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}
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if (value < 0) {
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decrementl(reg, -value);
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return;
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}
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if (value == 0) {
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return;
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}
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if (value == 1 && UseIncDec) {
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incl(reg);
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} else {
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addl(reg, value);
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}
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}
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public final void incrementl(AMD64Address dst, int value) {
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if (value == Integer.MIN_VALUE) {
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addl(dst, value);
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return;
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}
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if (value < 0) {
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decrementl(dst, -value);
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return;
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}
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if (value == 0) {
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return;
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}
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if (value == 1 && UseIncDec) {
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incl(dst);
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} else {
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addl(dst, value);
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}
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}
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public void movflt(Register dst, Register src) {
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assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
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if (UseXmmRegToRegMoveAll) {
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if (isAVX512Register(dst) || isAVX512Register(src)) {
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VexMoveOp.VMOVAPS.emit(this, AVXSize.XMM, dst, src);
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} else {
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movaps(dst, src);
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}
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} else {
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if (isAVX512Register(dst) || isAVX512Register(src)) {
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VexMoveOp.VMOVSS.emit(this, AVXSize.XMM, dst, src);
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} else {
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movss(dst, src);
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}
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}
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}
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public void movflt(Register dst, AMD64Address src) {
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assert dst.getRegisterCategory().equals(AMD64.XMM);
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if (isAVX512Register(dst)) {
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VexMoveOp.VMOVSS.emit(this, AVXSize.XMM, dst, src);
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} else {
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movss(dst, src);
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}
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}
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public void movflt(AMD64Address dst, Register src) {
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assert src.getRegisterCategory().equals(AMD64.XMM);
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if (isAVX512Register(src)) {
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VexMoveOp.VMOVSS.emit(this, AVXSize.XMM, dst, src);
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} else {
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movss(dst, src);
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}
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}
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public void movdbl(Register dst, Register src) {
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assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
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if (UseXmmRegToRegMoveAll) {
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if (isAVX512Register(dst) || isAVX512Register(src)) {
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VexMoveOp.VMOVAPD.emit(this, AVXSize.XMM, dst, src);
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} else {
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movapd(dst, src);
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}
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} else {
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if (isAVX512Register(dst) || isAVX512Register(src)) {
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VexMoveOp.VMOVSD.emit(this, AVXSize.XMM, dst, src);
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} else {
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movsd(dst, src);
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}
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}
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}
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public void movdbl(Register dst, AMD64Address src) {
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assert dst.getRegisterCategory().equals(AMD64.XMM);
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if (UseXmmLoadAndClearUpper) {
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if (isAVX512Register(dst)) {
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VexMoveOp.VMOVSD.emit(this, AVXSize.XMM, dst, src);
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} else {
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movsd(dst, src);
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}
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} else {
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assert !isAVX512Register(dst);
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movlpd(dst, src);
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}
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}
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public void movdbl(AMD64Address dst, Register src) {
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assert src.getRegisterCategory().equals(AMD64.XMM);
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if (isAVX512Register(src)) {
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VexMoveOp.VMOVSD.emit(this, AVXSize.XMM, dst, src);
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} else {
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movsd(dst, src);
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}
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}
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/**
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* Non-atomic write of a 64-bit constant to memory. Do not use if the address might be a
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* volatile field!
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*/
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public final void movlong(AMD64Address dst, long src) {
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if (NumUtil.isInt(src)) {
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AMD64MIOp.MOV.emit(this, OperandSize.QWORD, dst, (int) src);
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} else {
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AMD64Address high = new AMD64Address(dst.getBase(), dst.getIndex(), dst.getScale(), dst.getDisplacement() + 4);
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movl(dst, (int) (src & 0xFFFFFFFF));
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movl(high, (int) (src >> 32));
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}
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}
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public final void setl(ConditionFlag cc, Register dst) {
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setb(cc, dst);
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movzbl(dst, dst);
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}
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public final void setq(ConditionFlag cc, Register dst) {
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setb(cc, dst);
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movzbq(dst, dst);
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}
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public final void flog(Register dest, Register value, boolean base10) {
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if (base10) {
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fldlg2();
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} else {
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fldln2();
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}
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AMD64Address tmp = trigPrologue(value);
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fyl2x();
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trigEpilogue(dest, tmp);
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}
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public final void fsin(Register dest, Register value) {
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AMD64Address tmp = trigPrologue(value);
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fsin();
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trigEpilogue(dest, tmp);
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}
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public final void fcos(Register dest, Register value) {
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AMD64Address tmp = trigPrologue(value);
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fcos();
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trigEpilogue(dest, tmp);
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}
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public final void ftan(Register dest, Register value) {
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AMD64Address tmp = trigPrologue(value);
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fptan();
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fstp(0); // ftan pushes 1.0 in addition to the actual result, pop
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trigEpilogue(dest, tmp);
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}
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public final void fpop() {
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ffree(0);
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fincstp();
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}
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private AMD64Address trigPrologue(Register value) {
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assert value.getRegisterCategory().equals(AMD64.XMM);
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AMD64Address tmp = new AMD64Address(AMD64.rsp);
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subq(AMD64.rsp, AMD64Kind.DOUBLE.getSizeInBytes());
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movdbl(tmp, value);
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fldd(tmp);
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return tmp;
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}
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private void trigEpilogue(Register dest, AMD64Address tmp) {
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assert dest.getRegisterCategory().equals(AMD64.XMM);
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fstpd(tmp);
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movdbl(dest, tmp);
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addq(AMD64.rsp, AMD64Kind.DOUBLE.getSizeInBytes());
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}
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}
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