/*

 * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

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 */

#ifndef CPU_ARM_GC_SHARED_BARRIERSETASSEMBLER_ARM_HPP

#define CPU_ARM_GC_SHARED_BARRIERSETASSEMBLER_ARM_HPP

#include "asm/macroAssembler.hpp"

#include "memory/allocation.hpp"

#include "oops/access.hpp"

class BarrierSetAssembler: public CHeapObj<mtGC> {

public:

  virtual void arraycopy_prologue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop,

                                  Register addr, Register count, int callee_saved_regs) {}

  virtual void arraycopy_epilogue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop,

                                  Register addr, Register count, Register tmp) {}

};

#endif // CPU_ARM_GC_SHARED_BARRIERSETASSEMBLER_ARM_HPP