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/*
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* Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2016 SAP SE. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#ifndef OS_CPU_LINUX_S390_VM_ORDERACCESS_LINUX_S390_INLINE_HPP
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#define OS_CPU_LINUX_S390_VM_ORDERACCESS_LINUX_S390_INLINE_HPP
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#include "runtime/orderAccess.hpp"
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#include "vm_version_s390.hpp"
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// Implementation of class OrderAccess.
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//
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// machine barrier instructions:
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//
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// - z_sync two-way memory barrier, aka fence
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//
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// semantic barrier instructions:
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// (as defined in orderAccess.hpp)
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//
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// - z_release orders Store|Store, (maps to compiler barrier)
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// Load|Store
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// - z_acquire orders Load|Store, (maps to compiler barrier)
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// Load|Load
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// - z_fence orders Store|Store, (maps to z_sync)
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// Load|Store,
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// Load|Load,
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// Store|Load
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//
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// Only load-after-store-order is not guaranteed on z/Architecture, i.e. only 'fence'
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// is needed.
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// A compiler barrier, forcing the C++ compiler to invalidate all memory assumptions.
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#define inlasm_compiler_barrier() __asm__ volatile ("" : : : "memory");
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// "bcr 15, 0" is used as two way memory barrier.
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#define inlasm_zarch_sync() __asm__ __volatile__ ("bcr 15, 0" : : : "memory");
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// Release and acquire are empty on z/Architecture, but potential
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// optimizations of gcc must be forbidden by OrderAccess::release and
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// OrderAccess::acquire.
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#define inlasm_zarch_release() inlasm_compiler_barrier()
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#define inlasm_zarch_acquire() inlasm_compiler_barrier()
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#define inlasm_zarch_fence() inlasm_zarch_sync()
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inline void OrderAccess::loadload() { inlasm_compiler_barrier(); }
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inline void OrderAccess::storestore() { inlasm_compiler_barrier(); }
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inline void OrderAccess::loadstore() { inlasm_compiler_barrier(); }
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inline void OrderAccess::storeload() { inlasm_zarch_sync(); }
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inline void OrderAccess::acquire() { inlasm_zarch_acquire(); }
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inline void OrderAccess::release() { inlasm_zarch_release(); }
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inline void OrderAccess::fence() { inlasm_zarch_sync(); }
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template<> inline jbyte OrderAccess::specialized_load_acquire<jbyte> (volatile jbyte* p) { register jbyte t = *p; inlasm_zarch_acquire(); return t; }
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template<> inline jshort OrderAccess::specialized_load_acquire<jshort>(volatile jshort* p) { register jshort t = *p; inlasm_zarch_acquire(); return t; }
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template<> inline jint OrderAccess::specialized_load_acquire<jint> (volatile jint* p) { register jint t = *p; inlasm_zarch_acquire(); return t; }
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template<> inline jlong OrderAccess::specialized_load_acquire<jlong> (volatile jlong* p) { register jlong t = *p; inlasm_zarch_acquire(); return t; }
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#undef inlasm_compiler_barrier
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#undef inlasm_zarch_sync
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#undef inlasm_zarch_release
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#undef inlasm_zarch_acquire
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#undef inlasm_zarch_fence
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#define VM_HAS_GENERALIZED_ORDER_ACCESS 1
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#endif // OS_CPU_LINUX_S390_VM_ORDERACCESS_LINUX_S390_INLINE_HPP
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