hotspot/src/share/vm/opto/reg_split.cpp
author thartmann
Thu, 17 Mar 2016 09:41:46 +0100
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8151882: -XX:+Verbose prints messages even if no other flag is set Summary: We should only print messages if PrintOpto && WizardMode is set. Reviewed-by: kvn, neliasso
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/*
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 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#include "precompiled.hpp"
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#include "libadt/vectset.hpp"
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#include "memory/allocation.inline.hpp"
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#include "opto/addnode.hpp"
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#include "opto/c2compiler.hpp"
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#include "opto/callnode.hpp"
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#include "opto/cfgnode.hpp"
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#include "opto/chaitin.hpp"
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#include "opto/loopnode.hpp"
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#include "opto/machnode.hpp"
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//------------------------------Split--------------------------------------
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// Walk the graph in RPO and for each lrg which spills, propagate reaching
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// definitions.  During propagation, split the live range around regions of
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// High Register Pressure (HRP).  If a Def is in a region of Low Register
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// Pressure (LRP), it will not get spilled until we encounter a region of
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// HRP between it and one of its uses.  We will spill at the transition
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// point between LRP and HRP.  Uses in the HRP region will use the spilled
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// Def.  The first Use outside the HRP region will generate a SpillCopy to
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// hoist the live range back up into a register, and all subsequent uses
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// will use that new Def until another HRP region is encountered.  Defs in
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// HRP regions will get trailing SpillCopies to push the LRG down into the
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// stack immediately.
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//
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// As a side effect, unlink from (hence make dead) coalesced copies.
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//
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static const char out_of_nodes[] = "out of nodes during split";
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//------------------------------get_spillcopy_wide-----------------------------
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// Get a SpillCopy node with wide-enough masks.  Use the 'wide-mask', the
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// wide ideal-register spill-mask if possible.  If the 'wide-mask' does
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// not cover the input (or output), use the input (or output) mask instead.
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Node *PhaseChaitin::get_spillcopy_wide(MachSpillCopyNode::SpillType spill_type, Node *def, Node *use, uint uidx) {
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  // If ideal reg doesn't exist we've got a bad schedule happening
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  // that is forcing us to spill something that isn't spillable.
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  // Bail rather than abort
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  int ireg = def->ideal_reg();
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  if (ireg == 0 || ireg == Op_RegFlags) {
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    assert(false, "attempted to spill a non-spillable item: %d: %s <- %d: %s, ireg = %d, spill_type: %s",
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           def->_idx, def->Name(), use->_idx, use->Name(), ireg,
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           MachSpillCopyNode::spill_type(spill_type));
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    C->record_method_not_compilable("attempted to spill a non-spillable item");
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    return NULL;
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  }
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  if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) {
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    return NULL;
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  }
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  const RegMask *i_mask = &def->out_RegMask();
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  const RegMask *w_mask = C->matcher()->idealreg2spillmask[ireg];
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  const RegMask *o_mask = use ? &use->in_RegMask(uidx) : w_mask;
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  const RegMask *w_i_mask = w_mask->overlap( *i_mask ) ? w_mask : i_mask;
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  const RegMask *w_o_mask;
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  int num_regs = RegMask::num_registers(ireg);
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  bool is_vect = RegMask::is_vector(ireg);
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  if( w_mask->overlap( *o_mask ) && // Overlap AND
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      ((num_regs == 1) // Single use or aligned
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        ||  is_vect    // or vector
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        || !is_vect && o_mask->is_aligned_pairs()) ) {
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    assert(!is_vect || o_mask->is_aligned_sets(num_regs), "vectors are aligned");
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    // Don't come here for mis-aligned doubles
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    w_o_mask = w_mask;
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  } else {                      // wide ideal mask does not overlap with o_mask
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    // Mis-aligned doubles come here and XMM->FPR moves on x86.
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    w_o_mask = o_mask;          // Must target desired registers
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    // Does the ideal-reg-mask overlap with o_mask?  I.e., can I use
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    // a reg-reg move or do I need a trip across register classes
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    // (and thus through memory)?
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    if( !C->matcher()->idealreg2regmask[ireg]->overlap( *o_mask) && o_mask->is_UP() )
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      // Here we assume a trip through memory is required.
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      w_i_mask = &C->FIRST_STACK_mask();
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  }
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  return new MachSpillCopyNode(spill_type, def, *w_i_mask, *w_o_mask );
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}
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//------------------------------insert_proj------------------------------------
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// Insert the spill at chosen location.  Skip over any intervening Proj's or
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// Phis.  Skip over a CatchNode and projs, inserting in the fall-through block
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// instead.  Update high-pressure indices.  Create a new live range.
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void PhaseChaitin::insert_proj( Block *b, uint i, Node *spill, uint maxlrg ) {
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  // Skip intervening ProjNodes.  Do not insert between a ProjNode and
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  // its definer.
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  while( i < b->number_of_nodes() &&
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         (b->get_node(i)->is_Proj() ||
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          b->get_node(i)->is_Phi() ) )
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    i++;
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  // Do not insert between a call and his Catch
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  if( b->get_node(i)->is_Catch() ) {
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    // Put the instruction at the top of the fall-thru block.
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    // Find the fall-thru projection
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    while( 1 ) {
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      const CatchProjNode *cp = b->get_node(++i)->as_CatchProj();
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      if( cp->_con == CatchProjNode::fall_through_index )
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        break;
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    }
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    int sidx = i - b->end_idx()-1;
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    b = b->_succs[sidx];        // Switch to successor block
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    i = 1;                      // Right at start of block
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  }
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  b->insert_node(spill, i);    // Insert node in block
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  _cfg.map_node_to_block(spill,  b); // Update node->block mapping to reflect
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  // Adjust the point where we go hi-pressure
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  if( i <= b->_ihrp_index ) b->_ihrp_index++;
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  if( i <= b->_fhrp_index ) b->_fhrp_index++;
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  // Assign a new Live Range Number to the SpillCopy and grow
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  // the node->live range mapping.
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  new_lrg(spill,maxlrg);
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}
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//------------------------------split_DEF--------------------------------------
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// There are four categories of Split; UP/DOWN x DEF/USE
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// Only three of these really occur as DOWN/USE will always color
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// Any Split with a DEF cannot CISC-Spill now.  Thus we need
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// two helper routines, one for Split DEFS (insert after instruction),
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// one for Split USES (insert before instruction).  DEF insertion
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// happens inside Split, where the Leaveblock array is updated.
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uint PhaseChaitin::split_DEF( Node *def, Block *b, int loc, uint maxlrg, Node **Reachblock, Node **debug_defs, GrowableArray<uint> splits, int slidx ) {
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#ifdef ASSERT
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  // Increment the counter for this lrg
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  splits.at_put(slidx, splits.at(slidx)+1);
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#endif
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  // If we are spilling the memory op for an implicit null check, at the
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  // null check location (ie - null check is in HRP block) we need to do
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  // the null-check first, then spill-down in the following block.
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  // (The implicit_null_check function ensures the use is also dominated
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  // by the branch-not-taken block.)
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  Node *be = b->end();
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  if( be->is_MachNullCheck() && be->in(1) == def && def == b->get_node(loc)) {
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    // Spill goes in the branch-not-taken block
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    b = b->_succs[b->get_node(b->end_idx()+1)->Opcode() == Op_IfTrue];
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    loc = 0;                    // Just past the Region
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  }
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  assert( loc >= 0, "must insert past block head" );
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  // Get a def-side SpillCopy
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  Node *spill = get_spillcopy_wide(MachSpillCopyNode::Definition, def, NULL, 0);
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  // Did we fail to split?, then bail
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  if (!spill) {
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    return 0;
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  }
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  // Insert the spill at chosen location
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  insert_proj( b, loc+1, spill, maxlrg++);
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  // Insert new node into Reaches array
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  Reachblock[slidx] = spill;
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  // Update debug list of reaching down definitions by adding this one
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  debug_defs[slidx] = spill;
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  // return updated count of live ranges
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  return maxlrg;
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}
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//------------------------------split_USE--------------------------------------
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// Splits at uses can involve redeffing the LRG, so no CISC Spilling there.
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// Debug uses want to know if def is already stack enabled.
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uint PhaseChaitin::split_USE(MachSpillCopyNode::SpillType spill_type, Node *def, Block *b, Node *use, uint useidx, uint maxlrg, bool def_down, bool cisc_sp, GrowableArray<uint> splits, int slidx ) {
1
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#ifdef ASSERT
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  // Increment the counter for this lrg
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  splits.at_put(slidx, splits.at(slidx)+1);
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#endif
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  // Some setup stuff for handling debug node uses
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  JVMState* jvms = use->jvms();
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  uint debug_start = jvms ? jvms->debug_start() : 999999;
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  uint debug_end   = jvms ? jvms->debug_end()   : 999999;
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  //-------------------------------------------
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  // Check for use of debug info
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  if (useidx >= debug_start && useidx < debug_end) {
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    // Actually it's perfectly legal for constant debug info to appear
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    // just unlikely.  In this case the optimizer left a ConI of a 4
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    // as both inputs to a Phi with only a debug use.  It's a single-def
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    // live range of a rematerializable value.  The live range spills,
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    // rematerializes and now the ConI directly feeds into the debug info.
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    // assert(!def->is_Con(), "constant debug info already constructed directly");
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    // Special split handling for Debug Info
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    // If DEF is DOWN, just hook the edge and return
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    // If DEF is UP, Split it DOWN for this USE.
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    if( def->is_Mach() ) {
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      if( def_down ) {
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        // DEF is DOWN, so connect USE directly to the DEF
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        use->set_req(useidx, def);
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      } else {
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        // Block and index where the use occurs.
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        Block *b = _cfg.get_block_for_node(use);
1
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        // Put the clone just prior to use
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        int bindex = b->find_node(use);
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        // DEF is UP, so must copy it DOWN and hook in USE
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        // Insert SpillCopy before the USE, which uses DEF as its input,
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        // and defs a new live range, which is used by this node.
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        Node *spill = get_spillcopy_wide(spill_type, def,use,useidx);
1
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        // did we fail to split?
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        if (!spill) {
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          // Bail
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          return 0;
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        }
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        // insert into basic block
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        insert_proj( b, bindex, spill, maxlrg++ );
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        // Use the new split
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        use->set_req(useidx,spill);
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      }
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      // No further split handling needed for this use
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      return maxlrg;
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    }  // End special splitting for debug info live range
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  }  // If debug info
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  // CISC-SPILLING
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  // Finally, check to see if USE is CISC-Spillable, and if so,
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  // gather_lrg_masks will add the flags bit to its mask, and
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  // no use side copy is needed.  This frees up the live range
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  // register choices without causing copy coalescing, etc.
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  if( UseCISCSpill && cisc_sp ) {
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    int inp = use->cisc_operand();
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    if( inp != AdlcVMDeps::Not_cisc_spillable )
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      // Convert operand number to edge index number
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      inp = use->as_Mach()->operand_index(inp);
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    if( inp == (int)useidx ) {
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      use->set_req(useidx, def);
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#ifndef PRODUCT
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      if( TraceCISCSpill ) {
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        tty->print("  set_split: ");
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        use->dump();
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      }
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#endif
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      return maxlrg;
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    }
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  }
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  //-------------------------------------------
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  // Insert a Copy before the use
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  // Block and index where the use occurs.
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  int bindex;
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  // Phi input spill-copys belong at the end of the prior block
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  if( use->is_Phi() ) {
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    b = _cfg.get_block_for_node(b->pred(useidx));
1
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    bindex = b->end_idx();
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  } else {
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    // Put the clone just prior to use
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    bindex = b->find_node(use);
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  }
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  Node *spill = get_spillcopy_wide(spill_type, def, use, useidx );
1
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  if( !spill ) return 0;        // Bailed out
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  // Insert SpillCopy before the USE, which uses the reaching DEF as
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  // its input, and defs a new live range, which is used by this node.
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  insert_proj( b, bindex, spill, maxlrg++ );
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  // Use the spill/clone
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  use->set_req(useidx,spill);
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  // return updated live range count
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  return maxlrg;
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}
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//------------------------------clone_node----------------------------
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// Clone node with anti dependence check.
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Node* clone_node(Node* def, Block *b, Compile* C) {
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  if (def->needs_anti_dependence_check()) {
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#ifdef ASSERT
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    if (PrintOpto && WizardMode) {
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      tty->print_cr("RA attempts to clone node with anti_dependence:");
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      def->dump(-1); tty->cr();
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      tty->print_cr("into block:");
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      b->dump();
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    }
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   296
#endif
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    if (C->subsume_loads() == true && !C->failing()) {
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      // Retry with subsume_loads == false
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      // If this is the first failure, the sentinel string will "stick"
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      // to the Compile object, and the C2Compiler will see it and retry.
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      C->record_failure(C2Compiler::retry_no_subsuming_loads());
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    } else {
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      // Bailout without retry
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      C->record_method_not_compilable("RA Split failed: attempt to clone node with anti_dependence");
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    }
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    return 0;
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   307
  }
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  return def->clone();
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}
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1
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//------------------------------split_Rematerialize----------------------------
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// Clone a local copy of the def.
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Node *PhaseChaitin::split_Rematerialize(Node *def, Block *b, uint insidx, uint &maxlrg,
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                                        GrowableArray<uint> splits, int slidx, uint *lrg2reach,
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                                        Node **Reachblock, bool walkThru) {
1
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  // The input live ranges will be stretched to the site of the new
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  // instruction.  They might be stretched past a def and will thus
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  // have the old and new values of the same live range alive at the
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  // same time - a definite no-no.  Split out private copies of
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  // the inputs.
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   321
  if (def->req() > 1) {
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   322
    for (uint i = 1; i < def->req(); i++) {
1
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      Node *in = def->in(i);
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   324
      uint lidx = _lrg_map.live_range_id(in);
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   325
      // We do not need this for live ranges that are only defined once.
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   326
      // However, this is not true for spill copies that are added in this
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   327
      // Split() pass, since they might get coalesced later on in this pass.
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   328
      if (lidx < _lrg_map.max_lrg_id() && lrgs(lidx).is_singledef()) {
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   329
        continue;
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   330
      }
1
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      Block *b_def = _cfg.get_block_for_node(def);
1
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      int idx_def = b_def->find_node(def);
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   334
      // Cannot spill Op_RegFlags.
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   335
      Node *in_spill;
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   336
      if (in->ideal_reg() != Op_RegFlags) {
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   337
        in_spill = get_spillcopy_wide(MachSpillCopyNode::InputToRematerialization, in, def, i);
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   338
        if (!in_spill) { return 0; } // Bailed out
213af0859e7e 8141137: C2 fails rematerializing nodes using flag registers.
goetz
parents: 34174
diff changeset
   339
        insert_proj(b_def, idx_def, in_spill, maxlrg++);
213af0859e7e 8141137: C2 fails rematerializing nodes using flag registers.
goetz
parents: 34174
diff changeset
   340
        if (b_def == b) {
213af0859e7e 8141137: C2 fails rematerializing nodes using flag registers.
goetz
parents: 34174
diff changeset
   341
          insidx++;
213af0859e7e 8141137: C2 fails rematerializing nodes using flag registers.
goetz
parents: 34174
diff changeset
   342
        }
213af0859e7e 8141137: C2 fails rematerializing nodes using flag registers.
goetz
parents: 34174
diff changeset
   343
        def->set_req(i, in_spill);
213af0859e7e 8141137: C2 fails rematerializing nodes using flag registers.
goetz
parents: 34174
diff changeset
   344
      } else {
213af0859e7e 8141137: C2 fails rematerializing nodes using flag registers.
goetz
parents: 34174
diff changeset
   345
        // The 'in' defines a flag register. Flag registers can not be spilled.
213af0859e7e 8141137: C2 fails rematerializing nodes using flag registers.
goetz
parents: 34174
diff changeset
   346
        // Register allocation handles live ranges with flag registers
213af0859e7e 8141137: C2 fails rematerializing nodes using flag registers.
goetz
parents: 34174
diff changeset
   347
        // by rematerializing the def (in this case 'in'). Thus, this is not
213af0859e7e 8141137: C2 fails rematerializing nodes using flag registers.
goetz
parents: 34174
diff changeset
   348
        // critical if the input can be rematerialized, too.
213af0859e7e 8141137: C2 fails rematerializing nodes using flag registers.
goetz
parents: 34174
diff changeset
   349
        if (!in->rematerialize()) {
213af0859e7e 8141137: C2 fails rematerializing nodes using flag registers.
goetz
parents: 34174
diff changeset
   350
          assert(false, "Can not rematerialize %d: %s. Prolongs RegFlags live"
213af0859e7e 8141137: C2 fails rematerializing nodes using flag registers.
goetz
parents: 34174
diff changeset
   351
                 " range and defining node %d: %s may not be rematerialized.",
213af0859e7e 8141137: C2 fails rematerializing nodes using flag registers.
goetz
parents: 34174
diff changeset
   352
                 def->_idx, def->Name(), in->_idx, in->Name());
213af0859e7e 8141137: C2 fails rematerializing nodes using flag registers.
goetz
parents: 34174
diff changeset
   353
          C->record_method_not_compilable("attempted to spill a non-spillable item with RegFlags input");
213af0859e7e 8141137: C2 fails rematerializing nodes using flag registers.
goetz
parents: 34174
diff changeset
   354
          return 0; // Bailed out
213af0859e7e 8141137: C2 fails rematerializing nodes using flag registers.
goetz
parents: 34174
diff changeset
   355
        }
213af0859e7e 8141137: C2 fails rematerializing nodes using flag registers.
goetz
parents: 34174
diff changeset
   356
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   357
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   358
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   359
6188
95ea4d66089a 6973329: C2 with Zero based COOP produces code with broken anti-dependency on x86
kvn
parents: 5547
diff changeset
   360
  Node *spill = clone_node(def, b, C);
95ea4d66089a 6973329: C2 with Zero based COOP produces code with broken anti-dependency on x86
kvn
parents: 5547
diff changeset
   361
  if (spill == NULL || C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   362
    // Check when generating nodes
489c9b5090e2 Initial load
duke
parents:
diff changeset
   363
    return 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   364
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   365
489c9b5090e2 Initial load
duke
parents:
diff changeset
   366
  // See if any inputs are currently being spilled, and take the
489c9b5090e2 Initial load
duke
parents:
diff changeset
   367
  // latest copy of spilled inputs.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   368
  if( spill->req() > 1 ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   369
    for( uint i = 1; i < spill->req(); i++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   370
      Node *in = spill->in(i);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   371
      uint lidx = _lrg_map.find_id(in);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   372
489c9b5090e2 Initial load
duke
parents:
diff changeset
   373
      // Walk backwards thru spill copy node intermediates
1057
44220ef9a775 6732194: Data corruption dependent on -server/-client/-Xbatch
never
parents: 1
diff changeset
   374
      if (walkThru) {
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   375
        while (in->is_SpillCopy() && lidx >= _lrg_map.max_lrg_id()) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   376
          in = in->in(1);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   377
          lidx = _lrg_map.find_id(in);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   378
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   379
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   380
        if (lidx < _lrg_map.max_lrg_id() && lrgs(lidx).is_multidef()) {
1057
44220ef9a775 6732194: Data corruption dependent on -server/-client/-Xbatch
never
parents: 1
diff changeset
   381
          // walkThru found a multidef LRG, which is unsafe to use, so
44220ef9a775 6732194: Data corruption dependent on -server/-client/-Xbatch
never
parents: 1
diff changeset
   382
          // just keep the original def used in the clone.
44220ef9a775 6732194: Data corruption dependent on -server/-client/-Xbatch
never
parents: 1
diff changeset
   383
          in = spill->in(i);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   384
          lidx = _lrg_map.find_id(in);
1057
44220ef9a775 6732194: Data corruption dependent on -server/-client/-Xbatch
never
parents: 1
diff changeset
   385
        }
44220ef9a775 6732194: Data corruption dependent on -server/-client/-Xbatch
never
parents: 1
diff changeset
   386
      }
44220ef9a775 6732194: Data corruption dependent on -server/-client/-Xbatch
never
parents: 1
diff changeset
   387
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   388
      if (lidx < _lrg_map.max_lrg_id() && lrgs(lidx).reg() >= LRG::SPILL_REG) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   389
        Node *rdef = Reachblock[lrg2reach[lidx]];
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   390
        if (rdef) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   391
          spill->set_req(i, rdef);
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   392
        }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   393
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   394
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   395
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   396
489c9b5090e2 Initial load
duke
parents:
diff changeset
   397
489c9b5090e2 Initial load
duke
parents:
diff changeset
   398
  assert( spill->out_RegMask().is_UP(), "rematerialize to a reg" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   399
  // Rematerialized op is def->spilled+1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   400
  set_was_spilled(spill);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   401
  if( _spilled_once.test(def->_idx) )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   402
    set_was_spilled(spill);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   403
489c9b5090e2 Initial load
duke
parents:
diff changeset
   404
  insert_proj( b, insidx, spill, maxlrg++ );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   405
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   406
  // Increment the counter for this lrg
489c9b5090e2 Initial load
duke
parents:
diff changeset
   407
  splits.at_put(slidx, splits.at(slidx)+1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   408
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   409
  // See if the cloned def kills any flags, and copy those kills as well
489c9b5090e2 Initial load
duke
parents:
diff changeset
   410
  uint i = insidx+1;
19334
3aa9ca404965 8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents: 19330
diff changeset
   411
  int found_projs = clone_projs( b, i, def, spill, maxlrg);
3aa9ca404965 8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents: 19330
diff changeset
   412
  if (found_projs > 0) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   413
    // Adjust the point where we go hi-pressure
19334
3aa9ca404965 8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents: 19330
diff changeset
   414
    if (i <= b->_ihrp_index) {
3aa9ca404965 8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents: 19330
diff changeset
   415
      b->_ihrp_index += found_projs;
3aa9ca404965 8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents: 19330
diff changeset
   416
    }
3aa9ca404965 8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents: 19330
diff changeset
   417
    if (i <= b->_fhrp_index) {
3aa9ca404965 8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents: 19330
diff changeset
   418
      b->_fhrp_index += found_projs;
3aa9ca404965 8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents: 19330
diff changeset
   419
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   420
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   421
489c9b5090e2 Initial load
duke
parents:
diff changeset
   422
  return spill;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   423
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   424
489c9b5090e2 Initial load
duke
parents:
diff changeset
   425
//------------------------------is_high_pressure-------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   426
// Function to compute whether or not this live range is "high pressure"
489c9b5090e2 Initial load
duke
parents:
diff changeset
   427
// in this block - whether it spills eagerly or not.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   428
bool PhaseChaitin::is_high_pressure( Block *b, LRG *lrg, uint insidx ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   429
  if( lrg->_was_spilled1 ) return true;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   430
  // Forced spilling due to conflict?  Then split only at binding uses
489c9b5090e2 Initial load
duke
parents:
diff changeset
   431
  // or defs, not for supposed capacity problems.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   432
  // CNC - Turned off 7/8/99, causes too much spilling
489c9b5090e2 Initial load
duke
parents:
diff changeset
   433
  // if( lrg->_is_bound ) return false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   434
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 10255
diff changeset
   435
  // Use float pressure numbers for vectors.
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 10255
diff changeset
   436
  bool is_float_or_vector = lrg->_is_float || lrg->_is_vector;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   437
  // Not yet reached the high-pressure cutoff point, so low pressure
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 10255
diff changeset
   438
  uint hrp_idx = is_float_or_vector ? b->_fhrp_index : b->_ihrp_index;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   439
  if( insidx < hrp_idx ) return false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   440
  // Register pressure for the block as a whole depends on reg class
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 10255
diff changeset
   441
  int block_pres = is_float_or_vector ? b->_freg_pressure : b->_reg_pressure;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   442
  // Bound live ranges will split at the binding points first;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   443
  // Intermediate splits should assume the live range's register set
489c9b5090e2 Initial load
duke
parents:
diff changeset
   444
  // got "freed up" and that num_regs will become INT_PRESSURE.
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 10255
diff changeset
   445
  int bound_pres = is_float_or_vector ? FLOATPRESSURE : INTPRESSURE;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   446
  // Effective register pressure limit.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   447
  int lrg_pres = (lrg->get_invalid_mask_size() > lrg->num_regs())
489c9b5090e2 Initial load
duke
parents:
diff changeset
   448
    ? (lrg->get_invalid_mask_size() >> (lrg->num_regs()-1)) : bound_pres;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   449
  // High pressure if block pressure requires more register freedom
489c9b5090e2 Initial load
duke
parents:
diff changeset
   450
  // than live range has.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   451
  return block_pres >= lrg_pres;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   452
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   453
489c9b5090e2 Initial load
duke
parents:
diff changeset
   454
489c9b5090e2 Initial load
duke
parents:
diff changeset
   455
//------------------------------prompt_use---------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   456
// True if lidx is used before any real register is def'd in the block
489c9b5090e2 Initial load
duke
parents:
diff changeset
   457
bool PhaseChaitin::prompt_use( Block *b, uint lidx ) {
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   458
  if (lrgs(lidx)._was_spilled2) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   459
    return false;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   460
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   461
489c9b5090e2 Initial load
duke
parents:
diff changeset
   462
  // Scan block for 1st use.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   463
  for( uint i = 1; i <= b->end_idx(); i++ ) {
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   464
    Node *n = b->get_node(i);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   465
    // Ignore PHI use, these can be up or down
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   466
    if (n->is_Phi()) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   467
      continue;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   468
    }
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   469
    for (uint j = 1; j < n->req(); j++) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   470
      if (_lrg_map.find_id(n->in(j)) == lidx) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   471
        return true;          // Found 1st use!
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   472
      }
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   473
    }
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   474
    if (n->out_RegMask().is_NotEmpty()) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   475
      return false;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   476
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   477
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   478
  return false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   479
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   480
489c9b5090e2 Initial load
duke
parents:
diff changeset
   481
//------------------------------Split--------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   482
//----------Split Routine----------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   483
// ***** NEW SPLITTING HEURISTIC *****
489c9b5090e2 Initial load
duke
parents:
diff changeset
   484
// DEFS: If the DEF is in a High Register Pressure(HRP) Block, split there.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   485
//        Else, no split unless there is a HRP block between a DEF and
489c9b5090e2 Initial load
duke
parents:
diff changeset
   486
//        one of its uses, and then split at the HRP block.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   487
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   488
// USES: If USE is in HRP, split at use to leave main LRG on stack.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   489
//       Else, hoist LRG back up to register only (ie - split is also DEF)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   490
// We will compute a new maxlrg as we go
13520
a1ba7784ef54 7148109: C2 compiler consumes too much heap resources
kvn
parents: 13104
diff changeset
   491
uint PhaseChaitin::Split(uint maxlrg, ResourceArea* split_arena) {
26913
9ad70cd32368 8058968: Compiler time traces should be improved
shade
parents: 24923
diff changeset
   492
  Compile::TracePhase tp("regAllocSplit", &timers[_t_regAllocSplit]);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   493
13520
a1ba7784ef54 7148109: C2 compiler consumes too much heap resources
kvn
parents: 13104
diff changeset
   494
  // Free thread local resources used by this method on exit.
a1ba7784ef54 7148109: C2 compiler consumes too much heap resources
kvn
parents: 13104
diff changeset
   495
  ResourceMark rm(split_arena);
a1ba7784ef54 7148109: C2 compiler consumes too much heap resources
kvn
parents: 13104
diff changeset
   496
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   497
  uint                 bidx, pidx, slidx, insidx, inpidx, twoidx;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   498
  uint                 non_phi = 1, spill_cnt = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   499
  Node                *n1, *n2, *n3;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   500
  Node_List           *defs,*phis;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   501
  bool                *UPblock;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   502
  bool                 u1, u2, u3;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   503
  Block               *b, *pred;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   504
  PhiNode             *phi;
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   505
  GrowableArray<uint>  lidxs(split_arena, maxlrg, 0, 0);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   506
489c9b5090e2 Initial load
duke
parents:
diff changeset
   507
  // Array of counters to count splits per live range
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   508
  GrowableArray<uint>  splits(split_arena, maxlrg, 0, 0);
13520
a1ba7784ef54 7148109: C2 compiler consumes too much heap resources
kvn
parents: 13104
diff changeset
   509
a1ba7784ef54 7148109: C2 compiler consumes too much heap resources
kvn
parents: 13104
diff changeset
   510
#define NEW_SPLIT_ARRAY(type, size)\
a1ba7784ef54 7148109: C2 compiler consumes too much heap resources
kvn
parents: 13104
diff changeset
   511
  (type*) split_arena->allocate_bytes((size) * sizeof(type))
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   512
489c9b5090e2 Initial load
duke
parents:
diff changeset
   513
  //----------Setup Code----------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   514
  // Create a convenient mapping from lrg numbers to reaches/leaves indices
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   515
  uint *lrg2reach = NEW_SPLIT_ARRAY(uint, maxlrg);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   516
  // Keep track of DEFS & Phis for later passes
489c9b5090e2 Initial load
duke
parents:
diff changeset
   517
  defs = new Node_List();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   518
  phis = new Node_List();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   519
  // Gather info on which LRG's are spilling, and build maps
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   520
  for (bidx = 1; bidx < maxlrg; bidx++) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   521
    if (lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   522
      assert(!lrgs(bidx).mask().is_AllStack(),"AllStack should color");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   523
      lrg2reach[bidx] = spill_cnt;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   524
      spill_cnt++;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   525
      lidxs.append(bidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   526
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   527
      // Initialize the split counts to zero
489c9b5090e2 Initial load
duke
parents:
diff changeset
   528
      splits.append(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   529
#endif
34174
4db2fb26dc49 8140424: don't prefix developer and notproduct flag variables with CONST_ in product builds
twisti
parents: 26913
diff changeset
   530
      if (PrintOpto && WizardMode && lrgs(bidx)._was_spilled1) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   531
        tty->print_cr("Warning, 2nd spill of L%d",bidx);
34174
4db2fb26dc49 8140424: don't prefix developer and notproduct flag variables with CONST_ in product builds
twisti
parents: 26913
diff changeset
   532
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   533
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   534
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   535
489c9b5090e2 Initial load
duke
parents:
diff changeset
   536
  // Create side arrays for propagating reaching defs info.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   537
  // Each block needs a node pointer for each spilling live range for the
489c9b5090e2 Initial load
duke
parents:
diff changeset
   538
  // Def which is live into the block.  Phi nodes handle multiple input
489c9b5090e2 Initial load
duke
parents:
diff changeset
   539
  // Defs by querying the output of their predecessor blocks and resolving
489c9b5090e2 Initial load
duke
parents:
diff changeset
   540
  // them to a single Def at the phi.  The pointer is updated for each
489c9b5090e2 Initial load
duke
parents:
diff changeset
   541
  // Def in the block, and then becomes the output for the block when
489c9b5090e2 Initial load
duke
parents:
diff changeset
   542
  // processing of the block is complete.  We also need to track whether
489c9b5090e2 Initial load
duke
parents:
diff changeset
   543
  // a Def is UP or DOWN.  UP means that it should get a register (ie -
489c9b5090e2 Initial load
duke
parents:
diff changeset
   544
  // it is always in LRP regions), and DOWN means that it is probably
489c9b5090e2 Initial load
duke
parents:
diff changeset
   545
  // on the stack (ie - it crosses HRP regions).
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   546
  Node ***Reaches     = NEW_SPLIT_ARRAY( Node**, _cfg.number_of_blocks() + 1);
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   547
  bool  **UP          = NEW_SPLIT_ARRAY( bool*, _cfg.number_of_blocks() + 1);
13520
a1ba7784ef54 7148109: C2 compiler consumes too much heap resources
kvn
parents: 13104
diff changeset
   548
  Node  **debug_defs  = NEW_SPLIT_ARRAY( Node*, spill_cnt );
a1ba7784ef54 7148109: C2 compiler consumes too much heap resources
kvn
parents: 13104
diff changeset
   549
  VectorSet **UP_entry= NEW_SPLIT_ARRAY( VectorSet*, spill_cnt );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   550
489c9b5090e2 Initial load
duke
parents:
diff changeset
   551
  // Initialize Reaches & UP
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   552
  for (bidx = 0; bidx < _cfg.number_of_blocks() + 1; bidx++) {
13520
a1ba7784ef54 7148109: C2 compiler consumes too much heap resources
kvn
parents: 13104
diff changeset
   553
    Reaches[bidx]     = NEW_SPLIT_ARRAY( Node*, spill_cnt );
a1ba7784ef54 7148109: C2 compiler consumes too much heap resources
kvn
parents: 13104
diff changeset
   554
    UP[bidx]          = NEW_SPLIT_ARRAY( bool, spill_cnt );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   555
    Node **Reachblock = Reaches[bidx];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   556
    bool *UPblock     = UP[bidx];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   557
    for( slidx = 0; slidx < spill_cnt; slidx++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   558
      UPblock[slidx] = true;     // Assume they start in registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
   559
      Reachblock[slidx] = NULL;  // Assume that no def is present
489c9b5090e2 Initial load
duke
parents:
diff changeset
   560
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   561
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   562
13520
a1ba7784ef54 7148109: C2 compiler consumes too much heap resources
kvn
parents: 13104
diff changeset
   563
#undef NEW_SPLIT_ARRAY
a1ba7784ef54 7148109: C2 compiler consumes too much heap resources
kvn
parents: 13104
diff changeset
   564
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   565
  // Initialize to array of empty vectorsets
489c9b5090e2 Initial load
duke
parents:
diff changeset
   566
  for( slidx = 0; slidx < spill_cnt; slidx++ )
13520
a1ba7784ef54 7148109: C2 compiler consumes too much heap resources
kvn
parents: 13104
diff changeset
   567
    UP_entry[slidx] = new VectorSet(split_arena);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   568
489c9b5090e2 Initial load
duke
parents:
diff changeset
   569
  //----------PASS 1----------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   570
  //----------Propagation & Node Insertion Code----------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   571
  // Walk the Blocks in RPO for DEF & USE info
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   572
  for( bidx = 0; bidx < _cfg.number_of_blocks(); bidx++ ) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   573
489c9b5090e2 Initial load
duke
parents:
diff changeset
   574
    if (C->check_node_count(spill_cnt, out_of_nodes)) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   575
      return 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   576
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   577
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
   578
    b  = _cfg.get_block(bidx);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   579
    // Reaches & UP arrays for this block
21100
c9bfb5a57f96 8026939: assert(Reachblock != NULL) failed: Reachblock must be non-NULL
adlertz
parents: 21086
diff changeset
   580
    Node** Reachblock = Reaches[b->_pre_order];
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   581
    UPblock    = UP[b->_pre_order];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   582
    // Reset counter of start of non-Phi nodes in block
489c9b5090e2 Initial load
duke
parents:
diff changeset
   583
    non_phi = 1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   584
    //----------Block Entry Handling----------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   585
    // Check for need to insert a new phi
489c9b5090e2 Initial load
duke
parents:
diff changeset
   586
    // Cycle through this block's predecessors, collecting Reaches
489c9b5090e2 Initial load
duke
parents:
diff changeset
   587
    // info for each spilled LRG.  If they are identical, no phi is
489c9b5090e2 Initial load
duke
parents:
diff changeset
   588
    // needed.  If they differ, check for a phi, and insert if missing,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   589
    // or update edges if present.  Set current block's Reaches set to
489c9b5090e2 Initial load
duke
parents:
diff changeset
   590
    // be either the phi's or the reaching def, as appropriate.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   591
    // If no Phi is needed, check if the LRG needs to spill on entry
489c9b5090e2 Initial load
duke
parents:
diff changeset
   592
    // to the block due to HRP.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   593
    for( slidx = 0; slidx < spill_cnt; slidx++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   594
      // Grab the live range number
489c9b5090e2 Initial load
duke
parents:
diff changeset
   595
      uint lidx = lidxs.at(slidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   596
      // Do not bother splitting or putting in Phis for single-def
489c9b5090e2 Initial load
duke
parents:
diff changeset
   597
      // rematerialized live ranges.  This happens alot to constants
489c9b5090e2 Initial load
duke
parents:
diff changeset
   598
      // with long live ranges.
1057
44220ef9a775 6732194: Data corruption dependent on -server/-client/-Xbatch
never
parents: 1
diff changeset
   599
      if( lrgs(lidx).is_singledef() &&
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   600
          lrgs(lidx)._def->rematerialize() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   601
        // reset the Reaches & UP entries
489c9b5090e2 Initial load
duke
parents:
diff changeset
   602
        Reachblock[slidx] = lrgs(lidx)._def;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   603
        UPblock[slidx] = true;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   604
        // Record following instruction in case 'n' rematerializes and
489c9b5090e2 Initial load
duke
parents:
diff changeset
   605
        // kills flags
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 17877
diff changeset
   606
        Block *pred1 = _cfg.get_block_for_node(b->pred(1));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   607
        continue;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   608
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   609
489c9b5090e2 Initial load
duke
parents:
diff changeset
   610
      // Initialize needs_phi and needs_split
489c9b5090e2 Initial load
duke
parents:
diff changeset
   611
      bool needs_phi = false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   612
      bool needs_split = false;
1134
799dce8f3426 6746892: Register Allocator does not process a data phi with one unique input correctly
kvn
parents: 1057
diff changeset
   613
      bool has_phi = false;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   614
      // Walk the predecessor blocks to check inputs for that live range
489c9b5090e2 Initial load
duke
parents:
diff changeset
   615
      // Grab predecessor block header
489c9b5090e2 Initial load
duke
parents:
diff changeset
   616
      n1 = b->pred(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   617
      // Grab the appropriate reaching def info for inpidx
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 17877
diff changeset
   618
      pred = _cfg.get_block_for_node(n1);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   619
      pidx = pred->_pre_order;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   620
      Node **Ltmp = Reaches[pidx];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   621
      bool  *Utmp = UP[pidx];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   622
      n1 = Ltmp[slidx];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   623
      u1 = Utmp[slidx];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   624
      // Initialize node for saving type info
489c9b5090e2 Initial load
duke
parents:
diff changeset
   625
      n3 = n1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   626
      u3 = u1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   627
489c9b5090e2 Initial load
duke
parents:
diff changeset
   628
      // Compare inputs to see if a Phi is needed
489c9b5090e2 Initial load
duke
parents:
diff changeset
   629
      for( inpidx = 2; inpidx < b->num_preds(); inpidx++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   630
        // Grab predecessor block headers
489c9b5090e2 Initial load
duke
parents:
diff changeset
   631
        n2 = b->pred(inpidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   632
        // Grab the appropriate reaching def info for inpidx
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 17877
diff changeset
   633
        pred = _cfg.get_block_for_node(n2);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   634
        pidx = pred->_pre_order;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   635
        Ltmp = Reaches[pidx];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   636
        Utmp = UP[pidx];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   637
        n2 = Ltmp[slidx];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   638
        u2 = Utmp[slidx];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   639
        // For each LRG, decide if a phi is necessary
489c9b5090e2 Initial load
duke
parents:
diff changeset
   640
        if( n1 != n2 ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   641
          needs_phi = true;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   642
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   643
        // See if the phi has mismatched inputs, UP vs. DOWN
489c9b5090e2 Initial load
duke
parents:
diff changeset
   644
        if( n1 && n2 && (u1 != u2) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   645
          needs_split = true;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   646
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   647
        // Move n2/u2 to n1/u1 for next iteration
489c9b5090e2 Initial load
duke
parents:
diff changeset
   648
        n1 = n2;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   649
        u1 = u2;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   650
        // Preserve a non-NULL predecessor for later type referencing
489c9b5090e2 Initial load
duke
parents:
diff changeset
   651
        if( (n3 == NULL) && (n2 != NULL) ){
489c9b5090e2 Initial load
duke
parents:
diff changeset
   652
          n3 = n2;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   653
          u3 = u2;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   654
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   655
      }  // End for all potential Phi inputs
489c9b5090e2 Initial load
duke
parents:
diff changeset
   656
1134
799dce8f3426 6746892: Register Allocator does not process a data phi with one unique input correctly
kvn
parents: 1057
diff changeset
   657
      // check block for appropriate phinode & update edges
799dce8f3426 6746892: Register Allocator does not process a data phi with one unique input correctly
kvn
parents: 1057
diff changeset
   658
      for( insidx = 1; insidx <= b->end_idx(); insidx++ ) {
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   659
        n1 = b->get_node(insidx);
1134
799dce8f3426 6746892: Register Allocator does not process a data phi with one unique input correctly
kvn
parents: 1057
diff changeset
   660
        // bail if this is not a phi
799dce8f3426 6746892: Register Allocator does not process a data phi with one unique input correctly
kvn
parents: 1057
diff changeset
   661
        phi = n1->is_Phi() ? n1->as_Phi() : NULL;
799dce8f3426 6746892: Register Allocator does not process a data phi with one unique input correctly
kvn
parents: 1057
diff changeset
   662
        if( phi == NULL ) {
799dce8f3426 6746892: Register Allocator does not process a data phi with one unique input correctly
kvn
parents: 1057
diff changeset
   663
          // Keep track of index of first non-PhiNode instruction in block
799dce8f3426 6746892: Register Allocator does not process a data phi with one unique input correctly
kvn
parents: 1057
diff changeset
   664
          non_phi = insidx;
799dce8f3426 6746892: Register Allocator does not process a data phi with one unique input correctly
kvn
parents: 1057
diff changeset
   665
          // break out of the for loop as we have handled all phi nodes
799dce8f3426 6746892: Register Allocator does not process a data phi with one unique input correctly
kvn
parents: 1057
diff changeset
   666
          break;
799dce8f3426 6746892: Register Allocator does not process a data phi with one unique input correctly
kvn
parents: 1057
diff changeset
   667
        }
799dce8f3426 6746892: Register Allocator does not process a data phi with one unique input correctly
kvn
parents: 1057
diff changeset
   668
        // must be looking at a phi
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   669
        if (_lrg_map.find_id(n1) == lidxs.at(slidx)) {
1134
799dce8f3426 6746892: Register Allocator does not process a data phi with one unique input correctly
kvn
parents: 1057
diff changeset
   670
          // found the necessary phi
799dce8f3426 6746892: Register Allocator does not process a data phi with one unique input correctly
kvn
parents: 1057
diff changeset
   671
          needs_phi = false;
799dce8f3426 6746892: Register Allocator does not process a data phi with one unique input correctly
kvn
parents: 1057
diff changeset
   672
          has_phi = true;
799dce8f3426 6746892: Register Allocator does not process a data phi with one unique input correctly
kvn
parents: 1057
diff changeset
   673
          // initialize the Reaches entry for this LRG
799dce8f3426 6746892: Register Allocator does not process a data phi with one unique input correctly
kvn
parents: 1057
diff changeset
   674
          Reachblock[slidx] = phi;
799dce8f3426 6746892: Register Allocator does not process a data phi with one unique input correctly
kvn
parents: 1057
diff changeset
   675
          break;
799dce8f3426 6746892: Register Allocator does not process a data phi with one unique input correctly
kvn
parents: 1057
diff changeset
   676
        }  // end if found correct phi
799dce8f3426 6746892: Register Allocator does not process a data phi with one unique input correctly
kvn
parents: 1057
diff changeset
   677
      }  // end for all phi's
799dce8f3426 6746892: Register Allocator does not process a data phi with one unique input correctly
kvn
parents: 1057
diff changeset
   678
799dce8f3426 6746892: Register Allocator does not process a data phi with one unique input correctly
kvn
parents: 1057
diff changeset
   679
      // If a phi is needed or exist, check for it
799dce8f3426 6746892: Register Allocator does not process a data phi with one unique input correctly
kvn
parents: 1057
diff changeset
   680
      if( needs_phi || has_phi ) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   681
        // add new phinode if one not already found
489c9b5090e2 Initial load
duke
parents:
diff changeset
   682
        if( needs_phi ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   683
          // create a new phi node and insert it into the block
489c9b5090e2 Initial load
duke
parents:
diff changeset
   684
          // type is taken from left over pointer to a predecessor
489c9b5090e2 Initial load
duke
parents:
diff changeset
   685
          assert(n3,"No non-NULL reaching DEF for a Phi");
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 22914
diff changeset
   686
          phi = new PhiNode(b->head(), n3->bottom_type());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   687
          // initialize the Reaches entry for this LRG
489c9b5090e2 Initial load
duke
parents:
diff changeset
   688
          Reachblock[slidx] = phi;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   689
489c9b5090e2 Initial load
duke
parents:
diff changeset
   690
          // add node to block & node_to_block mapping
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   691
          insert_proj(b, insidx++, phi, maxlrg++);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   692
          non_phi++;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   693
          // Reset new phi's mapping to be the spilling live range
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   694
          _lrg_map.map(phi->_idx, lidx);
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   695
          assert(_lrg_map.find_id(phi) == lidx, "Bad update on Union-Find mapping");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   696
        }  // end if not found correct phi
489c9b5090e2 Initial load
duke
parents:
diff changeset
   697
        // Here you have either found or created the Phi, so record it
489c9b5090e2 Initial load
duke
parents:
diff changeset
   698
        assert(phi != NULL,"Must have a Phi Node here");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   699
        phis->push(phi);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   700
        // PhiNodes should either force the LRG UP or DOWN depending
489c9b5090e2 Initial load
duke
parents:
diff changeset
   701
        // on its inputs and the register pressure in the Phi's block.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   702
        UPblock[slidx] = true;  // Assume new DEF is UP
489c9b5090e2 Initial load
duke
parents:
diff changeset
   703
        // If entering a high-pressure area with no immediate use,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   704
        // assume Phi is DOWN
489c9b5090e2 Initial load
duke
parents:
diff changeset
   705
        if( is_high_pressure( b, &lrgs(lidx), b->end_idx()) && !prompt_use(b,lidx) )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   706
          UPblock[slidx] = false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   707
        // If we are not split up/down and all inputs are down, then we
489c9b5090e2 Initial load
duke
parents:
diff changeset
   708
        // are down
489c9b5090e2 Initial load
duke
parents:
diff changeset
   709
        if( !needs_split && !u3 )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   710
          UPblock[slidx] = false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   711
      }  // end if phi is needed
489c9b5090e2 Initial load
duke
parents:
diff changeset
   712
489c9b5090e2 Initial load
duke
parents:
diff changeset
   713
      // Do not need a phi, so grab the reaching DEF
489c9b5090e2 Initial load
duke
parents:
diff changeset
   714
      else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   715
        // Grab predecessor block header
489c9b5090e2 Initial load
duke
parents:
diff changeset
   716
        n1 = b->pred(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   717
        // Grab the appropriate reaching def info for k
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 17877
diff changeset
   718
        pred = _cfg.get_block_for_node(n1);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   719
        pidx = pred->_pre_order;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   720
        Node **Ltmp = Reaches[pidx];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   721
        bool  *Utmp = UP[pidx];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   722
        // reset the Reaches & UP entries
489c9b5090e2 Initial load
duke
parents:
diff changeset
   723
        Reachblock[slidx] = Ltmp[slidx];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   724
        UPblock[slidx] = Utmp[slidx];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   725
      }  // end else no Phi is needed
489c9b5090e2 Initial load
duke
parents:
diff changeset
   726
    }  // end for all spilling live ranges
489c9b5090e2 Initial load
duke
parents:
diff changeset
   727
    // DEBUG
489c9b5090e2 Initial load
duke
parents:
diff changeset
   728
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   729
    if(trace_spilling()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   730
      tty->print("/`\nBlock %d: ", b->_pre_order);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   731
      tty->print("Reaching Definitions after Phi handling\n");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   732
      for( uint x = 0; x < spill_cnt; x++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   733
        tty->print("Spill Idx %d: UP %d: Node\n",x,UPblock[x]);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   734
        if( Reachblock[x] )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   735
          Reachblock[x]->dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   736
        else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   737
          tty->print("Undefined\n");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   738
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   739
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   740
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   741
489c9b5090e2 Initial load
duke
parents:
diff changeset
   742
    //----------Non-Phi Node Splitting----------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   743
    // Since phi-nodes have now been handled, the Reachblock array for this
489c9b5090e2 Initial load
duke
parents:
diff changeset
   744
    // block is initialized with the correct starting value for the defs which
489c9b5090e2 Initial load
duke
parents:
diff changeset
   745
    // reach non-phi instructions in this block.  Thus, process non-phi
489c9b5090e2 Initial load
duke
parents:
diff changeset
   746
    // instructions normally, inserting SpillCopy nodes for all spill
489c9b5090e2 Initial load
duke
parents:
diff changeset
   747
    // locations.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   748
489c9b5090e2 Initial load
duke
parents:
diff changeset
   749
    // Memoize any DOWN reaching definitions for use as DEBUG info
489c9b5090e2 Initial load
duke
parents:
diff changeset
   750
    for( insidx = 0; insidx < spill_cnt; insidx++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   751
      debug_defs[insidx] = (UPblock[insidx]) ? NULL : Reachblock[insidx];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   752
      if( UPblock[insidx] )     // Memoize UP decision at block start
489c9b5090e2 Initial load
duke
parents:
diff changeset
   753
        UP_entry[insidx]->set( b->_pre_order );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   754
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   755
489c9b5090e2 Initial load
duke
parents:
diff changeset
   756
    //----------Walk Instructions in the Block and Split----------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   757
    // For all non-phi instructions in the block
489c9b5090e2 Initial load
duke
parents:
diff changeset
   758
    for( insidx = 1; insidx <= b->end_idx(); insidx++ ) {
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   759
      Node *n = b->get_node(insidx);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   760
      // Find the defining Node's live range index
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   761
      uint defidx = _lrg_map.find_id(n);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   762
      uint cnt = n->req();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   763
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   764
      if (n->is_Phi()) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   765
        // Skip phi nodes after removing dead copies.
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   766
        if (defidx < _lrg_map.max_lrg_id()) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   767
          // Check for useless Phis.  These appear if we spill, then
489c9b5090e2 Initial load
duke
parents:
diff changeset
   768
          // coalesce away copies.  Dont touch Phis in spilling live
489c9b5090e2 Initial load
duke
parents:
diff changeset
   769
          // ranges; they are busy getting modifed in this pass.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   770
          if( lrgs(defidx).reg() < LRG::SPILL_REG ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   771
            uint i;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   772
            Node *u = NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   773
            // Look for the Phi merging 2 unique inputs
489c9b5090e2 Initial load
duke
parents:
diff changeset
   774
            for( i = 1; i < cnt; i++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   775
              // Ignore repeats and self
489c9b5090e2 Initial load
duke
parents:
diff changeset
   776
              if( n->in(i) != u && n->in(i) != n ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   777
                // Found a unique input
489c9b5090e2 Initial load
duke
parents:
diff changeset
   778
                if( u != NULL ) // If it's the 2nd, bail out
489c9b5090e2 Initial load
duke
parents:
diff changeset
   779
                  break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   780
                u = n->in(i);   // Else record it
489c9b5090e2 Initial load
duke
parents:
diff changeset
   781
              }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   782
            }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   783
            assert( u, "at least 1 valid input expected" );
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   784
            if (i >= cnt) {    // Found one unique input
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   785
              assert(_lrg_map.find_id(n) == _lrg_map.find_id(u), "should be the same lrg");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   786
              n->replace_by(u); // Then replace with unique input
14623
70c4c1be0a14 7092905: C2: Keep track of the number of dead nodes
bharadwaj
parents: 13895
diff changeset
   787
              n->disconnect_inputs(NULL, C);
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   788
              b->remove_node(insidx);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   789
              insidx--;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   790
              b->_ihrp_index--;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   791
              b->_fhrp_index--;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   792
            }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   793
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   794
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   795
        continue;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   796
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   797
      assert( insidx > b->_ihrp_index ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
   798
              (b->_reg_pressure < (uint)INTPRESSURE) ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
   799
              b->_ihrp_index > 4000000 ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
   800
              b->_ihrp_index >= b->end_idx() ||
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   801
              !b->get_node(b->_ihrp_index)->is_Proj(), "" );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   802
      assert( insidx > b->_fhrp_index ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
   803
              (b->_freg_pressure < (uint)FLOATPRESSURE) ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
   804
              b->_fhrp_index > 4000000 ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
   805
              b->_fhrp_index >= b->end_idx() ||
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   806
              !b->get_node(b->_fhrp_index)->is_Proj(), "" );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   807
489c9b5090e2 Initial load
duke
parents:
diff changeset
   808
      // ********** Handle Crossing HRP Boundry **********
489c9b5090e2 Initial load
duke
parents:
diff changeset
   809
      if( (insidx == b->_ihrp_index) || (insidx == b->_fhrp_index) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   810
        for( slidx = 0; slidx < spill_cnt; slidx++ ) {
2131
98f9cef66a34 6810672: Comment typos
twisti
parents: 2030
diff changeset
   811
          // Check for need to split at HRP boundary - split if UP
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   812
          n1 = Reachblock[slidx];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   813
          // bail out if no reaching DEF
489c9b5090e2 Initial load
duke
parents:
diff changeset
   814
          if( n1 == NULL ) continue;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   815
          // bail out if live range is 'isolated' around inner loop
489c9b5090e2 Initial load
duke
parents:
diff changeset
   816
          uint lidx = lidxs.at(slidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   817
          // If live range is currently UP
489c9b5090e2 Initial load
duke
parents:
diff changeset
   818
          if( UPblock[slidx] ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   819
            // set location to insert spills at
489c9b5090e2 Initial load
duke
parents:
diff changeset
   820
            // SPLIT DOWN HERE - NO CISC SPILL
489c9b5090e2 Initial load
duke
parents:
diff changeset
   821
            if( is_high_pressure( b, &lrgs(lidx), insidx ) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   822
                !n1->rematerialize() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   823
              // If there is already a valid stack definition available, use it
489c9b5090e2 Initial load
duke
parents:
diff changeset
   824
              if( debug_defs[slidx] != NULL ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   825
                Reachblock[slidx] = debug_defs[slidx];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   826
              }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   827
              else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   828
                // Insert point is just past last use or def in the block
489c9b5090e2 Initial load
duke
parents:
diff changeset
   829
                int insert_point = insidx-1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   830
                while( insert_point > 0 ) {
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   831
                  Node *n = b->get_node(insert_point);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   832
                  // Hit top of block?  Quit going backwards
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   833
                  if (n->is_Phi()) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   834
                    break;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   835
                  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   836
                  // Found a def?  Better split after it.
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   837
                  if (_lrg_map.live_range_id(n) == lidx) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   838
                    break;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   839
                  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   840
                  // Look for a use
489c9b5090e2 Initial load
duke
parents:
diff changeset
   841
                  uint i;
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   842
                  for( i = 1; i < n->req(); i++ ) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   843
                    if (_lrg_map.live_range_id(n->in(i)) == lidx) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   844
                      break;
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   845
                    }
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   846
                  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   847
                  // Found a use?  Better split after it.
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   848
                  if (i < n->req()) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   849
                    break;
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   850
                  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   851
                  insert_point--;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   852
                }
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 10255
diff changeset
   853
                uint orig_eidx = b->end_idx();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   854
                maxlrg = split_DEF( n1, b, insert_point, maxlrg, Reachblock, debug_defs, splits, slidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   855
                // If it wasn't split bail
489c9b5090e2 Initial load
duke
parents:
diff changeset
   856
                if (!maxlrg) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   857
                  return 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   858
                }
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 10255
diff changeset
   859
                // Spill of NULL check mem op goes into the following block.
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   860
                if (b->end_idx() > orig_eidx) {
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 10255
diff changeset
   861
                  insidx++;
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   862
                }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   863
              }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   864
              // This is a new DEF, so update UP
489c9b5090e2 Initial load
duke
parents:
diff changeset
   865
              UPblock[slidx] = false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   866
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   867
              // DEBUG
489c9b5090e2 Initial load
duke
parents:
diff changeset
   868
              if( trace_spilling() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   869
                tty->print("\nNew Split DOWN DEF of Spill Idx ");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   870
                tty->print("%d, UP %d:\n",slidx,false);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   871
                n1->dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   872
              }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   873
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   874
            }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   875
          }  // end if LRG is UP
489c9b5090e2 Initial load
duke
parents:
diff changeset
   876
        }  // end for all spilling live ranges
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   877
        assert( b->get_node(insidx) == n, "got insidx set incorrectly" );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   878
      }  // end if crossing HRP Boundry
489c9b5090e2 Initial load
duke
parents:
diff changeset
   879
489c9b5090e2 Initial load
duke
parents:
diff changeset
   880
      // If the LRG index is oob, then this is a new spillcopy, skip it.
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   881
      if (defidx >= _lrg_map.max_lrg_id()) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   882
        continue;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   883
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   884
      LRG &deflrg = lrgs(defidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   885
      uint copyidx = n->is_Copy();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   886
      // Remove coalesced copy from CFG
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   887
      if (copyidx && defidx == _lrg_map.live_range_id(n->in(copyidx))) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   888
        n->replace_by( n->in(copyidx) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   889
        n->set_req( copyidx, NULL );
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   890
        b->remove_node(insidx--);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   891
        b->_ihrp_index--; // Adjust the point where we go hi-pressure
489c9b5090e2 Initial load
duke
parents:
diff changeset
   892
        b->_fhrp_index--;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   893
        continue;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   894
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   895
489c9b5090e2 Initial load
duke
parents:
diff changeset
   896
#define DERIVED 0
489c9b5090e2 Initial load
duke
parents:
diff changeset
   897
489c9b5090e2 Initial load
duke
parents:
diff changeset
   898
      // ********** Handle USES **********
489c9b5090e2 Initial load
duke
parents:
diff changeset
   899
      bool nullcheck = false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   900
      // Implicit null checks never use the spilled value
489c9b5090e2 Initial load
duke
parents:
diff changeset
   901
      if( n->is_MachNullCheck() )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   902
        nullcheck = true;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   903
      if( !nullcheck ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   904
        // Search all inputs for a Spill-USE
489c9b5090e2 Initial load
duke
parents:
diff changeset
   905
        JVMState* jvms = n->jvms();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   906
        uint oopoff = jvms ? jvms->oopoff() : cnt;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   907
        uint old_last = cnt - 1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   908
        for( inpidx = 1; inpidx < cnt; inpidx++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   909
          // Derived/base pairs may be added to our inputs during this loop.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   910
          // If inpidx > old_last, then one of these new inputs is being
489c9b5090e2 Initial load
duke
parents:
diff changeset
   911
          // handled. Skip the derived part of the pair, but process
489c9b5090e2 Initial load
duke
parents:
diff changeset
   912
          // the base like any other input.
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   913
          if (inpidx > old_last && ((inpidx - oopoff) & 1) == DERIVED) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   914
            continue;  // skip derived_debug added below
489c9b5090e2 Initial load
duke
parents:
diff changeset
   915
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   916
          // Get lidx of input
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   917
          uint useidx = _lrg_map.find_id(n->in(inpidx));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   918
          // Not a brand-new split, and it is a spill use
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   919
          if (useidx < _lrg_map.max_lrg_id() && lrgs(useidx).reg() >= LRG::SPILL_REG) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   920
            // Check for valid reaching DEF
489c9b5090e2 Initial load
duke
parents:
diff changeset
   921
            slidx = lrg2reach[useidx];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   922
            Node *def = Reachblock[slidx];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   923
            assert( def != NULL, "Using Undefined Value in Split()\n");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   924
489c9b5090e2 Initial load
duke
parents:
diff changeset
   925
            // (+++) %%%% remove this in favor of pre-pass in matcher.cpp
489c9b5090e2 Initial load
duke
parents:
diff changeset
   926
            // monitor references do not care where they live, so just hook
489c9b5090e2 Initial load
duke
parents:
diff changeset
   927
            if ( jvms && jvms->is_monitor_use(inpidx) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   928
              // The effect of this clone is to drop the node out of the block,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   929
              // so that the allocator does not see it anymore, and therefore
489c9b5090e2 Initial load
duke
parents:
diff changeset
   930
              // does not attempt to assign it a register.
6188
95ea4d66089a 6973329: C2 with Zero based COOP produces code with broken anti-dependency on x86
kvn
parents: 5547
diff changeset
   931
              def = clone_node(def, b, C);
95ea4d66089a 6973329: C2 with Zero based COOP produces code with broken anti-dependency on x86
kvn
parents: 5547
diff changeset
   932
              if (def == NULL || C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) {
95ea4d66089a 6973329: C2 with Zero based COOP produces code with broken anti-dependency on x86
kvn
parents: 5547
diff changeset
   933
                return 0;
95ea4d66089a 6973329: C2 with Zero based COOP produces code with broken anti-dependency on x86
kvn
parents: 5547
diff changeset
   934
              }
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
   935
              _lrg_map.extend(def->_idx, 0);
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 17877
diff changeset
   936
              _cfg.map_node_to_block(def, b);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   937
              n->set_req(inpidx, def);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   938
              continue;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   939
            }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   940
489c9b5090e2 Initial load
duke
parents:
diff changeset
   941
            // Rematerializable?  Then clone def at use site instead
489c9b5090e2 Initial load
duke
parents:
diff changeset
   942
            // of store/load
489c9b5090e2 Initial load
duke
parents:
diff changeset
   943
            if( def->rematerialize() ) {
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   944
              int old_size = b->number_of_nodes();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   945
              def = split_Rematerialize( def, b, insidx, maxlrg, splits, slidx, lrg2reach, Reachblock, true );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   946
              if( !def ) return 0; // Bail out
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
   947
              insidx += b->number_of_nodes()-old_size;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   948
            }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   949
489c9b5090e2 Initial load
duke
parents:
diff changeset
   950
            MachNode *mach = n->is_Mach() ? n->as_Mach() : NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   951
            // Base pointers and oopmap references do not care where they live.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   952
            if ((inpidx >= oopoff) ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
   953
                (mach && mach->ideal_Opcode() == Op_AddP && inpidx == AddPNode::Base)) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   954
              if (def->rematerialize() && lrgs(useidx)._was_spilled2) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   955
                // This def has been rematerialized a couple of times without
489c9b5090e2 Initial load
duke
parents:
diff changeset
   956
                // progress. It doesn't care if it lives UP or DOWN, so
489c9b5090e2 Initial load
duke
parents:
diff changeset
   957
                // spill it down now.
22914
0712db174bbb 8032656: Tag the MachSpillCopies with purpose information
adlertz
parents: 22234
diff changeset
   958
                maxlrg = split_USE(MachSpillCopyNode::BasePointerToMem, def,b,n,inpidx,maxlrg,false,false,splits,slidx);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   959
                // If it wasn't split bail
489c9b5090e2 Initial load
duke
parents:
diff changeset
   960
                if (!maxlrg) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   961
                  return 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   962
                }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   963
                insidx++;  // Reset iterator to skip USE side split
489c9b5090e2 Initial load
duke
parents:
diff changeset
   964
              } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   965
                // Just hook the def edge
489c9b5090e2 Initial load
duke
parents:
diff changeset
   966
                n->set_req(inpidx, def);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   967
              }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   968
489c9b5090e2 Initial load
duke
parents:
diff changeset
   969
              if (inpidx >= oopoff) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   970
                // After oopoff, we have derived/base pairs.  We must mention all
489c9b5090e2 Initial load
duke
parents:
diff changeset
   971
                // derived pointers here as derived/base pairs for GC.  If the
489c9b5090e2 Initial load
duke
parents:
diff changeset
   972
                // derived value is spilling and we have a copy both in Reachblock
489c9b5090e2 Initial load
duke
parents:
diff changeset
   973
                // (called here 'def') and debug_defs[slidx] we need to mention
489c9b5090e2 Initial load
duke
parents:
diff changeset
   974
                // both in derived/base pairs or kill one.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   975
                Node *derived_debug = debug_defs[slidx];
489c9b5090e2 Initial load
duke
parents:
diff changeset
   976
                if( ((inpidx - oopoff) & 1) == DERIVED && // derived vs base?
489c9b5090e2 Initial load
duke
parents:
diff changeset
   977
                    mach && mach->ideal_Opcode() != Op_Halt &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   978
                    derived_debug != NULL &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   979
                    derived_debug != def ) { // Actual 2nd value appears
489c9b5090e2 Initial load
duke
parents:
diff changeset
   980
                  // We have already set 'def' as a derived value.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   981
                  // Also set debug_defs[slidx] as a derived value.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   982
                  uint k;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   983
                  for( k = oopoff; k < cnt; k += 2 )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   984
                    if( n->in(k) == derived_debug )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   985
                      break;      // Found an instance of debug derived
489c9b5090e2 Initial load
duke
parents:
diff changeset
   986
                  if( k == cnt ) {// No instance of debug_defs[slidx]
489c9b5090e2 Initial load
duke
parents:
diff changeset
   987
                    // Add a derived/base pair to cover the debug info.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   988
                    // We have to process the added base later since it is not
489c9b5090e2 Initial load
duke
parents:
diff changeset
   989
                    // handled yet at this point but skip derived part.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   990
                    assert(((n->req() - oopoff) & 1) == DERIVED,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   991
                           "must match skip condition above");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   992
                    n->add_req( derived_debug );   // this will be skipped above
489c9b5090e2 Initial load
duke
parents:
diff changeset
   993
                    n->add_req( n->in(inpidx+1) ); // this will be processed
489c9b5090e2 Initial load
duke
parents:
diff changeset
   994
                    // Increment cnt to handle added input edges on
489c9b5090e2 Initial load
duke
parents:
diff changeset
   995
                    // subsequent iterations.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   996
                    cnt += 2;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   997
                  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   998
                }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   999
              }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1000
              continue;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1001
            }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1002
            // Special logic for DEBUG info
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1003
            if( jvms && b->_freq > BLOCK_FREQUENCY(0.5) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1004
              uint debug_start = jvms->debug_start();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1005
              // If this is debug info use & there is a reaching DOWN def
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1006
              if ((debug_start <= inpidx) && (debug_defs[slidx] != NULL)) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1007
                assert(inpidx < oopoff, "handle only debug info here");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1008
                // Just hook it in & move on
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1009
                n->set_req(inpidx, debug_defs[slidx]);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1010
                // (Note that this can make two sides of a split live at the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1011
                // same time: The debug def on stack, and another def in a
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1012
                // register.  The GC needs to know about both of them, but any
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1013
                // derived pointers after oopoff will refer to only one of the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1014
                // two defs and the GC would therefore miss the other.  Thus
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1015
                // this hack is only allowed for debug info which is Java state
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1016
                // and therefore never a derived pointer.)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1017
                continue;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1018
              }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1019
            }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1020
            // Grab register mask info
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1021
            const RegMask &dmask = def->out_RegMask();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1022
            const RegMask &umask = n->in_RegMask(inpidx);
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 10255
diff changeset
  1023
            bool is_vect = RegMask::is_vector(def->ideal_reg());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1024
            assert(inpidx < oopoff, "cannot use-split oop map info");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1025
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1026
            bool dup = UPblock[slidx];
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1027
            bool uup = umask.is_UP();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1028
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1029
            // Need special logic to handle bound USES. Insert a split at this
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1030
            // bound use if we can't rematerialize the def, or if we need the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1031
            // split to form a misaligned pair.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1032
            if( !umask.is_AllStack() &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1033
                (int)umask.Size() <= lrgs(useidx).num_regs() &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1034
                (!def->rematerialize() ||
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 10255
diff changeset
  1035
                 !is_vect && umask.is_misaligned_pair())) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1036
              // These need a Split regardless of overlap or pressure
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1037
              // SPLIT - NO DEF - NO CISC SPILL
22914
0712db174bbb 8032656: Tag the MachSpillCopies with purpose information
adlertz
parents: 22234
diff changeset
  1038
              maxlrg = split_USE(MachSpillCopyNode::Bound, def,b,n,inpidx,maxlrg,dup,false, splits,slidx);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1039
              // If it wasn't split bail
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1040
              if (!maxlrg) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1041
                return 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1042
              }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1043
              insidx++;  // Reset iterator to skip USE side split
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1044
              continue;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1045
            }
6272
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 6188
diff changeset
  1046
10255
bab46e6f7661 7069452: Cleanup NodeFlags
kvn
parents: 7441
diff changeset
  1047
            if (UseFPUForSpilling && n->is_MachCall() && !uup && !dup ) {
6272
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 6188
diff changeset
  1048
              // The use at the call can force the def down so insert
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 6188
diff changeset
  1049
              // a split before the use to allow the def more freedom.
22914
0712db174bbb 8032656: Tag the MachSpillCopies with purpose information
adlertz
parents: 22234
diff changeset
  1050
              maxlrg = split_USE(MachSpillCopyNode::CallUse, def,b,n,inpidx,maxlrg,dup,false, splits,slidx);
6272
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 6188
diff changeset
  1051
              // If it wasn't split bail
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 6188
diff changeset
  1052
              if (!maxlrg) {
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 6188
diff changeset
  1053
                return 0;
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 6188
diff changeset
  1054
              }
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 6188
diff changeset
  1055
              insidx++;  // Reset iterator to skip USE side split
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 6188
diff changeset
  1056
              continue;
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 6188
diff changeset
  1057
            }
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 6188
diff changeset
  1058
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1059
            // Here is the logic chart which describes USE Splitting:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1060
            // 0 = false or DOWN, 1 = true or UP
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1061
            //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1062
            // Overlap | DEF | USE | Action
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1063
            //-------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1064
            //    0    |  0  |  0  | Copy - mem -> mem
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1065
            //    0    |  0  |  1  | Split-UP - Check HRP
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1066
            //    0    |  1  |  0  | Split-DOWN - Debug Info?
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1067
            //    0    |  1  |  1  | Copy - reg -> reg
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1068
            //    1    |  0  |  0  | Reset Input Edge (no Split)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1069
            //    1    |  0  |  1  | Split-UP - Check HRP
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1070
            //    1    |  1  |  0  | Split-DOWN - Debug Info?
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1071
            //    1    |  1  |  1  | Reset Input Edge (no Split)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1072
            //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1073
            // So, if (dup == uup), then overlap test determines action,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1074
            // with true being no split, and false being copy. Else,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1075
            // if DEF is DOWN, Split-UP, and check HRP to decide on
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1076
            // resetting DEF. Finally if DEF is UP, Split-DOWN, with
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1077
            // special handling for Debug Info.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1078
            if( dup == uup ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1079
              if( dmask.overlap(umask) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1080
                // Both are either up or down, and there is overlap, No Split
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1081
                n->set_req(inpidx, def);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1082
              }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1083
              else {  // Both are either up or down, and there is no overlap
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1084
                if( dup ) {  // If UP, reg->reg copy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1085
                  // COPY ACROSS HERE - NO DEF - NO CISC SPILL
22914
0712db174bbb 8032656: Tag the MachSpillCopies with purpose information
adlertz
parents: 22234
diff changeset
  1086
                  maxlrg = split_USE(MachSpillCopyNode::RegToReg, def,b,n,inpidx,maxlrg,false,false, splits,slidx);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1087
                  // If it wasn't split bail
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1088
                  if (!maxlrg) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1089
                    return 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1090
                  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1091
                  insidx++;  // Reset iterator to skip USE side split
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1092
                }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1093
                else {       // DOWN, mem->mem copy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1094
                  // COPY UP & DOWN HERE - NO DEF - NO CISC SPILL
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1095
                  // First Split-UP to move value into Register
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1096
                  uint def_ideal = def->ideal_reg();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1097
                  const RegMask* tmp_rm = Matcher::idealreg2regmask[def_ideal];
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 22914
diff changeset
  1098
                  Node *spill = new MachSpillCopyNode(MachSpillCopyNode::MemToReg, def, dmask, *tmp_rm);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1099
                  insert_proj( b, insidx, spill, maxlrg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1100
                  // Then Split-DOWN as if previous Split was DEF
22914
0712db174bbb 8032656: Tag the MachSpillCopies with purpose information
adlertz
parents: 22234
diff changeset
  1101
                  maxlrg = split_USE(MachSpillCopyNode::RegToMem, spill,b,n,inpidx,maxlrg,false,false, splits,slidx);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1102
                  // If it wasn't split bail
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1103
                  if (!maxlrg) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1104
                    return 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1105
                  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1106
                  insidx += 2;  // Reset iterator to skip USE side splits
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1107
                }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1108
              }  // End else no overlap
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1109
            }  // End if dup == uup
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1110
            // dup != uup, so check dup for direction of Split
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1111
            else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1112
              if( dup ) {  // If UP, Split-DOWN and check Debug Info
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1113
                // If this node is already a SpillCopy, just patch the edge
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1114
                // except the case of spilling to stack.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1115
                if( n->is_SpillCopy() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1116
                  RegMask tmp_rm(umask);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1117
                  tmp_rm.SUBTRACT(Matcher::STACK_ONLY_mask);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1118
                  if( dmask.overlap(tmp_rm) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1119
                    if( def != n->in(inpidx) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1120
                      n->set_req(inpidx, def);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1121
                    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1122
                    continue;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1123
                  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1124
                }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1125
                // COPY DOWN HERE - NO DEF - NO CISC SPILL
22914
0712db174bbb 8032656: Tag the MachSpillCopies with purpose information
adlertz
parents: 22234
diff changeset
  1126
                maxlrg = split_USE(MachSpillCopyNode::RegToMem, def,b,n,inpidx,maxlrg,false,false, splits,slidx);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1127
                // If it wasn't split bail
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1128
                if (!maxlrg) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1129
                  return 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1130
                }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1131
                insidx++;  // Reset iterator to skip USE side split
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1132
                // Check for debug-info split.  Capture it for later
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1133
                // debug splits of the same value
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1134
                if (jvms && jvms->debug_start() <= inpidx && inpidx < oopoff)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1135
                  debug_defs[slidx] = n->in(inpidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1136
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1137
              }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1138
              else {       // DOWN, Split-UP and check register pressure
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1139
                if( is_high_pressure( b, &lrgs(useidx), insidx ) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1140
                  // COPY UP HERE - NO DEF - CISC SPILL
22914
0712db174bbb 8032656: Tag the MachSpillCopies with purpose information
adlertz
parents: 22234
diff changeset
  1141
                  maxlrg = split_USE(MachSpillCopyNode::MemToReg, def,b,n,inpidx,maxlrg,true,true, splits,slidx);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1142
                  // If it wasn't split bail
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1143
                  if (!maxlrg) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1144
                    return 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1145
                  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1146
                  insidx++;  // Reset iterator to skip USE side split
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1147
                } else {                          // LRP
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1148
                  // COPY UP HERE - WITH DEF - NO CISC SPILL
22914
0712db174bbb 8032656: Tag the MachSpillCopies with purpose information
adlertz
parents: 22234
diff changeset
  1149
                  maxlrg = split_USE(MachSpillCopyNode::MemToReg, def,b,n,inpidx,maxlrg,true,false, splits,slidx);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1150
                  // If it wasn't split bail
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1151
                  if (!maxlrg) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1152
                    return 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1153
                  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1154
                  // Flag this lift-up in a low-pressure block as
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1155
                  // already-spilled, so if it spills again it will
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1156
                  // spill hard (instead of not spilling hard and
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1157
                  // coalescing away).
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1158
                  set_was_spilled(n->in(inpidx));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1159
                  // Since this is a new DEF, update Reachblock & UP
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1160
                  Reachblock[slidx] = n->in(inpidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1161
                  UPblock[slidx] = true;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1162
                  insidx++;  // Reset iterator to skip USE side split
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1163
                }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1164
              }  // End else DOWN
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1165
            }  // End dup != uup
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1166
          }  // End if Spill USE
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1167
        }  // End For All Inputs
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1168
      }  // End If not nullcheck
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1169
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1170
      // ********** Handle DEFS **********
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1171
      // DEFS either Split DOWN in HRP regions or when the LRG is bound, or
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1172
      // just reset the Reaches info in LRP regions.  DEFS must always update
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1173
      // UP info.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1174
      if( deflrg.reg() >= LRG::SPILL_REG ) {    // Spilled?
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1175
        uint slidx = lrg2reach[defidx];
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1176
        // Add to defs list for later assignment of new live range number
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1177
        defs->push(n);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1178
        // Set a flag on the Node indicating it has already spilled.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1179
        // Only do it for capacity spills not conflict spills.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1180
        if( !deflrg._direct_conflict )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1181
          set_was_spilled(n);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1182
        assert(!n->is_Phi(),"Cannot insert Phi into DEFS list");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1183
        // Grab UP info for DEF
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1184
        const RegMask &dmask = n->out_RegMask();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1185
        bool defup = dmask.is_UP();
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 10255
diff changeset
  1186
        int ireg = n->ideal_reg();
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 10255
diff changeset
  1187
        bool is_vect = RegMask::is_vector(ireg);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1188
        // Only split at Def if this is a HRP block or bound (and spilled once)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1189
        if( !n->rematerialize() &&
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 10255
diff changeset
  1190
            (((dmask.is_bound(ireg) || !is_vect && dmask.is_misaligned_pair()) &&
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 10255
diff changeset
  1191
              (deflrg._direct_conflict || deflrg._must_spill)) ||
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1192
             // Check for LRG being up in a register and we are inside a high
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1193
             // pressure area.  Spill it down immediately.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1194
             (defup && is_high_pressure(b,&deflrg,insidx))) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1195
          assert( !n->rematerialize(), "" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1196
          assert( !n->is_SpillCopy(), "" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1197
          // Do a split at the def site.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1198
          maxlrg = split_DEF( n, b, insidx, maxlrg, Reachblock, debug_defs, splits, slidx );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1199
          // If it wasn't split bail
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1200
          if (!maxlrg) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1201
            return 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1202
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1203
          // Split DEF's Down
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1204
          UPblock[slidx] = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1205
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1206
          // DEBUG
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1207
          if( trace_spilling() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1208
            tty->print("\nNew Split DOWN DEF of Spill Idx ");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1209
            tty->print("%d, UP %d:\n",slidx,false);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1210
            n->dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1211
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1212
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1213
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1214
        else {                  // Neither bound nor HRP, must be LRP
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1215
          // otherwise, just record the def
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1216
          Reachblock[slidx] = n;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1217
          // UP should come from the outRegmask() of the DEF
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1218
          UPblock[slidx] = defup;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1219
          // Update debug list of reaching down definitions, kill if DEF is UP
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1220
          debug_defs[slidx] = defup ? NULL : n;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1221
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1222
          // DEBUG
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1223
          if( trace_spilling() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1224
            tty->print("\nNew DEF of Spill Idx ");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1225
            tty->print("%d, UP %d:\n",slidx,defup);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1226
            n->dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1227
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1228
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1229
        }  // End else LRP
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1230
      }  // End if spill def
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1231
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1232
      // ********** Split Left Over Mem-Mem Moves **********
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1233
      // Check for mem-mem copies and split them now.  Do not do this
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1234
      // to copies about to be spilled; they will be Split shortly.
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1235
      if (copyidx) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1236
        Node *use = n->in(copyidx);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1237
        uint useidx = _lrg_map.find_id(use);
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1238
        if (useidx < _lrg_map.max_lrg_id() &&       // This is not a new split
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1239
            OptoReg::is_stack(deflrg.reg()) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1240
            deflrg.reg() < LRG::SPILL_REG ) { // And DEF is from stack
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1241
          LRG &uselrg = lrgs(useidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1242
          if( OptoReg::is_stack(uselrg.reg()) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1243
              uselrg.reg() < LRG::SPILL_REG && // USE is from stack
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1244
              deflrg.reg() != uselrg.reg() ) { // Not trivially removed
13728
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 13520
diff changeset
  1245
            uint def_ideal_reg = n->bottom_type()->ideal_reg();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1246
            const RegMask &def_rm = *Matcher::idealreg2regmask[def_ideal_reg];
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1247
            const RegMask &use_rm = n->in_RegMask(copyidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1248
            if( def_rm.overlap(use_rm) && n->is_SpillCopy() ) {  // Bug 4707800, 'n' may be a storeSSL
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1249
              if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) {  // Check when generating nodes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1250
                return 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1251
              }
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 22914
diff changeset
  1252
              Node *spill = new MachSpillCopyNode(MachSpillCopyNode::MemToReg, use,use_rm,def_rm);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1253
              n->set_req(copyidx,spill);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1254
              n->as_MachSpillCopy()->set_in_RegMask(def_rm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1255
              // Put the spill just before the copy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1256
              insert_proj( b, insidx++, spill, maxlrg++ );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1257
            }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1258
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1259
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1260
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1261
    }  // End For All Instructions in Block - Non-PHI Pass
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1262
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1263
    // Check if each LRG is live out of this block so as not to propagate
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1264
    // beyond the last use of a LRG.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1265
    for( slidx = 0; slidx < spill_cnt; slidx++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1266
      uint defidx = lidxs.at(slidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1267
      IndexSet *liveout = _live->live(b);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1268
      if( !liveout->member(defidx) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1269
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1270
        // The index defidx is not live.  Check the liveout array to ensure that
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1271
        // it contains no members which compress to defidx.  Finding such an
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1272
        // instance may be a case to add liveout adjustment in compress_uf_map().
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1273
        // See 5063219.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1274
        uint member;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1275
        IndexSetIterator isi(liveout);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1276
        while ((member = isi.next()) != 0) {
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1277
          assert(defidx != _lrg_map.find_const(member), "Live out member has not been compressed");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1278
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1279
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1280
        Reachblock[slidx] = NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1281
      } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1282
        assert(Reachblock[slidx] != NULL,"No reaching definition for liveout value");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1283
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1284
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1285
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1286
    if( trace_spilling() )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1287
      b->dump();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1288
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1289
  }  // End For All Blocks
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1290
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1291
  //----------PASS 2----------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1292
  // Reset all DEF live range numbers here
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1293
  for( insidx = 0; insidx < defs->size(); insidx++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1294
    // Grab the def
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1295
    n1 = defs->at(insidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1296
    // Set new lidx for DEF
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1297
    new_lrg(n1, maxlrg++);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1298
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1299
  //----------Phi Node Splitting----------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1300
  // Clean up a phi here, and assign a new live range number
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1301
  // Cycle through this block's predecessors, collecting Reaches
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1302
  // info for each spilled LRG and update edges.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1303
  // Walk the phis list to patch inputs, split phis, and name phis
7441
47ea904dba6a 7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents: 7397
diff changeset
  1304
  uint lrgs_before_phi_split = maxlrg;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1305
  for( insidx = 0; insidx < phis->size(); insidx++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1306
    Node *phi = phis->at(insidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1307
    assert(phi->is_Phi(),"This list must only contain Phi Nodes");
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 17877
diff changeset
  1308
    Block *b = _cfg.get_block_for_node(phi);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1309
    // Grab the live range number
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1310
    uint lidx = _lrg_map.find_id(phi);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1311
    uint slidx = lrg2reach[lidx];
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1312
    // Update node to lidx map
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1313
    new_lrg(phi, maxlrg++);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1314
    // Get PASS1's up/down decision for the block.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1315
    int phi_up = !!UP_entry[slidx]->test(b->_pre_order);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1316
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1317
    // Force down if double-spilling live range
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1318
    if( lrgs(lidx)._was_spilled1 )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1319
      phi_up = false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1320
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1321
    // When splitting a Phi we an split it normal or "inverted".
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1322
    // An inverted split makes the splits target the Phi's UP/DOWN
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1323
    // sense inverted; then the Phi is followed by a final def-side
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1324
    // split to invert back.  It changes which blocks the spill code
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1325
    // goes in.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1326
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1327
    // Walk the predecessor blocks and assign the reaching def to the Phi.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1328
    // Split Phi nodes by placing USE side splits wherever the reaching
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1329
    // DEF has the wrong UP/DOWN value.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1330
    for( uint i = 1; i < b->num_preds(); i++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1331
      // Get predecessor block pre-order number
19279
4be3c2e6663c 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 17877
diff changeset
  1332
      Block *pred = _cfg.get_block_for_node(b->pred(i));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1333
      pidx = pred->_pre_order;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1334
      // Grab reaching def
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1335
      Node *def = Reaches[pidx][slidx];
21100
c9bfb5a57f96 8026939: assert(Reachblock != NULL) failed: Reachblock must be non-NULL
adlertz
parents: 21086
diff changeset
  1336
      Node** Reachblock = Reaches[pidx];
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1337
      assert( def, "must have reaching def" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1338
      // If input up/down sense and reg-pressure DISagree
21086
5effcc6ee607 8022783: Nashorn test fails with: assert(!def_outside->member(r))
adlertz
parents: 20699
diff changeset
  1339
      if (def->rematerialize()) {
7441
47ea904dba6a 7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents: 7397
diff changeset
  1340
        // Place the rematerialized node above any MSCs created during
47ea904dba6a 7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents: 7397
diff changeset
  1341
        // phi node splitting.  end_idx points at the insertion point
47ea904dba6a 7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents: 7397
diff changeset
  1342
        // so look at the node before it.
47ea904dba6a 7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents: 7397
diff changeset
  1343
        int insert = pred->end_idx();
47ea904dba6a 7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents: 7397
diff changeset
  1344
        while (insert >= 1 &&
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
  1345
               pred->get_node(insert - 1)->is_SpillCopy() &&
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
  1346
               _lrg_map.find(pred->get_node(insert - 1)) >= lrgs_before_phi_split) {
7441
47ea904dba6a 7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents: 7397
diff changeset
  1347
          insert--;
47ea904dba6a 7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents: 7397
diff changeset
  1348
        }
21100
c9bfb5a57f96 8026939: assert(Reachblock != NULL) failed: Reachblock must be non-NULL
adlertz
parents: 21086
diff changeset
  1349
        def = split_Rematerialize(def, pred, insert, maxlrg, splits, slidx, lrg2reach, Reachblock, false);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1350
        if (!def) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1351
          return 0;    // Bail out
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1352
        }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1353
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1354
      // Update the Phi's input edge array
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1355
      phi->set_req(i,def);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1356
      // Grab the UP/DOWN sense for the input
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1357
      u1 = UP[pidx][slidx];
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1358
      if( u1 != (phi_up != 0)) {
22914
0712db174bbb 8032656: Tag the MachSpillCopies with purpose information
adlertz
parents: 22234
diff changeset
  1359
        maxlrg = split_USE(MachSpillCopyNode::PhiLocationDifferToInputLocation, def, b, phi, i, maxlrg, !u1, false, splits,slidx);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1360
        // If it wasn't split bail
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1361
        if (!maxlrg) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1362
          return 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1363
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1364
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1365
    }  // End for all inputs to the Phi
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1366
  }  // End for all Phi Nodes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1367
  // Update _maxlrg to save Union asserts
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1368
  _lrg_map.set_max_lrg_id(maxlrg);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1369
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1370
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1371
  //----------PASS 3----------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1372
  // Pass over all Phi's to union the live ranges
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1373
  for( insidx = 0; insidx < phis->size(); insidx++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1374
    Node *phi = phis->at(insidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1375
    assert(phi->is_Phi(),"This list must only contain Phi Nodes");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1376
    // Walk all inputs to Phi and Union input live range with Phi live range
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1377
    for( uint i = 1; i < phi->req(); i++ ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1378
      // Grab the input node
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1379
      Node *n = phi->in(i);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1380
      assert(n, "node should exist");
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1381
      uint lidx = _lrg_map.find(n);
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1382
      uint pidx = _lrg_map.find(phi);
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1383
      if (lidx < pidx) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1384
        Union(n, phi);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1385
      }
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1386
      else if(lidx > pidx) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1387
        Union(phi, n);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1388
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1389
    }  // End for all inputs to the Phi Node
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1390
  }  // End for all Phi Nodes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1391
  // Now union all two address instructions
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1392
  for (insidx = 0; insidx < defs->size(); insidx++) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1393
    // Grab the def
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1394
    n1 = defs->at(insidx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1395
    // Set new lidx for DEF & handle 2-addr instructions
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1396
    if (n1->is_Mach() && ((twoidx = n1->as_Mach()->two_adr()) != 0)) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1397
      assert(_lrg_map.find(n1->in(twoidx)) < maxlrg,"Assigning bad live range index");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1398
      // Union the input and output live ranges
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1399
      uint lr1 = _lrg_map.find(n1);
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1400
      uint lr2 = _lrg_map.find(n1->in(twoidx));
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1401
      if (lr1 < lr2) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1402
        Union(n1, n1->in(twoidx));
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1403
      }
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1404
      else if (lr1 > lr2) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1405
        Union(n1->in(twoidx), n1);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1406
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1407
    }  // End if two address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1408
  }  // End for all defs
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1409
  // DEBUG
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1410
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1411
  // Validate all live range index assignments
19330
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  1412
  for (bidx = 0; bidx < _cfg.number_of_blocks(); bidx++) {
49d6711171e6 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 19279
diff changeset
  1413
    b  = _cfg.get_block(bidx);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1414
    for (insidx = 0; insidx <= b->end_idx(); insidx++) {
19717
7819ffdaf0ff 8023691: Create interface for nodes in class Block
adlertz
parents: 19334
diff changeset
  1415
      Node *n = b->get_node(insidx);
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1416
      uint defidx = _lrg_map.find(n);
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1417
      assert(defidx < _lrg_map.max_lrg_id(), "Bad live range index in Split");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1418
      assert(defidx < maxlrg,"Bad live range index in Split");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1419
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1420
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1421
  // Issue a warning if splitting made no progress
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1422
  int noprogress = 0;
17013
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1423
  for (slidx = 0; slidx < spill_cnt; slidx++) {
22a05c7f3314 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 14623
diff changeset
  1424
    if (PrintOpto && WizardMode && splits.at(slidx) == 0) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1425
      tty->print_cr("Failed to split live range %d", lidxs.at(slidx));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1426
      //BREAKPOINT;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1427
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1428
    else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1429
      noprogress++;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1430
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1431
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1432
  if(!noprogress) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1433
    tty->print_cr("Failed to make progress in Split");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1434
    //BREAKPOINT;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1435
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1436
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1437
  // Return updated count of live ranges
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1438
  return maxlrg;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1439
}