hotspot/src/cpu/sparc/vm/stubGenerator_sparc.cpp
author vlivanov
Mon, 09 May 2016 13:13:07 +0300
changeset 38246 518c89421883
parent 38241 32eab2eb41fd
parent 38209 b2a58604e046
child 46381 020219e46c86
permissions -rw-r--r--
Merge
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/*
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 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#include "precompiled.hpp"
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#include "asm/macroAssembler.inline.hpp"
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#include "interpreter/interpreter.hpp"
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#include "nativeInst_sparc.hpp"
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#include "oops/instanceOop.hpp"
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#include "oops/method.hpp"
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#include "oops/objArrayKlass.hpp"
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#include "oops/oop.inline.hpp"
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#include "prims/methodHandles.hpp"
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#include "runtime/frame.inline.hpp"
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#include "runtime/handles.inline.hpp"
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#include "runtime/sharedRuntime.hpp"
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#include "runtime/stubCodeGenerator.hpp"
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#include "runtime/stubRoutines.hpp"
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#include "runtime/thread.inline.hpp"
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#ifdef COMPILER2
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#include "opto/runtime.hpp"
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#endif
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// Declaration and definition of StubGenerator (no .hpp file).
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// For a more detailed description of the stub routine structure
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// see the comment in stubRoutines.hpp.
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#define __ _masm->
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#ifdef PRODUCT
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#define BLOCK_COMMENT(str) /* nothing */
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#else
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#define BLOCK_COMMENT(str) __ block_comment(str)
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#endif
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#define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
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// Note:  The register L7 is used as L7_thread_cache, and may not be used
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//        any other way within this module.
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static const Register& Lstub_temp = L2;
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// -------------------------------------------------------------------------------------------------------------------------
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// Stub Code definitions
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class StubGenerator: public StubCodeGenerator {
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 private:
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#ifdef PRODUCT
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#define inc_counter_np(a,b,c)
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#else
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#define inc_counter_np(counter, t1, t2) \
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  BLOCK_COMMENT("inc_counter " #counter); \
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  __ inc_counter(&counter, t1, t2);
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#endif
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  //----------------------------------------------------------------------------------------------------
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  // Call stubs are used to call Java from C
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  address generate_call_stub(address& return_pc) {
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    StubCodeMark mark(this, "StubRoutines", "call_stub");
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    address start = __ pc();
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    // Incoming arguments:
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    //
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    // o0         : call wrapper address
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    // o1         : result (address)
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    // o2         : result type
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    // o3         : method
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    // o4         : (interpreter) entry point
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    // o5         : parameters (address)
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    // [sp + 0x5c]: parameter size (in words)
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    // [sp + 0x60]: thread
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    //
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    // +---------------+ <--- sp + 0
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    // |               |
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    // . reg save area .
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    // |               |
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    // +---------------+ <--- sp + 0x40
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    // |               |
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    // . extra 7 slots .
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    // |               |
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    // +---------------+ <--- sp + 0x5c
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    // |  param. size  |
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    // +---------------+ <--- sp + 0x60
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    // |    thread     |
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    // +---------------+
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    // |               |
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    // note: if the link argument position changes, adjust
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    //       the code in frame::entry_frame_call_wrapper()
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    const Argument link           = Argument(0, false); // used only for GC
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    const Argument result         = Argument(1, false);
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    const Argument result_type    = Argument(2, false);
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    const Argument method         = Argument(3, false);
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    const Argument entry_point    = Argument(4, false);
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    const Argument parameters     = Argument(5, false);
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    const Argument parameter_size = Argument(6, false);
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    const Argument thread         = Argument(7, false);
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    // setup thread register
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    __ ld_ptr(thread.as_address(), G2_thread);
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    __ reinit_heapbase();
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#ifdef ASSERT
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    // make sure we have no pending exceptions
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    { const Register t = G3_scratch;
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      Label L;
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      __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), t);
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      __ br_null_short(t, Assembler::pt, L);
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      __ stop("StubRoutines::call_stub: entered with pending exception");
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      __ bind(L);
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    }
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#endif
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    // create activation frame & allocate space for parameters
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    { const Register t = G3_scratch;
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      __ ld_ptr(parameter_size.as_address(), t);                // get parameter size (in words)
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      __ add(t, frame::memory_parameter_word_sp_offset, t);     // add space for save area (in words)
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      __ round_to(t, WordsPerLong);                             // make sure it is multiple of 2 (in words)
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      __ sll(t, Interpreter::logStackElementSize, t);           // compute number of bytes
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      __ neg(t);                                                // negate so it can be used with save
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      __ save(SP, t, SP);                                       // setup new frame
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    }
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    // +---------------+ <--- sp + 0
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    // |               |
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    // . reg save area .
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    // |               |
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    // +---------------+ <--- sp + 0x40
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    // |               |
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    // . extra 7 slots .
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    // |               |
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    // +---------------+ <--- sp + 0x5c
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    // |  empty slot   |      (only if parameter size is even)
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    // +---------------+
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    // |               |
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    // .  parameters   .
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    // |               |
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    // +---------------+ <--- fp + 0
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    // |               |
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    // . reg save area .
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    // |               |
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    // +---------------+ <--- fp + 0x40
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    // |               |
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    // . extra 7 slots .
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    // |               |
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    // +---------------+ <--- fp + 0x5c
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    // |  param. size  |
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    // +---------------+ <--- fp + 0x60
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    // |    thread     |
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    // +---------------+
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    // |               |
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    // pass parameters if any
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    BLOCK_COMMENT("pass parameters if any");
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    { const Register src = parameters.as_in().as_register();
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      const Register dst = Lentry_args;
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      const Register tmp = G3_scratch;
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      const Register cnt = G4_scratch;
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      // test if any parameters & setup of Lentry_args
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      Label exit;
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      __ ld_ptr(parameter_size.as_in().as_address(), cnt);      // parameter counter
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      __ add( FP, STACK_BIAS, dst );
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      __ cmp_zero_and_br(Assembler::zero, cnt, exit);
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      __ delayed()->sub(dst, BytesPerWord, dst);                 // setup Lentry_args
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      // copy parameters if any
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      Label loop;
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      __ BIND(loop);
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      // Store parameter value
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      __ ld_ptr(src, 0, tmp);
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      __ add(src, BytesPerWord, src);
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      __ st_ptr(tmp, dst, 0);
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      __ deccc(cnt);
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      __ br(Assembler::greater, false, Assembler::pt, loop);
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      __ delayed()->sub(dst, Interpreter::stackElementSize, dst);
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   201
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      // done
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      __ BIND(exit);
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    }
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    // setup parameters, method & call Java function
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#ifdef ASSERT
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    // layout_activation_impl checks it's notion of saved SP against
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    // this register, so if this changes update it as well.
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    const Register saved_SP = Lscratch;
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    __ mov(SP, saved_SP);                               // keep track of SP before call
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#endif
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    // setup parameters
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    const Register t = G3_scratch;
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    __ ld_ptr(parameter_size.as_in().as_address(), t); // get parameter size (in words)
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    __ sll(t, Interpreter::logStackElementSize, t);    // compute number of bytes
1
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    __ sub(FP, t, Gargs);                              // setup parameter pointer
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#ifdef _LP64
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    __ add( Gargs, STACK_BIAS, Gargs );                // Account for LP64 stack bias
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#endif
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    __ mov(SP, O5_savedSP);
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    // do the call
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    //
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    // the following register must be setup:
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    //
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    // G2_thread
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    // G5_method
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    // Gargs
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    BLOCK_COMMENT("call Java function");
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    __ jmpl(entry_point.as_in().as_register(), G0, O7);
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    __ delayed()->mov(method.as_in().as_register(), G5_method);   // setup method
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   235
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    BLOCK_COMMENT("call_stub_return_address:");
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    return_pc = __ pc();
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   238
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    // The callee, if it wasn't interpreted, can return with SP changed so
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    // we can no longer assert of change of SP.
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   241
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    // store result depending on type
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    // (everything that is not T_OBJECT, T_LONG, T_FLOAT, or T_DOUBLE
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    //  is treated as T_INT)
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    { const Register addr = result     .as_in().as_register();
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      const Register type = result_type.as_in().as_register();
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      Label is_long, is_float, is_double, is_object, exit;
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      __            cmp(type, T_OBJECT);  __ br(Assembler::equal, false, Assembler::pn, is_object);
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      __ delayed()->cmp(type, T_FLOAT);   __ br(Assembler::equal, false, Assembler::pn, is_float);
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      __ delayed()->cmp(type, T_DOUBLE);  __ br(Assembler::equal, false, Assembler::pn, is_double);
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      __ delayed()->cmp(type, T_LONG);    __ br(Assembler::equal, false, Assembler::pn, is_long);
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      __ delayed()->nop();
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   253
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      // store int result
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      __ st(O0, addr, G0);
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   256
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      __ BIND(exit);
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      __ ret();
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      __ delayed()->restore();
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   260
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      __ BIND(is_object);
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      __ ba(exit);
1
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      __ delayed()->st_ptr(O0, addr, G0);
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   264
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      __ BIND(is_float);
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      __ ba(exit);
1
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      __ delayed()->stf(FloatRegisterImpl::S, F0, addr, G0);
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   268
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      __ BIND(is_double);
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      __ ba(exit);
1
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      __ delayed()->stf(FloatRegisterImpl::D, F0, addr, G0);
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   272
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      __ BIND(is_long);
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#ifdef _LP64
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      __ ba(exit);
1
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      __ delayed()->st_long(O0, addr, G0);      // store entire long
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#else
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#if defined(COMPILER2)
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  // All return values are where we want them, except for Longs.  C2 returns
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  // longs in G1 in the 32-bit build whereas the interpreter wants them in O0/O1.
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  // Since the interpreter will return longs in G1 and O0/O1 in the 32bit
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  // build we simply always use G1.
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  // Note: I tried to make c2 return longs in O0/O1 and G1 so we wouldn't have to
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  // do this here. Unfortunately if we did a rethrow we'd see an machepilog node
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  // first which would move g1 -> O0/O1 and destroy the exception we were throwing.
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      __ ba(exit);
1
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      __ delayed()->stx(G1, addr, G0);  // store entire long
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#else
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      __ st(O1, addr, BytesPerInt);
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      __ ba(exit);
1
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      __ delayed()->st(O0, addr, G0);
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#endif /* COMPILER2 */
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#endif /* _LP64 */
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     }
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     return start;
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  }
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   298
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  //----------------------------------------------------------------------------------------------------
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  // Return point for a Java call if there's an exception thrown in Java code.
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  // The exception is caught and transformed into a pending exception stored in
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  // JavaThread that can be tested from within the VM.
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  //
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  // Oexception: exception oop
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   306
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  address generate_catch_exception() {
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   308
    StubCodeMark mark(this, "StubRoutines", "catch_exception");
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   309
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    address start = __ pc();
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    // verify that thread corresponds
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    __ verify_thread();
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   313
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    const Register& temp_reg = Gtemp;
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    Address pending_exception_addr    (G2_thread, Thread::pending_exception_offset());
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    Address exception_file_offset_addr(G2_thread, Thread::exception_file_offset   ());
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    Address exception_line_offset_addr(G2_thread, Thread::exception_line_offset   ());
1
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    // set pending exception
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    __ verify_oop(Oexception);
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   321
    __ st_ptr(Oexception, pending_exception_addr);
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   322
    __ set((intptr_t)__FILE__, temp_reg);
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   323
    __ st_ptr(temp_reg, exception_file_offset_addr);
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   324
    __ set((intptr_t)__LINE__, temp_reg);
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   325
    __ st(temp_reg, exception_line_offset_addr);
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   326
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    // complete return to VM
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    assert(StubRoutines::_call_stub_return_address != NULL, "must have been generated before");
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    AddressLiteral stub_ret(StubRoutines::_call_stub_return_address);
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    __ jump_to(stub_ret, temp_reg);
1
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   332
    __ delayed()->nop();
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   333
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   334
    return start;
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   335
  }
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   336
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   337
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  //----------------------------------------------------------------------------------------------------
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  // Continuation point for runtime calls returning with a pending exception
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   340
  // The pending exception check happened in the runtime or native call stub
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   341
  // The pending exception in Thread is converted into a Java-level exception
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   342
  //
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   343
  // Contract with Java-level exception handler: O0 = exception
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  //                                             O1 = throwing pc
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   345
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   346
  address generate_forward_exception() {
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   347
    StubCodeMark mark(this, "StubRoutines", "forward_exception");
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    address start = __ pc();
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   349
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    // Upon entry, O7 has the return address returning into Java
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    // (interpreted or compiled) code; i.e. the return address
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    // becomes the throwing pc.
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   353
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   354
    const Register& handler_reg = Gtemp;
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   355
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   356
    Address exception_addr(G2_thread, Thread::pending_exception_offset());
1
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   357
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   358
#ifdef ASSERT
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   359
    // make sure that this code is only executed if there is a pending exception
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    { Label L;
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   361
      __ ld_ptr(exception_addr, Gtemp);
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   362
      __ br_notnull_short(Gtemp, Assembler::pt, L);
1
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   363
      __ stop("StubRoutines::forward exception: no pending exception (1)");
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   364
      __ bind(L);
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   365
    }
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   366
#endif
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   367
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   368
    // compute exception handler into handler_reg
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   369
    __ get_thread();
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   370
    __ ld_ptr(exception_addr, Oexception);
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   371
    __ verify_oop(Oexception);
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   372
    __ save_frame(0);             // compensates for compiler weakness
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   373
    __ add(O7->after_save(), frame::pc_return_offset, Lscratch); // save the issuing PC
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    BLOCK_COMMENT("call exception_handler_for_return_address");
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    __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), G2_thread, Lscratch);
1
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   376
    __ mov(O0, handler_reg);
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   377
    __ restore();                 // compensates for compiler weakness
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   378
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   379
    __ ld_ptr(exception_addr, Oexception);
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   380
    __ add(O7, frame::pc_return_offset, Oissuing_pc); // save the issuing PC
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   381
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   382
#ifdef ASSERT
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   383
    // make sure exception is set
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   384
    { Label L;
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10004
diff changeset
   385
      __ br_notnull_short(Oexception, Assembler::pt, L);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   386
      __ stop("StubRoutines::forward exception: no pending exception (2)");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   387
      __ bind(L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   388
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   389
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   390
    // jump to exception handler
489c9b5090e2 Initial load
duke
parents:
diff changeset
   391
    __ jmp(handler_reg, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   392
    // clear pending exception
489c9b5090e2 Initial load
duke
parents:
diff changeset
   393
    __ delayed()->st_ptr(G0, exception_addr);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   394
489c9b5090e2 Initial load
duke
parents:
diff changeset
   395
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   396
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   397
18740
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   398
  // Safefetch stubs.
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   399
  void generate_safefetch(const char* name, int size, address* entry,
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   400
                          address* fault_pc, address* continuation_pc) {
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   401
    // safefetch signatures:
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   402
    //   int      SafeFetch32(int*      adr, int      errValue);
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   403
    //   intptr_t SafeFetchN (intptr_t* adr, intptr_t errValue);
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   404
    //
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   405
    // arguments:
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   406
    //   o0 = adr
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   407
    //   o1 = errValue
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   408
    //
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   409
    // result:
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   410
    //   o0  = *adr or errValue
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   411
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   412
    StubCodeMark mark(this, "StubRoutines", name);
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   413
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   414
    // Entry point, pc or function descriptor.
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   415
    __ align(CodeEntryAlignment);
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   416
    *entry = __ pc();
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   417
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   418
    __ mov(O0, G1);  // g1 = o0
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   419
    __ mov(O1, O0);  // o0 = o1
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   420
    // Load *adr into c_rarg1, may fault.
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   421
    *fault_pc = __ pc();
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   422
    switch (size) {
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   423
      case 4:
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   424
        // int32_t
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   425
        __ ldsw(G1, 0, O0);  // o0 = [g1]
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   426
        break;
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   427
      case 8:
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   428
        // int64_t
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   429
        __ ldx(G1, 0, O0);   // o0 = [g1]
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   430
        break;
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   431
      default:
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   432
        ShouldNotReachHere();
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   433
    }
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   434
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   435
    // return errValue or *adr
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   436
    *continuation_pc = __ pc();
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   437
    // By convention with the trap handler we ensure there is a non-CTI
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   438
    // instruction in the trap shadow.
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   439
    __ nop();
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   440
    __ retl();
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   441
    __ delayed()->nop();
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
   442
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   443
489c9b5090e2 Initial load
duke
parents:
diff changeset
   444
  //------------------------------------------------------------------------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   445
  // Continuation point for throwing of implicit exceptions that are not handled in
489c9b5090e2 Initial load
duke
parents:
diff changeset
   446
  // the current activation. Fabricates an exception oop and initiates normal
489c9b5090e2 Initial load
duke
parents:
diff changeset
   447
  // exception dispatching in this frame. Only callee-saved registers are preserved
489c9b5090e2 Initial load
duke
parents:
diff changeset
   448
  // (through the normal register window / RegisterMap handling).
489c9b5090e2 Initial load
duke
parents:
diff changeset
   449
  // If the compiler needs all registers to be preserved between the fault
489c9b5090e2 Initial load
duke
parents:
diff changeset
   450
  // point and the exception handler then it must assume responsibility for that in
489c9b5090e2 Initial load
duke
parents:
diff changeset
   451
  // AbstractCompiler::continuation_for_implicit_null_exception or
489c9b5090e2 Initial load
duke
parents:
diff changeset
   452
  // continuation_for_implicit_division_by_zero_exception. All other implicit
489c9b5090e2 Initial load
duke
parents:
diff changeset
   453
  // exceptions (e.g., NullPointerException or AbstractMethodError on entry) are
489c9b5090e2 Initial load
duke
parents:
diff changeset
   454
  // either at call sites or otherwise assume that stack unwinding will be initiated,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   455
  // so caller saved registers were assumed volatile in the compiler.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   456
489c9b5090e2 Initial load
duke
parents:
diff changeset
   457
  // Note that we generate only this stub into a RuntimeStub, because it needs to be
489c9b5090e2 Initial load
duke
parents:
diff changeset
   458
  // properly traversed and ignored during GC, so we change the meaning of the "__"
489c9b5090e2 Initial load
duke
parents:
diff changeset
   459
  // macro within this method.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   460
#undef __
489c9b5090e2 Initial load
duke
parents:
diff changeset
   461
#define __ masm->
489c9b5090e2 Initial load
duke
parents:
diff changeset
   462
10545
fec876499aae 7088020: SEGV in JNIHandleBlock::release_block
never
parents: 10512
diff changeset
   463
  address generate_throw_exception(const char* name, address runtime_entry,
10004
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8498
diff changeset
   464
                                   Register arg1 = noreg, Register arg2 = noreg) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   465
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   466
    int insts_size = VerifyThread ? 1 * K : 600;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   467
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   468
    int insts_size = VerifyThread ? 1 * K : 256;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   469
#endif /* ASSERT */
489c9b5090e2 Initial load
duke
parents:
diff changeset
   470
    int locs_size  = 32;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   471
489c9b5090e2 Initial load
duke
parents:
diff changeset
   472
    CodeBuffer      code(name, insts_size, locs_size);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   473
    MacroAssembler* masm = new MacroAssembler(&code);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   474
489c9b5090e2 Initial load
duke
parents:
diff changeset
   475
    __ verify_thread();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   476
489c9b5090e2 Initial load
duke
parents:
diff changeset
   477
    // This is an inlined and slightly modified version of call_VM
489c9b5090e2 Initial load
duke
parents:
diff changeset
   478
    // which has the ability to fetch the return PC out of thread-local storage
489c9b5090e2 Initial load
duke
parents:
diff changeset
   479
    __ assert_not_delayed();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   480
489c9b5090e2 Initial load
duke
parents:
diff changeset
   481
    // Note that we always push a frame because on the SPARC
489c9b5090e2 Initial load
duke
parents:
diff changeset
   482
    // architecture, for all of our implicit exception kinds at call
489c9b5090e2 Initial load
duke
parents:
diff changeset
   483
    // sites, the implicit exception is taken before the callee frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
   484
    // is pushed.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   485
    __ save_frame(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   486
489c9b5090e2 Initial load
duke
parents:
diff changeset
   487
    int frame_complete = __ offset();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   488
489c9b5090e2 Initial load
duke
parents:
diff changeset
   489
    // Note that we always have a runtime stub frame on the top of stack by this point
489c9b5090e2 Initial load
duke
parents:
diff changeset
   490
    Register last_java_sp = SP;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   491
    // 64-bit last_java_sp is biased!
489c9b5090e2 Initial load
duke
parents:
diff changeset
   492
    __ set_last_Java_frame(last_java_sp, G0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   493
    if (VerifyThread)  __ mov(G2_thread, O0); // about to be smashed; pass early
489c9b5090e2 Initial load
duke
parents:
diff changeset
   494
    __ save_thread(noreg);
10004
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8498
diff changeset
   495
    if (arg1 != noreg) {
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8498
diff changeset
   496
      assert(arg2 != O1, "clobbered");
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8498
diff changeset
   497
      __ mov(arg1, O1);
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8498
diff changeset
   498
    }
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8498
diff changeset
   499
    if (arg2 != noreg) {
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8498
diff changeset
   500
      __ mov(arg2, O2);
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8498
diff changeset
   501
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   502
    // do the call
489c9b5090e2 Initial load
duke
parents:
diff changeset
   503
    BLOCK_COMMENT("call runtime_entry");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   504
    __ call(runtime_entry, relocInfo::runtime_call_type);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   505
    if (!VerifyThread)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   506
      __ delayed()->mov(G2_thread, O0);  // pass thread as first argument
489c9b5090e2 Initial load
duke
parents:
diff changeset
   507
    else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   508
      __ delayed()->nop();             // (thread already passed)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   509
    __ restore_thread(noreg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   510
    __ reset_last_Java_frame();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   511
489c9b5090e2 Initial load
duke
parents:
diff changeset
   512
    // check for pending exceptions. use Gtemp as scratch register.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   513
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   514
    Label L;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   515
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2338
diff changeset
   516
    Address exception_addr(G2_thread, Thread::pending_exception_offset());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   517
    Register scratch_reg = Gtemp;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   518
    __ ld_ptr(exception_addr, scratch_reg);
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10004
diff changeset
   519
    __ br_notnull_short(scratch_reg, Assembler::pt, L);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   520
    __ should_not_reach_here();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   521
    __ bind(L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   522
#endif // ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   523
    BLOCK_COMMENT("call forward_exception_entry");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   524
    __ call(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   525
    // we use O7 linkage so that forward_exception_entry has the issuing PC
489c9b5090e2 Initial load
duke
parents:
diff changeset
   526
    __ delayed()->restore();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   527
489c9b5090e2 Initial load
duke
parents:
diff changeset
   528
    RuntimeStub* stub = RuntimeStub::new_runtime_stub(name, &code, frame_complete, masm->total_frame_size_in_bytes(0), NULL, false);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   529
    return stub->entry_point();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   530
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   531
489c9b5090e2 Initial load
duke
parents:
diff changeset
   532
#undef __
489c9b5090e2 Initial load
duke
parents:
diff changeset
   533
#define __ _masm->
489c9b5090e2 Initial load
duke
parents:
diff changeset
   534
489c9b5090e2 Initial load
duke
parents:
diff changeset
   535
489c9b5090e2 Initial load
duke
parents:
diff changeset
   536
  // Generate a routine that sets all the registers so we
489c9b5090e2 Initial load
duke
parents:
diff changeset
   537
  // can tell if the stop routine prints them correctly.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   538
  address generate_test_stop() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   539
    StubCodeMark mark(this, "StubRoutines", "test_stop");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   540
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   541
489c9b5090e2 Initial load
duke
parents:
diff changeset
   542
    int i;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   543
489c9b5090e2 Initial load
duke
parents:
diff changeset
   544
    __ save_frame(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   545
489c9b5090e2 Initial load
duke
parents:
diff changeset
   546
    static jfloat zero = 0.0, one = 1.0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   547
489c9b5090e2 Initial load
duke
parents:
diff changeset
   548
    // put addr in L0, then load through L0 to F0
489c9b5090e2 Initial load
duke
parents:
diff changeset
   549
    __ set((intptr_t)&zero, L0);  __ ldf( FloatRegisterImpl::S, L0, 0, F0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   550
    __ set((intptr_t)&one,  L0);  __ ldf( FloatRegisterImpl::S, L0, 0, F1); // 1.0 to F1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   551
489c9b5090e2 Initial load
duke
parents:
diff changeset
   552
    // use add to put 2..18 in F2..F18
489c9b5090e2 Initial load
duke
parents:
diff changeset
   553
    for ( i = 2;  i <= 18;  ++i ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   554
      __ fadd( FloatRegisterImpl::S, F1, as_FloatRegister(i-1),  as_FloatRegister(i));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   555
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   556
489c9b5090e2 Initial load
duke
parents:
diff changeset
   557
    // Now put double 2 in F16, double 18 in F18
489c9b5090e2 Initial load
duke
parents:
diff changeset
   558
    __ ftof( FloatRegisterImpl::S, FloatRegisterImpl::D, F2, F16 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   559
    __ ftof( FloatRegisterImpl::S, FloatRegisterImpl::D, F18, F18 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   560
489c9b5090e2 Initial load
duke
parents:
diff changeset
   561
    // use add to put 20..32 in F20..F32
489c9b5090e2 Initial load
duke
parents:
diff changeset
   562
    for (i = 20; i < 32; i += 2) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   563
      __ fadd( FloatRegisterImpl::D, F16, as_FloatRegister(i-2),  as_FloatRegister(i));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   564
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   565
489c9b5090e2 Initial load
duke
parents:
diff changeset
   566
    // put 0..7 in i's, 8..15 in l's, 16..23 in o's, 24..31 in g's
489c9b5090e2 Initial load
duke
parents:
diff changeset
   567
    for ( i = 0; i < 8; ++i ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   568
      if (i < 6) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   569
        __ set(     i, as_iRegister(i));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   570
        __ set(16 + i, as_oRegister(i));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   571
        __ set(24 + i, as_gRegister(i));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   572
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   573
      __ set( 8 + i, as_lRegister(i));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   574
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   575
489c9b5090e2 Initial load
duke
parents:
diff changeset
   576
    __ stop("testing stop");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   577
489c9b5090e2 Initial load
duke
parents:
diff changeset
   578
489c9b5090e2 Initial load
duke
parents:
diff changeset
   579
    __ ret();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   580
    __ delayed()->restore();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   581
489c9b5090e2 Initial load
duke
parents:
diff changeset
   582
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   583
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   584
489c9b5090e2 Initial load
duke
parents:
diff changeset
   585
489c9b5090e2 Initial load
duke
parents:
diff changeset
   586
  address generate_stop_subroutine() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   587
    StubCodeMark mark(this, "StubRoutines", "stop_subroutine");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   588
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   589
489c9b5090e2 Initial load
duke
parents:
diff changeset
   590
    __ stop_subroutine();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   591
489c9b5090e2 Initial load
duke
parents:
diff changeset
   592
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   593
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   594
489c9b5090e2 Initial load
duke
parents:
diff changeset
   595
  address generate_flush_callers_register_windows() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   596
    StubCodeMark mark(this, "StubRoutines", "flush_callers_register_windows");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   597
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   598
18097
acd70736bd60 8008407: remove SPARC V8 support
morris
parents: 14633
diff changeset
   599
    __ flushw();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   600
    __ retl(false);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   601
    __ delayed()->add( FP, STACK_BIAS, O0 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   602
    // The returned value must be a stack pointer whose register save area
489c9b5090e2 Initial load
duke
parents:
diff changeset
   603
    // is flushed, and will stay flushed while the caller executes.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   604
489c9b5090e2 Initial load
duke
parents:
diff changeset
   605
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   606
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   607
489c9b5090e2 Initial load
duke
parents:
diff changeset
   608
  // Support for jint Atomic::xchg(jint exchange_value, volatile jint* dest).
489c9b5090e2 Initial load
duke
parents:
diff changeset
   609
  //
18097
acd70736bd60 8008407: remove SPARC V8 support
morris
parents: 14633
diff changeset
   610
  // Arguments:
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   611
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   612
  //      exchange_value: O0
489c9b5090e2 Initial load
duke
parents:
diff changeset
   613
  //      dest:           O1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   614
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   615
  // Results:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   616
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   617
  //     O0: the value previously stored in dest
489c9b5090e2 Initial load
duke
parents:
diff changeset
   618
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   619
  address generate_atomic_xchg() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   620
    StubCodeMark mark(this, "StubRoutines", "atomic_xchg");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   621
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   622
489c9b5090e2 Initial load
duke
parents:
diff changeset
   623
    if (UseCASForSwap) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   624
      // Use CAS instead of swap, just in case the MP hardware
489c9b5090e2 Initial load
duke
parents:
diff changeset
   625
      // prefers to work with just one kind of synch. instruction.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   626
      Label retry;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   627
      __ BIND(retry);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   628
      __ mov(O0, O3);       // scratch copy of exchange value
489c9b5090e2 Initial load
duke
parents:
diff changeset
   629
      __ ld(O1, 0, O2);     // observe the previous value
489c9b5090e2 Initial load
duke
parents:
diff changeset
   630
      // try to replace O2 with O3
18097
acd70736bd60 8008407: remove SPARC V8 support
morris
parents: 14633
diff changeset
   631
      __ cas(O1, O2, O3);
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10004
diff changeset
   632
      __ cmp_and_br_short(O2, O3, Assembler::notEqual, Assembler::pn, retry);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   633
489c9b5090e2 Initial load
duke
parents:
diff changeset
   634
      __ retl(false);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   635
      __ delayed()->mov(O2, O0);  // report previous value to caller
489c9b5090e2 Initial load
duke
parents:
diff changeset
   636
    } else {
18097
acd70736bd60 8008407: remove SPARC V8 support
morris
parents: 14633
diff changeset
   637
      __ retl(false);
acd70736bd60 8008407: remove SPARC V8 support
morris
parents: 14633
diff changeset
   638
      __ delayed()->swap(O1, 0, O0);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   639
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   640
489c9b5090e2 Initial load
duke
parents:
diff changeset
   641
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   642
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   643
489c9b5090e2 Initial load
duke
parents:
diff changeset
   644
489c9b5090e2 Initial load
duke
parents:
diff changeset
   645
  // Support for jint Atomic::cmpxchg(jint exchange_value, volatile jint* dest, jint compare_value)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   646
  //
18097
acd70736bd60 8008407: remove SPARC V8 support
morris
parents: 14633
diff changeset
   647
  // Arguments:
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   648
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   649
  //      exchange_value: O0
489c9b5090e2 Initial load
duke
parents:
diff changeset
   650
  //      dest:           O1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   651
  //      compare_value:  O2
489c9b5090e2 Initial load
duke
parents:
diff changeset
   652
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   653
  // Results:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   654
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   655
  //     O0: the value previously stored in dest
489c9b5090e2 Initial load
duke
parents:
diff changeset
   656
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   657
  address generate_atomic_cmpxchg() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   658
    StubCodeMark mark(this, "StubRoutines", "atomic_cmpxchg");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   659
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   660
489c9b5090e2 Initial load
duke
parents:
diff changeset
   661
    // cmpxchg(dest, compare_value, exchange_value)
18097
acd70736bd60 8008407: remove SPARC V8 support
morris
parents: 14633
diff changeset
   662
    __ cas(O1, O2, O0);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   663
    __ retl(false);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   664
    __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   665
489c9b5090e2 Initial load
duke
parents:
diff changeset
   666
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   667
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   668
489c9b5090e2 Initial load
duke
parents:
diff changeset
   669
  // Support for jlong Atomic::cmpxchg(jlong exchange_value, volatile jlong *dest, jlong compare_value)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   670
  //
18097
acd70736bd60 8008407: remove SPARC V8 support
morris
parents: 14633
diff changeset
   671
  // Arguments:
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   672
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   673
  //      exchange_value: O1:O0
489c9b5090e2 Initial load
duke
parents:
diff changeset
   674
  //      dest:           O2
489c9b5090e2 Initial load
duke
parents:
diff changeset
   675
  //      compare_value:  O4:O3
489c9b5090e2 Initial load
duke
parents:
diff changeset
   676
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   677
  // Results:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   678
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   679
  //     O1:O0: the value previously stored in dest
489c9b5090e2 Initial load
duke
parents:
diff changeset
   680
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   681
  // Overwrites: G1,G2,G3
489c9b5090e2 Initial load
duke
parents:
diff changeset
   682
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   683
  address generate_atomic_cmpxchg_long() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   684
    StubCodeMark mark(this, "StubRoutines", "atomic_cmpxchg_long");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   685
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   686
489c9b5090e2 Initial load
duke
parents:
diff changeset
   687
    __ sllx(O0, 32, O0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   688
    __ srl(O1, 0, O1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   689
    __ or3(O0,O1,O0);      // O0 holds 64-bit value from compare_value
489c9b5090e2 Initial load
duke
parents:
diff changeset
   690
    __ sllx(O3, 32, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   691
    __ srl(O4, 0, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   692
    __ or3(O3,O4,O3);     // O3 holds 64-bit value from exchange_value
489c9b5090e2 Initial load
duke
parents:
diff changeset
   693
    __ casx(O2, O3, O0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   694
    __ srl(O0, 0, O1);    // unpacked return value in O1:O0
489c9b5090e2 Initial load
duke
parents:
diff changeset
   695
    __ retl(false);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   696
    __ delayed()->srlx(O0, 32, O0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   697
489c9b5090e2 Initial load
duke
parents:
diff changeset
   698
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   699
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   700
489c9b5090e2 Initial load
duke
parents:
diff changeset
   701
489c9b5090e2 Initial load
duke
parents:
diff changeset
   702
  // Support for jint Atomic::add(jint add_value, volatile jint* dest).
489c9b5090e2 Initial load
duke
parents:
diff changeset
   703
  //
18097
acd70736bd60 8008407: remove SPARC V8 support
morris
parents: 14633
diff changeset
   704
  // Arguments:
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   705
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   706
  //      add_value: O0   (e.g., +1 or -1)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   707
  //      dest:      O1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   708
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   709
  // Results:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   710
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   711
  //     O0: the new value stored in dest
489c9b5090e2 Initial load
duke
parents:
diff changeset
   712
  //
18097
acd70736bd60 8008407: remove SPARC V8 support
morris
parents: 14633
diff changeset
   713
  // Overwrites: O3
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   714
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   715
  address generate_atomic_add() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   716
    StubCodeMark mark(this, "StubRoutines", "atomic_add");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   717
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   718
    __ BIND(_atomic_add_stub);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   719
18097
acd70736bd60 8008407: remove SPARC V8 support
morris
parents: 14633
diff changeset
   720
    Label(retry);
acd70736bd60 8008407: remove SPARC V8 support
morris
parents: 14633
diff changeset
   721
    __ BIND(retry);
acd70736bd60 8008407: remove SPARC V8 support
morris
parents: 14633
diff changeset
   722
acd70736bd60 8008407: remove SPARC V8 support
morris
parents: 14633
diff changeset
   723
    __ lduw(O1, 0, O2);
acd70736bd60 8008407: remove SPARC V8 support
morris
parents: 14633
diff changeset
   724
    __ add(O0, O2, O3);
acd70736bd60 8008407: remove SPARC V8 support
morris
parents: 14633
diff changeset
   725
    __ cas(O1, O2, O3);
acd70736bd60 8008407: remove SPARC V8 support
morris
parents: 14633
diff changeset
   726
    __ cmp_and_br_short(O2, O3, Assembler::notEqual, Assembler::pn, retry);
acd70736bd60 8008407: remove SPARC V8 support
morris
parents: 14633
diff changeset
   727
    __ retl(false);
acd70736bd60 8008407: remove SPARC V8 support
morris
parents: 14633
diff changeset
   728
    __ delayed()->add(O0, O2, O0); // note that cas made O2==O3
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   729
489c9b5090e2 Initial load
duke
parents:
diff changeset
   730
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   731
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   732
  Label _atomic_add_stub;  // called from other stubs
489c9b5090e2 Initial load
duke
parents:
diff changeset
   733
489c9b5090e2 Initial load
duke
parents:
diff changeset
   734
489c9b5090e2 Initial load
duke
parents:
diff changeset
   735
  // Support for uint StubRoutine::Sparc::partial_subtype_check( Klass sub, Klass super );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   736
  // Arguments :
489c9b5090e2 Initial load
duke
parents:
diff changeset
   737
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   738
  //      ret  : O0, returned
489c9b5090e2 Initial load
duke
parents:
diff changeset
   739
  //      icc/xcc: set as O0 (depending on wordSize)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   740
  //      sub  : O1, argument, not changed
489c9b5090e2 Initial load
duke
parents:
diff changeset
   741
  //      super: O2, argument, not changed
489c9b5090e2 Initial load
duke
parents:
diff changeset
   742
  //      raddr: O7, blown by call
489c9b5090e2 Initial load
duke
parents:
diff changeset
   743
  address generate_partial_subtype_check() {
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
   744
    __ align(CodeEntryAlignment);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   745
    StubCodeMark mark(this, "StubRoutines", "partial_subtype_check");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   746
    address start = __ pc();
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
   747
    Label miss;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   748
489c9b5090e2 Initial load
duke
parents:
diff changeset
   749
#if defined(COMPILER2) && !defined(_LP64)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   750
    // Do not use a 'save' because it blows the 64-bit O registers.
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
   751
    __ add(SP,-4*wordSize,SP);  // Make space for 4 temps (stack must be 2 words aligned)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   752
    __ st_ptr(L0,SP,(frame::register_save_words+0)*wordSize);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   753
    __ st_ptr(L1,SP,(frame::register_save_words+1)*wordSize);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   754
    __ st_ptr(L2,SP,(frame::register_save_words+2)*wordSize);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   755
    __ st_ptr(L3,SP,(frame::register_save_words+3)*wordSize);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   756
    Register Rret   = O0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   757
    Register Rsub   = O1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   758
    Register Rsuper = O2;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   759
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   760
    __ save_frame(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   761
    Register Rret   = I0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   762
    Register Rsub   = I1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   763
    Register Rsuper = I2;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   764
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   765
489c9b5090e2 Initial load
duke
parents:
diff changeset
   766
    Register L0_ary_len = L0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   767
    Register L1_ary_ptr = L1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   768
    Register L2_super   = L2;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   769
    Register L3_index   = L3;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   770
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
   771
    __ check_klass_subtype_slow_path(Rsub, Rsuper,
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
   772
                                     L0, L1, L2, L3,
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
   773
                                     NULL, &miss);
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
   774
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
   775
    // Match falls through here.
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
   776
    __ addcc(G0,0,Rret);        // set Z flags, Z result
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   777
489c9b5090e2 Initial load
duke
parents:
diff changeset
   778
#if defined(COMPILER2) && !defined(_LP64)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   779
    __ ld_ptr(SP,(frame::register_save_words+0)*wordSize,L0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   780
    __ ld_ptr(SP,(frame::register_save_words+1)*wordSize,L1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   781
    __ ld_ptr(SP,(frame::register_save_words+2)*wordSize,L2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   782
    __ ld_ptr(SP,(frame::register_save_words+3)*wordSize,L3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   783
    __ retl();                  // Result in Rret is zero; flags set to Z
489c9b5090e2 Initial load
duke
parents:
diff changeset
   784
    __ delayed()->add(SP,4*wordSize,SP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   785
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   786
    __ ret();                   // Result in Rret is zero; flags set to Z
489c9b5090e2 Initial load
duke
parents:
diff changeset
   787
    __ delayed()->restore();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   788
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   789
489c9b5090e2 Initial load
duke
parents:
diff changeset
   790
    __ BIND(miss);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   791
    __ addcc(G0,1,Rret);        // set NZ flags, NZ result
489c9b5090e2 Initial load
duke
parents:
diff changeset
   792
489c9b5090e2 Initial load
duke
parents:
diff changeset
   793
#if defined(COMPILER2) && !defined(_LP64)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   794
    __ ld_ptr(SP,(frame::register_save_words+0)*wordSize,L0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   795
    __ ld_ptr(SP,(frame::register_save_words+1)*wordSize,L1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   796
    __ ld_ptr(SP,(frame::register_save_words+2)*wordSize,L2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   797
    __ ld_ptr(SP,(frame::register_save_words+3)*wordSize,L3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   798
    __ retl();                  // Result in Rret is != 0; flags set to NZ
489c9b5090e2 Initial load
duke
parents:
diff changeset
   799
    __ delayed()->add(SP,4*wordSize,SP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   800
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   801
    __ ret();                   // Result in Rret is != 0; flags set to NZ
489c9b5090e2 Initial load
duke
parents:
diff changeset
   802
    __ delayed()->restore();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   803
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   804
489c9b5090e2 Initial load
duke
parents:
diff changeset
   805
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   806
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   807
489c9b5090e2 Initial load
duke
parents:
diff changeset
   808
489c9b5090e2 Initial load
duke
parents:
diff changeset
   809
  // Called from MacroAssembler::verify_oop
489c9b5090e2 Initial load
duke
parents:
diff changeset
   810
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   811
  address generate_verify_oop_subroutine() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   812
    StubCodeMark mark(this, "StubRoutines", "verify_oop_stub");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   813
489c9b5090e2 Initial load
duke
parents:
diff changeset
   814
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   815
489c9b5090e2 Initial load
duke
parents:
diff changeset
   816
    __ verify_oop_subroutine();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   817
489c9b5090e2 Initial load
duke
parents:
diff changeset
   818
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   819
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   820
489c9b5090e2 Initial load
duke
parents:
diff changeset
   821
489c9b5090e2 Initial load
duke
parents:
diff changeset
   822
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   823
  // Verify that a register contains clean 32-bits positive value
489c9b5090e2 Initial load
duke
parents:
diff changeset
   824
  // (high 32-bits are 0) so it could be used in 64-bits shifts (sllx, srax).
489c9b5090e2 Initial load
duke
parents:
diff changeset
   825
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   826
  //  Input:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   827
  //    Rint  -  32-bits value
489c9b5090e2 Initial load
duke
parents:
diff changeset
   828
  //    Rtmp  -  scratch
489c9b5090e2 Initial load
duke
parents:
diff changeset
   829
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   830
  void assert_clean_int(Register Rint, Register Rtmp) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   831
#if defined(ASSERT) && defined(_LP64)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   832
    __ signx(Rint, Rtmp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   833
    __ cmp(Rint, Rtmp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   834
    __ breakpoint_trap(Assembler::notEqual, Assembler::xcc);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   835
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   836
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   837
489c9b5090e2 Initial load
duke
parents:
diff changeset
   838
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   839
  //  Generate overlap test for array copy stubs
489c9b5090e2 Initial load
duke
parents:
diff changeset
   840
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   841
  //  Input:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   842
  //    O0    -  array1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   843
  //    O1    -  array2
489c9b5090e2 Initial load
duke
parents:
diff changeset
   844
  //    O2    -  element count
489c9b5090e2 Initial load
duke
parents:
diff changeset
   845
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   846
  //  Kills temps:  O3, O4
489c9b5090e2 Initial load
duke
parents:
diff changeset
   847
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   848
  void array_overlap_test(address no_overlap_target, int log2_elem_size) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   849
    assert(no_overlap_target != NULL, "must be generated");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   850
    array_overlap_test(no_overlap_target, NULL, log2_elem_size);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   851
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   852
  void array_overlap_test(Label& L_no_overlap, int log2_elem_size) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   853
    array_overlap_test(NULL, &L_no_overlap, log2_elem_size);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   854
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   855
  void array_overlap_test(address no_overlap_target, Label* NOLp, int log2_elem_size) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   856
    const Register from       = O0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   857
    const Register to         = O1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   858
    const Register count      = O2;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   859
    const Register to_from    = O3; // to - from
489c9b5090e2 Initial load
duke
parents:
diff changeset
   860
    const Register byte_count = O4; // count << log2_elem_size
489c9b5090e2 Initial load
duke
parents:
diff changeset
   861
489c9b5090e2 Initial load
duke
parents:
diff changeset
   862
      __ subcc(to, from, to_from);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   863
      __ sll_ptr(count, log2_elem_size, byte_count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   864
      if (NOLp == NULL)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   865
        __ brx(Assembler::lessEqualUnsigned, false, Assembler::pt, no_overlap_target);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   866
      else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   867
        __ brx(Assembler::lessEqualUnsigned, false, Assembler::pt, (*NOLp));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   868
      __ delayed()->cmp(to_from, byte_count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   869
      if (NOLp == NULL)
6057
e660446e0804 6962569: assembler_sparc.cpp:1969: assert(false) failed: error
tonyp
parents: 5702
diff changeset
   870
        __ brx(Assembler::greaterEqualUnsigned, false, Assembler::pt, no_overlap_target);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   871
      else
6057
e660446e0804 6962569: assembler_sparc.cpp:1969: assert(false) failed: error
tonyp
parents: 5702
diff changeset
   872
        __ brx(Assembler::greaterEqualUnsigned, false, Assembler::pt, (*NOLp));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   873
      __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   874
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   875
489c9b5090e2 Initial load
duke
parents:
diff changeset
   876
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   877
  //  Generate pre-write barrier for array.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   878
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   879
  //  Input:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   880
  //     addr     - register containing starting address
489c9b5090e2 Initial load
duke
parents:
diff changeset
   881
  //     count    - register containing element count
489c9b5090e2 Initial load
duke
parents:
diff changeset
   882
  //     tmp      - scratch register
489c9b5090e2 Initial load
duke
parents:
diff changeset
   883
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   884
  //  The input registers are overwritten.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   885
  //
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   886
  void gen_write_ref_array_pre_barrier(Register addr, Register count, bool dest_uninitialized) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   887
    BarrierSet* bs = Universe::heap()->barrier_set();
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   888
    switch (bs->kind()) {
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   889
      case BarrierSet::G1SATBCTLogging:
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   890
        // With G1, don't generate the call if we statically know that the target in uninitialized
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   891
        if (!dest_uninitialized) {
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   892
          __ save_frame(0);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   893
          // Save the necessary global regs... will be used after.
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   894
          if (addr->is_global()) {
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   895
            __ mov(addr, L0);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   896
          }
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   897
          if (count->is_global()) {
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   898
            __ mov(count, L1);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   899
          }
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   900
          __ mov(addr->after_save(), O0);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   901
          // Get the count into O1
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   902
          __ call(CAST_FROM_FN_PTR(address, BarrierSet::static_write_ref_array_pre));
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   903
          __ delayed()->mov(count->after_save(), O1);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   904
          if (addr->is_global()) {
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   905
            __ mov(L0, addr);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   906
          }
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   907
          if (count->is_global()) {
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   908
            __ mov(L1, count);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   909
          }
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   910
          __ restore();
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   911
        }
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   912
        break;
32596
8feecdee3156 8072817: CardTableExtension kind() should be BarrierSet::CardTableExtension
kbarrett
parents: 31515
diff changeset
   913
      case BarrierSet::CardTableForRS:
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   914
      case BarrierSet::CardTableExtension:
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   915
      case BarrierSet::ModRef:
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   916
        break;
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   917
      default:
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   918
        ShouldNotReachHere();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   919
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   920
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   921
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   922
  //  Generate post-write barrier for array.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   923
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   924
  //  Input:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   925
  //     addr     - register containing starting address
489c9b5090e2 Initial load
duke
parents:
diff changeset
   926
  //     count    - register containing element count
489c9b5090e2 Initial load
duke
parents:
diff changeset
   927
  //     tmp      - scratch register
489c9b5090e2 Initial load
duke
parents:
diff changeset
   928
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   929
  //  The input registers are overwritten.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   930
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   931
  void gen_write_ref_array_post_barrier(Register addr, Register count,
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
   932
                                        Register tmp) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   933
    BarrierSet* bs = Universe::heap()->barrier_set();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   934
489c9b5090e2 Initial load
duke
parents:
diff changeset
   935
    switch (bs->kind()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   936
      case BarrierSet::G1SATBCTLogging:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   937
        {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   938
          // Get some new fresh output registers.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   939
          __ save_frame(0);
1374
4c24294029a9 6711316: Open source the Garbage-First garbage collector
ysr
parents: 360
diff changeset
   940
          __ mov(addr->after_save(), O0);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   941
          __ call(CAST_FROM_FN_PTR(address, BarrierSet::static_write_ref_array_post));
1374
4c24294029a9 6711316: Open source the Garbage-First garbage collector
ysr
parents: 360
diff changeset
   942
          __ delayed()->mov(count->after_save(), O1);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   943
          __ restore();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   944
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   945
        break;
32596
8feecdee3156 8072817: CardTableExtension kind() should be BarrierSet::CardTableExtension
kbarrett
parents: 31515
diff changeset
   946
      case BarrierSet::CardTableForRS:
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   947
      case BarrierSet::CardTableExtension:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   948
        {
29325
0e86e64c66e5 8069016: Add BarrierSet downcast support
kbarrett
parents: 27691
diff changeset
   949
          CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   950
          assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   951
          assert_different_registers(addr, count, tmp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   952
489c9b5090e2 Initial load
duke
parents:
diff changeset
   953
          Label L_loop;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   954
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
   955
          __ sll_ptr(count, LogBytesPerHeapOop, count);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
   956
          __ sub(count, BytesPerHeapOop, count);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   957
          __ add(count, addr, count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   958
          // Use two shifts to clear out those low order two bits! (Cannot opt. into 1.)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   959
          __ srl_ptr(addr, CardTableModRefBS::card_shift, addr);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   960
          __ srl_ptr(count, CardTableModRefBS::card_shift, count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   961
          __ sub(count, addr, count);
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2338
diff changeset
   962
          AddressLiteral rs(ct->byte_map_base);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2338
diff changeset
   963
          __ set(rs, tmp);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   964
        __ BIND(L_loop);
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2338
diff changeset
   965
          __ stb(G0, tmp, addr);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   966
          __ subcc(count, 1, count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   967
          __ brx(Assembler::greaterEqual, false, Assembler::pt, L_loop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   968
          __ delayed()->add(addr, 1, addr);
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2338
diff changeset
   969
        }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   970
        break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   971
      case BarrierSet::ModRef:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   972
        break;
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2338
diff changeset
   973
      default:
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   974
        ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   975
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   976
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   977
10512
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
   978
  //
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
   979
  // Generate main code for disjoint arraycopy
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
   980
  //
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
   981
  typedef void (StubGenerator::*CopyLoopFunc)(Register from, Register to, Register count, int count_dec,
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
   982
                                              Label& L_loop, bool use_prefetch, bool use_bis);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
   983
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
   984
  void disjoint_copy_core(Register from, Register to, Register count, int log2_elem_size,
24326
d3fdd5c16fe0 8022070: Compilation error in stubGenerator_sparc.cpp with some compilers
mikael
parents: 22505
diff changeset
   985
                          int iter_size, StubGenerator::CopyLoopFunc copy_loop_func) {
10512
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
   986
    Label L_copy;
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
   987
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
   988
    assert(log2_elem_size <= 3, "the following code should be changed");
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
   989
    int count_dec = 16>>log2_elem_size;
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
   990
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
   991
    int prefetch_dist = MAX2(ArraycopySrcPrefetchDistance, ArraycopyDstPrefetchDistance);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
   992
    assert(prefetch_dist < 4096, "invalid value");
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
   993
    prefetch_dist = (prefetch_dist + (iter_size-1)) & (-iter_size); // round up to one iteration copy size
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
   994
    int prefetch_count = (prefetch_dist >> log2_elem_size); // elements count
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
   995
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
   996
    if (UseBlockCopy) {
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
   997
      Label L_block_copy, L_block_copy_prefetch, L_skip_block_copy;
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
   998
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
   999
      // 64 bytes tail + bytes copied in one loop iteration
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1000
      int tail_size = 64 + iter_size;
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1001
      int block_copy_count = (MAX2(tail_size, (int)BlockCopyLowLimit)) >> log2_elem_size;
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1002
      // Use BIS copy only for big arrays since it requires membar.
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1003
      __ set(block_copy_count, O4);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1004
      __ cmp_and_br_short(count, O4, Assembler::lessUnsigned, Assembler::pt, L_skip_block_copy);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1005
      // This code is for disjoint source and destination:
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1006
      //   to <= from || to >= from+count
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1007
      // but BIS will stomp over 'from' if (to > from-tail_size && to <= from)
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1008
      __ sub(from, to, O4);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1009
      __ srax(O4, 4, O4); // divide by 16 since following short branch have only 5 bits for imm.
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1010
      __ cmp_and_br_short(O4, (tail_size>>4), Assembler::lessEqualUnsigned, Assembler::pn, L_skip_block_copy);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1011
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1012
      __ wrasi(G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1013
      // BIS should not be used to copy tail (64 bytes+iter_size)
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1014
      // to avoid zeroing of following values.
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1015
      __ sub(count, (tail_size>>log2_elem_size), count); // count is still positive >= 0
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1016
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1017
      if (prefetch_count > 0) { // rounded up to one iteration count
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1018
        // Do prefetching only if copy size is bigger
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1019
        // than prefetch distance.
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1020
        __ set(prefetch_count, O4);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1021
        __ cmp_and_brx_short(count, O4, Assembler::less, Assembler::pt, L_block_copy);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1022
        __ sub(count, prefetch_count, count);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1023
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1024
        (this->*copy_loop_func)(from, to, count, count_dec, L_block_copy_prefetch, true, true);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1025
        __ add(count, prefetch_count, count); // restore count
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1026
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1027
      } // prefetch_count > 0
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1028
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1029
      (this->*copy_loop_func)(from, to, count, count_dec, L_block_copy, false, true);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1030
      __ add(count, (tail_size>>log2_elem_size), count); // restore count
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1031
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1032
      __ wrasi(G0, Assembler::ASI_PRIMARY_NOFAULT);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1033
      // BIS needs membar.
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1034
      __ membar(Assembler::StoreLoad);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1035
      // Copy tail
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1036
      __ ba_short(L_copy);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1037
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1038
      __ BIND(L_skip_block_copy);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1039
    } // UseBlockCopy
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1040
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1041
    if (prefetch_count > 0) { // rounded up to one iteration count
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1042
      // Do prefetching only if copy size is bigger
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1043
      // than prefetch distance.
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1044
      __ set(prefetch_count, O4);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1045
      __ cmp_and_brx_short(count, O4, Assembler::lessUnsigned, Assembler::pt, L_copy);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1046
      __ sub(count, prefetch_count, count);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1047
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1048
      Label L_copy_prefetch;
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1049
      (this->*copy_loop_func)(from, to, count, count_dec, L_copy_prefetch, true, false);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1050
      __ add(count, prefetch_count, count); // restore count
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1051
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1052
    } // prefetch_count > 0
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1053
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1054
    (this->*copy_loop_func)(from, to, count, count_dec, L_copy, false, false);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1055
  }
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1056
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1057
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1058
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1059
  //
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1060
  // Helper methods for copy_16_bytes_forward_with_shift()
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1061
  //
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1062
  void copy_16_bytes_shift_loop(Register from, Register to, Register count, int count_dec,
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1063
                                Label& L_loop, bool use_prefetch, bool use_bis) {
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1064
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1065
    const Register left_shift  = G1; // left  shift bit counter
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1066
    const Register right_shift = G5; // right shift bit counter
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1067
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1068
    __ align(OptoLoopAlignment);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1069
    __ BIND(L_loop);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1070
    if (use_prefetch) {
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1071
      if (ArraycopySrcPrefetchDistance > 0) {
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1072
        __ prefetch(from, ArraycopySrcPrefetchDistance, Assembler::severalReads);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1073
      }
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1074
      if (ArraycopyDstPrefetchDistance > 0) {
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1075
        __ prefetch(to, ArraycopyDstPrefetchDistance, Assembler::severalWritesAndPossiblyReads);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1076
      }
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1077
    }
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1078
    __ ldx(from, 0, O4);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1079
    __ ldx(from, 8, G4);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1080
    __ inc(to, 16);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1081
    __ inc(from, 16);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1082
    __ deccc(count, count_dec); // Can we do next iteration after this one?
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1083
    __ srlx(O4, right_shift, G3);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1084
    __ bset(G3, O3);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1085
    __ sllx(O4, left_shift,  O4);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1086
    __ srlx(G4, right_shift, G3);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1087
    __ bset(G3, O4);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1088
    if (use_bis) {
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1089
      __ stxa(O3, to, -16);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1090
      __ stxa(O4, to, -8);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1091
    } else {
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1092
      __ stx(O3, to, -16);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1093
      __ stx(O4, to, -8);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1094
    }
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1095
    __ brx(Assembler::greaterEqual, false, Assembler::pt, L_loop);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1096
    __ delayed()->sllx(G4, left_shift,  O3);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1097
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1098
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1099
  // Copy big chunks forward with shift
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1100
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1101
  // Inputs:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1102
  //   from      - source arrays
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1103
  //   to        - destination array aligned to 8-bytes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1104
  //   count     - elements count to copy >= the count equivalent to 16 bytes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1105
  //   count_dec - elements count's decrement equivalent to 16 bytes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1106
  //   L_copy_bytes - copy exit label
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1107
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1108
  void copy_16_bytes_forward_with_shift(Register from, Register to,
10512
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1109
                     Register count, int log2_elem_size, Label& L_copy_bytes) {
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1110
    Label L_aligned_copy, L_copy_last_bytes;
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1111
    assert(log2_elem_size <= 3, "the following code should be changed");
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1112
    int count_dec = 16>>log2_elem_size;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1113
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1114
    // if both arrays have the same alignment mod 8, do 8 bytes aligned copy
10512
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1115
    __ andcc(from, 7, G1); // misaligned bytes
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1116
    __ br(Assembler::zero, false, Assembler::pt, L_aligned_copy);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1117
    __ delayed()->nop();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1118
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1119
    const Register left_shift  = G1; // left  shift bit counter
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1120
    const Register right_shift = G5; // right shift bit counter
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1121
10512
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1122
    __ sll(G1, LogBitsPerByte, left_shift);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1123
    __ mov(64, right_shift);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1124
    __ sub(right_shift, left_shift, right_shift);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1125
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1126
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1127
    // Load 2 aligned 8-bytes chunks and use one from previous iteration
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1128
    // to form 2 aligned 8-bytes chunks to store.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1129
    //
10512
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1130
    __ dec(count, count_dec);   // Pre-decrement 'count'
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1131
    __ andn(from, 7, from);     // Align address
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1132
    __ ldx(from, 0, O3);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1133
    __ inc(from, 8);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1134
    __ sllx(O3, left_shift,  O3);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1135
24326
d3fdd5c16fe0 8022070: Compilation error in stubGenerator_sparc.cpp with some compilers
mikael
parents: 22505
diff changeset
  1136
    disjoint_copy_core(from, to, count, log2_elem_size, 16, &StubGenerator::copy_16_bytes_shift_loop);
10512
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1137
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1138
    __ inccc(count, count_dec>>1 ); // + 8 bytes
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1139
    __ brx(Assembler::negative, true, Assembler::pn, L_copy_last_bytes);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1140
    __ delayed()->inc(count, count_dec>>1); // restore 'count'
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1141
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1142
    // copy 8 bytes, part of them already loaded in O3
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1143
    __ ldx(from, 0, O4);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1144
    __ inc(to, 8);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1145
    __ inc(from, 8);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1146
    __ srlx(O4, right_shift, G3);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1147
    __ bset(O3, G3);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1148
    __ stx(G3, to, -8);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1149
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1150
    __ BIND(L_copy_last_bytes);
10512
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1151
    __ srl(right_shift, LogBitsPerByte, right_shift); // misaligned bytes
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1152
    __ br(Assembler::always, false, Assembler::pt, L_copy_bytes);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1153
    __ delayed()->sub(from, right_shift, from);       // restore address
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1154
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1155
    __ BIND(L_aligned_copy);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1156
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1157
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1158
  // Copy big chunks backward with shift
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1159
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1160
  // Inputs:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1161
  //   end_from  - source arrays end address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1162
  //   end_to    - destination array end address aligned to 8-bytes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1163
  //   count     - elements count to copy >= the count equivalent to 16 bytes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1164
  //   count_dec - elements count's decrement equivalent to 16 bytes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1165
  //   L_aligned_copy - aligned copy exit label
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1166
  //   L_copy_bytes   - copy exit label
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1167
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1168
  void copy_16_bytes_backward_with_shift(Register end_from, Register end_to,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1169
                     Register count, int count_dec,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1170
                     Label& L_aligned_copy, Label& L_copy_bytes) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1171
    Label L_loop, L_copy_last_bytes;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1172
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1173
    // if both arrays have the same alignment mod 8, do 8 bytes aligned copy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1174
      __ andcc(end_from, 7, G1); // misaligned bytes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1175
      __ br(Assembler::zero, false, Assembler::pt, L_aligned_copy);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1176
      __ delayed()->deccc(count, count_dec); // Pre-decrement 'count'
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1177
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1178
    const Register left_shift  = G1; // left  shift bit counter
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1179
    const Register right_shift = G5; // right shift bit counter
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1180
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1181
      __ sll(G1, LogBitsPerByte, left_shift);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1182
      __ mov(64, right_shift);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1183
      __ sub(right_shift, left_shift, right_shift);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1184
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1185
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1186
    // Load 2 aligned 8-bytes chunks and use one from previous iteration
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1187
    // to form 2 aligned 8-bytes chunks to store.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1188
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1189
      __ andn(end_from, 7, end_from);     // Align address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1190
      __ ldx(end_from, 0, O3);
5249
5cac34e6fe54 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 5248
diff changeset
  1191
      __ align(OptoLoopAlignment);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1192
    __ BIND(L_loop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1193
      __ ldx(end_from, -8, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1194
      __ deccc(count, count_dec); // Can we do next iteration after this one?
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1195
      __ ldx(end_from, -16, G4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1196
      __ dec(end_to, 16);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1197
      __ dec(end_from, 16);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1198
      __ srlx(O3, right_shift, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1199
      __ sllx(O4, left_shift,  G3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1200
      __ bset(G3, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1201
      __ stx(O3, end_to, 8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1202
      __ srlx(O4, right_shift, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1203
      __ sllx(G4, left_shift,  G3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1204
      __ bset(G3, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1205
      __ stx(O4, end_to, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1206
      __ brx(Assembler::greaterEqual, false, Assembler::pt, L_loop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1207
      __ delayed()->mov(G4, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1208
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1209
      __ inccc(count, count_dec>>1 ); // + 8 bytes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1210
      __ brx(Assembler::negative, true, Assembler::pn, L_copy_last_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1211
      __ delayed()->inc(count, count_dec>>1); // restore 'count'
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1212
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1213
      // copy 8 bytes, part of them already loaded in O3
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1214
      __ ldx(end_from, -8, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1215
      __ dec(end_to, 8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1216
      __ dec(end_from, 8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1217
      __ srlx(O3, right_shift, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1218
      __ sllx(O4, left_shift,  G3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1219
      __ bset(O3, G3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1220
      __ stx(G3, end_to, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1221
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1222
    __ BIND(L_copy_last_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1223
      __ srl(left_shift, LogBitsPerByte, left_shift);    // misaligned bytes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1224
      __ br(Assembler::always, false, Assembler::pt, L_copy_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1225
      __ delayed()->add(end_from, left_shift, end_from); // restore address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1226
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1227
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1228
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1229
  //  Generate stub for disjoint byte copy.  If "aligned" is true, the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1230
  //  "from" and "to" addresses are assumed to be heapword aligned.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1231
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1232
  // Arguments for generated stub:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1233
  //      from:  O0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1234
  //      to:    O1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1235
  //      count: O2 treated as signed
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1236
  //
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1237
  address generate_disjoint_byte_copy(bool aligned, address *entry, const char *name) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1238
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1239
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1240
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1241
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1242
    Label L_skip_alignment, L_align;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1243
    Label L_copy_byte, L_copy_byte_loop, L_exit;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1244
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1245
    const Register from      = O0;   // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1246
    const Register to        = O1;   // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1247
    const Register count     = O2;   // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1248
    const Register offset    = O5;   // offset from start of arrays
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1249
    // O3, O4, G3, G4 are used as temp registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1250
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1251
    assert_clean_int(count, O3);     // Make sure 'count' is clean int.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1252
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1253
    if (entry != NULL) {
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1254
      *entry = __ pc();
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1255
      // caller can pass a 64-bit byte count here (from Unsafe.copyMemory)
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1256
      BLOCK_COMMENT("Entry:");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1257
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1258
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1259
    // for short arrays, just do single element copy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1260
    __ cmp(count, 23); // 16 + 7
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1261
    __ brx(Assembler::less, false, Assembler::pn, L_copy_byte);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1262
    __ delayed()->mov(G0, offset);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1263
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1264
    if (aligned) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1265
      // 'aligned' == true when it is known statically during compilation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1266
      // of this arraycopy call site that both 'from' and 'to' addresses
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1267
      // are HeapWordSize aligned (see LibraryCallKit::basictype2arraycopy()).
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1268
      //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1269
      // Aligned arrays have 4 bytes alignment in 32-bits VM
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1270
      // and 8 bytes - in 64-bits VM. So we do it only for 32-bits VM
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1271
      //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1272
#ifndef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1273
      // copy a 4-bytes word if necessary to align 'to' to 8 bytes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1274
      __ andcc(to, 7, G0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1275
      __ br(Assembler::zero, false, Assembler::pn, L_skip_alignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1276
      __ delayed()->ld(from, 0, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1277
      __ inc(from, 4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1278
      __ inc(to, 4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1279
      __ dec(count, 4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1280
      __ st(O3, to, -4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1281
    __ BIND(L_skip_alignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1282
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1283
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1284
      // copy bytes to align 'to' on 8 byte boundary
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1285
      __ andcc(to, 7, G1); // misaligned bytes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1286
      __ br(Assembler::zero, false, Assembler::pt, L_skip_alignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1287
      __ delayed()->neg(G1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1288
      __ inc(G1, 8);       // bytes need to copy to next 8-bytes alignment
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1289
      __ sub(count, G1, count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1290
    __ BIND(L_align);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1291
      __ ldub(from, 0, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1292
      __ deccc(G1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1293
      __ inc(from);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1294
      __ stb(O3, to, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1295
      __ br(Assembler::notZero, false, Assembler::pt, L_align);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1296
      __ delayed()->inc(to);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1297
    __ BIND(L_skip_alignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1298
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1299
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1300
    if (!aligned)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1301
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1302
    {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1303
      // Copy with shift 16 bytes per iteration if arrays do not have
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1304
      // the same alignment mod 8, otherwise fall through to the next
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1305
      // code for aligned copy.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1306
      // The compare above (count >= 23) guarantes 'count' >= 16 bytes.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1307
      // Also jump over aligned copy after the copy with shift completed.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1308
10512
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1309
      copy_16_bytes_forward_with_shift(from, to, count, 0, L_copy_byte);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1310
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1311
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1312
    // Both array are 8 bytes aligned, copy 16 bytes at a time
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1313
      __ and3(count, 7, G4); // Save count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1314
      __ srl(count, 3, count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1315
     generate_disjoint_long_copy_core(aligned);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1316
      __ mov(G4, count);     // Restore count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1317
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1318
    // copy tailing bytes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1319
    __ BIND(L_copy_byte);
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10004
diff changeset
  1320
      __ cmp_and_br_short(count, 0, Assembler::equal, Assembler::pt, L_exit);
5249
5cac34e6fe54 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 5248
diff changeset
  1321
      __ align(OptoLoopAlignment);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1322
    __ BIND(L_copy_byte_loop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1323
      __ ldub(from, offset, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1324
      __ deccc(count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1325
      __ stb(O3, to, offset);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1326
      __ brx(Assembler::notZero, false, Assembler::pt, L_copy_byte_loop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1327
      __ delayed()->inc(offset);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1328
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1329
    __ BIND(L_exit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1330
      // O3, O4 are used as temp registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1331
      inc_counter_np(SharedRuntime::_jbyte_array_copy_ctr, O3, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1332
      __ retl();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1333
      __ delayed()->mov(G0, O0); // return 0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1334
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1335
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1336
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1337
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1338
  //  Generate stub for conjoint byte copy.  If "aligned" is true, the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1339
  //  "from" and "to" addresses are assumed to be heapword aligned.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1340
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1341
  // Arguments for generated stub:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1342
  //      from:  O0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1343
  //      to:    O1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1344
  //      count: O2 treated as signed
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1345
  //
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1346
  address generate_conjoint_byte_copy(bool aligned, address nooverlap_target,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1347
                                      address *entry, const char *name) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1348
    // Do reverse copy.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1349
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1350
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1351
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1352
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1353
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1354
    Label L_skip_alignment, L_align, L_aligned_copy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1355
    Label L_copy_byte, L_copy_byte_loop, L_exit;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1356
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1357
    const Register from      = O0;   // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1358
    const Register to        = O1;   // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1359
    const Register count     = O2;   // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1360
    const Register end_from  = from; // source array end address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1361
    const Register end_to    = to;   // destination array end address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1362
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1363
    assert_clean_int(count, O3);     // Make sure 'count' is clean int.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1364
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1365
    if (entry != NULL) {
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1366
      *entry = __ pc();
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1367
      // caller can pass a 64-bit byte count here (from Unsafe.copyMemory)
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1368
      BLOCK_COMMENT("Entry:");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1369
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1370
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1371
    array_overlap_test(nooverlap_target, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1372
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1373
    __ add(to, count, end_to);       // offset after last copied element
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1374
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1375
    // for short arrays, just do single element copy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1376
    __ cmp(count, 23); // 16 + 7
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1377
    __ brx(Assembler::less, false, Assembler::pn, L_copy_byte);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1378
    __ delayed()->add(from, count, end_from);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1379
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1380
    {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1381
      // Align end of arrays since they could be not aligned even
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1382
      // when arrays itself are aligned.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1383
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1384
      // copy bytes to align 'end_to' on 8 byte boundary
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1385
      __ andcc(end_to, 7, G1); // misaligned bytes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1386
      __ br(Assembler::zero, false, Assembler::pt, L_skip_alignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1387
      __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1388
      __ sub(count, G1, count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1389
    __ BIND(L_align);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1390
      __ dec(end_from);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1391
      __ dec(end_to);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1392
      __ ldub(end_from, 0, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1393
      __ deccc(G1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1394
      __ brx(Assembler::notZero, false, Assembler::pt, L_align);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1395
      __ delayed()->stb(O3, end_to, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1396
    __ BIND(L_skip_alignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1397
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1398
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1399
    if (aligned) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1400
      // Both arrays are aligned to 8-bytes in 64-bits VM.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1401
      // The 'count' is decremented in copy_16_bytes_backward_with_shift()
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1402
      // in unaligned case.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1403
      __ dec(count, 16);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1404
    } else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1405
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1406
    {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1407
      // Copy with shift 16 bytes per iteration if arrays do not have
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1408
      // the same alignment mod 8, otherwise jump to the next
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1409
      // code for aligned copy (and substracting 16 from 'count' before jump).
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1410
      // The compare above (count >= 11) guarantes 'count' >= 16 bytes.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1411
      // Also jump over aligned copy after the copy with shift completed.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1412
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1413
      copy_16_bytes_backward_with_shift(end_from, end_to, count, 16,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1414
                                        L_aligned_copy, L_copy_byte);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1415
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1416
    // copy 4 elements (16 bytes) at a time
5249
5cac34e6fe54 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 5248
diff changeset
  1417
      __ align(OptoLoopAlignment);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1418
    __ BIND(L_aligned_copy);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1419
      __ dec(end_from, 16);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1420
      __ ldx(end_from, 8, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1421
      __ ldx(end_from, 0, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1422
      __ dec(end_to, 16);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1423
      __ deccc(count, 16);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1424
      __ stx(O3, end_to, 8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1425
      __ brx(Assembler::greaterEqual, false, Assembler::pt, L_aligned_copy);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1426
      __ delayed()->stx(O4, end_to, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1427
      __ inc(count, 16);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1428
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1429
    // copy 1 element (2 bytes) at a time
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1430
    __ BIND(L_copy_byte);
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10004
diff changeset
  1431
      __ cmp_and_br_short(count, 0, Assembler::equal, Assembler::pt, L_exit);
5249
5cac34e6fe54 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 5248
diff changeset
  1432
      __ align(OptoLoopAlignment);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1433
    __ BIND(L_copy_byte_loop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1434
      __ dec(end_from);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1435
      __ dec(end_to);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1436
      __ ldub(end_from, 0, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1437
      __ deccc(count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1438
      __ brx(Assembler::greater, false, Assembler::pt, L_copy_byte_loop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1439
      __ delayed()->stb(O4, end_to, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1440
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1441
    __ BIND(L_exit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1442
    // O3, O4 are used as temp registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1443
    inc_counter_np(SharedRuntime::_jbyte_array_copy_ctr, O3, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1444
    __ retl();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1445
    __ delayed()->mov(G0, O0); // return 0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1446
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1447
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1448
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1449
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1450
  //  Generate stub for disjoint short copy.  If "aligned" is true, the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1451
  //  "from" and "to" addresses are assumed to be heapword aligned.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1452
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1453
  // Arguments for generated stub:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1454
  //      from:  O0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1455
  //      to:    O1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1456
  //      count: O2 treated as signed
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1457
  //
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1458
  address generate_disjoint_short_copy(bool aligned, address *entry, const char * name) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1459
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1460
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1461
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1462
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1463
    Label L_skip_alignment, L_skip_alignment2;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1464
    Label L_copy_2_bytes, L_copy_2_bytes_loop, L_exit;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1465
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1466
    const Register from      = O0;   // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1467
    const Register to        = O1;   // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1468
    const Register count     = O2;   // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1469
    const Register offset    = O5;   // offset from start of arrays
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1470
    // O3, O4, G3, G4 are used as temp registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1471
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1472
    assert_clean_int(count, O3);     // Make sure 'count' is clean int.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1473
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1474
    if (entry != NULL) {
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1475
      *entry = __ pc();
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1476
      // caller can pass a 64-bit byte count here (from Unsafe.copyMemory)
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1477
      BLOCK_COMMENT("Entry:");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1478
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1479
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1480
    // for short arrays, just do single element copy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1481
    __ cmp(count, 11); // 8 + 3  (22 bytes)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1482
    __ brx(Assembler::less, false, Assembler::pn, L_copy_2_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1483
    __ delayed()->mov(G0, offset);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1484
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1485
    if (aligned) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1486
      // 'aligned' == true when it is known statically during compilation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1487
      // of this arraycopy call site that both 'from' and 'to' addresses
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1488
      // are HeapWordSize aligned (see LibraryCallKit::basictype2arraycopy()).
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1489
      //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1490
      // Aligned arrays have 4 bytes alignment in 32-bits VM
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1491
      // and 8 bytes - in 64-bits VM.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1492
      //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1493
#ifndef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1494
      // copy a 2-elements word if necessary to align 'to' to 8 bytes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1495
      __ andcc(to, 7, G0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1496
      __ br(Assembler::zero, false, Assembler::pt, L_skip_alignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1497
      __ delayed()->ld(from, 0, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1498
      __ inc(from, 4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1499
      __ inc(to, 4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1500
      __ dec(count, 2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1501
      __ st(O3, to, -4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1502
    __ BIND(L_skip_alignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1503
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1504
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1505
      // copy 1 element if necessary to align 'to' on an 4 bytes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1506
      __ andcc(to, 3, G0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1507
      __ br(Assembler::zero, false, Assembler::pt, L_skip_alignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1508
      __ delayed()->lduh(from, 0, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1509
      __ inc(from, 2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1510
      __ inc(to, 2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1511
      __ dec(count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1512
      __ sth(O3, to, -2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1513
    __ BIND(L_skip_alignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1514
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1515
      // copy 2 elements to align 'to' on an 8 byte boundary
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1516
      __ andcc(to, 7, G0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1517
      __ br(Assembler::zero, false, Assembler::pn, L_skip_alignment2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1518
      __ delayed()->lduh(from, 0, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1519
      __ dec(count, 2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1520
      __ lduh(from, 2, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1521
      __ inc(from, 4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1522
      __ inc(to, 4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1523
      __ sth(O3, to, -4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1524
      __ sth(O4, to, -2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1525
    __ BIND(L_skip_alignment2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1526
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1527
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1528
    if (!aligned)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1529
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1530
    {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1531
      // Copy with shift 16 bytes per iteration if arrays do not have
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1532
      // the same alignment mod 8, otherwise fall through to the next
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1533
      // code for aligned copy.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1534
      // The compare above (count >= 11) guarantes 'count' >= 16 bytes.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1535
      // Also jump over aligned copy after the copy with shift completed.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1536
10512
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1537
      copy_16_bytes_forward_with_shift(from, to, count, 1, L_copy_2_bytes);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1538
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1539
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1540
    // Both array are 8 bytes aligned, copy 16 bytes at a time
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1541
      __ and3(count, 3, G4); // Save
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1542
      __ srl(count, 2, count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1543
     generate_disjoint_long_copy_core(aligned);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1544
      __ mov(G4, count); // restore
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1545
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1546
    // copy 1 element at a time
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1547
    __ BIND(L_copy_2_bytes);
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10004
diff changeset
  1548
      __ cmp_and_br_short(count, 0, Assembler::equal, Assembler::pt, L_exit);
5249
5cac34e6fe54 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 5248
diff changeset
  1549
      __ align(OptoLoopAlignment);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1550
    __ BIND(L_copy_2_bytes_loop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1551
      __ lduh(from, offset, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1552
      __ deccc(count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1553
      __ sth(O3, to, offset);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1554
      __ brx(Assembler::notZero, false, Assembler::pt, L_copy_2_bytes_loop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1555
      __ delayed()->inc(offset, 2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1556
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1557
    __ BIND(L_exit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1558
      // O3, O4 are used as temp registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1559
      inc_counter_np(SharedRuntime::_jshort_array_copy_ctr, O3, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1560
      __ retl();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1561
      __ delayed()->mov(G0, O0); // return 0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1562
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1563
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1564
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1565
  //
6433
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1566
  //  Generate stub for disjoint short fill.  If "aligned" is true, the
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1567
  //  "to" address is assumed to be heapword aligned.
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1568
  //
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1569
  // Arguments for generated stub:
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1570
  //      to:    O0
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1571
  //      value: O1
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1572
  //      count: O2 treated as signed
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1573
  //
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1574
  address generate_fill(BasicType t, bool aligned, const char* name) {
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1575
    __ align(CodeEntryAlignment);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1576
    StubCodeMark mark(this, "StubRoutines", name);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1577
    address start = __ pc();
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1578
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1579
    const Register to        = O0;   // source array address
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1580
    const Register value     = O1;   // fill value
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1581
    const Register count     = O2;   // elements count
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1582
    // O3 is used as a temp register
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1583
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1584
    assert_clean_int(count, O3);     // Make sure 'count' is clean int.
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1585
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1586
    Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
6464
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1587
    Label L_fill_2_bytes, L_fill_elements, L_fill_32_bytes;
6433
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1588
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1589
    int shift = -1;
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1590
    switch (t) {
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1591
       case T_BYTE:
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1592
        shift = 2;
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1593
        break;
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1594
       case T_SHORT:
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1595
        shift = 1;
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1596
        break;
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1597
      case T_INT:
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1598
         shift = 0;
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1599
        break;
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1600
      default: ShouldNotReachHere();
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1601
    }
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1602
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1603
    BLOCK_COMMENT("Entry:");
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1604
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1605
    if (t == T_BYTE) {
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1606
      // Zero extend value
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1607
      __ and3(value, 0xff, value);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1608
      __ sllx(value, 8, O3);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1609
      __ or3(value, O3, value);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1610
    }
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1611
    if (t == T_SHORT) {
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1612
      // Zero extend value
6464
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1613
      __ sllx(value, 48, value);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1614
      __ srlx(value, 48, value);
6433
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1615
    }
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1616
    if (t == T_BYTE || t == T_SHORT) {
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1617
      __ sllx(value, 16, O3);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1618
      __ or3(value, O3, value);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1619
    }
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1620
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1621
    __ cmp(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
6464
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1622
    __ brx(Assembler::lessUnsigned, false, Assembler::pn, L_fill_elements); // use unsigned cmp
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1623
    __ delayed()->andcc(count, 1, G0);
6433
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1624
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1625
    if (!aligned && (t == T_BYTE || t == T_SHORT)) {
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1626
      // align source address at 4 bytes address boundary
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1627
      if (t == T_BYTE) {
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1628
        // One byte misalignment happens only for byte arrays
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1629
        __ andcc(to, 1, G0);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1630
        __ br(Assembler::zero, false, Assembler::pt, L_skip_align1);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1631
        __ delayed()->nop();
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1632
        __ stb(value, to, 0);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1633
        __ inc(to, 1);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1634
        __ dec(count, 1);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1635
        __ BIND(L_skip_align1);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1636
      }
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1637
      // Two bytes misalignment happens only for byte and short (char) arrays
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1638
      __ andcc(to, 2, G0);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1639
      __ br(Assembler::zero, false, Assembler::pt, L_skip_align2);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1640
      __ delayed()->nop();
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1641
      __ sth(value, to, 0);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1642
      __ inc(to, 2);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1643
      __ dec(count, 1 << (shift - 1));
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1644
      __ BIND(L_skip_align2);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1645
    }
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1646
#ifdef _LP64
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1647
    if (!aligned) {
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1648
#endif
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1649
    // align to 8 bytes, we know we are 4 byte aligned to start
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1650
    __ andcc(to, 7, G0);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1651
    __ br(Assembler::zero, false, Assembler::pt, L_fill_32_bytes);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1652
    __ delayed()->nop();
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1653
    __ stw(value, to, 0);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1654
    __ inc(to, 4);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1655
    __ dec(count, 1 << shift);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1656
    __ BIND(L_fill_32_bytes);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1657
#ifdef _LP64
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1658
    }
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1659
#endif
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1660
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1661
    if (t == T_INT) {
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1662
      // Zero extend value
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1663
      __ srl(value, 0, value);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1664
    }
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1665
    if (t == T_BYTE || t == T_SHORT || t == T_INT) {
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1666
      __ sllx(value, 32, O3);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1667
      __ or3(value, O3, value);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1668
    }
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1669
6452
cc624b341ab2 6981773: incorrect fill value with OptimizeFill
never
parents: 6433
diff changeset
  1670
    Label L_check_fill_8_bytes;
cc624b341ab2 6981773: incorrect fill value with OptimizeFill
never
parents: 6433
diff changeset
  1671
    // Fill 32-byte chunks
cc624b341ab2 6981773: incorrect fill value with OptimizeFill
never
parents: 6433
diff changeset
  1672
    __ subcc(count, 8 << shift, count);
cc624b341ab2 6981773: incorrect fill value with OptimizeFill
never
parents: 6433
diff changeset
  1673
    __ brx(Assembler::less, false, Assembler::pt, L_check_fill_8_bytes);
cc624b341ab2 6981773: incorrect fill value with OptimizeFill
never
parents: 6433
diff changeset
  1674
    __ delayed()->nop();
cc624b341ab2 6981773: incorrect fill value with OptimizeFill
never
parents: 6433
diff changeset
  1675
6464
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1676
    Label L_fill_32_bytes_loop, L_fill_4_bytes;
6433
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1677
    __ align(16);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1678
    __ BIND(L_fill_32_bytes_loop);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1679
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1680
    __ stx(value, to, 0);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1681
    __ stx(value, to, 8);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1682
    __ stx(value, to, 16);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1683
    __ stx(value, to, 24);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1684
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1685
    __ subcc(count, 8 << shift, count);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1686
    __ brx(Assembler::greaterEqual, false, Assembler::pt, L_fill_32_bytes_loop);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1687
    __ delayed()->add(to, 32, to);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1688
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1689
    __ BIND(L_check_fill_8_bytes);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1690
    __ addcc(count, 8 << shift, count);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1691
    __ brx(Assembler::zero, false, Assembler::pn, L_exit);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1692
    __ delayed()->subcc(count, 1 << (shift + 1), count);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1693
    __ brx(Assembler::less, false, Assembler::pn, L_fill_4_bytes);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1694
    __ delayed()->andcc(count, 1<<shift, G0);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1695
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1696
    //
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1697
    // length is too short, just fill 8 bytes at a time
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1698
    //
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1699
    Label L_fill_8_bytes_loop;
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1700
    __ BIND(L_fill_8_bytes_loop);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1701
    __ stx(value, to, 0);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1702
    __ subcc(count, 1 << (shift + 1), count);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1703
    __ brx(Assembler::greaterEqual, false, Assembler::pn, L_fill_8_bytes_loop);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1704
    __ delayed()->add(to, 8, to);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1705
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1706
    // fill trailing 4 bytes
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1707
    __ andcc(count, 1<<shift, G0);  // in delay slot of branches
6464
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1708
    if (t == T_INT) {
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1709
      __ BIND(L_fill_elements);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1710
    }
6433
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1711
    __ BIND(L_fill_4_bytes);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1712
    __ brx(Assembler::zero, false, Assembler::pt, L_fill_2_bytes);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1713
    if (t == T_BYTE || t == T_SHORT) {
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1714
      __ delayed()->andcc(count, 1<<(shift-1), G0);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1715
    } else {
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1716
      __ delayed()->nop();
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1717
    }
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1718
    __ stw(value, to, 0);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1719
    if (t == T_BYTE || t == T_SHORT) {
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1720
      __ inc(to, 4);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1721
      // fill trailing 2 bytes
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1722
      __ andcc(count, 1<<(shift-1), G0); // in delay slot of branches
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1723
      __ BIND(L_fill_2_bytes);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1724
      __ brx(Assembler::zero, false, Assembler::pt, L_fill_byte);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1725
      __ delayed()->andcc(count, 1, count);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1726
      __ sth(value, to, 0);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1727
      if (t == T_BYTE) {
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1728
        __ inc(to, 2);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1729
        // fill trailing byte
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1730
        __ andcc(count, 1, count);  // in delay slot of branches
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1731
        __ BIND(L_fill_byte);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1732
        __ brx(Assembler::zero, false, Assembler::pt, L_exit);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1733
        __ delayed()->nop();
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1734
        __ stb(value, to, 0);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1735
      } else {
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1736
        __ BIND(L_fill_byte);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1737
      }
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1738
    } else {
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1739
      __ BIND(L_fill_2_bytes);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1740
    }
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1741
    __ BIND(L_exit);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1742
    __ retl();
6464
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1743
    __ delayed()->nop();
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1744
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1745
    // Handle copies less than 8 bytes.  Int is handled elsewhere.
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1746
    if (t == T_BYTE) {
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1747
      __ BIND(L_fill_elements);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1748
      Label L_fill_2, L_fill_4;
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1749
      // in delay slot __ andcc(count, 1, G0);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1750
      __ brx(Assembler::zero, false, Assembler::pt, L_fill_2);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1751
      __ delayed()->andcc(count, 2, G0);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1752
      __ stb(value, to, 0);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1753
      __ inc(to, 1);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1754
      __ BIND(L_fill_2);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1755
      __ brx(Assembler::zero, false, Assembler::pt, L_fill_4);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1756
      __ delayed()->andcc(count, 4, G0);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1757
      __ stb(value, to, 0);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1758
      __ stb(value, to, 1);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1759
      __ inc(to, 2);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1760
      __ BIND(L_fill_4);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1761
      __ brx(Assembler::zero, false, Assembler::pt, L_exit);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1762
      __ delayed()->nop();
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1763
      __ stb(value, to, 0);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1764
      __ stb(value, to, 1);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1765
      __ stb(value, to, 2);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1766
      __ retl();
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1767
      __ delayed()->stb(value, to, 3);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1768
    }
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1769
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1770
    if (t == T_SHORT) {
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1771
      Label L_fill_2;
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1772
      __ BIND(L_fill_elements);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1773
      // in delay slot __ andcc(count, 1, G0);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1774
      __ brx(Assembler::zero, false, Assembler::pt, L_fill_2);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1775
      __ delayed()->andcc(count, 2, G0);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1776
      __ sth(value, to, 0);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1777
      __ inc(to, 2);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1778
      __ BIND(L_fill_2);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1779
      __ brx(Assembler::zero, false, Assembler::pt, L_exit);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1780
      __ delayed()->nop();
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1781
      __ sth(value, to, 0);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1782
      __ retl();
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1783
      __ delayed()->sth(value, to, 2);
cd40daf5b832 6982370: SIGBUS in jbyte_fill
never
parents: 6452
diff changeset
  1784
    }
6433
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1785
    return start;
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1786
  }
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1787
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  1788
  //
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1789
  //  Generate stub for conjoint short copy.  If "aligned" is true, the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1790
  //  "from" and "to" addresses are assumed to be heapword aligned.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1791
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1792
  // Arguments for generated stub:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1793
  //      from:  O0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1794
  //      to:    O1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1795
  //      count: O2 treated as signed
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1796
  //
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1797
  address generate_conjoint_short_copy(bool aligned, address nooverlap_target,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1798
                                       address *entry, const char *name) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1799
    // Do reverse copy.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1800
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1801
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1802
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1803
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1804
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1805
    Label L_skip_alignment, L_skip_alignment2, L_aligned_copy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1806
    Label L_copy_2_bytes, L_copy_2_bytes_loop, L_exit;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1807
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1808
    const Register from      = O0;   // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1809
    const Register to        = O1;   // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1810
    const Register count     = O2;   // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1811
    const Register end_from  = from; // source array end address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1812
    const Register end_to    = to;   // destination array end address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1813
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1814
    const Register byte_count = O3;  // bytes count to copy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1815
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1816
    assert_clean_int(count, O3);     // Make sure 'count' is clean int.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1817
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1818
    if (entry != NULL) {
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1819
      *entry = __ pc();
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1820
      // caller can pass a 64-bit byte count here (from Unsafe.copyMemory)
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1821
      BLOCK_COMMENT("Entry:");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  1822
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1823
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1824
    array_overlap_test(nooverlap_target, 1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1825
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1826
    __ sllx(count, LogBytesPerShort, byte_count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1827
    __ add(to, byte_count, end_to);  // offset after last copied element
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1828
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1829
    // for short arrays, just do single element copy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1830
    __ cmp(count, 11); // 8 + 3  (22 bytes)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1831
    __ brx(Assembler::less, false, Assembler::pn, L_copy_2_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1832
    __ delayed()->add(from, byte_count, end_from);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1833
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1834
    {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1835
      // Align end of arrays since they could be not aligned even
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1836
      // when arrays itself are aligned.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1837
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1838
      // copy 1 element if necessary to align 'end_to' on an 4 bytes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1839
      __ andcc(end_to, 3, G0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1840
      __ br(Assembler::zero, false, Assembler::pt, L_skip_alignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1841
      __ delayed()->lduh(end_from, -2, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1842
      __ dec(end_from, 2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1843
      __ dec(end_to, 2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1844
      __ dec(count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1845
      __ sth(O3, end_to, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1846
    __ BIND(L_skip_alignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1847
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1848
      // copy 2 elements to align 'end_to' on an 8 byte boundary
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1849
      __ andcc(end_to, 7, G0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1850
      __ br(Assembler::zero, false, Assembler::pn, L_skip_alignment2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1851
      __ delayed()->lduh(end_from, -2, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1852
      __ dec(count, 2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1853
      __ lduh(end_from, -4, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1854
      __ dec(end_from, 4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1855
      __ dec(end_to, 4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1856
      __ sth(O3, end_to, 2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1857
      __ sth(O4, end_to, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1858
    __ BIND(L_skip_alignment2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1859
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1860
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1861
    if (aligned) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1862
      // Both arrays are aligned to 8-bytes in 64-bits VM.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1863
      // The 'count' is decremented in copy_16_bytes_backward_with_shift()
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1864
      // in unaligned case.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1865
      __ dec(count, 8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1866
    } else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1867
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1868
    {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1869
      // Copy with shift 16 bytes per iteration if arrays do not have
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1870
      // the same alignment mod 8, otherwise jump to the next
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1871
      // code for aligned copy (and substracting 8 from 'count' before jump).
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1872
      // The compare above (count >= 11) guarantes 'count' >= 16 bytes.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1873
      // Also jump over aligned copy after the copy with shift completed.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1874
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1875
      copy_16_bytes_backward_with_shift(end_from, end_to, count, 8,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1876
                                        L_aligned_copy, L_copy_2_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1877
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1878
    // copy 4 elements (16 bytes) at a time
5249
5cac34e6fe54 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 5248
diff changeset
  1879
      __ align(OptoLoopAlignment);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1880
    __ BIND(L_aligned_copy);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1881
      __ dec(end_from, 16);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1882
      __ ldx(end_from, 8, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1883
      __ ldx(end_from, 0, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1884
      __ dec(end_to, 16);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1885
      __ deccc(count, 8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1886
      __ stx(O3, end_to, 8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1887
      __ brx(Assembler::greaterEqual, false, Assembler::pt, L_aligned_copy);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1888
      __ delayed()->stx(O4, end_to, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1889
      __ inc(count, 8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1890
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1891
    // copy 1 element (2 bytes) at a time
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1892
    __ BIND(L_copy_2_bytes);
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10004
diff changeset
  1893
      __ cmp_and_br_short(count, 0, Assembler::equal, Assembler::pt, L_exit);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1894
    __ BIND(L_copy_2_bytes_loop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1895
      __ dec(end_from, 2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1896
      __ dec(end_to, 2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1897
      __ lduh(end_from, 0, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1898
      __ deccc(count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1899
      __ brx(Assembler::greater, false, Assembler::pt, L_copy_2_bytes_loop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1900
      __ delayed()->sth(O4, end_to, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1901
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1902
    __ BIND(L_exit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1903
    // O3, O4 are used as temp registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1904
    inc_counter_np(SharedRuntime::_jshort_array_copy_ctr, O3, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1905
    __ retl();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1906
    __ delayed()->mov(G0, O0); // return 0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1907
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1908
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1909
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1910
  //
10512
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1911
  // Helper methods for generate_disjoint_int_copy_core()
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1912
  //
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1913
  void copy_16_bytes_loop(Register from, Register to, Register count, int count_dec,
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1914
                          Label& L_loop, bool use_prefetch, bool use_bis) {
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1915
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1916
    __ align(OptoLoopAlignment);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1917
    __ BIND(L_loop);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1918
    if (use_prefetch) {
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1919
      if (ArraycopySrcPrefetchDistance > 0) {
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1920
        __ prefetch(from, ArraycopySrcPrefetchDistance, Assembler::severalReads);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1921
      }
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1922
      if (ArraycopyDstPrefetchDistance > 0) {
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1923
        __ prefetch(to, ArraycopyDstPrefetchDistance, Assembler::severalWritesAndPossiblyReads);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1924
      }
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1925
    }
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1926
    __ ldx(from, 4, O4);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1927
    __ ldx(from, 12, G4);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1928
    __ inc(to, 16);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1929
    __ inc(from, 16);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1930
    __ deccc(count, 4); // Can we do next iteration after this one?
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1931
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1932
    __ srlx(O4, 32, G3);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1933
    __ bset(G3, O3);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1934
    __ sllx(O4, 32, O4);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1935
    __ srlx(G4, 32, G3);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1936
    __ bset(G3, O4);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1937
    if (use_bis) {
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1938
      __ stxa(O3, to, -16);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1939
      __ stxa(O4, to, -8);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1940
    } else {
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1941
      __ stx(O3, to, -16);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1942
      __ stx(O4, to, -8);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1943
    }
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1944
    __ brx(Assembler::greaterEqual, false, Assembler::pt, L_loop);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1945
    __ delayed()->sllx(G4, 32,  O3);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1946
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1947
  }
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1948
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1949
  //
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1950
  //  Generate core code for disjoint int copy (and oop copy on 32-bit).
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1951
  //  If "aligned" is true, the "from" and "to" addresses are assumed
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1952
  //  to be heapword aligned.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1953
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1954
  // Arguments:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1955
  //      from:  O0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1956
  //      to:    O1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1957
  //      count: O2 treated as signed
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1958
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1959
  void generate_disjoint_int_copy_core(bool aligned) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1960
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1961
    Label L_skip_alignment, L_aligned_copy;
10512
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  1962
    Label L_copy_4_bytes, L_copy_4_bytes_loop, L_exit;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1963
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1964
    const Register from      = O0;   // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1965
    const Register to        = O1;   // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1966
    const Register count     = O2;   // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1967
    const Register offset    = O5;   // offset from start of arrays
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1968
    // O3, O4, G3, G4 are used as temp registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1969
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1970
    // 'aligned' == true when it is known statically during compilation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1971
    // of this arraycopy call site that both 'from' and 'to' addresses
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1972
    // are HeapWordSize aligned (see LibraryCallKit::basictype2arraycopy()).
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1973
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1974
    // Aligned arrays have 4 bytes alignment in 32-bits VM
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1975
    // and 8 bytes - in 64-bits VM.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1976
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1977
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1978
    if (!aligned)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1979
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1980
    {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1981
      // The next check could be put under 'ifndef' since the code in
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1982
      // generate_disjoint_long_copy_core() has own checks and set 'offset'.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1983
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1984
      // for short arrays, just do single element copy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1985
      __ cmp(count, 5); // 4 + 1 (20 bytes)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1986
      __ brx(Assembler::lessEqual, false, Assembler::pn, L_copy_4_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1987
      __ delayed()->mov(G0, offset);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1988
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1989
      // copy 1 element to align 'to' on an 8 byte boundary
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1990
      __ andcc(to, 7, G0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1991
      __ br(Assembler::zero, false, Assembler::pt, L_skip_alignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1992
      __ delayed()->ld(from, 0, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1993
      __ inc(from, 4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1994
      __ inc(to, 4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1995
      __ dec(count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1996
      __ st(O3, to, -4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1997
    __ BIND(L_skip_alignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1998
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1999
    // if arrays have same alignment mod 8, do 4 elements copy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2000
      __ andcc(from, 7, G0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2001
      __ br(Assembler::zero, false, Assembler::pt, L_aligned_copy);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2002
      __ delayed()->ld(from, 0, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2003
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2004
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2005
    // Load 2 aligned 8-bytes chunks and use one from previous iteration
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2006
    // to form 2 aligned 8-bytes chunks to store.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2007
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2008
    // copy_16_bytes_forward_with_shift() is not used here since this
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2009
    // code is more optimal.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2010
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2011
    // copy with shift 4 elements (16 bytes) at a time
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2012
      __ dec(count, 4);   // The cmp at the beginning guaranty count >= 4
10512
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2013
      __ sllx(O3, 32,  O3);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2014
24326
d3fdd5c16fe0 8022070: Compilation error in stubGenerator_sparc.cpp with some compilers
mikael
parents: 22505
diff changeset
  2015
      disjoint_copy_core(from, to, count, 2, 16, &StubGenerator::copy_16_bytes_loop);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2016
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2017
      __ br(Assembler::always, false, Assembler::pt, L_copy_4_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2018
      __ delayed()->inc(count, 4); // restore 'count'
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2019
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2020
    __ BIND(L_aligned_copy);
10512
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2021
    } // !aligned
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2022
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2023
    // copy 4 elements (16 bytes) at a time
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2024
      __ and3(count, 1, G4); // Save
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2025
      __ srl(count, 1, count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2026
     generate_disjoint_long_copy_core(aligned);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2027
      __ mov(G4, count);     // Restore
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2028
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2029
    // copy 1 element at a time
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2030
    __ BIND(L_copy_4_bytes);
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10004
diff changeset
  2031
      __ cmp_and_br_short(count, 0, Assembler::equal, Assembler::pt, L_exit);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2032
    __ BIND(L_copy_4_bytes_loop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2033
      __ ld(from, offset, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2034
      __ deccc(count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2035
      __ st(O3, to, offset);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2036
      __ brx(Assembler::notZero, false, Assembler::pt, L_copy_4_bytes_loop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2037
      __ delayed()->inc(offset, 4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2038
    __ BIND(L_exit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2039
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2040
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2041
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2042
  //  Generate stub for disjoint int copy.  If "aligned" is true, the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2043
  //  "from" and "to" addresses are assumed to be heapword aligned.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2044
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2045
  // Arguments for generated stub:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2046
  //      from:  O0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2047
  //      to:    O1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2048
  //      count: O2 treated as signed
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2049
  //
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2050
  address generate_disjoint_int_copy(bool aligned, address *entry, const char *name) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2051
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2052
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2053
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2054
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2055
    const Register count = O2;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2056
    assert_clean_int(count, O3);     // Make sure 'count' is clean int.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2057
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2058
    if (entry != NULL) {
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2059
      *entry = __ pc();
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2060
      // caller can pass a 64-bit byte count here (from Unsafe.copyMemory)
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2061
      BLOCK_COMMENT("Entry:");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2062
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2063
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2064
    generate_disjoint_int_copy_core(aligned);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2065
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2066
    // O3, O4 are used as temp registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2067
    inc_counter_np(SharedRuntime::_jint_array_copy_ctr, O3, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2068
    __ retl();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2069
    __ delayed()->mov(G0, O0); // return 0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2070
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2071
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2072
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2073
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2074
  //  Generate core code for conjoint int copy (and oop copy on 32-bit).
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2075
  //  If "aligned" is true, the "from" and "to" addresses are assumed
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2076
  //  to be heapword aligned.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2077
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2078
  // Arguments:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2079
  //      from:  O0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2080
  //      to:    O1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2081
  //      count: O2 treated as signed
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2082
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2083
  void generate_conjoint_int_copy_core(bool aligned) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2084
    // Do reverse copy.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2085
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2086
    Label L_skip_alignment, L_aligned_copy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2087
    Label L_copy_16_bytes,  L_copy_4_bytes, L_copy_4_bytes_loop, L_exit;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2088
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2089
    const Register from      = O0;   // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2090
    const Register to        = O1;   // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2091
    const Register count     = O2;   // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2092
    const Register end_from  = from; // source array end address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2093
    const Register end_to    = to;   // destination array end address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2094
    // O3, O4, O5, G3 are used as temp registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2095
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2096
    const Register byte_count = O3;  // bytes count to copy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2097
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2098
      __ sllx(count, LogBytesPerInt, byte_count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2099
      __ add(to, byte_count, end_to); // offset after last copied element
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2100
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2101
      __ cmp(count, 5); // for short arrays, just do single element copy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2102
      __ brx(Assembler::lessEqual, false, Assembler::pn, L_copy_4_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2103
      __ delayed()->add(from, byte_count, end_from);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2104
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2105
    // copy 1 element to align 'to' on an 8 byte boundary
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2106
      __ andcc(end_to, 7, G0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2107
      __ br(Assembler::zero, false, Assembler::pt, L_skip_alignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2108
      __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2109
      __ dec(count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2110
      __ dec(end_from, 4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2111
      __ dec(end_to,   4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2112
      __ ld(end_from, 0, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2113
      __ st(O4, end_to, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2114
    __ BIND(L_skip_alignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2115
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2116
    // Check if 'end_from' and 'end_to' has the same alignment.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2117
      __ andcc(end_from, 7, G0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2118
      __ br(Assembler::zero, false, Assembler::pt, L_aligned_copy);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2119
      __ delayed()->dec(count, 4); // The cmp at the start guaranty cnt >= 4
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2120
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2121
    // copy with shift 4 elements (16 bytes) at a time
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2122
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2123
    // Load 2 aligned 8-bytes chunks and use one from previous iteration
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2124
    // to form 2 aligned 8-bytes chunks to store.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2125
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2126
      __ ldx(end_from, -4, O3);
5249
5cac34e6fe54 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 5248
diff changeset
  2127
      __ align(OptoLoopAlignment);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2128
    __ BIND(L_copy_16_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2129
      __ ldx(end_from, -12, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2130
      __ deccc(count, 4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2131
      __ ldx(end_from, -20, O5);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2132
      __ dec(end_to, 16);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2133
      __ dec(end_from, 16);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2134
      __ srlx(O3, 32, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2135
      __ sllx(O4, 32, G3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2136
      __ bset(G3, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2137
      __ stx(O3, end_to, 8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2138
      __ srlx(O4, 32, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2139
      __ sllx(O5, 32, G3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2140
      __ bset(O4, G3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2141
      __ stx(G3, end_to, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2142
      __ brx(Assembler::greaterEqual, false, Assembler::pt, L_copy_16_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2143
      __ delayed()->mov(O5, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2144
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2145
      __ br(Assembler::always, false, Assembler::pt, L_copy_4_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2146
      __ delayed()->inc(count, 4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2147
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2148
    // copy 4 elements (16 bytes) at a time
5249
5cac34e6fe54 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 5248
diff changeset
  2149
      __ align(OptoLoopAlignment);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2150
    __ BIND(L_aligned_copy);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2151
      __ dec(end_from, 16);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2152
      __ ldx(end_from, 8, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2153
      __ ldx(end_from, 0, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2154
      __ dec(end_to, 16);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2155
      __ deccc(count, 4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2156
      __ stx(O3, end_to, 8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2157
      __ brx(Assembler::greaterEqual, false, Assembler::pt, L_aligned_copy);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2158
      __ delayed()->stx(O4, end_to, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2159
      __ inc(count, 4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2160
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2161
    // copy 1 element (4 bytes) at a time
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2162
    __ BIND(L_copy_4_bytes);
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10004
diff changeset
  2163
      __ cmp_and_br_short(count, 0, Assembler::equal, Assembler::pt, L_exit);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2164
    __ BIND(L_copy_4_bytes_loop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2165
      __ dec(end_from, 4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2166
      __ dec(end_to, 4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2167
      __ ld(end_from, 0, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2168
      __ deccc(count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2169
      __ brx(Assembler::greater, false, Assembler::pt, L_copy_4_bytes_loop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2170
      __ delayed()->st(O4, end_to, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2171
    __ BIND(L_exit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2172
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2173
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2174
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2175
  //  Generate stub for conjoint int copy.  If "aligned" is true, the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2176
  //  "from" and "to" addresses are assumed to be heapword aligned.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2177
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2178
  // Arguments for generated stub:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2179
  //      from:  O0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2180
  //      to:    O1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2181
  //      count: O2 treated as signed
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2182
  //
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2183
  address generate_conjoint_int_copy(bool aligned, address nooverlap_target,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2184
                                     address *entry, const char *name) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2185
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2186
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2187
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2188
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2189
    assert_clean_int(O2, O3);     // Make sure 'count' is clean int.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2190
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2191
    if (entry != NULL) {
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2192
      *entry = __ pc();
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2193
      // caller can pass a 64-bit byte count here (from Unsafe.copyMemory)
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2194
      BLOCK_COMMENT("Entry:");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2195
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2196
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2197
    array_overlap_test(nooverlap_target, 2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2198
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2199
    generate_conjoint_int_copy_core(aligned);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2200
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2201
    // O3, O4 are used as temp registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2202
    inc_counter_np(SharedRuntime::_jint_array_copy_ctr, O3, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2203
    __ retl();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2204
    __ delayed()->mov(G0, O0); // return 0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2205
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2206
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2207
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2208
  //
10512
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2209
  // Helper methods for generate_disjoint_long_copy_core()
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2210
  //
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2211
  void copy_64_bytes_loop(Register from, Register to, Register count, int count_dec,
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2212
                          Label& L_loop, bool use_prefetch, bool use_bis) {
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2213
    __ align(OptoLoopAlignment);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2214
    __ BIND(L_loop);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2215
    for (int off = 0; off < 64; off += 16) {
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2216
      if (use_prefetch && (off & 31) == 0) {
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2217
        if (ArraycopySrcPrefetchDistance > 0) {
10566
630c177ec580 7081933: Use zeroing elimination optimization for large array
kvn
parents: 10545
diff changeset
  2218
          __ prefetch(from, ArraycopySrcPrefetchDistance+off, Assembler::severalReads);
10512
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2219
        }
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2220
        if (ArraycopyDstPrefetchDistance > 0) {
10566
630c177ec580 7081933: Use zeroing elimination optimization for large array
kvn
parents: 10545
diff changeset
  2221
          __ prefetch(to, ArraycopyDstPrefetchDistance+off, Assembler::severalWritesAndPossiblyReads);
10512
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2222
        }
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2223
      }
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2224
      __ ldx(from,  off+0, O4);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2225
      __ ldx(from,  off+8, O5);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2226
      if (use_bis) {
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2227
        __ stxa(O4, to,  off+0);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2228
        __ stxa(O5, to,  off+8);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2229
      } else {
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2230
        __ stx(O4, to,  off+0);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2231
        __ stx(O5, to,  off+8);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2232
      }
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2233
    }
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2234
    __ deccc(count, 8);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2235
    __ inc(from, 64);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2236
    __ brx(Assembler::greaterEqual, false, Assembler::pt, L_loop);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2237
    __ delayed()->inc(to, 64);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2238
  }
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2239
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2240
  //
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2241
  //  Generate core code for disjoint long copy (and oop copy on 64-bit).
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2242
  //  "aligned" is ignored, because we must make the stronger
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2243
  //  assumption that both addresses are always 64-bit aligned.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2244
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2245
  // Arguments:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2246
  //      from:  O0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2247
  //      to:    O1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2248
  //      count: O2 treated as signed
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2249
  //
5248
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2250
  // count -= 2;
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2251
  // if ( count >= 0 ) { // >= 2 elements
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2252
  //   if ( count > 6) { // >= 8 elements
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2253
  //     count -= 6; // original count - 8
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2254
  //     do {
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2255
  //       copy_8_elements;
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2256
  //       count -= 8;
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2257
  //     } while ( count >= 0 );
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2258
  //     count += 6;
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2259
  //   }
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2260
  //   if ( count >= 0 ) { // >= 2 elements
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2261
  //     do {
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2262
  //       copy_2_elements;
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2263
  //     } while ( (count=count-2) >= 0 );
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2264
  //   }
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2265
  // }
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2266
  // count += 2;
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2267
  // if ( count != 0 ) { // 1 element left
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2268
  //   copy_1_element;
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2269
  // }
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2270
  //
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2271
  void generate_disjoint_long_copy_core(bool aligned) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2272
    Label L_copy_8_bytes, L_copy_16_bytes, L_exit;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2273
    const Register from    = O0;  // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2274
    const Register to      = O1;  // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2275
    const Register count   = O2;  // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2276
    const Register offset0 = O4;  // element offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2277
    const Register offset8 = O5;  // next element offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2278
10512
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2279
    __ deccc(count, 2);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2280
    __ mov(G0, offset0);   // offset from start of arrays (0)
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2281
    __ brx(Assembler::negative, false, Assembler::pn, L_copy_8_bytes );
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2282
    __ delayed()->add(offset0, 8, offset8);
5248
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2283
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2284
    // Copy by 64 bytes chunks
10512
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2285
5248
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2286
    const Register from64 = O3;  // source address
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2287
    const Register to64   = G3;  // destination address
10512
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2288
    __ subcc(count, 6, O3);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2289
    __ brx(Assembler::negative, false, Assembler::pt, L_copy_16_bytes );
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2290
    __ delayed()->mov(to,   to64);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2291
    // Now we can use O4(offset0), O5(offset8) as temps
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2292
    __ mov(O3, count);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2293
    // count >= 0 (original count - 8)
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2294
    __ mov(from, from64);
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2295
24326
d3fdd5c16fe0 8022070: Compilation error in stubGenerator_sparc.cpp with some compilers
mikael
parents: 22505
diff changeset
  2296
    disjoint_copy_core(from64, to64, count, 3, 64, &StubGenerator::copy_64_bytes_loop);
5248
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2297
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2298
      // Restore O4(offset0), O5(offset8)
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2299
      __ sub(from64, from, offset0);
10512
935fc9d89f08 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 10501
diff changeset
  2300
      __ inccc(count, 6); // restore count
5248
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2301
      __ brx(Assembler::negative, false, Assembler::pn, L_copy_8_bytes );
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2302
      __ delayed()->add(offset0, 8, offset8);
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2303
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2304
      // Copy by 16 bytes chunks
5249
5cac34e6fe54 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 5248
diff changeset
  2305
      __ align(OptoLoopAlignment);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2306
    __ BIND(L_copy_16_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2307
      __ ldx(from, offset0, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2308
      __ ldx(from, offset8, G3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2309
      __ deccc(count, 2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2310
      __ stx(O3, to, offset0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2311
      __ inc(offset0, 16);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2312
      __ stx(G3, to, offset8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2313
      __ brx(Assembler::greaterEqual, false, Assembler::pt, L_copy_16_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2314
      __ delayed()->inc(offset8, 16);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2315
5248
5eddf88cc3c9 6940677: Use 64 bytes chunk copy for arraycopy on Sparc
kvn
parents: 5046
diff changeset
  2316
      // Copy last 8 bytes
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2317
    __ BIND(L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2318
      __ inccc(count, 2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2319
      __ brx(Assembler::zero, true, Assembler::pn, L_exit );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2320
      __ delayed()->mov(offset0, offset8); // Set O5 used by other stubs
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2321
      __ ldx(from, offset0, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2322
      __ stx(O3, to, offset0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2323
    __ BIND(L_exit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2324
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2325
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2326
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2327
  //  Generate stub for disjoint long copy.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2328
  //  "aligned" is ignored, because we must make the stronger
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2329
  //  assumption that both addresses are always 64-bit aligned.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2330
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2331
  // Arguments for generated stub:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2332
  //      from:  O0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2333
  //      to:    O1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2334
  //      count: O2 treated as signed
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2335
  //
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2336
  address generate_disjoint_long_copy(bool aligned, address *entry, const char *name) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2337
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2338
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2339
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2340
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2341
    assert_clean_int(O2, O3);     // Make sure 'count' is clean int.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2342
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2343
    if (entry != NULL) {
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2344
      *entry = __ pc();
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2345
      // caller can pass a 64-bit byte count here (from Unsafe.copyMemory)
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2346
      BLOCK_COMMENT("Entry:");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2347
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2348
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2349
    generate_disjoint_long_copy_core(aligned);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2350
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2351
    // O3, O4 are used as temp registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2352
    inc_counter_np(SharedRuntime::_jlong_array_copy_ctr, O3, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2353
    __ retl();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2354
    __ delayed()->mov(G0, O0); // return 0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2355
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2356
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2357
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2358
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2359
  //  Generate core code for conjoint long copy (and oop copy on 64-bit).
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2360
  //  "aligned" is ignored, because we must make the stronger
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2361
  //  assumption that both addresses are always 64-bit aligned.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2362
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2363
  // Arguments:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2364
  //      from:  O0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2365
  //      to:    O1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2366
  //      count: O2 treated as signed
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2367
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2368
  void generate_conjoint_long_copy_core(bool aligned) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2369
    // Do reverse copy.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2370
    Label L_copy_8_bytes, L_copy_16_bytes, L_exit;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2371
    const Register from    = O0;  // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2372
    const Register to      = O1;  // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2373
    const Register count   = O2;  // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2374
    const Register offset8 = O4;  // element offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2375
    const Register offset0 = O5;  // previous element offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2376
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2377
      __ subcc(count, 1, count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2378
      __ brx(Assembler::lessEqual, false, Assembler::pn, L_copy_8_bytes );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2379
      __ delayed()->sllx(count, LogBytesPerLong, offset8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2380
      __ sub(offset8, 8, offset0);
5249
5cac34e6fe54 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 5248
diff changeset
  2381
      __ align(OptoLoopAlignment);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2382
    __ BIND(L_copy_16_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2383
      __ ldx(from, offset8, O2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2384
      __ ldx(from, offset0, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2385
      __ stx(O2, to, offset8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2386
      __ deccc(offset8, 16);      // use offset8 as counter
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2387
      __ stx(O3, to, offset0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2388
      __ brx(Assembler::greater, false, Assembler::pt, L_copy_16_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2389
      __ delayed()->dec(offset0, 16);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2390
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2391
    __ BIND(L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2392
      __ brx(Assembler::negative, false, Assembler::pn, L_exit );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2393
      __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2394
      __ ldx(from, 0, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2395
      __ stx(O3, to, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2396
    __ BIND(L_exit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2397
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2398
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2399
  //  Generate stub for conjoint long copy.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2400
  //  "aligned" is ignored, because we must make the stronger
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2401
  //  assumption that both addresses are always 64-bit aligned.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2402
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2403
  // Arguments for generated stub:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2404
  //      from:  O0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2405
  //      to:    O1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2406
  //      count: O2 treated as signed
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2407
  //
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2408
  address generate_conjoint_long_copy(bool aligned, address nooverlap_target,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2409
                                      address *entry, const char *name) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2410
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2411
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2412
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2413
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2414
    assert(aligned, "Should always be aligned");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2415
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2416
    assert_clean_int(O2, O3);     // Make sure 'count' is clean int.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2417
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2418
    if (entry != NULL) {
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2419
      *entry = __ pc();
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2420
      // caller can pass a 64-bit byte count here (from Unsafe.copyMemory)
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2421
      BLOCK_COMMENT("Entry:");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2422
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2423
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2424
    array_overlap_test(nooverlap_target, 3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2425
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2426
    generate_conjoint_long_copy_core(aligned);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2427
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2428
    // O3, O4 are used as temp registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2429
    inc_counter_np(SharedRuntime::_jlong_array_copy_ctr, O3, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2430
    __ retl();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2431
    __ delayed()->mov(G0, O0); // return 0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2432
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2433
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2434
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2435
  //  Generate stub for disjoint oop copy.  If "aligned" is true, the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2436
  //  "from" and "to" addresses are assumed to be heapword aligned.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2437
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2438
  // Arguments for generated stub:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2439
  //      from:  O0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2440
  //      to:    O1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2441
  //      count: O2 treated as signed
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2442
  //
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2443
  address generate_disjoint_oop_copy(bool aligned, address *entry, const char *name,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2444
                                     bool dest_uninitialized = false) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2445
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2446
    const Register from  = O0;  // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2447
    const Register to    = O1;  // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2448
    const Register count = O2;  // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2449
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2450
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2451
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2452
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2453
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2454
    assert_clean_int(count, O3);     // Make sure 'count' is clean int.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2455
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2456
    if (entry != NULL) {
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2457
      *entry = __ pc();
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2458
      // caller can pass a 64-bit byte count here
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2459
      BLOCK_COMMENT("Entry:");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2460
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2461
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2462
    // save arguments for barrier generation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2463
    __ mov(to, G1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2464
    __ mov(count, G5);
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2465
    gen_write_ref_array_pre_barrier(G1, G5, dest_uninitialized);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2466
  #ifdef _LP64
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2467
    assert_clean_int(count, O3);     // Make sure 'count' is clean int.
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2468
    if (UseCompressedOops) {
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2469
      generate_disjoint_int_copy_core(aligned);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2470
    } else {
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2471
      generate_disjoint_long_copy_core(aligned);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2472
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2473
  #else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2474
    generate_disjoint_int_copy_core(aligned);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2475
  #endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2476
    // O0 is used as temp register
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2477
    gen_write_ref_array_post_barrier(G1, G5, O0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2478
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2479
    // O3, O4 are used as temp registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2480
    inc_counter_np(SharedRuntime::_oop_array_copy_ctr, O3, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2481
    __ retl();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2482
    __ delayed()->mov(G0, O0); // return 0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2483
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2484
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2485
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2486
  //  Generate stub for conjoint oop copy.  If "aligned" is true, the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2487
  //  "from" and "to" addresses are assumed to be heapword aligned.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2488
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2489
  // Arguments for generated stub:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2490
  //      from:  O0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2491
  //      to:    O1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2492
  //      count: O2 treated as signed
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2493
  //
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2494
  address generate_conjoint_oop_copy(bool aligned, address nooverlap_target,
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2495
                                     address *entry, const char *name,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2496
                                     bool dest_uninitialized = false) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2497
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2498
    const Register from  = O0;  // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2499
    const Register to    = O1;  // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2500
    const Register count = O2;  // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2501
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2502
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2503
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2504
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2505
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2506
    assert_clean_int(count, O3);     // Make sure 'count' is clean int.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2507
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2508
    if (entry != NULL) {
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2509
      *entry = __ pc();
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2510
      // caller can pass a 64-bit byte count here
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2511
      BLOCK_COMMENT("Entry:");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2512
    }
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2513
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2514
    array_overlap_test(nooverlap_target, LogBytesPerHeapOop);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2515
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2516
    // save arguments for barrier generation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2517
    __ mov(to, G1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2518
    __ mov(count, G5);
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2519
    gen_write_ref_array_pre_barrier(G1, G5, dest_uninitialized);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2520
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2521
  #ifdef _LP64
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2522
    if (UseCompressedOops) {
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2523
      generate_conjoint_int_copy_core(aligned);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2524
    } else {
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2525
      generate_conjoint_long_copy_core(aligned);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2526
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2527
  #else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2528
    generate_conjoint_int_copy_core(aligned);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2529
  #endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2530
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2531
    // O0 is used as temp register
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2532
    gen_write_ref_array_post_barrier(G1, G5, O0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2533
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2534
    // O3, O4 are used as temp registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2535
    inc_counter_np(SharedRuntime::_oop_array_copy_ctr, O3, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2536
    __ retl();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2537
    __ delayed()->mov(G0, O0); // return 0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2538
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2539
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2540
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2541
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2542
  // Helper for generating a dynamic type check.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2543
  // Smashes only the given temp registers.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2544
  void generate_type_check(Register sub_klass,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2545
                           Register super_check_offset,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2546
                           Register super_klass,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2547
                           Register temp,
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
  2548
                           Label& L_success) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2549
    assert_different_registers(sub_klass, super_check_offset, super_klass, temp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2550
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2551
    BLOCK_COMMENT("type_check:");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2552
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
  2553
    Label L_miss, L_pop_to_miss;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2554
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2555
    assert_clean_int(super_check_offset, temp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2556
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
  2557
    __ check_klass_subtype_fast_path(sub_klass, super_klass, temp, noreg,
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
  2558
                                     &L_success, &L_miss, NULL,
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
  2559
                                     super_check_offset);
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
  2560
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
  2561
    BLOCK_COMMENT("type_check_slow_path:");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2562
    __ save_frame(0);
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
  2563
    __ check_klass_subtype_slow_path(sub_klass->after_save(),
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
  2564
                                     super_klass->after_save(),
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
  2565
                                     L0, L1, L2, L4,
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
  2566
                                     NULL, &L_pop_to_miss);
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10004
diff changeset
  2567
    __ ba(L_success);
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
  2568
    __ delayed()->restore();
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
  2569
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
  2570
    __ bind(L_pop_to_miss);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2571
    __ restore();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2572
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2573
    // Fall through on failure!
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2574
    __ BIND(L_miss);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2575
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2576
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2577
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2578
  //  Generate stub for checked oop copy.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2579
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2580
  // Arguments for generated stub:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2581
  //      from:  O0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2582
  //      to:    O1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2583
  //      count: O2 treated as signed
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2584
  //      ckoff: O3 (super_check_offset)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2585
  //      ckval: O4 (super_klass)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2586
  //      ret:   O0 zero for success; (-1^K) where K is partial transfer count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2587
  //
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2588
  address generate_checkcast_copy(const char *name, address *entry, bool dest_uninitialized = false) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2589
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2590
    const Register O0_from   = O0;      // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2591
    const Register O1_to     = O1;      // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2592
    const Register O2_count  = O2;      // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2593
    const Register O3_ckoff  = O3;      // super_check_offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2594
    const Register O4_ckval  = O4;      // super_klass
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2595
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2596
    const Register O5_offset = O5;      // loop var, with stride wordSize
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2597
    const Register G1_remain = G1;      // loop var, with stride -1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2598
    const Register G3_oop    = G3;      // actual oop copied
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2599
    const Register G4_klass  = G4;      // oop._klass
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2600
    const Register G5_super  = G5;      // oop._klass._primary_supers[ckval]
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2601
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2602
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2603
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2604
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2605
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2606
#ifdef ASSERT
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
  2607
    // We sometimes save a frame (see generate_type_check below).
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2608
    // If this will cause trouble, let's fail now instead of later.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2609
    __ save_frame(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2610
    __ restore();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2611
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2612
6770
a67870aaedb3 6980792: Crash "exception happened outside interpreter, nmethods and vtable stubs (1)"
never
parents: 6464
diff changeset
  2613
    assert_clean_int(O2_count, G1);     // Make sure 'count' is clean int.
a67870aaedb3 6980792: Crash "exception happened outside interpreter, nmethods and vtable stubs (1)"
never
parents: 6464
diff changeset
  2614
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2615
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2616
    // caller guarantees that the arrays really are different
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2617
    // otherwise, we would have to make conjoint checks
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2618
    { Label L;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2619
      __ mov(O3, G1);           // spill: overlap test smashes O3
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2620
      __ mov(O4, G4);           // spill: overlap test smashes O4
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2621
      array_overlap_test(L, LogBytesPerHeapOop);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2622
      __ stop("checkcast_copy within a single array");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2623
      __ bind(L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2624
      __ mov(G1, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2625
      __ mov(G4, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2626
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2627
#endif //ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2628
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2629
    if (entry != NULL) {
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2630
      *entry = __ pc();
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2631
      // caller can pass a 64-bit byte count here (from generic stub)
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2632
      BLOCK_COMMENT("Entry:");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2633
    }
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2634
    gen_write_ref_array_pre_barrier(O1_to, O2_count, dest_uninitialized);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2635
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2636
    Label load_element, store_element, do_card_marks, fail, done;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2637
    __ addcc(O2_count, 0, G1_remain);   // initialize loop index, and test it
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2638
    __ brx(Assembler::notZero, false, Assembler::pt, load_element);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2639
    __ delayed()->mov(G0, O5_offset);   // offset from start of arrays
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2640
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2641
    // Empty array:  Nothing to do.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2642
    inc_counter_np(SharedRuntime::_checkcast_array_copy_ctr, O3, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2643
    __ retl();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2644
    __ delayed()->set(0, O0);           // return 0 on (trivial) success
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2645
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2646
    // ======== begin loop ========
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2647
    // (Loop is rotated; its entry is load_element.)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2648
    // Loop variables:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2649
    //   (O5 = 0; ; O5 += wordSize) --- offset from src, dest arrays
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2650
    //   (O2 = len; O2 != 0; O2--) --- number of oops *remaining*
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2651
    //   G3, G4, G5 --- current oop, oop.klass, oop.klass.super
5249
5cac34e6fe54 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 5248
diff changeset
  2652
    __ align(OptoLoopAlignment);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2653
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
  2654
    __ BIND(store_element);
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
  2655
    __ deccc(G1_remain);                // decrement the count
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2656
    __ store_heap_oop(G3_oop, O1_to, O5_offset); // store the oop
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2657
    __ inc(O5_offset, heapOopSize);     // step to next offset
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2658
    __ brx(Assembler::zero, true, Assembler::pt, do_card_marks);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2659
    __ delayed()->set(0, O0);           // return -1 on success
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2660
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2661
    // ======== loop entry is here ========
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
  2662
    __ BIND(load_element);
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2663
    __ load_heap_oop(O0_from, O5_offset, G3_oop);  // load the oop
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10004
diff changeset
  2664
    __ br_null_short(G3_oop, Assembler::pt, store_element);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2665
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2666
    __ load_klass(G3_oop, G4_klass); // query the object klass
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2667
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2668
    generate_type_check(G4_klass, O3_ckoff, O4_ckval, G5_super,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2669
                        // branch to this on success:
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
  2670
                        store_element);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2671
    // ======== end loop ========
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2672
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2673
    // It was a real error; we must depend on the caller to finish the job.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2674
    // Register G1 has number of *remaining* oops, O2 number of *total* oops.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2675
    // Emit GC store barriers for the oops we have copied (O2 minus G1),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2676
    // and report their number to the caller.
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
  2677
    __ BIND(fail);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2678
    __ subcc(O2_count, G1_remain, O2_count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2679
    __ brx(Assembler::zero, false, Assembler::pt, done);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2680
    __ delayed()->not1(O2_count, O0);   // report (-1^K) to caller
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2681
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
  2682
    __ BIND(do_card_marks);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2683
    gen_write_ref_array_post_barrier(O1_to, O2_count, O3);   // store check on O1[0..O2]
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2684
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 2254
diff changeset
  2685
    __ BIND(done);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2686
    inc_counter_np(SharedRuntime::_checkcast_array_copy_ctr, O3, O4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2687
    __ retl();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2688
    __ delayed()->nop();             // return value in 00
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2689
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2690
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2691
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2692
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2693
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2694
  //  Generate 'unsafe' array copy stub
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2695
  //  Though just as safe as the other stubs, it takes an unscaled
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2696
  //  size_t argument instead of an element count.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2697
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2698
  // Arguments for generated stub:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2699
  //      from:  O0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2700
  //      to:    O1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2701
  //      count: O2 byte count, treated as ssize_t, can be zero
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2702
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2703
  // Examines the alignment of the operands and dispatches
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2704
  // to a long, int, short, or byte copy loop.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2705
  //
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2706
  address generate_unsafe_copy(const char* name,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2707
                               address byte_copy_entry,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2708
                               address short_copy_entry,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2709
                               address int_copy_entry,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2710
                               address long_copy_entry) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2711
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2712
    const Register O0_from   = O0;      // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2713
    const Register O1_to     = O1;      // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2714
    const Register O2_count  = O2;      // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2715
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2716
    const Register G1_bits   = G1;      // test copy of low bits
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2717
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2718
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2719
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2720
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2721
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2722
    // bump this on entry, not on exit:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2723
    inc_counter_np(SharedRuntime::_unsafe_array_copy_ctr, G1, G3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2724
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2725
    __ or3(O0_from, O1_to, G1_bits);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2726
    __ or3(O2_count,       G1_bits, G1_bits);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2727
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2728
    __ btst(BytesPerLong-1, G1_bits);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2729
    __ br(Assembler::zero, true, Assembler::pt,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2730
          long_copy_entry, relocInfo::runtime_call_type);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2731
    // scale the count on the way out:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2732
    __ delayed()->srax(O2_count, LogBytesPerLong, O2_count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2733
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2734
    __ btst(BytesPerInt-1, G1_bits);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2735
    __ br(Assembler::zero, true, Assembler::pt,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2736
          int_copy_entry, relocInfo::runtime_call_type);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2737
    // scale the count on the way out:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2738
    __ delayed()->srax(O2_count, LogBytesPerInt, O2_count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2739
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2740
    __ btst(BytesPerShort-1, G1_bits);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2741
    __ br(Assembler::zero, true, Assembler::pt,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2742
          short_copy_entry, relocInfo::runtime_call_type);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2743
    // scale the count on the way out:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2744
    __ delayed()->srax(O2_count, LogBytesPerShort, O2_count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2745
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2746
    __ br(Assembler::always, false, Assembler::pt,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2747
          byte_copy_entry, relocInfo::runtime_call_type);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2748
    __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2749
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2750
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2751
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2752
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2753
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2754
  // Perform range checks on the proposed arraycopy.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2755
  // Kills the two temps, but nothing else.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2756
  // Also, clean the sign bits of src_pos and dst_pos.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2757
  void arraycopy_range_checks(Register src,     // source array oop (O0)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2758
                              Register src_pos, // source position (O1)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2759
                              Register dst,     // destination array oo (O2)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2760
                              Register dst_pos, // destination position (O3)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2761
                              Register length,  // length of copy (O4)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2762
                              Register temp1, Register temp2,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2763
                              Label& L_failed) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2764
    BLOCK_COMMENT("arraycopy_range_checks:");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2765
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2766
    //  if (src_pos + length > arrayOop(src)->length() ) FAIL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2767
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2768
    const Register array_length = temp1;  // scratch
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2769
    const Register end_pos      = temp2;  // scratch
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2770
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2771
    // Note:  This next instruction may be in the delay slot of a branch:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2772
    __ add(length, src_pos, end_pos);  // src_pos + length
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2773
    __ lduw(src, arrayOopDesc::length_offset_in_bytes(), array_length);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2774
    __ cmp(end_pos, array_length);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2775
    __ br(Assembler::greater, false, Assembler::pn, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2776
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2777
    //  if (dst_pos + length > arrayOop(dst)->length() ) FAIL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2778
    __ delayed()->add(length, dst_pos, end_pos); // dst_pos + length
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2779
    __ lduw(dst, arrayOopDesc::length_offset_in_bytes(), array_length);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2780
    __ cmp(end_pos, array_length);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2781
    __ br(Assembler::greater, false, Assembler::pn, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2782
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2783
    // Have to clean up high 32-bits of 'src_pos' and 'dst_pos'.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2784
    // Move with sign extension can be used since they are positive.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2785
    __ delayed()->signx(src_pos, src_pos);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2786
    __ signx(dst_pos, dst_pos);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2787
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2788
    BLOCK_COMMENT("arraycopy_range_checks done");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2789
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2790
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2791
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2792
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2793
  //  Generate generic array copy stubs
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2794
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2795
  //  Input:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2796
  //    O0    -  src oop
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2797
  //    O1    -  src_pos
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2798
  //    O2    -  dst oop
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2799
  //    O3    -  dst_pos
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2800
  //    O4    -  element count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2801
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2802
  //  Output:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2803
  //    O0 ==  0  -  success
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2804
  //    O0 == -1  -  need to call System.arraycopy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2805
  //
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2806
  address generate_generic_copy(const char *name,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2807
                                address entry_jbyte_arraycopy,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2808
                                address entry_jshort_arraycopy,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2809
                                address entry_jint_arraycopy,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2810
                                address entry_oop_arraycopy,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2811
                                address entry_jlong_arraycopy,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2812
                                address entry_checkcast_arraycopy) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2813
    Label L_failed, L_objArray;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2814
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2815
    // Input registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2816
    const Register src      = O0;  // source array oop
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2817
    const Register src_pos  = O1;  // source position
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2818
    const Register dst      = O2;  // destination array oop
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2819
    const Register dst_pos  = O3;  // destination position
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2820
    const Register length   = O4;  // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2821
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2822
    // registers used as temp
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2823
    const Register G3_src_klass = G3; // source array klass
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2824
    const Register G4_dst_klass = G4; // destination array klass
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2825
    const Register G5_lh        = G5; // layout handler
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2826
    const Register O5_temp      = O5;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2827
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2828
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2829
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2830
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2831
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2832
    // bump this on entry, not on exit:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2833
    inc_counter_np(SharedRuntime::_generic_array_copy_ctr, G1, G3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2834
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2835
    // In principle, the int arguments could be dirty.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2836
    //assert_clean_int(src_pos, G1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2837
    //assert_clean_int(dst_pos, G1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2838
    //assert_clean_int(length, G1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2839
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2840
    //-----------------------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2841
    // Assembler stubs will be used for this call to arraycopy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2842
    // if the following conditions are met:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2843
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2844
    // (1) src and dst must not be null.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2845
    // (2) src_pos must not be negative.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2846
    // (3) dst_pos must not be negative.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2847
    // (4) length  must not be negative.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2848
    // (5) src klass and dst klass should be the same and not NULL.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2849
    // (6) src and dst should be arrays.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2850
    // (7) src_pos + length must not exceed length of src.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2851
    // (8) dst_pos + length must not exceed length of dst.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2852
    BLOCK_COMMENT("arraycopy initial argument checks");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2853
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2854
    //  if (src == NULL) return -1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2855
    __ br_null(src, false, Assembler::pn, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2856
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2857
    //  if (src_pos < 0) return -1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2858
    __ delayed()->tst(src_pos);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2859
    __ br(Assembler::negative, false, Assembler::pn, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2860
    __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2861
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2862
    //  if (dst == NULL) return -1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2863
    __ br_null(dst, false, Assembler::pn, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2864
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2865
    //  if (dst_pos < 0) return -1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2866
    __ delayed()->tst(dst_pos);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2867
    __ br(Assembler::negative, false, Assembler::pn, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2868
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2869
    //  if (length < 0) return -1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2870
    __ delayed()->tst(length);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2871
    __ br(Assembler::negative, false, Assembler::pn, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2872
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2873
    BLOCK_COMMENT("arraycopy argument klass checks");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2874
    //  get src->klass()
19979
ebe1dbb6e1aa 8015107: NPG: Use consistent naming for metaspace concepts
ehelin
parents: 18740
diff changeset
  2875
    if (UseCompressedClassPointers) {
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2876
      __ delayed()->nop(); // ??? not good
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2877
      __ load_klass(src, G3_src_klass);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2878
    } else {
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2879
      __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), G3_src_klass);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2880
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2881
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2882
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2883
    //  assert(src->klass() != NULL);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2884
    BLOCK_COMMENT("assert klasses not null");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2885
    { Label L_a, L_b;
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10004
diff changeset
  2886
      __ br_notnull_short(G3_src_klass, Assembler::pt, L_b); // it is broken if klass is NULL
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2887
      __ bind(L_a);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2888
      __ stop("broken null klass");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2889
      __ bind(L_b);
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2890
      __ load_klass(dst, G4_dst_klass);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2891
      __ br_null(G4_dst_klass, false, Assembler::pn, L_a); // this would be broken also
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2892
      __ delayed()->mov(G0, G4_dst_klass);      // scribble the temp
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2893
      BLOCK_COMMENT("assert done");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2894
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2895
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2896
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2897
    // Load layout helper
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2898
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2899
    //  |array_tag|     | header_size | element_type |     |log2_element_size|
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2900
    // 32        30    24            16              8     2                 0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2901
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2902
    //   array_tag: typeArray = 0x3, objArray = 0x2, non-array = 0x0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2903
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2904
11430
718fc06da49a 7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents: 10566
diff changeset
  2905
    int lh_offset = in_bytes(Klass::layout_helper_offset());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2906
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2907
    // Load 32-bits signed value. Use br() instruction with it to check icc.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2908
    __ lduw(G3_src_klass, lh_offset, G5_lh);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2909
19979
ebe1dbb6e1aa 8015107: NPG: Use consistent naming for metaspace concepts
ehelin
parents: 18740
diff changeset
  2910
    if (UseCompressedClassPointers) {
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2911
      __ load_klass(dst, G4_dst_klass);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2912
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2913
    // Handle objArrays completely differently...
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2914
    juint objArray_lh = Klass::array_layout_helper(T_OBJECT);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2915
    __ set(objArray_lh, O5_temp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2916
    __ cmp(G5_lh,       O5_temp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2917
    __ br(Assembler::equal, false, Assembler::pt, L_objArray);
19979
ebe1dbb6e1aa 8015107: NPG: Use consistent naming for metaspace concepts
ehelin
parents: 18740
diff changeset
  2918
    if (UseCompressedClassPointers) {
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2919
      __ delayed()->nop();
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2920
    } else {
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2921
      __ delayed()->ld_ptr(dst, oopDesc::klass_offset_in_bytes(), G4_dst_klass);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2922
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2923
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2924
    //  if (src->klass() != dst->klass()) return -1;
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10004
diff changeset
  2925
    __ cmp_and_brx_short(G3_src_klass, G4_dst_klass, Assembler::notEqual, Assembler::pn, L_failed);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2926
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2927
    //  if (!src->is_Array()) return -1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2928
    __ cmp(G5_lh, Klass::_lh_neutral_value); // < 0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2929
    __ br(Assembler::greaterEqual, false, Assembler::pn, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2930
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2931
    // At this point, it is known to be a typeArray (array_tag 0x3).
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2932
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2933
    __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2934
    { Label L;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2935
      jint lh_prim_tag_in_place = (Klass::_lh_array_tag_type_value << Klass::_lh_array_tag_shift);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2936
      __ set(lh_prim_tag_in_place, O5_temp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2937
      __ cmp(G5_lh,                O5_temp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2938
      __ br(Assembler::greaterEqual, false, Assembler::pt, L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2939
      __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2940
      __ stop("must be a primitive array");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2941
      __ bind(L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2942
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2943
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2944
    __ delayed();                               // match next insn to prev branch
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2945
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2946
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2947
    arraycopy_range_checks(src, src_pos, dst, dst_pos, length,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2948
                           O5_temp, G4_dst_klass, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2949
13952
e3cf184080bc 8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents: 13728
diff changeset
  2950
    // TypeArrayKlass
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2951
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2952
    // src_addr = (src + array_header_in_bytes()) + (src_pos << log2elemsize);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2953
    // dst_addr = (dst + array_header_in_bytes()) + (dst_pos << log2elemsize);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2954
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2955
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2956
    const Register G4_offset = G4_dst_klass;    // array offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2957
    const Register G3_elsize = G3_src_klass;    // log2 element size
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2958
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2959
    __ srl(G5_lh, Klass::_lh_header_size_shift, G4_offset);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2960
    __ and3(G4_offset, Klass::_lh_header_size_mask, G4_offset); // array_offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2961
    __ add(src, G4_offset, src);       // src array offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2962
    __ add(dst, G4_offset, dst);       // dst array offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2963
    __ and3(G5_lh, Klass::_lh_log2_element_size_mask, G3_elsize); // log2 element size
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2964
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2965
    // next registers should be set before the jump to corresponding stub
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2966
    const Register from     = O0;  // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2967
    const Register to       = O1;  // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2968
    const Register count    = O2;  // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2969
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2970
    // 'from', 'to', 'count' registers should be set in this order
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2971
    // since they are the same as 'src', 'src_pos', 'dst'.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2972
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2973
    BLOCK_COMMENT("scale indexes to element size");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2974
    __ sll_ptr(src_pos, G3_elsize, src_pos);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2975
    __ sll_ptr(dst_pos, G3_elsize, dst_pos);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2976
    __ add(src, src_pos, from);       // src_addr
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2977
    __ add(dst, dst_pos, to);         // dst_addr
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2978
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2979
    BLOCK_COMMENT("choose copy loop based on element size");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2980
    __ cmp(G3_elsize, 0);
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2981
    __ br(Assembler::equal, true, Assembler::pt, entry_jbyte_arraycopy);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2982
    __ delayed()->signx(length, count); // length
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2983
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2984
    __ cmp(G3_elsize, LogBytesPerShort);
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2985
    __ br(Assembler::equal, true, Assembler::pt, entry_jshort_arraycopy);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2986
    __ delayed()->signx(length, count); // length
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2987
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2988
    __ cmp(G3_elsize, LogBytesPerInt);
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2989
    __ br(Assembler::equal, true, Assembler::pt, entry_jint_arraycopy);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2990
    __ delayed()->signx(length, count); // length
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2991
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2992
    { Label L;
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10004
diff changeset
  2993
      __ cmp_and_br_short(G3_elsize, LogBytesPerLong, Assembler::equal, Assembler::pt, L);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2994
      __ stop("must be long copy, but elsize is wrong");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2995
      __ bind(L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2996
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2997
#endif
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  2998
    __ br(Assembler::always, false, Assembler::pt, entry_jlong_arraycopy);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2999
    __ delayed()->signx(length, count); // length
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3000
13952
e3cf184080bc 8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents: 13728
diff changeset
  3001
    // ObjArrayKlass
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3002
  __ BIND(L_objArray);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3003
    // live at this point:  G3_src_klass, G4_dst_klass, src[_pos], dst[_pos], length
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3004
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3005
    Label L_plain_copy, L_checkcast_copy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3006
    //  test array classes for subtyping
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3007
    __ cmp(G3_src_klass, G4_dst_klass);         // usual case is exact equality
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3008
    __ brx(Assembler::notEqual, true, Assembler::pn, L_checkcast_copy);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3009
    __ delayed()->lduw(G4_dst_klass, lh_offset, O5_temp); // hoisted from below
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3010
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3011
    // Identically typed arrays can be copied without element-wise checks.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3012
    arraycopy_range_checks(src, src_pos, dst, dst_pos, length,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3013
                           O5_temp, G5_lh, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3014
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3015
    __ add(src, arrayOopDesc::base_offset_in_bytes(T_OBJECT), src); //src offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3016
    __ add(dst, arrayOopDesc::base_offset_in_bytes(T_OBJECT), dst); //dst offset
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  3017
    __ sll_ptr(src_pos, LogBytesPerHeapOop, src_pos);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  3018
    __ sll_ptr(dst_pos, LogBytesPerHeapOop, dst_pos);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3019
    __ add(src, src_pos, from);       // src_addr
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3020
    __ add(dst, dst_pos, to);         // dst_addr
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3021
  __ BIND(L_plain_copy);
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3022
    __ br(Assembler::always, false, Assembler::pt, entry_oop_arraycopy);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3023
    __ delayed()->signx(length, count); // length
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3024
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3025
  __ BIND(L_checkcast_copy);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3026
    // live at this point:  G3_src_klass, G4_dst_klass
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3027
    {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3028
      // Before looking at dst.length, make sure dst is also an objArray.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3029
      // lduw(G4_dst_klass, lh_offset, O5_temp); // hoisted to delay slot
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3030
      __ cmp(G5_lh,                    O5_temp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3031
      __ br(Assembler::notEqual, false, Assembler::pn, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3032
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3033
      // It is safe to examine both src.length and dst.length.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3034
      __ delayed();                             // match next insn to prev branch
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3035
      arraycopy_range_checks(src, src_pos, dst, dst_pos, length,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3036
                             O5_temp, G5_lh, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3037
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3038
      // Marshal the base address arguments now, freeing registers.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3039
      __ add(src, arrayOopDesc::base_offset_in_bytes(T_OBJECT), src); //src offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3040
      __ add(dst, arrayOopDesc::base_offset_in_bytes(T_OBJECT), dst); //dst offset
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  3041
      __ sll_ptr(src_pos, LogBytesPerHeapOop, src_pos);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  3042
      __ sll_ptr(dst_pos, LogBytesPerHeapOop, dst_pos);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3043
      __ add(src, src_pos, from);               // src_addr
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3044
      __ add(dst, dst_pos, to);                 // dst_addr
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3045
      __ signx(length, count);                  // length (reloaded)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3046
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3047
      Register sco_temp = O3;                   // this register is free now
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3048
      assert_different_registers(from, to, count, sco_temp,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3049
                                 G4_dst_klass, G3_src_klass);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3050
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3051
      // Generate the type check.
11430
718fc06da49a 7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents: 10566
diff changeset
  3052
      int sco_offset = in_bytes(Klass::super_check_offset_offset());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3053
      __ lduw(G4_dst_klass, sco_offset, sco_temp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3054
      generate_type_check(G3_src_klass, sco_temp, G4_dst_klass,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3055
                          O5_temp, L_plain_copy);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3056
13952
e3cf184080bc 8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents: 13728
diff changeset
  3057
      // Fetch destination element klass from the ObjArrayKlass header.
e3cf184080bc 8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents: 13728
diff changeset
  3058
      int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3059
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3060
      // the checkcast_copy loop needs two extra arguments:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3061
      __ ld_ptr(G4_dst_klass, ek_offset, O4);   // dest elem klass
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3062
      // lduw(O4, sco_offset, O3);              // sco of elem klass
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3063
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3064
      __ br(Assembler::always, false, Assembler::pt, entry_checkcast_arraycopy);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3065
      __ delayed()->lduw(O4, sco_offset, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3066
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3067
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3068
  __ BIND(L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3069
    __ retl();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3070
    __ delayed()->sub(G0, 1, O0); // return -1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3071
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3072
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3073
10501
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3074
  //
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3075
  //  Generate stub for heap zeroing.
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3076
  //  "to" address is aligned to jlong (8 bytes).
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3077
  //
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3078
  // Arguments for generated stub:
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3079
  //      to:    O0
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3080
  //      count: O1 treated as signed (count of HeapWord)
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3081
  //             count could be 0
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3082
  //
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3083
  address generate_zero_aligned_words(const char* name) {
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3084
    __ align(CodeEntryAlignment);
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3085
    StubCodeMark mark(this, "StubRoutines", name);
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3086
    address start = __ pc();
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3087
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3088
    const Register to    = O0;   // source array address
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3089
    const Register count = O1;   // HeapWords count
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3090
    const Register temp  = O2;   // scratch
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3091
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3092
    Label Ldone;
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3093
    __ sllx(count, LogHeapWordSize, count); // to bytes count
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3094
    // Use BIS for zeroing
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3095
    __ bis_zeroing(to, count, temp, Ldone);
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3096
    __ bind(Ldone);
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3097
    __ retl();
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3098
    __ delayed()->nop();
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3099
    return start;
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3100
}
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3101
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3102
  void generate_arraycopy_stubs() {
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3103
    address entry;
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3104
    address entry_jbyte_arraycopy;
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3105
    address entry_jshort_arraycopy;
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3106
    address entry_jint_arraycopy;
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3107
    address entry_oop_arraycopy;
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3108
    address entry_jlong_arraycopy;
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3109
    address entry_checkcast_arraycopy;
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3110
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3111
    //*** jbyte
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3112
    // Always need aligned and unaligned versions
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3113
    StubRoutines::_jbyte_disjoint_arraycopy         = generate_disjoint_byte_copy(false, &entry,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3114
                                                                                  "jbyte_disjoint_arraycopy");
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3115
    StubRoutines::_jbyte_arraycopy                  = generate_conjoint_byte_copy(false, entry,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3116
                                                                                  &entry_jbyte_arraycopy,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3117
                                                                                  "jbyte_arraycopy");
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3118
    StubRoutines::_arrayof_jbyte_disjoint_arraycopy = generate_disjoint_byte_copy(true, &entry,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3119
                                                                                  "arrayof_jbyte_disjoint_arraycopy");
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3120
    StubRoutines::_arrayof_jbyte_arraycopy          = generate_conjoint_byte_copy(true, entry, NULL,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3121
                                                                                  "arrayof_jbyte_arraycopy");
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3122
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3123
    //*** jshort
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3124
    // Always need aligned and unaligned versions
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3125
    StubRoutines::_jshort_disjoint_arraycopy         = generate_disjoint_short_copy(false, &entry,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3126
                                                                                    "jshort_disjoint_arraycopy");
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3127
    StubRoutines::_jshort_arraycopy                  = generate_conjoint_short_copy(false, entry,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3128
                                                                                    &entry_jshort_arraycopy,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3129
                                                                                    "jshort_arraycopy");
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3130
    StubRoutines::_arrayof_jshort_disjoint_arraycopy = generate_disjoint_short_copy(true, &entry,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3131
                                                                                    "arrayof_jshort_disjoint_arraycopy");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3132
    StubRoutines::_arrayof_jshort_arraycopy          = generate_conjoint_short_copy(true, entry, NULL,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3133
                                                                                    "arrayof_jshort_arraycopy");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3134
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3135
    //*** jint
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3136
    // Aligned versions
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3137
    StubRoutines::_arrayof_jint_disjoint_arraycopy = generate_disjoint_int_copy(true, &entry,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3138
                                                                                "arrayof_jint_disjoint_arraycopy");
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3139
    StubRoutines::_arrayof_jint_arraycopy          = generate_conjoint_int_copy(true, entry, &entry_jint_arraycopy,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3140
                                                                                "arrayof_jint_arraycopy");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3141
#ifdef _LP64
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3142
    // In 64 bit we need both aligned and unaligned versions of jint arraycopy.
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3143
    // entry_jint_arraycopy always points to the unaligned version (notice that we overwrite it).
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3144
    StubRoutines::_jint_disjoint_arraycopy         = generate_disjoint_int_copy(false, &entry,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3145
                                                                                "jint_disjoint_arraycopy");
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3146
    StubRoutines::_jint_arraycopy                  = generate_conjoint_int_copy(false, entry,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3147
                                                                                &entry_jint_arraycopy,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3148
                                                                                "jint_arraycopy");
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3149
#else
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3150
    // In 32 bit jints are always HeapWordSize aligned, so always use the aligned version
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3151
    // (in fact in 32bit we always have a pre-loop part even in the aligned version,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3152
    //  because it uses 64-bit loads/stores, so the aligned flag is actually ignored).
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3153
    StubRoutines::_jint_disjoint_arraycopy = StubRoutines::_arrayof_jint_disjoint_arraycopy;
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3154
    StubRoutines::_jint_arraycopy          = StubRoutines::_arrayof_jint_arraycopy;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3155
#endif
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3156
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3157
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3158
    //*** jlong
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3159
    // It is always aligned
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3160
    StubRoutines::_arrayof_jlong_disjoint_arraycopy = generate_disjoint_long_copy(true, &entry,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3161
                                                                                  "arrayof_jlong_disjoint_arraycopy");
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3162
    StubRoutines::_arrayof_jlong_arraycopy          = generate_conjoint_long_copy(true, entry, &entry_jlong_arraycopy,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3163
                                                                                  "arrayof_jlong_arraycopy");
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3164
    StubRoutines::_jlong_disjoint_arraycopy         = StubRoutines::_arrayof_jlong_disjoint_arraycopy;
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3165
    StubRoutines::_jlong_arraycopy                  = StubRoutines::_arrayof_jlong_arraycopy;
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3166
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3167
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3168
    //*** oops
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3169
    // Aligned versions
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3170
    StubRoutines::_arrayof_oop_disjoint_arraycopy        = generate_disjoint_oop_copy(true, &entry,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3171
                                                                                      "arrayof_oop_disjoint_arraycopy");
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3172
    StubRoutines::_arrayof_oop_arraycopy                 = generate_conjoint_oop_copy(true, entry, &entry_oop_arraycopy,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3173
                                                                                      "arrayof_oop_arraycopy");
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3174
    // Aligned versions without pre-barriers
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3175
    StubRoutines::_arrayof_oop_disjoint_arraycopy_uninit = generate_disjoint_oop_copy(true, &entry,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3176
                                                                                      "arrayof_oop_disjoint_arraycopy_uninit",
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3177
                                                                                      /*dest_uninitialized*/true);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3178
    StubRoutines::_arrayof_oop_arraycopy_uninit          = generate_conjoint_oop_copy(true, entry, NULL,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3179
                                                                                      "arrayof_oop_arraycopy_uninit",
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3180
                                                                                      /*dest_uninitialized*/true);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3181
#ifdef _LP64
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3182
    if (UseCompressedOops) {
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3183
      // With compressed oops we need unaligned versions, notice that we overwrite entry_oop_arraycopy.
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3184
      StubRoutines::_oop_disjoint_arraycopy            = generate_disjoint_oop_copy(false, &entry,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3185
                                                                                    "oop_disjoint_arraycopy");
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3186
      StubRoutines::_oop_arraycopy                     = generate_conjoint_oop_copy(false, entry, &entry_oop_arraycopy,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3187
                                                                                    "oop_arraycopy");
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3188
      // Unaligned versions without pre-barriers
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3189
      StubRoutines::_oop_disjoint_arraycopy_uninit     = generate_disjoint_oop_copy(false, &entry,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3190
                                                                                    "oop_disjoint_arraycopy_uninit",
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3191
                                                                                    /*dest_uninitialized*/true);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3192
      StubRoutines::_oop_arraycopy_uninit              = generate_conjoint_oop_copy(false, entry, NULL,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3193
                                                                                    "oop_arraycopy_uninit",
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3194
                                                                                    /*dest_uninitialized*/true);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3195
    } else
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3196
#endif
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3197
    {
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3198
      // oop arraycopy is always aligned on 32bit and 64bit without compressed oops
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3199
      StubRoutines::_oop_disjoint_arraycopy            = StubRoutines::_arrayof_oop_disjoint_arraycopy;
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3200
      StubRoutines::_oop_arraycopy                     = StubRoutines::_arrayof_oop_arraycopy;
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3201
      StubRoutines::_oop_disjoint_arraycopy_uninit     = StubRoutines::_arrayof_oop_disjoint_arraycopy_uninit;
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3202
      StubRoutines::_oop_arraycopy_uninit              = StubRoutines::_arrayof_oop_arraycopy_uninit;
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3203
    }
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3204
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3205
    StubRoutines::_checkcast_arraycopy        = generate_checkcast_copy("checkcast_arraycopy", &entry_checkcast_arraycopy);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3206
    StubRoutines::_checkcast_arraycopy_uninit = generate_checkcast_copy("checkcast_arraycopy_uninit", NULL,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3207
                                                                        /*dest_uninitialized*/true);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  3208
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3209
    StubRoutines::_unsafe_arraycopy    = generate_unsafe_copy("unsafe_arraycopy",
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3210
                                                              entry_jbyte_arraycopy,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3211
                                                              entry_jshort_arraycopy,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3212
                                                              entry_jint_arraycopy,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3213
                                                              entry_jlong_arraycopy);
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3214
    StubRoutines::_generic_arraycopy   = generate_generic_copy("generic_arraycopy",
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3215
                                                               entry_jbyte_arraycopy,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3216
                                                               entry_jshort_arraycopy,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3217
                                                               entry_jint_arraycopy,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3218
                                                               entry_oop_arraycopy,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3219
                                                               entry_jlong_arraycopy,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7397
diff changeset
  3220
                                                               entry_checkcast_arraycopy);
6433
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  3221
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  3222
    StubRoutines::_jbyte_fill = generate_fill(T_BYTE, false, "jbyte_fill");
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  3223
    StubRoutines::_jshort_fill = generate_fill(T_SHORT, false, "jshort_fill");
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  3224
    StubRoutines::_jint_fill = generate_fill(T_INT, false, "jint_fill");
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  3225
    StubRoutines::_arrayof_jbyte_fill = generate_fill(T_BYTE, true, "arrayof_jbyte_fill");
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  3226
    StubRoutines::_arrayof_jshort_fill = generate_fill(T_SHORT, true, "arrayof_jshort_fill");
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 6057
diff changeset
  3227
    StubRoutines::_arrayof_jint_fill = generate_fill(T_INT, true, "arrayof_jint_fill");
10501
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3228
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3229
    if (UseBlockZeroing) {
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3230
      StubRoutines::_zero_aligned_words = generate_zero_aligned_words("zero_aligned_words");
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10252
diff changeset
  3231
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3232
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3233
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3234
  address generate_aescrypt_encryptBlock() {
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3235
    // required since we read expanded key 'int' array starting first element without alignment considerations
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3236
    assert((arrayOopDesc::base_offset_in_bytes(T_INT) & 7) == 0,
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3237
           "the following code assumes that first element of an int array is aligned to 8 bytes");
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3238
    __ align(CodeEntryAlignment);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3239
    StubCodeMark mark(this, "StubRoutines", "aescrypt_encryptBlock");
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3240
    Label L_load_misaligned_input, L_load_expanded_key, L_doLast128bit, L_storeOutput, L_store_misaligned_output;
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3241
    address start = __ pc();
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3242
    Register from = O0; // source byte array
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3243
    Register to = O1;   // destination byte array
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3244
    Register key = O2;  // expanded key array
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3245
    const Register keylen = O4; //reg for storing expanded key array length
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3246
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3247
    // read expanded key length
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3248
    __ ldsw(Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)), keylen, 0);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3249
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3250
    // Method to address arbitrary alignment for load instructions:
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3251
    // Check last 3 bits of 'from' address to see if it is aligned to 8-byte boundary
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3252
    // If zero/aligned then continue with double FP load instructions
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3253
    // If not zero/mis-aligned then alignaddr will set GSR.align with number of bytes to skip during faligndata
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3254
    // alignaddr will also convert arbitrary aligned 'from' address to nearest 8-byte aligned address
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3255
    // load 3 * 8-byte components (to read 16 bytes input) in 3 different FP regs starting at this aligned address
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3256
    // faligndata will then extract (based on GSR.align value) the appropriate 8 bytes from the 2 source regs
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3257
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3258
    // check for 8-byte alignment since source byte array may have an arbitrary alignment if offset mod 8 is non-zero
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3259
    __ andcc(from, 7, G0);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3260
    __ br(Assembler::notZero, true, Assembler::pn, L_load_misaligned_input);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3261
    __ delayed()->alignaddr(from, G0, from);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3262
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3263
    // aligned case: load input into F54-F56
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3264
    __ ldf(FloatRegisterImpl::D, from, 0, F54);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3265
    __ ldf(FloatRegisterImpl::D, from, 8, F56);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3266
    __ ba_short(L_load_expanded_key);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3267
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3268
    __ BIND(L_load_misaligned_input);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3269
    __ ldf(FloatRegisterImpl::D, from, 0, F54);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3270
    __ ldf(FloatRegisterImpl::D, from, 8, F56);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3271
    __ ldf(FloatRegisterImpl::D, from, 16, F58);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3272
    __ faligndata(F54, F56, F54);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3273
    __ faligndata(F56, F58, F56);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3274
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3275
    __ BIND(L_load_expanded_key);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3276
    // Since we load expanded key buffers starting first element, 8-byte alignment is guaranteed
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3277
    for ( int i = 0;  i <= 38; i += 2 ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3278
      __ ldf(FloatRegisterImpl::D, key, i*4, as_FloatRegister(i));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3279
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3280
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3281
    // perform cipher transformation
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3282
    __ fxor(FloatRegisterImpl::D, F0, F54, F54);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3283
    __ fxor(FloatRegisterImpl::D, F2, F56, F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3284
    // rounds 1 through 8
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3285
    for ( int i = 4;  i <= 28; i += 8 ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3286
      __ aes_eround01(as_FloatRegister(i), F54, F56, F58);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3287
      __ aes_eround23(as_FloatRegister(i+2), F54, F56, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3288
      __ aes_eround01(as_FloatRegister(i+4), F58, F60, F54);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3289
      __ aes_eround23(as_FloatRegister(i+6), F58, F60, F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3290
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3291
    __ aes_eround01(F36, F54, F56, F58); //round 9
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3292
    __ aes_eround23(F38, F54, F56, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3293
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3294
    // 128-bit original key size
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3295
    __ cmp_and_brx_short(keylen, 44, Assembler::equal, Assembler::pt, L_doLast128bit);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3296
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3297
    for ( int i = 40;  i <= 50; i += 2 ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3298
      __ ldf(FloatRegisterImpl::D, key, i*4, as_FloatRegister(i) );
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3299
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3300
    __ aes_eround01(F40, F58, F60, F54); //round 10
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3301
    __ aes_eround23(F42, F58, F60, F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3302
    __ aes_eround01(F44, F54, F56, F58); //round 11
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3303
    __ aes_eround23(F46, F54, F56, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3304
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3305
    // 192-bit original key size
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3306
    __ cmp_and_brx_short(keylen, 52, Assembler::equal, Assembler::pt, L_storeOutput);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3307
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3308
    __ ldf(FloatRegisterImpl::D, key, 208, F52);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3309
    __ aes_eround01(F48, F58, F60, F54); //round 12
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3310
    __ aes_eround23(F50, F58, F60, F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3311
    __ ldf(FloatRegisterImpl::D, key, 216, F46);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3312
    __ ldf(FloatRegisterImpl::D, key, 224, F48);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3313
    __ ldf(FloatRegisterImpl::D, key, 232, F50);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3314
    __ aes_eround01(F52, F54, F56, F58); //round 13
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3315
    __ aes_eround23(F46, F54, F56, F60);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3316
    __ ba_short(L_storeOutput);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3317
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3318
    __ BIND(L_doLast128bit);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3319
    __ ldf(FloatRegisterImpl::D, key, 160, F48);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3320
    __ ldf(FloatRegisterImpl::D, key, 168, F50);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3321
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3322
    __ BIND(L_storeOutput);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3323
    // perform last round of encryption common for all key sizes
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3324
    __ aes_eround01_l(F48, F58, F60, F54); //last round
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3325
    __ aes_eround23_l(F50, F58, F60, F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3326
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3327
    // Method to address arbitrary alignment for store instructions:
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3328
    // Check last 3 bits of 'dest' address to see if it is aligned to 8-byte boundary
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3329
    // If zero/aligned then continue with double FP store instructions
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3330
    // If not zero/mis-aligned then edge8n will generate edge mask in result reg (O3 in below case)
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3331
    // Example: If dest address is 0x07 and nearest 8-byte aligned address is 0x00 then edge mask will be 00000001
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3332
    // Compute (8-n) where n is # of bytes skipped by partial store(stpartialf) inst from edge mask, n=7 in this case
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3333
    // We get the value of n from the andcc that checks 'dest' alignment. n is available in O5 in below case.
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3334
    // Set GSR.align to (8-n) using alignaddr
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3335
    // Circular byte shift store values by n places so that the original bytes are at correct position for stpartialf
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3336
    // Set the arbitrarily aligned 'dest' address to nearest 8-byte aligned address
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3337
    // Store (partial) the original first (8-n) bytes starting at the original 'dest' address
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3338
    // Negate the edge mask so that the subsequent stpartialf can store the original (8-n-1)th through 8th bytes at appropriate address
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3339
    // We need to execute this process for both the 8-byte result values
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3340
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3341
    // check for 8-byte alignment since dest byte array may have arbitrary alignment if offset mod 8 is non-zero
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3342
    __ andcc(to, 7, O5);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3343
    __ br(Assembler::notZero, true, Assembler::pn, L_store_misaligned_output);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3344
    __ delayed()->edge8n(to, G0, O3);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3345
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3346
    // aligned case: store output into the destination array
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3347
    __ stf(FloatRegisterImpl::D, F54, to, 0);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3348
    __ retl();
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3349
    __ delayed()->stf(FloatRegisterImpl::D, F56, to, 8);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3350
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3351
    __ BIND(L_store_misaligned_output);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3352
    __ add(to, 8, O4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3353
    __ mov(8, O2);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3354
    __ sub(O2, O5, O2);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3355
    __ alignaddr(O2, G0, O2);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3356
    __ faligndata(F54, F54, F54);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3357
    __ faligndata(F56, F56, F56);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3358
    __ and3(to, -8, to);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3359
    __ and3(O4, -8, O4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3360
    __ stpartialf(to, O3, F54, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3361
    __ stpartialf(O4, O3, F56, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3362
    __ add(to, 8, to);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3363
    __ add(O4, 8, O4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3364
    __ orn(G0, O3, O3);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3365
    __ stpartialf(to, O3, F54, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3366
    __ retl();
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3367
    __ delayed()->stpartialf(O4, O3, F56, Assembler::ASI_PST8_PRIMARY);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3368
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3369
    return start;
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3370
  }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3371
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3372
  address generate_aescrypt_decryptBlock() {
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3373
    assert((arrayOopDesc::base_offset_in_bytes(T_INT) & 7) == 0,
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3374
           "the following code assumes that first element of an int array is aligned to 8 bytes");
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3375
    // required since we read original key 'byte' array as well in the decryption stubs
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3376
    assert((arrayOopDesc::base_offset_in_bytes(T_BYTE) & 7) == 0,
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3377
           "the following code assumes that first element of a byte array is aligned to 8 bytes");
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3378
    __ align(CodeEntryAlignment);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3379
    StubCodeMark mark(this, "StubRoutines", "aescrypt_decryptBlock");
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3380
    address start = __ pc();
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3381
    Label L_load_misaligned_input, L_load_original_key, L_expand192bit, L_expand256bit, L_reload_misaligned_input;
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3382
    Label L_256bit_transform, L_common_transform, L_store_misaligned_output;
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3383
    Register from = O0; // source byte array
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3384
    Register to = O1;   // destination byte array
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3385
    Register key = O2;  // expanded key array
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3386
    Register original_key = O3;  // original key array only required during decryption
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3387
    const Register keylen = O4;  // reg for storing expanded key array length
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3388
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3389
    // read expanded key array length
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3390
    __ ldsw(Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)), keylen, 0);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3391
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3392
    // save 'from' since we may need to recheck alignment in case of 256-bit decryption
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3393
    __ mov(from, G1);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3394
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3395
    // check for 8-byte alignment since source byte array may have an arbitrary alignment if offset mod 8 is non-zero
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3396
    __ andcc(from, 7, G0);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3397
    __ br(Assembler::notZero, true, Assembler::pn, L_load_misaligned_input);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3398
    __ delayed()->alignaddr(from, G0, from);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3399
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3400
    // aligned case: load input into F52-F54
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3401
    __ ldf(FloatRegisterImpl::D, from, 0, F52);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3402
    __ ldf(FloatRegisterImpl::D, from, 8, F54);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3403
    __ ba_short(L_load_original_key);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3404
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3405
    __ BIND(L_load_misaligned_input);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3406
    __ ldf(FloatRegisterImpl::D, from, 0, F52);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3407
    __ ldf(FloatRegisterImpl::D, from, 8, F54);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3408
    __ ldf(FloatRegisterImpl::D, from, 16, F56);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3409
    __ faligndata(F52, F54, F52);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3410
    __ faligndata(F54, F56, F54);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3411
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3412
    __ BIND(L_load_original_key);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3413
    // load original key from SunJCE expanded decryption key
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3414
    // Since we load original key buffer starting first element, 8-byte alignment is guaranteed
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3415
    for ( int i = 0;  i <= 3; i++ ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3416
      __ ldf(FloatRegisterImpl::S, original_key, i*4, as_FloatRegister(i));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3417
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3418
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3419
    // 256-bit original key size
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3420
    __ cmp_and_brx_short(keylen, 60, Assembler::equal, Assembler::pn, L_expand256bit);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3421
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3422
    // 192-bit original key size
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3423
    __ cmp_and_brx_short(keylen, 52, Assembler::equal, Assembler::pn, L_expand192bit);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3424
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3425
    // 128-bit original key size
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3426
    // perform key expansion since SunJCE decryption-key expansion is not compatible with SPARC crypto instructions
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3427
    for ( int i = 0;  i <= 36; i += 4 ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3428
      __ aes_kexpand1(as_FloatRegister(i), as_FloatRegister(i+2), i/4, as_FloatRegister(i+4));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3429
      __ aes_kexpand2(as_FloatRegister(i+2), as_FloatRegister(i+4), as_FloatRegister(i+6));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3430
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3431
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3432
    // perform 128-bit key specific inverse cipher transformation
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3433
    __ fxor(FloatRegisterImpl::D, F42, F54, F54);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3434
    __ fxor(FloatRegisterImpl::D, F40, F52, F52);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3435
    __ ba_short(L_common_transform);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3436
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3437
    __ BIND(L_expand192bit);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3438
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3439
    // start loading rest of the 192-bit key
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3440
    __ ldf(FloatRegisterImpl::S, original_key, 16, F4);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3441
    __ ldf(FloatRegisterImpl::S, original_key, 20, F5);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3442
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3443
    // perform key expansion since SunJCE decryption-key expansion is not compatible with SPARC crypto instructions
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3444
    for ( int i = 0;  i <= 36; i += 6 ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3445
      __ aes_kexpand1(as_FloatRegister(i), as_FloatRegister(i+4), i/6, as_FloatRegister(i+6));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3446
      __ aes_kexpand2(as_FloatRegister(i+2), as_FloatRegister(i+6), as_FloatRegister(i+8));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3447
      __ aes_kexpand2(as_FloatRegister(i+4), as_FloatRegister(i+8), as_FloatRegister(i+10));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3448
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3449
    __ aes_kexpand1(F42, F46, 7, F48);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3450
    __ aes_kexpand2(F44, F48, F50);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3451
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3452
    // perform 192-bit key specific inverse cipher transformation
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3453
    __ fxor(FloatRegisterImpl::D, F50, F54, F54);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3454
    __ fxor(FloatRegisterImpl::D, F48, F52, F52);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3455
    __ aes_dround23(F46, F52, F54, F58);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3456
    __ aes_dround01(F44, F52, F54, F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3457
    __ aes_dround23(F42, F56, F58, F54);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3458
    __ aes_dround01(F40, F56, F58, F52);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3459
    __ ba_short(L_common_transform);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3460
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3461
    __ BIND(L_expand256bit);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3462
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3463
    // load rest of the 256-bit key
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3464
    for ( int i = 4;  i <= 7; i++ ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3465
      __ ldf(FloatRegisterImpl::S, original_key, i*4, as_FloatRegister(i));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3466
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3467
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3468
    // perform key expansion since SunJCE decryption-key expansion is not compatible with SPARC crypto instructions
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3469
    for ( int i = 0;  i <= 40; i += 8 ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3470
      __ aes_kexpand1(as_FloatRegister(i), as_FloatRegister(i+6), i/8, as_FloatRegister(i+8));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3471
      __ aes_kexpand2(as_FloatRegister(i+2), as_FloatRegister(i+8), as_FloatRegister(i+10));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3472
      __ aes_kexpand0(as_FloatRegister(i+4), as_FloatRegister(i+10), as_FloatRegister(i+12));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3473
      __ aes_kexpand2(as_FloatRegister(i+6), as_FloatRegister(i+12), as_FloatRegister(i+14));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3474
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3475
    __ aes_kexpand1(F48, F54, 6, F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3476
    __ aes_kexpand2(F50, F56, F58);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3477
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3478
    for ( int i = 0;  i <= 6; i += 2 ) {
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3479
      __ fsrc2(FloatRegisterImpl::D, as_FloatRegister(58-i), as_FloatRegister(i));
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3480
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3481
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3482
    // reload original 'from' address
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3483
    __ mov(G1, from);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3484
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3485
    // re-check 8-byte alignment
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3486
    __ andcc(from, 7, G0);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3487
    __ br(Assembler::notZero, true, Assembler::pn, L_reload_misaligned_input);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3488
    __ delayed()->alignaddr(from, G0, from);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3489
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3490
    // aligned case: load input into F52-F54
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3491
    __ ldf(FloatRegisterImpl::D, from, 0, F52);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3492
    __ ldf(FloatRegisterImpl::D, from, 8, F54);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3493
    __ ba_short(L_256bit_transform);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3494
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3495
    __ BIND(L_reload_misaligned_input);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3496
    __ ldf(FloatRegisterImpl::D, from, 0, F52);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3497
    __ ldf(FloatRegisterImpl::D, from, 8, F54);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3498
    __ ldf(FloatRegisterImpl::D, from, 16, F56);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3499
    __ faligndata(F52, F54, F52);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3500
    __ faligndata(F54, F56, F54);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3501
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3502
    // perform 256-bit key specific inverse cipher transformation
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3503
    __ BIND(L_256bit_transform);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3504
    __ fxor(FloatRegisterImpl::D, F0, F54, F54);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3505
    __ fxor(FloatRegisterImpl::D, F2, F52, F52);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3506
    __ aes_dround23(F4, F52, F54, F58);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3507
    __ aes_dround01(F6, F52, F54, F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3508
    __ aes_dround23(F50, F56, F58, F54);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3509
    __ aes_dround01(F48, F56, F58, F52);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3510
    __ aes_dround23(F46, F52, F54, F58);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3511
    __ aes_dround01(F44, F52, F54, F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3512
    __ aes_dround23(F42, F56, F58, F54);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3513
    __ aes_dround01(F40, F56, F58, F52);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3514
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3515
    for ( int i = 0;  i <= 7; i++ ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3516
      __ ldf(FloatRegisterImpl::S, original_key, i*4, as_FloatRegister(i));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3517
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3518
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3519
    // perform inverse cipher transformations common for all key sizes
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3520
    __ BIND(L_common_transform);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3521
    for ( int i = 38;  i >= 6; i -= 8 ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3522
      __ aes_dround23(as_FloatRegister(i), F52, F54, F58);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3523
      __ aes_dround01(as_FloatRegister(i-2), F52, F54, F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3524
      if ( i != 6) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3525
        __ aes_dround23(as_FloatRegister(i-4), F56, F58, F54);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3526
        __ aes_dround01(as_FloatRegister(i-6), F56, F58, F52);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3527
      } else {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3528
        __ aes_dround23_l(as_FloatRegister(i-4), F56, F58, F54);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3529
        __ aes_dround01_l(as_FloatRegister(i-6), F56, F58, F52);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3530
      }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3531
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3532
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3533
    // check for 8-byte alignment since dest byte array may have arbitrary alignment if offset mod 8 is non-zero
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3534
    __ andcc(to, 7, O5);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3535
    __ br(Assembler::notZero, true, Assembler::pn, L_store_misaligned_output);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3536
    __ delayed()->edge8n(to, G0, O3);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3537
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3538
    // aligned case: store output into the destination array
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3539
    __ stf(FloatRegisterImpl::D, F52, to, 0);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3540
    __ retl();
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3541
    __ delayed()->stf(FloatRegisterImpl::D, F54, to, 8);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3542
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3543
    __ BIND(L_store_misaligned_output);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3544
    __ add(to, 8, O4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3545
    __ mov(8, O2);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3546
    __ sub(O2, O5, O2);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3547
    __ alignaddr(O2, G0, O2);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3548
    __ faligndata(F52, F52, F52);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3549
    __ faligndata(F54, F54, F54);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3550
    __ and3(to, -8, to);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3551
    __ and3(O4, -8, O4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3552
    __ stpartialf(to, O3, F52, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3553
    __ stpartialf(O4, O3, F54, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3554
    __ add(to, 8, to);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3555
    __ add(O4, 8, O4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3556
    __ orn(G0, O3, O3);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3557
    __ stpartialf(to, O3, F52, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3558
    __ retl();
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3559
    __ delayed()->stpartialf(O4, O3, F54, Assembler::ASI_PST8_PRIMARY);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3560
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3561
    return start;
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3562
  }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3563
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3564
  address generate_cipherBlockChaining_encryptAESCrypt() {
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3565
    assert((arrayOopDesc::base_offset_in_bytes(T_INT) & 7) == 0,
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3566
           "the following code assumes that first element of an int array is aligned to 8 bytes");
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3567
    assert((arrayOopDesc::base_offset_in_bytes(T_BYTE) & 7) == 0,
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3568
           "the following code assumes that first element of a byte array is aligned to 8 bytes");
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3569
    __ align(CodeEntryAlignment);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3570
    StubCodeMark mark(this, "StubRoutines", "cipherBlockChaining_encryptAESCrypt");
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3571
    Label L_cbcenc128, L_load_misaligned_input_128bit, L_128bit_transform, L_store_misaligned_output_128bit;
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3572
    Label L_check_loop_end_128bit, L_cbcenc192, L_load_misaligned_input_192bit, L_192bit_transform;
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3573
    Label L_store_misaligned_output_192bit, L_check_loop_end_192bit, L_cbcenc256, L_load_misaligned_input_256bit;
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3574
    Label L_256bit_transform, L_store_misaligned_output_256bit, L_check_loop_end_256bit;
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3575
    address start = __ pc();
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3576
    Register from = I0; // source byte array
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3577
    Register to = I1;   // destination byte array
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3578
    Register key = I2;  // expanded key array
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3579
    Register rvec = I3; // init vector
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3580
    const Register len_reg = I4; // cipher length
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3581
    const Register keylen = I5;  // reg for storing expanded key array length
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3582
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3583
    __ save_frame(0);
24488
6872367f4335 8043274: Test compiler/7184394/TestAESMain.java gets NPE on solaris
kvn
parents: 24328
diff changeset
  3584
    // save cipher len to return in the end
6872367f4335 8043274: Test compiler/7184394/TestAESMain.java gets NPE on solaris
kvn
parents: 24328
diff changeset
  3585
    __ mov(len_reg, L0);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3586
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3587
    // read expanded key length
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3588
    __ ldsw(Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)), keylen, 0);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3589
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3590
    // load initial vector, 8-byte alignment is guranteed
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3591
    __ ldf(FloatRegisterImpl::D, rvec, 0, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3592
    __ ldf(FloatRegisterImpl::D, rvec, 8, F62);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3593
    // load key, 8-byte alignment is guranteed
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3594
    __ ldx(key,0,G1);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3595
    __ ldx(key,8,G5);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3596
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3597
    // start loading expanded key, 8-byte alignment is guranteed
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3598
    for ( int i = 0, j = 16;  i <= 38; i += 2, j += 8 ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3599
      __ ldf(FloatRegisterImpl::D, key, j, as_FloatRegister(i));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3600
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3601
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3602
    // 128-bit original key size
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3603
    __ cmp_and_brx_short(keylen, 44, Assembler::equal, Assembler::pt, L_cbcenc128);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3604
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3605
    for ( int i = 40, j = 176;  i <= 46; i += 2, j += 8 ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3606
      __ ldf(FloatRegisterImpl::D, key, j, as_FloatRegister(i));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3607
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3608
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3609
    // 192-bit original key size
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3610
    __ cmp_and_brx_short(keylen, 52, Assembler::equal, Assembler::pt, L_cbcenc192);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3611
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3612
    for ( int i = 48, j = 208;  i <= 54; i += 2, j += 8 ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3613
      __ ldf(FloatRegisterImpl::D, key, j, as_FloatRegister(i));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3614
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3615
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3616
    // 256-bit original key size
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3617
    __ ba_short(L_cbcenc256);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3618
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3619
    __ align(OptoLoopAlignment);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3620
    __ BIND(L_cbcenc128);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3621
    // check for 8-byte alignment since source byte array may have an arbitrary alignment if offset mod 8 is non-zero
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3622
    __ andcc(from, 7, G0);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3623
    __ br(Assembler::notZero, true, Assembler::pn, L_load_misaligned_input_128bit);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3624
    __ delayed()->mov(from, L1); // save original 'from' address before alignaddr
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3625
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3626
    // aligned case: load input into G3 and G4
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3627
    __ ldx(from,0,G3);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3628
    __ ldx(from,8,G4);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3629
    __ ba_short(L_128bit_transform);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3630
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3631
    __ BIND(L_load_misaligned_input_128bit);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3632
    // can clobber F48, F50 and F52 as they are not used in 128 and 192-bit key encryption
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3633
    __ alignaddr(from, G0, from);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3634
    __ ldf(FloatRegisterImpl::D, from, 0, F48);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3635
    __ ldf(FloatRegisterImpl::D, from, 8, F50);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3636
    __ ldf(FloatRegisterImpl::D, from, 16, F52);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3637
    __ faligndata(F48, F50, F48);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3638
    __ faligndata(F50, F52, F50);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3639
    __ movdtox(F48, G3);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3640
    __ movdtox(F50, G4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3641
    __ mov(L1, from);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3642
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3643
    __ BIND(L_128bit_transform);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3644
    __ xor3(G1,G3,G3);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3645
    __ xor3(G5,G4,G4);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3646
    __ movxtod(G3,F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3647
    __ movxtod(G4,F58);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3648
    __ fxor(FloatRegisterImpl::D, F60, F56, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3649
    __ fxor(FloatRegisterImpl::D, F62, F58, F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3650
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3651
    // TEN_EROUNDS
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3652
    for ( int i = 0;  i <= 32; i += 8 ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3653
      __ aes_eround01(as_FloatRegister(i), F60, F62, F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3654
      __ aes_eround23(as_FloatRegister(i+2), F60, F62, F58);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3655
      if (i != 32 ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3656
        __ aes_eround01(as_FloatRegister(i+4), F56, F58, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3657
        __ aes_eround23(as_FloatRegister(i+6), F56, F58, F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3658
      } else {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3659
        __ aes_eround01_l(as_FloatRegister(i+4), F56, F58, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3660
        __ aes_eround23_l(as_FloatRegister(i+6), F56, F58, F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3661
      }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3662
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3663
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3664
    // check for 8-byte alignment since dest byte array may have arbitrary alignment if offset mod 8 is non-zero
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3665
    __ andcc(to, 7, L1);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3666
    __ br(Assembler::notZero, true, Assembler::pn, L_store_misaligned_output_128bit);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3667
    __ delayed()->edge8n(to, G0, L2);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3668
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3669
    // aligned case: store output into the destination array
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3670
    __ stf(FloatRegisterImpl::D, F60, to, 0);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3671
    __ stf(FloatRegisterImpl::D, F62, to, 8);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3672
    __ ba_short(L_check_loop_end_128bit);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3673
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3674
    __ BIND(L_store_misaligned_output_128bit);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3675
    __ add(to, 8, L3);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3676
    __ mov(8, L4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3677
    __ sub(L4, L1, L4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3678
    __ alignaddr(L4, G0, L4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3679
    // save cipher text before circular right shift
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3680
    // as it needs to be stored as iv for next block (see code before next retl)
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3681
    __ movdtox(F60, L6);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3682
    __ movdtox(F62, L7);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3683
    __ faligndata(F60, F60, F60);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3684
    __ faligndata(F62, F62, F62);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3685
    __ mov(to, L5);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3686
    __ and3(to, -8, to);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3687
    __ and3(L3, -8, L3);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3688
    __ stpartialf(to, L2, F60, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3689
    __ stpartialf(L3, L2, F62, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3690
    __ add(to, 8, to);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3691
    __ add(L3, 8, L3);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3692
    __ orn(G0, L2, L2);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3693
    __ stpartialf(to, L2, F60, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3694
    __ stpartialf(L3, L2, F62, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3695
    __ mov(L5, to);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3696
    __ movxtod(L6, F60);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3697
    __ movxtod(L7, F62);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3698
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3699
    __ BIND(L_check_loop_end_128bit);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3700
    __ add(from, 16, from);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3701
    __ add(to, 16, to);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3702
    __ subcc(len_reg, 16, len_reg);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3703
    __ br(Assembler::notEqual, false, Assembler::pt, L_cbcenc128);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3704
    __ delayed()->nop();
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3705
    // re-init intial vector for next block, 8-byte alignment is guaranteed
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3706
    __ stf(FloatRegisterImpl::D, F60, rvec, 0);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3707
    __ stf(FloatRegisterImpl::D, F62, rvec, 8);
24488
6872367f4335 8043274: Test compiler/7184394/TestAESMain.java gets NPE on solaris
kvn
parents: 24328
diff changeset
  3708
    __ mov(L0, I0);
6872367f4335 8043274: Test compiler/7184394/TestAESMain.java gets NPE on solaris
kvn
parents: 24328
diff changeset
  3709
    __ ret();
6872367f4335 8043274: Test compiler/7184394/TestAESMain.java gets NPE on solaris
kvn
parents: 24328
diff changeset
  3710
    __ delayed()->restore();
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3711
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3712
    __ align(OptoLoopAlignment);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3713
    __ BIND(L_cbcenc192);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3714
    // check for 8-byte alignment since source byte array may have an arbitrary alignment if offset mod 8 is non-zero
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3715
    __ andcc(from, 7, G0);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3716
    __ br(Assembler::notZero, true, Assembler::pn, L_load_misaligned_input_192bit);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3717
    __ delayed()->mov(from, L1); // save original 'from' address before alignaddr
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3718
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3719
    // aligned case: load input into G3 and G4
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3720
    __ ldx(from,0,G3);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3721
    __ ldx(from,8,G4);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3722
    __ ba_short(L_192bit_transform);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3723
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3724
    __ BIND(L_load_misaligned_input_192bit);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3725
    // can clobber F48, F50 and F52 as they are not used in 128 and 192-bit key encryption
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3726
    __ alignaddr(from, G0, from);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3727
    __ ldf(FloatRegisterImpl::D, from, 0, F48);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3728
    __ ldf(FloatRegisterImpl::D, from, 8, F50);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3729
    __ ldf(FloatRegisterImpl::D, from, 16, F52);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3730
    __ faligndata(F48, F50, F48);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3731
    __ faligndata(F50, F52, F50);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3732
    __ movdtox(F48, G3);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3733
    __ movdtox(F50, G4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3734
    __ mov(L1, from);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3735
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3736
    __ BIND(L_192bit_transform);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3737
    __ xor3(G1,G3,G3);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3738
    __ xor3(G5,G4,G4);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3739
    __ movxtod(G3,F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3740
    __ movxtod(G4,F58);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3741
    __ fxor(FloatRegisterImpl::D, F60, F56, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3742
    __ fxor(FloatRegisterImpl::D, F62, F58, F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3743
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3744
    // TWELEVE_EROUNDS
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3745
    for ( int i = 0;  i <= 40; i += 8 ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3746
      __ aes_eround01(as_FloatRegister(i), F60, F62, F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3747
      __ aes_eround23(as_FloatRegister(i+2), F60, F62, F58);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3748
      if (i != 40 ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3749
        __ aes_eround01(as_FloatRegister(i+4), F56, F58, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3750
        __ aes_eround23(as_FloatRegister(i+6), F56, F58, F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3751
      } else {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3752
        __ aes_eround01_l(as_FloatRegister(i+4), F56, F58, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3753
        __ aes_eround23_l(as_FloatRegister(i+6), F56, F58, F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3754
      }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3755
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3756
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3757
    // check for 8-byte alignment since dest byte array may have arbitrary alignment if offset mod 8 is non-zero
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3758
    __ andcc(to, 7, L1);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3759
    __ br(Assembler::notZero, true, Assembler::pn, L_store_misaligned_output_192bit);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3760
    __ delayed()->edge8n(to, G0, L2);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3761
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3762
    // aligned case: store output into the destination array
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3763
    __ stf(FloatRegisterImpl::D, F60, to, 0);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3764
    __ stf(FloatRegisterImpl::D, F62, to, 8);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3765
    __ ba_short(L_check_loop_end_192bit);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3766
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3767
    __ BIND(L_store_misaligned_output_192bit);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3768
    __ add(to, 8, L3);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3769
    __ mov(8, L4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3770
    __ sub(L4, L1, L4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3771
    __ alignaddr(L4, G0, L4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3772
    __ movdtox(F60, L6);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3773
    __ movdtox(F62, L7);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3774
    __ faligndata(F60, F60, F60);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3775
    __ faligndata(F62, F62, F62);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3776
    __ mov(to, L5);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3777
    __ and3(to, -8, to);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3778
    __ and3(L3, -8, L3);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3779
    __ stpartialf(to, L2, F60, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3780
    __ stpartialf(L3, L2, F62, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3781
    __ add(to, 8, to);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3782
    __ add(L3, 8, L3);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3783
    __ orn(G0, L2, L2);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3784
    __ stpartialf(to, L2, F60, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3785
    __ stpartialf(L3, L2, F62, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3786
    __ mov(L5, to);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3787
    __ movxtod(L6, F60);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3788
    __ movxtod(L7, F62);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3789
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3790
    __ BIND(L_check_loop_end_192bit);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3791
    __ add(from, 16, from);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3792
    __ subcc(len_reg, 16, len_reg);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3793
    __ add(to, 16, to);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3794
    __ br(Assembler::notEqual, false, Assembler::pt, L_cbcenc192);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3795
    __ delayed()->nop();
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3796
    // re-init intial vector for next block, 8-byte alignment is guaranteed
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3797
    __ stf(FloatRegisterImpl::D, F60, rvec, 0);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3798
    __ stf(FloatRegisterImpl::D, F62, rvec, 8);
24488
6872367f4335 8043274: Test compiler/7184394/TestAESMain.java gets NPE on solaris
kvn
parents: 24328
diff changeset
  3799
    __ mov(L0, I0);
6872367f4335 8043274: Test compiler/7184394/TestAESMain.java gets NPE on solaris
kvn
parents: 24328
diff changeset
  3800
    __ ret();
6872367f4335 8043274: Test compiler/7184394/TestAESMain.java gets NPE on solaris
kvn
parents: 24328
diff changeset
  3801
    __ delayed()->restore();
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3802
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3803
    __ align(OptoLoopAlignment);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3804
    __ BIND(L_cbcenc256);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3805
    // check for 8-byte alignment since source byte array may have an arbitrary alignment if offset mod 8 is non-zero
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3806
    __ andcc(from, 7, G0);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3807
    __ br(Assembler::notZero, true, Assembler::pn, L_load_misaligned_input_256bit);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3808
    __ delayed()->mov(from, L1); // save original 'from' address before alignaddr
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3809
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3810
    // aligned case: load input into G3 and G4
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3811
    __ ldx(from,0,G3);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3812
    __ ldx(from,8,G4);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3813
    __ ba_short(L_256bit_transform);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3814
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3815
    __ BIND(L_load_misaligned_input_256bit);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3816
    // cannot clobber F48, F50 and F52. F56, F58 can be used though
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3817
    __ alignaddr(from, G0, from);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3818
    __ movdtox(F60, L2); // save F60 before overwriting
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3819
    __ ldf(FloatRegisterImpl::D, from, 0, F56);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3820
    __ ldf(FloatRegisterImpl::D, from, 8, F58);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3821
    __ ldf(FloatRegisterImpl::D, from, 16, F60);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3822
    __ faligndata(F56, F58, F56);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3823
    __ faligndata(F58, F60, F58);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3824
    __ movdtox(F56, G3);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3825
    __ movdtox(F58, G4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3826
    __ mov(L1, from);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3827
    __ movxtod(L2, F60);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3828
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3829
    __ BIND(L_256bit_transform);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3830
    __ xor3(G1,G3,G3);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3831
    __ xor3(G5,G4,G4);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3832
    __ movxtod(G3,F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3833
    __ movxtod(G4,F58);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3834
    __ fxor(FloatRegisterImpl::D, F60, F56, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3835
    __ fxor(FloatRegisterImpl::D, F62, F58, F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3836
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3837
    // FOURTEEN_EROUNDS
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3838
    for ( int i = 0;  i <= 48; i += 8 ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3839
      __ aes_eround01(as_FloatRegister(i), F60, F62, F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3840
      __ aes_eround23(as_FloatRegister(i+2), F60, F62, F58);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3841
      if (i != 48 ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3842
        __ aes_eround01(as_FloatRegister(i+4), F56, F58, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3843
        __ aes_eround23(as_FloatRegister(i+6), F56, F58, F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3844
      } else {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3845
        __ aes_eround01_l(as_FloatRegister(i+4), F56, F58, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3846
        __ aes_eround23_l(as_FloatRegister(i+6), F56, F58, F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3847
      }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3848
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3849
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3850
    // check for 8-byte alignment since dest byte array may have arbitrary alignment if offset mod 8 is non-zero
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3851
    __ andcc(to, 7, L1);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3852
    __ br(Assembler::notZero, true, Assembler::pn, L_store_misaligned_output_256bit);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3853
    __ delayed()->edge8n(to, G0, L2);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3854
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3855
    // aligned case: store output into the destination array
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3856
    __ stf(FloatRegisterImpl::D, F60, to, 0);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3857
    __ stf(FloatRegisterImpl::D, F62, to, 8);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3858
    __ ba_short(L_check_loop_end_256bit);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3859
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3860
    __ BIND(L_store_misaligned_output_256bit);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3861
    __ add(to, 8, L3);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3862
    __ mov(8, L4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3863
    __ sub(L4, L1, L4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3864
    __ alignaddr(L4, G0, L4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3865
    __ movdtox(F60, L6);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3866
    __ movdtox(F62, L7);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3867
    __ faligndata(F60, F60, F60);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3868
    __ faligndata(F62, F62, F62);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3869
    __ mov(to, L5);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3870
    __ and3(to, -8, to);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3871
    __ and3(L3, -8, L3);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3872
    __ stpartialf(to, L2, F60, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3873
    __ stpartialf(L3, L2, F62, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3874
    __ add(to, 8, to);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3875
    __ add(L3, 8, L3);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3876
    __ orn(G0, L2, L2);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3877
    __ stpartialf(to, L2, F60, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3878
    __ stpartialf(L3, L2, F62, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3879
    __ mov(L5, to);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3880
    __ movxtod(L6, F60);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3881
    __ movxtod(L7, F62);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3882
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3883
    __ BIND(L_check_loop_end_256bit);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3884
    __ add(from, 16, from);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3885
    __ subcc(len_reg, 16, len_reg);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3886
    __ add(to, 16, to);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3887
    __ br(Assembler::notEqual, false, Assembler::pt, L_cbcenc256);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3888
    __ delayed()->nop();
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3889
    // re-init intial vector for next block, 8-byte alignment is guaranteed
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3890
    __ stf(FloatRegisterImpl::D, F60, rvec, 0);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3891
    __ stf(FloatRegisterImpl::D, F62, rvec, 8);
24488
6872367f4335 8043274: Test compiler/7184394/TestAESMain.java gets NPE on solaris
kvn
parents: 24328
diff changeset
  3892
    __ mov(L0, I0);
6872367f4335 8043274: Test compiler/7184394/TestAESMain.java gets NPE on solaris
kvn
parents: 24328
diff changeset
  3893
    __ ret();
6872367f4335 8043274: Test compiler/7184394/TestAESMain.java gets NPE on solaris
kvn
parents: 24328
diff changeset
  3894
    __ delayed()->restore();
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3895
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3896
    return start;
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3897
  }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3898
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3899
  address generate_cipherBlockChaining_decryptAESCrypt_Parallel() {
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3900
    assert((arrayOopDesc::base_offset_in_bytes(T_INT) & 7) == 0,
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3901
           "the following code assumes that first element of an int array is aligned to 8 bytes");
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3902
    assert((arrayOopDesc::base_offset_in_bytes(T_BYTE) & 7) == 0,
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3903
           "the following code assumes that first element of a byte array is aligned to 8 bytes");
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3904
    __ align(CodeEntryAlignment);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3905
    StubCodeMark mark(this, "StubRoutines", "cipherBlockChaining_decryptAESCrypt");
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3906
    Label L_cbcdec_end, L_expand192bit, L_expand256bit, L_dec_first_block_start;
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3907
    Label L_dec_first_block128, L_dec_first_block192, L_dec_next2_blocks128, L_dec_next2_blocks192, L_dec_next2_blocks256;
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3908
    Label L_load_misaligned_input_first_block, L_transform_first_block, L_load_misaligned_next2_blocks128, L_transform_next2_blocks128;
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3909
    Label L_load_misaligned_next2_blocks192, L_transform_next2_blocks192, L_load_misaligned_next2_blocks256, L_transform_next2_blocks256;
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3910
    Label L_store_misaligned_output_first_block, L_check_decrypt_end, L_store_misaligned_output_next2_blocks128;
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3911
    Label L_check_decrypt_loop_end128, L_store_misaligned_output_next2_blocks192, L_check_decrypt_loop_end192;
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3912
    Label L_store_misaligned_output_next2_blocks256, L_check_decrypt_loop_end256;
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3913
    address start = __ pc();
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3914
    Register from = I0; // source byte array
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3915
    Register to = I1;   // destination byte array
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3916
    Register key = I2;  // expanded key array
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3917
    Register rvec = I3; // init vector
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3918
    const Register len_reg = I4; // cipher length
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3919
    const Register original_key = I5;  // original key array only required during decryption
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3920
    const Register keylen = L6;  // reg for storing expanded key array length
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3921
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3922
    __ save_frame(0); //args are read from I* registers since we save the frame in the beginning
24488
6872367f4335 8043274: Test compiler/7184394/TestAESMain.java gets NPE on solaris
kvn
parents: 24328
diff changeset
  3923
    // save cipher len to return in the end
6872367f4335 8043274: Test compiler/7184394/TestAESMain.java gets NPE on solaris
kvn
parents: 24328
diff changeset
  3924
    __ mov(len_reg, L7);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3925
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3926
    // load original key from SunJCE expanded decryption key
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3927
    // Since we load original key buffer starting first element, 8-byte alignment is guaranteed
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3928
    for ( int i = 0;  i <= 3; i++ ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3929
      __ ldf(FloatRegisterImpl::S, original_key, i*4, as_FloatRegister(i));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3930
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3931
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3932
    // load initial vector, 8-byte alignment is guaranteed
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3933
    __ ldx(rvec,0,L0);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3934
    __ ldx(rvec,8,L1);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3935
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3936
    // read expanded key array length
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3937
    __ ldsw(Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)), keylen, 0);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3938
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3939
    // 256-bit original key size
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3940
    __ cmp_and_brx_short(keylen, 60, Assembler::equal, Assembler::pn, L_expand256bit);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3941
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3942
    // 192-bit original key size
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3943
    __ cmp_and_brx_short(keylen, 52, Assembler::equal, Assembler::pn, L_expand192bit);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3944
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3945
    // 128-bit original key size
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3946
    // perform key expansion since SunJCE decryption-key expansion is not compatible with SPARC crypto instructions
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3947
    for ( int i = 0;  i <= 36; i += 4 ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3948
      __ aes_kexpand1(as_FloatRegister(i), as_FloatRegister(i+2), i/4, as_FloatRegister(i+4));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3949
      __ aes_kexpand2(as_FloatRegister(i+2), as_FloatRegister(i+4), as_FloatRegister(i+6));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3950
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3951
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3952
    // load expanded key[last-1] and key[last] elements
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3953
    __ movdtox(F40,L2);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3954
    __ movdtox(F42,L3);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3955
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3956
    __ and3(len_reg, 16, L4);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3957
    __ br_null_short(L4, Assembler::pt, L_dec_next2_blocks128);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3958
    __ nop();
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3959
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3960
    __ ba_short(L_dec_first_block_start);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3961
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3962
    __ BIND(L_expand192bit);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3963
    // load rest of the 192-bit key
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3964
    __ ldf(FloatRegisterImpl::S, original_key, 16, F4);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3965
    __ ldf(FloatRegisterImpl::S, original_key, 20, F5);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3966
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3967
    // perform key expansion since SunJCE decryption-key expansion is not compatible with SPARC crypto instructions
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3968
    for ( int i = 0;  i <= 36; i += 6 ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3969
      __ aes_kexpand1(as_FloatRegister(i), as_FloatRegister(i+4), i/6, as_FloatRegister(i+6));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3970
      __ aes_kexpand2(as_FloatRegister(i+2), as_FloatRegister(i+6), as_FloatRegister(i+8));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3971
      __ aes_kexpand2(as_FloatRegister(i+4), as_FloatRegister(i+8), as_FloatRegister(i+10));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3972
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3973
    __ aes_kexpand1(F42, F46, 7, F48);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3974
    __ aes_kexpand2(F44, F48, F50);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3975
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3976
    // load expanded key[last-1] and key[last] elements
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3977
    __ movdtox(F48,L2);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3978
    __ movdtox(F50,L3);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3979
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3980
    __ and3(len_reg, 16, L4);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3981
    __ br_null_short(L4, Assembler::pt, L_dec_next2_blocks192);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3982
    __ nop();
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3983
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  3984
    __ ba_short(L_dec_first_block_start);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3985
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3986
    __ BIND(L_expand256bit);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3987
    // load rest of the 256-bit key
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3988
    for ( int i = 4;  i <= 7; i++ ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3989
      __ ldf(FloatRegisterImpl::S, original_key, i*4, as_FloatRegister(i));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3990
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3991
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3992
    // perform key expansion since SunJCE decryption-key expansion is not compatible with SPARC crypto instructions
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3993
    for ( int i = 0;  i <= 40; i += 8 ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3994
      __ aes_kexpand1(as_FloatRegister(i), as_FloatRegister(i+6), i/8, as_FloatRegister(i+8));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3995
      __ aes_kexpand2(as_FloatRegister(i+2), as_FloatRegister(i+8), as_FloatRegister(i+10));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3996
      __ aes_kexpand0(as_FloatRegister(i+4), as_FloatRegister(i+10), as_FloatRegister(i+12));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3997
      __ aes_kexpand2(as_FloatRegister(i+6), as_FloatRegister(i+12), as_FloatRegister(i+14));
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3998
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  3999
    __ aes_kexpand1(F48, F54, 6, F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4000
    __ aes_kexpand2(F50, F56, F58);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4001
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4002
    // load expanded key[last-1] and key[last] elements
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4003
    __ movdtox(F56,L2);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4004
    __ movdtox(F58,L3);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4005
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4006
    __ and3(len_reg, 16, L4);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4007
    __ br_null_short(L4, Assembler::pt, L_dec_next2_blocks256);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4008
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4009
    __ BIND(L_dec_first_block_start);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4010
    // check for 8-byte alignment since source byte array may have an arbitrary alignment if offset mod 8 is non-zero
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4011
    __ andcc(from, 7, G0);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4012
    __ br(Assembler::notZero, true, Assembler::pn, L_load_misaligned_input_first_block);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4013
    __ delayed()->mov(from, G1); // save original 'from' address before alignaddr
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4014
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4015
    // aligned case: load input into L4 and L5
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4016
    __ ldx(from,0,L4);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4017
    __ ldx(from,8,L5);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4018
    __ ba_short(L_transform_first_block);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4019
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4020
    __ BIND(L_load_misaligned_input_first_block);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4021
    __ alignaddr(from, G0, from);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4022
    // F58, F60, F62 can be clobbered
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4023
    __ ldf(FloatRegisterImpl::D, from, 0, F58);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4024
    __ ldf(FloatRegisterImpl::D, from, 8, F60);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4025
    __ ldf(FloatRegisterImpl::D, from, 16, F62);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4026
    __ faligndata(F58, F60, F58);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4027
    __ faligndata(F60, F62, F60);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4028
    __ movdtox(F58, L4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4029
    __ movdtox(F60, L5);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4030
    __ mov(G1, from);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4031
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4032
    __ BIND(L_transform_first_block);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4033
    __ xor3(L2,L4,G1);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4034
    __ movxtod(G1,F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4035
    __ xor3(L3,L5,G1);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4036
    __ movxtod(G1,F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4037
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4038
    // 128-bit original key size
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4039
    __ cmp_and_brx_short(keylen, 44, Assembler::equal, Assembler::pn, L_dec_first_block128);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4040
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4041
    // 192-bit original key size
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4042
    __ cmp_and_brx_short(keylen, 52, Assembler::equal, Assembler::pn, L_dec_first_block192);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4043
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4044
    __ aes_dround23(F54, F60, F62, F58);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4045
    __ aes_dround01(F52, F60, F62, F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4046
    __ aes_dround23(F50, F56, F58, F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4047
    __ aes_dround01(F48, F56, F58, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4048
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4049
    __ BIND(L_dec_first_block192);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4050
    __ aes_dround23(F46, F60, F62, F58);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4051
    __ aes_dround01(F44, F60, F62, F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4052
    __ aes_dround23(F42, F56, F58, F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4053
    __ aes_dround01(F40, F56, F58, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4054
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4055
    __ BIND(L_dec_first_block128);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4056
    for ( int i = 38;  i >= 6; i -= 8 ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4057
      __ aes_dround23(as_FloatRegister(i), F60, F62, F58);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4058
      __ aes_dround01(as_FloatRegister(i-2), F60, F62, F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4059
      if ( i != 6) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4060
        __ aes_dround23(as_FloatRegister(i-4), F56, F58, F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4061
        __ aes_dround01(as_FloatRegister(i-6), F56, F58, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4062
      } else {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4063
        __ aes_dround23_l(as_FloatRegister(i-4), F56, F58, F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4064
        __ aes_dround01_l(as_FloatRegister(i-6), F56, F58, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4065
      }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4066
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4067
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4068
    __ movxtod(L0,F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4069
    __ movxtod(L1,F58);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4070
    __ mov(L4,L0);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4071
    __ mov(L5,L1);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4072
    __ fxor(FloatRegisterImpl::D, F56, F60, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4073
    __ fxor(FloatRegisterImpl::D, F58, F62, F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4074
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4075
    // check for 8-byte alignment since dest byte array may have arbitrary alignment if offset mod 8 is non-zero
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4076
    __ andcc(to, 7, G1);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4077
    __ br(Assembler::notZero, true, Assembler::pn, L_store_misaligned_output_first_block);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4078
    __ delayed()->edge8n(to, G0, G2);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4079
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4080
    // aligned case: store output into the destination array
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4081
    __ stf(FloatRegisterImpl::D, F60, to, 0);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4082
    __ stf(FloatRegisterImpl::D, F62, to, 8);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4083
    __ ba_short(L_check_decrypt_end);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4084
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4085
    __ BIND(L_store_misaligned_output_first_block);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4086
    __ add(to, 8, G3);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4087
    __ mov(8, G4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4088
    __ sub(G4, G1, G4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4089
    __ alignaddr(G4, G0, G4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4090
    __ faligndata(F60, F60, F60);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4091
    __ faligndata(F62, F62, F62);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4092
    __ mov(to, G1);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4093
    __ and3(to, -8, to);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4094
    __ and3(G3, -8, G3);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4095
    __ stpartialf(to, G2, F60, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4096
    __ stpartialf(G3, G2, F62, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4097
    __ add(to, 8, to);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4098
    __ add(G3, 8, G3);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4099
    __ orn(G0, G2, G2);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4100
    __ stpartialf(to, G2, F60, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4101
    __ stpartialf(G3, G2, F62, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4102
    __ mov(G1, to);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4103
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4104
    __ BIND(L_check_decrypt_end);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4105
    __ add(from, 16, from);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4106
    __ add(to, 16, to);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4107
    __ subcc(len_reg, 16, len_reg);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4108
    __ br(Assembler::equal, false, Assembler::pt, L_cbcdec_end);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4109
    __ delayed()->nop();
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4110
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4111
    // 256-bit original key size
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4112
    __ cmp_and_brx_short(keylen, 60, Assembler::equal, Assembler::pn, L_dec_next2_blocks256);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4113
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4114
    // 192-bit original key size
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4115
    __ cmp_and_brx_short(keylen, 52, Assembler::equal, Assembler::pn, L_dec_next2_blocks192);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4116
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4117
    __ align(OptoLoopAlignment);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4118
    __ BIND(L_dec_next2_blocks128);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4119
    __ nop();
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4120
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4121
    // check for 8-byte alignment since source byte array may have an arbitrary alignment if offset mod 8 is non-zero
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4122
    __ andcc(from, 7, G0);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4123
    __ br(Assembler::notZero, true, Assembler::pn, L_load_misaligned_next2_blocks128);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4124
    __ delayed()->mov(from, G1); // save original 'from' address before alignaddr
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4125
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4126
    // aligned case: load input into G4, G5, L4 and L5
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4127
    __ ldx(from,0,G4);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4128
    __ ldx(from,8,G5);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4129
    __ ldx(from,16,L4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4130
    __ ldx(from,24,L5);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4131
    __ ba_short(L_transform_next2_blocks128);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4132
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4133
    __ BIND(L_load_misaligned_next2_blocks128);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4134
    __ alignaddr(from, G0, from);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4135
    // F40, F42, F58, F60, F62 can be clobbered
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4136
    __ ldf(FloatRegisterImpl::D, from, 0, F40);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4137
    __ ldf(FloatRegisterImpl::D, from, 8, F42);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4138
    __ ldf(FloatRegisterImpl::D, from, 16, F60);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4139
    __ ldf(FloatRegisterImpl::D, from, 24, F62);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4140
    __ ldf(FloatRegisterImpl::D, from, 32, F58);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4141
    __ faligndata(F40, F42, F40);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4142
    __ faligndata(F42, F60, F42);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4143
    __ faligndata(F60, F62, F60);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4144
    __ faligndata(F62, F58, F62);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4145
    __ movdtox(F40, G4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4146
    __ movdtox(F42, G5);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4147
    __ movdtox(F60, L4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4148
    __ movdtox(F62, L5);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4149
    __ mov(G1, from);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4150
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4151
    __ BIND(L_transform_next2_blocks128);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4152
    // F40:F42 used for first 16-bytes
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4153
    __ xor3(L2,G4,G1);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4154
    __ movxtod(G1,F40);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4155
    __ xor3(L3,G5,G1);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4156
    __ movxtod(G1,F42);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4157
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4158
    // F60:F62 used for next 16-bytes
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4159
    __ xor3(L2,L4,G1);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4160
    __ movxtod(G1,F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4161
    __ xor3(L3,L5,G1);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4162
    __ movxtod(G1,F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4163
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4164
    for ( int i = 38;  i >= 6; i -= 8 ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4165
      __ aes_dround23(as_FloatRegister(i), F40, F42, F44);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4166
      __ aes_dround01(as_FloatRegister(i-2), F40, F42, F46);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4167
      __ aes_dround23(as_FloatRegister(i), F60, F62, F58);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4168
      __ aes_dround01(as_FloatRegister(i-2), F60, F62, F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4169
      if (i != 6 ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4170
        __ aes_dround23(as_FloatRegister(i-4), F46, F44, F42);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4171
        __ aes_dround01(as_FloatRegister(i-6), F46, F44, F40);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4172
        __ aes_dround23(as_FloatRegister(i-4), F56, F58, F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4173
        __ aes_dround01(as_FloatRegister(i-6), F56, F58, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4174
      } else {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4175
        __ aes_dround23_l(as_FloatRegister(i-4), F46, F44, F42);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4176
        __ aes_dround01_l(as_FloatRegister(i-6), F46, F44, F40);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4177
        __ aes_dround23_l(as_FloatRegister(i-4), F56, F58, F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4178
        __ aes_dround01_l(as_FloatRegister(i-6), F56, F58, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4179
      }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4180
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4181
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4182
    __ movxtod(L0,F46);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4183
    __ movxtod(L1,F44);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4184
    __ fxor(FloatRegisterImpl::D, F46, F40, F40);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4185
    __ fxor(FloatRegisterImpl::D, F44, F42, F42);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4186
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4187
    __ movxtod(G4,F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4188
    __ movxtod(G5,F58);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4189
    __ mov(L4,L0);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4190
    __ mov(L5,L1);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4191
    __ fxor(FloatRegisterImpl::D, F56, F60, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4192
    __ fxor(FloatRegisterImpl::D, F58, F62, F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4193
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4194
    // For mis-aligned store of 32 bytes of result we can do:
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4195
    // Circular right-shift all 4 FP registers so that 'head' and 'tail'
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4196
    // parts that need to be stored starting at mis-aligned address are in a FP reg
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4197
    // the other 3 FP regs can thus be stored using regular store
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4198
    // we then use the edge + partial-store mechanism to store the 'head' and 'tail' parts
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4199
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4200
    // check for 8-byte alignment since dest byte array may have arbitrary alignment if offset mod 8 is non-zero
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4201
    __ andcc(to, 7, G1);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4202
    __ br(Assembler::notZero, true, Assembler::pn, L_store_misaligned_output_next2_blocks128);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4203
    __ delayed()->edge8n(to, G0, G2);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4204
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4205
    // aligned case: store output into the destination array
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4206
    __ stf(FloatRegisterImpl::D, F40, to, 0);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4207
    __ stf(FloatRegisterImpl::D, F42, to, 8);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4208
    __ stf(FloatRegisterImpl::D, F60, to, 16);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4209
    __ stf(FloatRegisterImpl::D, F62, to, 24);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4210
    __ ba_short(L_check_decrypt_loop_end128);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4211
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4212
    __ BIND(L_store_misaligned_output_next2_blocks128);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4213
    __ mov(8, G4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4214
    __ sub(G4, G1, G4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4215
    __ alignaddr(G4, G0, G4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4216
    __ faligndata(F40, F42, F56); // F56 can be clobbered
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4217
    __ faligndata(F42, F60, F42);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4218
    __ faligndata(F60, F62, F60);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4219
    __ faligndata(F62, F40, F40);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4220
    __ mov(to, G1);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4221
    __ and3(to, -8, to);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4222
    __ stpartialf(to, G2, F40, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4223
    __ stf(FloatRegisterImpl::D, F56, to, 8);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4224
    __ stf(FloatRegisterImpl::D, F42, to, 16);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4225
    __ stf(FloatRegisterImpl::D, F60, to, 24);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4226
    __ add(to, 32, to);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4227
    __ orn(G0, G2, G2);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4228
    __ stpartialf(to, G2, F40, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4229
    __ mov(G1, to);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4230
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4231
    __ BIND(L_check_decrypt_loop_end128);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4232
    __ add(from, 32, from);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4233
    __ add(to, 32, to);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4234
    __ subcc(len_reg, 32, len_reg);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4235
    __ br(Assembler::notEqual, false, Assembler::pt, L_dec_next2_blocks128);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4236
    __ delayed()->nop();
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4237
    __ ba_short(L_cbcdec_end);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4238
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4239
    __ align(OptoLoopAlignment);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4240
    __ BIND(L_dec_next2_blocks192);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4241
    __ nop();
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4242
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4243
    // check for 8-byte alignment since source byte array may have an arbitrary alignment if offset mod 8 is non-zero
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4244
    __ andcc(from, 7, G0);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4245
    __ br(Assembler::notZero, true, Assembler::pn, L_load_misaligned_next2_blocks192);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4246
    __ delayed()->mov(from, G1); // save original 'from' address before alignaddr
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4247
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4248
    // aligned case: load input into G4, G5, L4 and L5
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4249
    __ ldx(from,0,G4);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4250
    __ ldx(from,8,G5);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4251
    __ ldx(from,16,L4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4252
    __ ldx(from,24,L5);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4253
    __ ba_short(L_transform_next2_blocks192);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4254
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4255
    __ BIND(L_load_misaligned_next2_blocks192);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4256
    __ alignaddr(from, G0, from);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4257
    // F48, F50, F52, F60, F62 can be clobbered
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4258
    __ ldf(FloatRegisterImpl::D, from, 0, F48);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4259
    __ ldf(FloatRegisterImpl::D, from, 8, F50);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4260
    __ ldf(FloatRegisterImpl::D, from, 16, F60);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4261
    __ ldf(FloatRegisterImpl::D, from, 24, F62);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4262
    __ ldf(FloatRegisterImpl::D, from, 32, F52);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4263
    __ faligndata(F48, F50, F48);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4264
    __ faligndata(F50, F60, F50);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4265
    __ faligndata(F60, F62, F60);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4266
    __ faligndata(F62, F52, F62);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4267
    __ movdtox(F48, G4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4268
    __ movdtox(F50, G5);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4269
    __ movdtox(F60, L4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4270
    __ movdtox(F62, L5);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4271
    __ mov(G1, from);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4272
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4273
    __ BIND(L_transform_next2_blocks192);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4274
    // F48:F50 used for first 16-bytes
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4275
    __ xor3(L2,G4,G1);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4276
    __ movxtod(G1,F48);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4277
    __ xor3(L3,G5,G1);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4278
    __ movxtod(G1,F50);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4279
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4280
    // F60:F62 used for next 16-bytes
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4281
    __ xor3(L2,L4,G1);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4282
    __ movxtod(G1,F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4283
    __ xor3(L3,L5,G1);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4284
    __ movxtod(G1,F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4285
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4286
    for ( int i = 46;  i >= 6; i -= 8 ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4287
      __ aes_dround23(as_FloatRegister(i), F48, F50, F52);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4288
      __ aes_dround01(as_FloatRegister(i-2), F48, F50, F54);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4289
      __ aes_dround23(as_FloatRegister(i), F60, F62, F58);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4290
      __ aes_dround01(as_FloatRegister(i-2), F60, F62, F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4291
      if (i != 6 ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4292
        __ aes_dround23(as_FloatRegister(i-4), F54, F52, F50);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4293
        __ aes_dround01(as_FloatRegister(i-6), F54, F52, F48);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4294
        __ aes_dround23(as_FloatRegister(i-4), F56, F58, F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4295
        __ aes_dround01(as_FloatRegister(i-6), F56, F58, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4296
      } else {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4297
        __ aes_dround23_l(as_FloatRegister(i-4), F54, F52, F50);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4298
        __ aes_dround01_l(as_FloatRegister(i-6), F54, F52, F48);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4299
        __ aes_dround23_l(as_FloatRegister(i-4), F56, F58, F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4300
        __ aes_dround01_l(as_FloatRegister(i-6), F56, F58, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4301
      }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4302
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4303
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4304
    __ movxtod(L0,F54);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4305
    __ movxtod(L1,F52);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4306
    __ fxor(FloatRegisterImpl::D, F54, F48, F48);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4307
    __ fxor(FloatRegisterImpl::D, F52, F50, F50);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4308
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4309
    __ movxtod(G4,F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4310
    __ movxtod(G5,F58);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4311
    __ mov(L4,L0);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4312
    __ mov(L5,L1);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4313
    __ fxor(FloatRegisterImpl::D, F56, F60, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4314
    __ fxor(FloatRegisterImpl::D, F58, F62, F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4315
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4316
    // check for 8-byte alignment since dest byte array may have arbitrary alignment if offset mod 8 is non-zero
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4317
    __ andcc(to, 7, G1);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4318
    __ br(Assembler::notZero, true, Assembler::pn, L_store_misaligned_output_next2_blocks192);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4319
    __ delayed()->edge8n(to, G0, G2);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4320
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4321
    // aligned case: store output into the destination array
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4322
    __ stf(FloatRegisterImpl::D, F48, to, 0);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4323
    __ stf(FloatRegisterImpl::D, F50, to, 8);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4324
    __ stf(FloatRegisterImpl::D, F60, to, 16);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4325
    __ stf(FloatRegisterImpl::D, F62, to, 24);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4326
    __ ba_short(L_check_decrypt_loop_end192);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4327
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4328
    __ BIND(L_store_misaligned_output_next2_blocks192);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4329
    __ mov(8, G4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4330
    __ sub(G4, G1, G4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4331
    __ alignaddr(G4, G0, G4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4332
    __ faligndata(F48, F50, F56); // F56 can be clobbered
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4333
    __ faligndata(F50, F60, F50);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4334
    __ faligndata(F60, F62, F60);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4335
    __ faligndata(F62, F48, F48);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4336
    __ mov(to, G1);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4337
    __ and3(to, -8, to);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4338
    __ stpartialf(to, G2, F48, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4339
    __ stf(FloatRegisterImpl::D, F56, to, 8);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4340
    __ stf(FloatRegisterImpl::D, F50, to, 16);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4341
    __ stf(FloatRegisterImpl::D, F60, to, 24);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4342
    __ add(to, 32, to);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4343
    __ orn(G0, G2, G2);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4344
    __ stpartialf(to, G2, F48, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4345
    __ mov(G1, to);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4346
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4347
    __ BIND(L_check_decrypt_loop_end192);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4348
    __ add(from, 32, from);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4349
    __ add(to, 32, to);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4350
    __ subcc(len_reg, 32, len_reg);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4351
    __ br(Assembler::notEqual, false, Assembler::pt, L_dec_next2_blocks192);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4352
    __ delayed()->nop();
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4353
    __ ba_short(L_cbcdec_end);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4354
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4355
    __ align(OptoLoopAlignment);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4356
    __ BIND(L_dec_next2_blocks256);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4357
    __ nop();
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4358
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4359
    // check for 8-byte alignment since source byte array may have an arbitrary alignment if offset mod 8 is non-zero
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4360
    __ andcc(from, 7, G0);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4361
    __ br(Assembler::notZero, true, Assembler::pn, L_load_misaligned_next2_blocks256);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4362
    __ delayed()->mov(from, G1); // save original 'from' address before alignaddr
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4363
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4364
    // aligned case: load input into G4, G5, L4 and L5
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4365
    __ ldx(from,0,G4);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4366
    __ ldx(from,8,G5);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4367
    __ ldx(from,16,L4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4368
    __ ldx(from,24,L5);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4369
    __ ba_short(L_transform_next2_blocks256);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4370
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4371
    __ BIND(L_load_misaligned_next2_blocks256);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4372
    __ alignaddr(from, G0, from);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4373
    // F0, F2, F4, F60, F62 can be clobbered
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4374
    __ ldf(FloatRegisterImpl::D, from, 0, F0);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4375
    __ ldf(FloatRegisterImpl::D, from, 8, F2);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4376
    __ ldf(FloatRegisterImpl::D, from, 16, F60);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4377
    __ ldf(FloatRegisterImpl::D, from, 24, F62);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4378
    __ ldf(FloatRegisterImpl::D, from, 32, F4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4379
    __ faligndata(F0, F2, F0);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4380
    __ faligndata(F2, F60, F2);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4381
    __ faligndata(F60, F62, F60);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4382
    __ faligndata(F62, F4, F62);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4383
    __ movdtox(F0, G4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4384
    __ movdtox(F2, G5);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4385
    __ movdtox(F60, L4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4386
    __ movdtox(F62, L5);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4387
    __ mov(G1, from);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4388
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4389
    __ BIND(L_transform_next2_blocks256);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4390
    // F0:F2 used for first 16-bytes
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4391
    __ xor3(L2,G4,G1);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4392
    __ movxtod(G1,F0);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4393
    __ xor3(L3,G5,G1);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4394
    __ movxtod(G1,F2);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4395
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4396
    // F60:F62 used for next 16-bytes
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4397
    __ xor3(L2,L4,G1);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4398
    __ movxtod(G1,F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4399
    __ xor3(L3,L5,G1);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4400
    __ movxtod(G1,F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4401
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4402
    __ aes_dround23(F54, F0, F2, F4);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4403
    __ aes_dround01(F52, F0, F2, F6);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4404
    __ aes_dround23(F54, F60, F62, F58);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4405
    __ aes_dround01(F52, F60, F62, F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4406
    __ aes_dround23(F50, F6, F4, F2);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4407
    __ aes_dround01(F48, F6, F4, F0);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4408
    __ aes_dround23(F50, F56, F58, F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4409
    __ aes_dround01(F48, F56, F58, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4410
    // save F48:F54 in temp registers
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4411
    __ movdtox(F54,G2);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4412
    __ movdtox(F52,G3);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4413
    __ movdtox(F50,G6);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4414
    __ movdtox(F48,G1);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4415
    for ( int i = 46;  i >= 14; i -= 8 ) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4416
      __ aes_dround23(as_FloatRegister(i), F0, F2, F4);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4417
      __ aes_dround01(as_FloatRegister(i-2), F0, F2, F6);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4418
      __ aes_dround23(as_FloatRegister(i), F60, F62, F58);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4419
      __ aes_dround01(as_FloatRegister(i-2), F60, F62, F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4420
      __ aes_dround23(as_FloatRegister(i-4), F6, F4, F2);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4421
      __ aes_dround01(as_FloatRegister(i-6), F6, F4, F0);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4422
      __ aes_dround23(as_FloatRegister(i-4), F56, F58, F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4423
      __ aes_dround01(as_FloatRegister(i-6), F56, F58, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4424
    }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4425
    // init F48:F54 with F0:F6 values (original key)
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4426
    __ ldf(FloatRegisterImpl::D, original_key, 0, F48);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4427
    __ ldf(FloatRegisterImpl::D, original_key, 8, F50);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4428
    __ ldf(FloatRegisterImpl::D, original_key, 16, F52);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4429
    __ ldf(FloatRegisterImpl::D, original_key, 24, F54);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4430
    __ aes_dround23(F54, F0, F2, F4);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4431
    __ aes_dround01(F52, F0, F2, F6);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4432
    __ aes_dround23(F54, F60, F62, F58);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4433
    __ aes_dround01(F52, F60, F62, F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4434
    __ aes_dround23_l(F50, F6, F4, F2);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4435
    __ aes_dround01_l(F48, F6, F4, F0);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4436
    __ aes_dround23_l(F50, F56, F58, F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4437
    __ aes_dround01_l(F48, F56, F58, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4438
    // re-init F48:F54 with their original values
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4439
    __ movxtod(G2,F54);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4440
    __ movxtod(G3,F52);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4441
    __ movxtod(G6,F50);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4442
    __ movxtod(G1,F48);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4443
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4444
    __ movxtod(L0,F6);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4445
    __ movxtod(L1,F4);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4446
    __ fxor(FloatRegisterImpl::D, F6, F0, F0);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4447
    __ fxor(FloatRegisterImpl::D, F4, F2, F2);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4448
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4449
    __ movxtod(G4,F56);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4450
    __ movxtod(G5,F58);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4451
    __ mov(L4,L0);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4452
    __ mov(L5,L1);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4453
    __ fxor(FloatRegisterImpl::D, F56, F60, F60);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4454
    __ fxor(FloatRegisterImpl::D, F58, F62, F62);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4455
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4456
    // check for 8-byte alignment since dest byte array may have arbitrary alignment if offset mod 8 is non-zero
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4457
    __ andcc(to, 7, G1);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4458
    __ br(Assembler::notZero, true, Assembler::pn, L_store_misaligned_output_next2_blocks256);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4459
    __ delayed()->edge8n(to, G0, G2);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4460
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4461
    // aligned case: store output into the destination array
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4462
    __ stf(FloatRegisterImpl::D, F0, to, 0);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4463
    __ stf(FloatRegisterImpl::D, F2, to, 8);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4464
    __ stf(FloatRegisterImpl::D, F60, to, 16);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4465
    __ stf(FloatRegisterImpl::D, F62, to, 24);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4466
    __ ba_short(L_check_decrypt_loop_end256);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4467
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4468
    __ BIND(L_store_misaligned_output_next2_blocks256);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4469
    __ mov(8, G4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4470
    __ sub(G4, G1, G4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4471
    __ alignaddr(G4, G0, G4);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4472
    __ faligndata(F0, F2, F56); // F56 can be clobbered
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4473
    __ faligndata(F2, F60, F2);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4474
    __ faligndata(F60, F62, F60);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4475
    __ faligndata(F62, F0, F0);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4476
    __ mov(to, G1);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4477
    __ and3(to, -8, to);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4478
    __ stpartialf(to, G2, F0, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4479
    __ stf(FloatRegisterImpl::D, F56, to, 8);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4480
    __ stf(FloatRegisterImpl::D, F2, to, 16);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4481
    __ stf(FloatRegisterImpl::D, F60, to, 24);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4482
    __ add(to, 32, to);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4483
    __ orn(G0, G2, G2);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4484
    __ stpartialf(to, G2, F0, Assembler::ASI_PST8_PRIMARY);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4485
    __ mov(G1, to);
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4486
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4487
    __ BIND(L_check_decrypt_loop_end256);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4488
    __ add(from, 32, from);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4489
    __ add(to, 32, to);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4490
    __ subcc(len_reg, 32, len_reg);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4491
    __ br(Assembler::notEqual, false, Assembler::pt, L_dec_next2_blocks256);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4492
    __ delayed()->nop();
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4493
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4494
    __ BIND(L_cbcdec_end);
24328
bddefb356fba 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 24326
diff changeset
  4495
    // re-init intial vector for next block, 8-byte alignment is guaranteed
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4496
    __ stx(L0, rvec, 0);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4497
    __ stx(L1, rvec, 8);
24488
6872367f4335 8043274: Test compiler/7184394/TestAESMain.java gets NPE on solaris
kvn
parents: 24328
diff changeset
  4498
    __ mov(L7, I0);
6872367f4335 8043274: Test compiler/7184394/TestAESMain.java gets NPE on solaris
kvn
parents: 24328
diff changeset
  4499
    __ ret();
6872367f4335 8043274: Test compiler/7184394/TestAESMain.java gets NPE on solaris
kvn
parents: 24328
diff changeset
  4500
    __ delayed()->restore();
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4501
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4502
    return start;
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4503
  }
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  4504
24953
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4505
  address generate_sha1_implCompress(bool multi_block, const char *name) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4506
    __ align(CodeEntryAlignment);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4507
    StubCodeMark mark(this, "StubRoutines", name);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4508
    address start = __ pc();
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4509
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4510
    Label L_sha1_loop, L_sha1_unaligned_input, L_sha1_unaligned_input_loop;
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4511
    int i;
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4512
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4513
    Register buf   = O0; // byte[] source+offset
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4514
    Register state = O1; // int[]  SHA.state
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4515
    Register ofs   = O2; // int    offset
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4516
    Register limit = O3; // int    limit
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4517
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4518
    // load state into F0-F4
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4519
    for (i = 0; i < 5; i++) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4520
      __ ldf(FloatRegisterImpl::S, state, i*4, as_FloatRegister(i));
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4521
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4522
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4523
    __ andcc(buf, 7, G0);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4524
    __ br(Assembler::notZero, false, Assembler::pn, L_sha1_unaligned_input);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4525
    __ delayed()->nop();
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4526
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4527
    __ BIND(L_sha1_loop);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4528
    // load buf into F8-F22
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4529
    for (i = 0; i < 8; i++) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4530
      __ ldf(FloatRegisterImpl::D, buf, i*8, as_FloatRegister(i*2 + 8));
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4531
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4532
    __ sha1();
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4533
    if (multi_block) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4534
      __ add(ofs, 64, ofs);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4535
      __ add(buf, 64, buf);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4536
      __ cmp_and_brx_short(ofs, limit, Assembler::lessEqual, Assembler::pt, L_sha1_loop);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4537
      __ mov(ofs, O0); // to be returned
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4538
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4539
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4540
    // store F0-F4 into state and return
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4541
    for (i = 0; i < 4; i++) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4542
      __ stf(FloatRegisterImpl::S, as_FloatRegister(i), state, i*4);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4543
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4544
    __ retl();
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4545
    __ delayed()->stf(FloatRegisterImpl::S, F4, state, 0x10);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4546
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4547
    __ BIND(L_sha1_unaligned_input);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4548
    __ alignaddr(buf, G0, buf);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4549
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4550
    __ BIND(L_sha1_unaligned_input_loop);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4551
    // load buf into F8-F22
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4552
    for (i = 0; i < 9; i++) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4553
      __ ldf(FloatRegisterImpl::D, buf, i*8, as_FloatRegister(i*2 + 8));
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4554
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4555
    for (i = 0; i < 8; i++) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4556
      __ faligndata(as_FloatRegister(i*2 + 8), as_FloatRegister(i*2 + 10), as_FloatRegister(i*2 + 8));
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4557
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4558
    __ sha1();
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4559
    if (multi_block) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4560
      __ add(ofs, 64, ofs);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4561
      __ add(buf, 64, buf);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4562
      __ cmp_and_brx_short(ofs, limit, Assembler::lessEqual, Assembler::pt, L_sha1_unaligned_input_loop);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4563
      __ mov(ofs, O0); // to be returned
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4564
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4565
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4566
    // store F0-F4 into state and return
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4567
    for (i = 0; i < 4; i++) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4568
      __ stf(FloatRegisterImpl::S, as_FloatRegister(i), state, i*4);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4569
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4570
    __ retl();
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4571
    __ delayed()->stf(FloatRegisterImpl::S, F4, state, 0x10);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4572
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4573
    return start;
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4574
  }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4575
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4576
  address generate_sha256_implCompress(bool multi_block, const char *name) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4577
    __ align(CodeEntryAlignment);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4578
    StubCodeMark mark(this, "StubRoutines", name);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4579
    address start = __ pc();
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4580
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4581
    Label L_sha256_loop, L_sha256_unaligned_input, L_sha256_unaligned_input_loop;
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4582
    int i;
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4583
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4584
    Register buf   = O0; // byte[] source+offset
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4585
    Register state = O1; // int[]  SHA2.state
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4586
    Register ofs   = O2; // int    offset
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4587
    Register limit = O3; // int    limit
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4588
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4589
    // load state into F0-F7
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4590
    for (i = 0; i < 8; i++) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4591
      __ ldf(FloatRegisterImpl::S, state, i*4, as_FloatRegister(i));
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4592
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4593
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4594
    __ andcc(buf, 7, G0);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4595
    __ br(Assembler::notZero, false, Assembler::pn, L_sha256_unaligned_input);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4596
    __ delayed()->nop();
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4597
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4598
    __ BIND(L_sha256_loop);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4599
    // load buf into F8-F22
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4600
    for (i = 0; i < 8; i++) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4601
      __ ldf(FloatRegisterImpl::D, buf, i*8, as_FloatRegister(i*2 + 8));
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4602
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4603
    __ sha256();
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4604
    if (multi_block) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4605
      __ add(ofs, 64, ofs);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4606
      __ add(buf, 64, buf);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4607
      __ cmp_and_brx_short(ofs, limit, Assembler::lessEqual, Assembler::pt, L_sha256_loop);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4608
      __ mov(ofs, O0); // to be returned
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4609
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4610
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4611
    // store F0-F7 into state and return
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4612
    for (i = 0; i < 7; i++) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4613
      __ stf(FloatRegisterImpl::S, as_FloatRegister(i), state, i*4);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4614
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4615
    __ retl();
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4616
    __ delayed()->stf(FloatRegisterImpl::S, F7, state, 0x1c);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4617
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4618
    __ BIND(L_sha256_unaligned_input);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4619
    __ alignaddr(buf, G0, buf);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4620
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4621
    __ BIND(L_sha256_unaligned_input_loop);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4622
    // load buf into F8-F22
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4623
    for (i = 0; i < 9; i++) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4624
      __ ldf(FloatRegisterImpl::D, buf, i*8, as_FloatRegister(i*2 + 8));
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4625
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4626
    for (i = 0; i < 8; i++) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4627
      __ faligndata(as_FloatRegister(i*2 + 8), as_FloatRegister(i*2 + 10), as_FloatRegister(i*2 + 8));
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4628
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4629
    __ sha256();
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4630
    if (multi_block) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4631
      __ add(ofs, 64, ofs);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4632
      __ add(buf, 64, buf);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4633
      __ cmp_and_brx_short(ofs, limit, Assembler::lessEqual, Assembler::pt, L_sha256_unaligned_input_loop);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4634
      __ mov(ofs, O0); // to be returned
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4635
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4636
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4637
    // store F0-F7 into state and return
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4638
    for (i = 0; i < 7; i++) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4639
      __ stf(FloatRegisterImpl::S, as_FloatRegister(i), state, i*4);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4640
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4641
    __ retl();
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4642
    __ delayed()->stf(FloatRegisterImpl::S, F7, state, 0x1c);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4643
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4644
    return start;
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4645
  }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4646
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4647
  address generate_sha512_implCompress(bool multi_block, const char *name) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4648
    __ align(CodeEntryAlignment);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4649
    StubCodeMark mark(this, "StubRoutines", name);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4650
    address start = __ pc();
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4651
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4652
    Label L_sha512_loop, L_sha512_unaligned_input, L_sha512_unaligned_input_loop;
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4653
    int i;
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4654
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4655
    Register buf   = O0; // byte[] source+offset
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4656
    Register state = O1; // long[] SHA5.state
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4657
    Register ofs   = O2; // int    offset
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4658
    Register limit = O3; // int    limit
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4659
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4660
    // load state into F0-F14
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4661
    for (i = 0; i < 8; i++) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4662
      __ ldf(FloatRegisterImpl::D, state, i*8, as_FloatRegister(i*2));
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4663
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4664
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4665
    __ andcc(buf, 7, G0);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4666
    __ br(Assembler::notZero, false, Assembler::pn, L_sha512_unaligned_input);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4667
    __ delayed()->nop();
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4668
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4669
    __ BIND(L_sha512_loop);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4670
    // load buf into F16-F46
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4671
    for (i = 0; i < 16; i++) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4672
      __ ldf(FloatRegisterImpl::D, buf, i*8, as_FloatRegister(i*2 + 16));
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4673
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4674
    __ sha512();
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4675
    if (multi_block) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4676
      __ add(ofs, 128, ofs);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4677
      __ add(buf, 128, buf);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4678
      __ cmp_and_brx_short(ofs, limit, Assembler::lessEqual, Assembler::pt, L_sha512_loop);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4679
      __ mov(ofs, O0); // to be returned
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4680
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4681
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4682
    // store F0-F14 into state and return
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4683
    for (i = 0; i < 7; i++) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4684
      __ stf(FloatRegisterImpl::D, as_FloatRegister(i*2), state, i*8);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4685
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4686
    __ retl();
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4687
    __ delayed()->stf(FloatRegisterImpl::D, F14, state, 0x38);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4688
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4689
    __ BIND(L_sha512_unaligned_input);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4690
    __ alignaddr(buf, G0, buf);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4691
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4692
    __ BIND(L_sha512_unaligned_input_loop);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4693
    // load buf into F16-F46
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4694
    for (i = 0; i < 17; i++) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4695
      __ ldf(FloatRegisterImpl::D, buf, i*8, as_FloatRegister(i*2 + 16));
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4696
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4697
    for (i = 0; i < 16; i++) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4698
      __ faligndata(as_FloatRegister(i*2 + 16), as_FloatRegister(i*2 + 18), as_FloatRegister(i*2 + 16));
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4699
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4700
    __ sha512();
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4701
    if (multi_block) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4702
      __ add(ofs, 128, ofs);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4703
      __ add(buf, 128, buf);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4704
      __ cmp_and_brx_short(ofs, limit, Assembler::lessEqual, Assembler::pt, L_sha512_unaligned_input_loop);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4705
      __ mov(ofs, O0); // to be returned
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4706
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4707
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4708
    // store F0-F14 into state and return
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4709
    for (i = 0; i < 7; i++) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4710
      __ stf(FloatRegisterImpl::D, as_FloatRegister(i*2), state, i*8);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4711
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4712
    __ retl();
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4713
    __ delayed()->stf(FloatRegisterImpl::D, F14, state, 0x38);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4714
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4715
    return start;
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4716
  }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  4717
31404
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4718
  /* Single and multi-block ghash operations */
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4719
  address generate_ghash_processBlocks() {
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4720
      __ align(CodeEntryAlignment);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4721
      Label L_ghash_loop, L_aligned, L_main;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4722
      StubCodeMark mark(this, "StubRoutines", "ghash_processBlocks");
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4723
      address start = __ pc();
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4724
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4725
      Register state = I0;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4726
      Register subkeyH = I1;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4727
      Register data = I2;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4728
      Register len = I3;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4729
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4730
      __ save_frame(0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4731
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4732
      __ ldx(state, 0, O0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4733
      __ ldx(state, 8, O1);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4734
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4735
      // Loop label for multiblock operations
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4736
      __ BIND(L_ghash_loop);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4737
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4738
      // Check if 'data' is unaligned
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4739
      __ andcc(data, 7, G1);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4740
      __ br(Assembler::zero, false, Assembler::pt, L_aligned);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4741
      __ delayed()->nop();
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4742
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4743
      Register left_shift = L1;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4744
      Register right_shift = L2;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4745
      Register data_ptr = L3;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4746
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4747
      // Get left and right shift values in bits
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4748
      __ sll(G1, LogBitsPerByte, left_shift);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4749
      __ mov(64, right_shift);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4750
      __ sub(right_shift, left_shift, right_shift);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4751
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4752
      // Align to read 'data'
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4753
      __ sub(data, G1, data_ptr);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4754
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4755
      // Load first 8 bytes of 'data'
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4756
      __ ldx(data_ptr, 0, O4);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4757
      __ sllx(O4, left_shift, O4);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4758
      __ ldx(data_ptr, 8, O5);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4759
      __ srlx(O5, right_shift, G4);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4760
      __ bset(G4, O4);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4761
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4762
      // Load second 8 bytes of 'data'
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4763
      __ sllx(O5, left_shift, O5);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4764
      __ ldx(data_ptr, 16, G4);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4765
      __ srlx(G4, right_shift, G4);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4766
      __ ba(L_main);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4767
      __ delayed()->bset(G4, O5);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4768
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4769
      // If 'data' is aligned, load normally
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4770
      __ BIND(L_aligned);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4771
      __ ldx(data, 0, O4);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4772
      __ ldx(data, 8, O5);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4773
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4774
      __ BIND(L_main);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4775
      __ ldx(subkeyH, 0, O2);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4776
      __ ldx(subkeyH, 8, O3);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4777
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4778
      __ xor3(O0, O4, O0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4779
      __ xor3(O1, O5, O1);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4780
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4781
      __ xmulxhi(O0, O3, G3);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4782
      __ xmulx(O0, O2, O5);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4783
      __ xmulxhi(O1, O2, G4);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4784
      __ xmulxhi(O1, O3, G5);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4785
      __ xmulx(O0, O3, G1);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4786
      __ xmulx(O1, O3, G2);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4787
      __ xmulx(O1, O2, O3);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4788
      __ xmulxhi(O0, O2, O4);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4789
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4790
      __ mov(0xE1, O0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4791
      __ sllx(O0, 56, O0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4792
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4793
      __ xor3(O5, G3, O5);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4794
      __ xor3(O5, G4, O5);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4795
      __ xor3(G5, G1, G1);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4796
      __ xor3(G1, O3, G1);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4797
      __ srlx(G2, 63, O1);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4798
      __ srlx(G1, 63, G3);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4799
      __ sllx(G2, 63, O3);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4800
      __ sllx(G2, 58, O2);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4801
      __ xor3(O3, O2, O2);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4802
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4803
      __ sllx(G1, 1, G1);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4804
      __ or3(G1, O1, G1);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4805
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4806
      __ xor3(G1, O2, G1);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4807
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4808
      __ sllx(G2, 1, G2);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4809
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4810
      __ xmulxhi(G1, O0, O1);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4811
      __ xmulx(G1, O0, O2);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4812
      __ xmulxhi(G2, O0, O3);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4813
      __ xmulx(G2, O0, G1);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4814
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4815
      __ xor3(O4, O1, O4);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4816
      __ xor3(O5, O2, O5);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4817
      __ xor3(O5, O3, O5);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4818
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4819
      __ sllx(O4, 1, O2);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4820
      __ srlx(O5, 63, O3);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4821
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4822
      __ or3(O2, O3, O0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4823
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4824
      __ sllx(O5, 1, O1);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4825
      __ srlx(G1, 63, O2);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4826
      __ or3(O1, O2, O1);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4827
      __ xor3(O1, G3, O1);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4828
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4829
      __ deccc(len);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4830
      __ br(Assembler::notZero, true, Assembler::pt, L_ghash_loop);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4831
      __ delayed()->add(data, 16, data);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4832
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4833
      __ stx(O0, I0, 0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4834
      __ stx(O1, I0, 8);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4835
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4836
      __ ret();
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4837
      __ delayed()->restore();
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4838
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4839
      return start;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4840
  }
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  4841
31515
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4842
  /**
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4843
   *  Arguments:
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4844
   *
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4845
   * Inputs:
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4846
   *   O0   - int   crc
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4847
   *   O1   - byte* buf
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4848
   *   O2   - int   len
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4849
   *   O3   - int*  table
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4850
   *
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4851
   * Output:
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4852
   *   O0   - int crc result
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4853
   */
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4854
  address generate_updateBytesCRC32C() {
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4855
    assert(UseCRC32CIntrinsics, "need CRC32C instruction");
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4856
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4857
    __ align(CodeEntryAlignment);
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4858
    StubCodeMark mark(this, "StubRoutines", "updateBytesCRC32C");
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4859
    address start = __ pc();
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4860
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4861
    const Register crc   = O0;  // crc
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4862
    const Register buf   = O1;  // source java byte array address
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4863
    const Register len   = O2;  // number of bytes
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4864
    const Register table = O3;  // byteTable
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4865
38237
d972e3a2df53 8155162: java.util.zip.CRC32C Interpreter/C1 intrinsics support on SPARC
kvn
parents: 37466
diff changeset
  4866
    __ kernel_crc32c(crc, buf, len, table);
d972e3a2df53 8155162: java.util.zip.CRC32C Interpreter/C1 intrinsics support on SPARC
kvn
parents: 37466
diff changeset
  4867
31515
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4868
    __ retl();
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4869
    __ delayed()->nop();
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4870
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4871
    return start;
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4872
  }
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
  4873
32581
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4874
#define ADLER32_NUM_TEMPS 16
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4875
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4876
  /**
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4877
   *  Arguments:
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4878
   *
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4879
   * Inputs:
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4880
   *   O0   - int   adler
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4881
   *   O1   - byte* buff
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4882
   *   O2   - int   len
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4883
   *
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4884
   * Output:
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4885
   *   O0   - int adler result
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4886
   */
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4887
  address generate_updateBytesAdler32() {
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4888
    __ align(CodeEntryAlignment);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4889
    StubCodeMark mark(this, "StubRoutines", "updateBytesAdler32");
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4890
    address start = __ pc();
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4891
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4892
    Label L_cleanup_loop, L_cleanup_loop_check;
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4893
    Label L_main_loop_check, L_main_loop, L_inner_loop, L_inner_loop_check;
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4894
    Label L_nmax_check_done;
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4895
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4896
    // Aliases
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4897
    Register s1     = O0;
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4898
    Register s2     = O3;
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4899
    Register buff   = O1;
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4900
    Register len    = O2;
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4901
    Register temp[ADLER32_NUM_TEMPS] = {L0, L1, L2, L3, L4, L5, L6, L7, I0, I1, I2, I3, I4, I5, G3, I7};
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4902
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4903
    // Max number of bytes we can process before having to take the mod
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4904
    // 0x15B0 is 5552 in decimal, the largest n such that 255n(n+1)/2 + (n+1)(BASE-1) <= 2^32-1
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4905
    unsigned long NMAX = 0x15B0;
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4906
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4907
    // Zero-out the upper bits of len
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4908
    __ clruwu(len);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4909
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4910
    // Create the mask 0xFFFF
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4911
    __ set64(0x00FFFF, O4, O5); // O5 is the temp register
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4912
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4913
    // s1 is initialized to the lower 16 bits of adler
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4914
    // s2 is initialized to the upper 16 bits of adler
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4915
    __ srlx(O0, 16, O5); // adler >> 16
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4916
    __ and3(O0, O4, s1); // s1  = (adler & 0xFFFF)
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4917
    __ and3(O5, O4, s2); // s2  = ((adler >> 16) & 0xFFFF)
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4918
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4919
    // The pipelined loop needs at least 16 elements for 1 iteration
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4920
    // It does check this, but it is more effective to skip to the cleanup loop
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4921
    // Setup the constant for cutoff checking
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4922
    __ mov(15, O4);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4923
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4924
    // Check if we are above the cutoff, if not go to the cleanup loop immediately
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4925
    __ cmp_and_br_short(len, O4, Assembler::lessEqualUnsigned, Assembler::pt, L_cleanup_loop_check);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4926
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4927
    // Free up some registers for our use
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4928
    for (int i = 0; i < ADLER32_NUM_TEMPS; i++) {
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4929
      __ movxtod(temp[i], as_FloatRegister(2*i));
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4930
    }
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4931
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4932
    // Loop maintenance stuff is done at the end of the loop, so skip to there
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4933
    __ ba_short(L_main_loop_check);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4934
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4935
    __ BIND(L_main_loop);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4936
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4937
    // Prologue for inner loop
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4938
    __ ldub(buff, 0, L0);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4939
    __ dec(O5);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4940
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4941
    for (int i = 1; i < 8; i++) {
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4942
      __ ldub(buff, i, temp[i]);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4943
    }
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4944
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4945
    __ inc(buff, 8);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4946
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4947
    // Inner loop processes 16 elements at a time, might never execute if only 16 elements
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4948
    // to be processed by the outter loop
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4949
    __ ba_short(L_inner_loop_check);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4950
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4951
    __ BIND(L_inner_loop);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4952
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4953
    for (int i = 0; i < 8; i++) {
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4954
      __ ldub(buff, (2*i), temp[(8+(2*i)) % ADLER32_NUM_TEMPS]);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4955
      __ add(s1, temp[i], s1);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4956
      __ ldub(buff, (2*i)+1, temp[(8+(2*i)+1) % ADLER32_NUM_TEMPS]);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4957
      __ add(s2, s1, s2);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4958
    }
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4959
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4960
    // Original temp 0-7 used and new loads to temp 0-7 issued
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4961
    // temp 8-15 ready to be consumed
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4962
    __ add(s1, I0, s1);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4963
    __ dec(O5);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4964
    __ add(s2, s1, s2);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4965
    __ add(s1, I1, s1);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4966
    __ inc(buff, 16);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4967
    __ add(s2, s1, s2);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4968
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4969
    for (int i = 0; i < 6; i++) {
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4970
      __ add(s1, temp[10+i], s1);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4971
      __ add(s2, s1, s2);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4972
    }
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4973
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4974
    __ BIND(L_inner_loop_check);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4975
    __ nop();
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4976
    __ cmp_and_br_short(O5, 0, Assembler::notEqual, Assembler::pt, L_inner_loop);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4977
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4978
    // Epilogue
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4979
    for (int i = 0; i < 4; i++) {
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4980
      __ ldub(buff, (2*i), temp[8+(2*i)]);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4981
      __ add(s1, temp[i], s1);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4982
      __ ldub(buff, (2*i)+1, temp[8+(2*i)+1]);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4983
      __ add(s2, s1, s2);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4984
    }
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4985
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4986
    __ add(s1, temp[4], s1);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4987
    __ inc(buff, 8);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4988
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4989
    for (int i = 0; i < 11; i++) {
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4990
      __ add(s2, s1, s2);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4991
      __ add(s1, temp[5+i], s1);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4992
    }
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4993
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4994
    __ add(s2, s1, s2);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4995
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4996
    // Take the mod for s1 and s2
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4997
    __ set64(0xFFF1, L0, L1);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4998
    __ udivx(s1, L0, L1);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  4999
    __ udivx(s2, L0, L2);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5000
    __ mulx(L0, L1, L1);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5001
    __ mulx(L0, L2, L2);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5002
    __ sub(s1, L1, s1);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5003
    __ sub(s2, L2, s2);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5004
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5005
    // Make sure there is something left to process
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5006
    __ BIND(L_main_loop_check);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5007
    __ set64(NMAX, L0, L1);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5008
    // k = len < NMAX ? len : NMAX
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5009
    __ cmp_and_br_short(len, L0, Assembler::greaterEqualUnsigned, Assembler::pt, L_nmax_check_done);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5010
    __ andn(len, 0x0F, L0); // only loop a multiple of 16 times
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5011
    __ BIND(L_nmax_check_done);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5012
    __ mov(L0, O5);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5013
    __ sub(len, L0, len); // len -= k
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5014
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5015
    __ srlx(O5, 4, O5); // multiplies of 16
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5016
    __ cmp_and_br_short(O5, 0, Assembler::notEqual, Assembler::pt, L_main_loop);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5017
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5018
    // Restore anything we used, take the mod one last time, combine and return
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5019
    // Restore any registers we saved
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5020
    for (int i = 0; i < ADLER32_NUM_TEMPS; i++) {
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5021
      __ movdtox(as_FloatRegister(2*i), temp[i]);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5022
    }
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5023
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5024
    // There might be nothing left to process
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5025
    __ ba_short(L_cleanup_loop_check);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5026
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5027
    __ BIND(L_cleanup_loop);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5028
    __ ldub(buff, 0, O4); // load single byte form buffer
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5029
    __ inc(buff); // buff++
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5030
    __ add(s1, O4, s1); // s1 += *buff++;
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5031
    __ dec(len); // len--
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5032
    __ add(s1, s2, s2); // s2 += s1;
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5033
    __ BIND(L_cleanup_loop_check);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5034
    __ nop();
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5035
    __ cmp_and_br_short(len, 0, Assembler::notEqual, Assembler::pt, L_cleanup_loop);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5036
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5037
    // Take the mod one last time
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5038
    __ set64(0xFFF1, O1, O2);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5039
    __ udivx(s1, O1, O2);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5040
    __ udivx(s2, O1, O5);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5041
    __ mulx(O1, O2, O2);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5042
    __ mulx(O1, O5, O5);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5043
    __ sub(s1, O2, s1);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5044
    __ sub(s2, O5, s2);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5045
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5046
    // Combine lower bits and higher bits
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5047
    __ sllx(s2, 16, s2); // s2 = s2 << 16
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5048
    __ or3(s1, s2, s1);  // adler = s2 | s1
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5049
    // Final return value is in O0
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5050
    __ retl();
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5051
    __ delayed()->nop();
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5052
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5053
    return start;
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5054
  }
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5055
34205
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5056
/**
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5057
   *  Arguments:
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5058
   *
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5059
   * Inputs:
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5060
   *   O0   - int   crc
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5061
   *   O1   - byte* buf
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5062
   *   O2   - int   len
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5063
   *   O3   - int*  table
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5064
   *
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5065
   * Output:
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5066
   *   O0   - int crc result
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5067
   */
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5068
  address generate_updateBytesCRC32() {
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5069
    assert(UseCRC32Intrinsics, "need VIS3 instructions");
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5070
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5071
    __ align(CodeEntryAlignment);
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5072
    StubCodeMark mark(this, "StubRoutines", "updateBytesCRC32");
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5073
    address start = __ pc();
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5074
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5075
    const Register crc   = O0; // crc
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5076
    const Register buf   = O1; // source java byte array address
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5077
    const Register len   = O2; // length
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5078
    const Register table = O3; // crc_table address (reuse register)
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5079
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5080
    __ kernel_crc32(crc, buf, len, table);
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5081
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5082
    __ retl();
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5083
    __ delayed()->nop();
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5084
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5085
    return start;
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5086
  }
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5087
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5088
  void generate_initial() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5089
    // Generates all stubs and initializes the entry points
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5090
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5091
    //------------------------------------------------------------------------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5092
    // entry points that exist in all platforms
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5093
    // Note: This is code that could be shared among different platforms - however the benefit seems to be smaller than
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5094
    //       the disadvantage of having a much more complicated generator structure. See also comment in stubRoutines.hpp.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5095
    StubRoutines::_forward_exception_entry                 = generate_forward_exception();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5096
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5097
    StubRoutines::_call_stub_entry                         = generate_call_stub(StubRoutines::_call_stub_return_address);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5098
    StubRoutines::_catch_exception_entry                   = generate_catch_exception();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5099
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5100
    //------------------------------------------------------------------------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5101
    // entry points that are platform specific
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5102
    StubRoutines::Sparc::_test_stop_entry                  = generate_test_stop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5103
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5104
    StubRoutines::Sparc::_stop_subroutine_entry            = generate_stop_subroutine();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5105
    StubRoutines::Sparc::_flush_callers_register_windows_entry = generate_flush_callers_register_windows();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5106
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5107
#if !defined(COMPILER2) && !defined(_LP64)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5108
    StubRoutines::_atomic_xchg_entry         = generate_atomic_xchg();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5109
    StubRoutines::_atomic_cmpxchg_entry      = generate_atomic_cmpxchg();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5110
    StubRoutines::_atomic_add_entry          = generate_atomic_add();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5111
    StubRoutines::_atomic_xchg_ptr_entry     = StubRoutines::_atomic_xchg_entry;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5112
    StubRoutines::_atomic_cmpxchg_ptr_entry  = StubRoutines::_atomic_cmpxchg_entry;
27691
733f189ad1f7 8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents: 24953
diff changeset
  5113
    StubRoutines::_atomic_cmpxchg_byte_entry = ShouldNotCallThisStub();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5114
    StubRoutines::_atomic_cmpxchg_long_entry = generate_atomic_cmpxchg_long();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5115
    StubRoutines::_atomic_add_ptr_entry      = StubRoutines::_atomic_add_entry;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5116
#endif  // COMPILER2 !=> _LP64
10004
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8498
diff changeset
  5117
11411
16b151e1e088 7116216: StackOverflow GC crash
bdelsart
parents: 10566
diff changeset
  5118
    // Build this early so it's available for the interpreter.
35071
a0910b1d3e0d 8046936: JEP 270: Reserved Stack Areas for Critical Sections
fparain
parents: 34205
diff changeset
  5119
    StubRoutines::_throw_StackOverflowError_entry =
a0910b1d3e0d 8046936: JEP 270: Reserved Stack Areas for Critical Sections
fparain
parents: 34205
diff changeset
  5120
            generate_throw_exception("StackOverflowError throw_exception",
a0910b1d3e0d 8046936: JEP 270: Reserved Stack Areas for Critical Sections
fparain
parents: 34205
diff changeset
  5121
            CAST_FROM_FN_PTR(address, SharedRuntime::throw_StackOverflowError));
a0910b1d3e0d 8046936: JEP 270: Reserved Stack Areas for Critical Sections
fparain
parents: 34205
diff changeset
  5122
    StubRoutines::_throw_delayed_StackOverflowError_entry =
a0910b1d3e0d 8046936: JEP 270: Reserved Stack Areas for Critical Sections
fparain
parents: 34205
diff changeset
  5123
            generate_throw_exception("delayed StackOverflowError throw_exception",
a0910b1d3e0d 8046936: JEP 270: Reserved Stack Areas for Critical Sections
fparain
parents: 34205
diff changeset
  5124
            CAST_FROM_FN_PTR(address, SharedRuntime::throw_delayed_StackOverflowError));
34205
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5125
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5126
    if (UseCRC32Intrinsics) {
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5127
      // set table address before stub generation which use it
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5128
      StubRoutines::_crc_table_adr = (address)StubRoutines::Sparc::_crc_table;
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5129
      StubRoutines::_updateBytesCRC32 = generate_updateBytesCRC32();
9ec51d30a11e 8143012: CRC32 Intrinsics support on SPARC
kvn
parents: 32627
diff changeset
  5130
    }
38237
d972e3a2df53 8155162: java.util.zip.CRC32C Interpreter/C1 intrinsics support on SPARC
kvn
parents: 37466
diff changeset
  5131
d972e3a2df53 8155162: java.util.zip.CRC32C Interpreter/C1 intrinsics support on SPARC
kvn
parents: 37466
diff changeset
  5132
    if (UseCRC32CIntrinsics) {
d972e3a2df53 8155162: java.util.zip.CRC32C Interpreter/C1 intrinsics support on SPARC
kvn
parents: 37466
diff changeset
  5133
      // set table address before stub generation which use it
d972e3a2df53 8155162: java.util.zip.CRC32C Interpreter/C1 intrinsics support on SPARC
kvn
parents: 37466
diff changeset
  5134
      StubRoutines::_crc32c_table_addr = (address)StubRoutines::Sparc::_crc32c_table;
d972e3a2df53 8155162: java.util.zip.CRC32C Interpreter/C1 intrinsics support on SPARC
kvn
parents: 37466
diff changeset
  5135
      StubRoutines::_updateBytesCRC32C = generate_updateBytesCRC32C();
d972e3a2df53 8155162: java.util.zip.CRC32C Interpreter/C1 intrinsics support on SPARC
kvn
parents: 37466
diff changeset
  5136
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5137
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5138
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5139
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5140
  void generate_all() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5141
    // Generates all stubs and initializes the entry points
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5142
2254
f13dda645a4b 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 1502
diff changeset
  5143
    // Generate partial_subtype_check first here since its code depends on
f13dda645a4b 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 1502
diff changeset
  5144
    // UseZeroBaseCompressedOops which is defined after heap initialization.
f13dda645a4b 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 1502
diff changeset
  5145
    StubRoutines::Sparc::_partial_subtype_check                = generate_partial_subtype_check();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5146
    // These entry points require SharedInfo::stack0 to be set up in non-core builds
10545
fec876499aae 7088020: SEGV in JNIHandleBlock::release_block
never
parents: 10512
diff changeset
  5147
    StubRoutines::_throw_AbstractMethodError_entry         = generate_throw_exception("AbstractMethodError throw_exception",          CAST_FROM_FN_PTR(address, SharedRuntime::throw_AbstractMethodError));
fec876499aae 7088020: SEGV in JNIHandleBlock::release_block
never
parents: 10512
diff changeset
  5148
    StubRoutines::_throw_IncompatibleClassChangeError_entry= generate_throw_exception("IncompatibleClassChangeError throw_exception", CAST_FROM_FN_PTR(address, SharedRuntime::throw_IncompatibleClassChangeError));
fec876499aae 7088020: SEGV in JNIHandleBlock::release_block
never
parents: 10512
diff changeset
  5149
    StubRoutines::_throw_NullPointerException_at_call_entry= generate_throw_exception("NullPointerException at call throw_exception", CAST_FROM_FN_PTR(address, SharedRuntime::throw_NullPointerException_at_call));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5150
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5151
    // support for verify_oop (must happen after universe_init)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5152
    StubRoutines::_verify_oop_subroutine_entry     = generate_verify_oop_subroutine();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5153
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5154
    // arraycopy stubs used by compilers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5155
    generate_arraycopy_stubs();
4645
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 2571
diff changeset
  5156
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 2571
diff changeset
  5157
    // Don't initialize the platform math functions since sparc
0c5f5b94e93a 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 2571
diff changeset
  5158
    // doesn't have intrinsics for these operations.
18740
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
  5159
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
  5160
    // Safefetch stubs.
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
  5161
    generate_safefetch("SafeFetch32", sizeof(int),     &StubRoutines::_safefetch32_entry,
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
  5162
                                                       &StubRoutines::_safefetch32_fault_pc,
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
  5163
                                                       &StubRoutines::_safefetch32_continuation_pc);
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
  5164
    generate_safefetch("SafeFetchN", sizeof(intptr_t), &StubRoutines::_safefetchN_entry,
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
  5165
                                                       &StubRoutines::_safefetchN_fault_pc,
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18097
diff changeset
  5166
                                                       &StubRoutines::_safefetchN_continuation_pc);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  5167
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  5168
    // generate AES intrinsics code
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  5169
    if (UseAESIntrinsics) {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  5170
      StubRoutines::_aescrypt_encryptBlock = generate_aescrypt_encryptBlock();
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  5171
      StubRoutines::_aescrypt_decryptBlock = generate_aescrypt_decryptBlock();
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  5172
      StubRoutines::_cipherBlockChaining_encryptAESCrypt = generate_cipherBlockChaining_encryptAESCrypt();
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  5173
      StubRoutines::_cipherBlockChaining_decryptAESCrypt = generate_cipherBlockChaining_decryptAESCrypt_Parallel();
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22234
diff changeset
  5174
    }
31404
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  5175
    // generate GHASH intrinsics code
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  5176
    if (UseGHASHIntrinsics) {
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  5177
      StubRoutines::_ghash_processBlocks = generate_ghash_processBlocks();
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 29695
diff changeset
  5178
    }
24953
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  5179
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  5180
    // generate SHA1/SHA256/SHA512 intrinsics code
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  5181
    if (UseSHA1Intrinsics) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  5182
      StubRoutines::_sha1_implCompress     = generate_sha1_implCompress(false,   "sha1_implCompress");
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  5183
      StubRoutines::_sha1_implCompressMB   = generate_sha1_implCompress(true,    "sha1_implCompressMB");
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  5184
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  5185
    if (UseSHA256Intrinsics) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  5186
      StubRoutines::_sha256_implCompress   = generate_sha256_implCompress(false, "sha256_implCompress");
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  5187
      StubRoutines::_sha256_implCompressMB = generate_sha256_implCompress(true,  "sha256_implCompressMB");
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  5188
    }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  5189
    if (UseSHA512Intrinsics) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  5190
      StubRoutines::_sha512_implCompress   = generate_sha512_implCompress(false, "sha512_implCompress");
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  5191
      StubRoutines::_sha512_implCompressMB = generate_sha512_implCompress(true,  "sha512_implCompressMB");
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24488
diff changeset
  5192
    }
32581
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5193
    // generate Adler32 intrinsics code
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5194
    if (UseAdler32Intrinsics) {
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5195
      StubRoutines::_updateBytesAdler32 = generate_updateBytesAdler32();
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31515
diff changeset
  5196
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5197
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5198
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5199
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5200
 public:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5201
  StubGenerator(CodeBuffer* code, bool all) : StubCodeGenerator(code) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5202
    // replace the standard masm with a special one:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5203
    _masm = new MacroAssembler(code);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5204
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5205
    _stub_count = !all ? 0x100 : 0x200;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5206
    if (all) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5207
      generate_all();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5208
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5209
      generate_initial();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5210
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5211
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5212
    // make sure this stub is available for all local calls
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5213
    if (_atomic_add_stub.is_unbound()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5214
      // generate a second time, if necessary
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5215
      (void) generate_atomic_add();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5216
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5217
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5218
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5219
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5220
 private:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5221
  int _stub_count;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5222
  void stub_prolog(StubCodeDesc* cdesc) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5223
    # ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5224
      // put extra information in the stub code, to make it more readable
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5225
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5226
// Write the high part of the address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5227
// [RGV] Check if there is a dependency on the size of this prolog
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5228
      __ emit_data((intptr_t)cdesc >> 32,    relocInfo::none);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5229
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5230
      __ emit_data((intptr_t)cdesc,    relocInfo::none);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5231
      __ emit_data(++_stub_count, relocInfo::none);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5232
    # endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5233
    align(true);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5234
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5235
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5236
  void align(bool at_header = false) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5237
    // %%%%% move this constant somewhere else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5238
    // UltraSPARC cache line size is 8 instructions:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5239
    const unsigned int icache_line_size = 32;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5240
    const unsigned int icache_half_line_size = 16;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5241
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5242
    if (at_header) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5243
      while ((intptr_t)(__ pc()) % icache_line_size != 0) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5244
        __ emit_data(0, relocInfo::none);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5245
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5246
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5247
      while ((intptr_t)(__ pc()) % icache_half_line_size != 0) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5248
        __ nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5249
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5250
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5251
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5252
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5253
}; // end class declaration
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5254
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5255
void StubGenerator_generate(CodeBuffer* code, bool all) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5256
  StubGenerator g(code, all);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5257
}