author | stefank |
Mon, 25 Nov 2019 12:32:40 +0100 | |
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parent 59249 | 29b0d0b61615 |
child 59252 | 623722a6aeb9 |
permissions | -rw-r--r-- |
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/* |
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* Copyright (c) 1999, 2019, Oracle and/or its affiliates. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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||
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#ifndef OS_CPU_WINDOWS_X86_ATOMIC_WINDOWS_X86_HPP |
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#define OS_CPU_WINDOWS_X86_ATOMIC_WINDOWS_X86_HPP |
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#include "runtime/os.hpp" |
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// Note that in MSVC, volatile memory accesses are explicitly |
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// guaranteed to have acquire release semantics (w.r.t. compiler |
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// reordering) and therefore does not even need a compiler barrier |
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// for normal acquire release accesses. And all generalized |
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// bound calls like release_store go through Atomic::load |
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// and Atomic::store which do volatile memory accesses. |
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template<> inline void ScopedFence<X_ACQUIRE>::postfix() { } |
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template<> inline void ScopedFence<RELEASE_X>::prefix() { } |
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template<> inline void ScopedFence<RELEASE_X_FENCE>::prefix() { } |
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template<> inline void ScopedFence<RELEASE_X_FENCE>::postfix() { OrderAccess::fence(); } |
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// The following alternative implementations are needed because |
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// Windows 95 doesn't support (some of) the corresponding Windows NT |
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// calls. Furthermore, these versions allow inlining in the caller. |
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// (More precisely: The documentation for InterlockedExchange says |
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// it is supported for Windows 95. However, when single-stepping |
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// through the assembly code we cannot step into the routine and |
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// when looking at the routine address we see only garbage code. |
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// Better safe then sorry!). Was bug 7/31/98 (gri). |
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// |
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// Performance note: On uniprocessors, the 'lock' prefixes are not |
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// necessary (and expensive). We should generate separate cases if |
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// this becomes a performance problem. |
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#pragma warning(disable: 4035) // Disables warnings reporting missing return statement |
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template<size_t byte_size> |
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struct Atomic::PlatformAdd |
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: Atomic::AddAndFetch<Atomic::PlatformAdd<byte_size> > |
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{ |
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template<typename D, typename I> |
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D add_and_fetch(D volatile* dest, I add_value, atomic_memory_order order) const; |
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}; |
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#ifdef AMD64 |
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template<> |
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template<typename D, typename I> |
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inline D Atomic::PlatformAdd<4>::add_and_fetch(D volatile* dest, I add_value, |
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atomic_memory_order order) const { |
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return add_using_helper<int32_t>(os::atomic_add_func, dest, add_value); |
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} |
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template<> |
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template<typename D, typename I> |
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inline D Atomic::PlatformAdd<8>::add_and_fetch(D volatile* dest, I add_value, |
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atomic_memory_order order) const { |
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return add_using_helper<int64_t>(os::atomic_add_long_func, dest, add_value); |
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} |
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#define DEFINE_STUB_XCHG(ByteSize, StubType, StubName) \ |
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template<> \ |
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template<typename T> \ |
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inline T Atomic::PlatformXchg<ByteSize>::operator()(T volatile* dest, \ |
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T exchange_value, \ |
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atomic_memory_order order) const { \ |
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STATIC_ASSERT(ByteSize == sizeof(T)); \ |
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return xchg_using_helper<StubType>(StubName, dest, exchange_value); \ |
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} |
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DEFINE_STUB_XCHG(4, int32_t, os::atomic_xchg_func) |
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DEFINE_STUB_XCHG(8, int64_t, os::atomic_xchg_long_func) |
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#undef DEFINE_STUB_XCHG |
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#define DEFINE_STUB_CMPXCHG(ByteSize, StubType, StubName) \ |
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template<> \ |
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template<typename T> \ |
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inline T Atomic::PlatformCmpxchg<ByteSize>::operator()(T exchange_value, \ |
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T volatile* dest, \ |
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T compare_value, \ |
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atomic_memory_order order) const { \ |
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STATIC_ASSERT(ByteSize == sizeof(T)); \ |
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return cmpxchg_using_helper<StubType>(StubName, exchange_value, dest, compare_value); \ |
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} |
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DEFINE_STUB_CMPXCHG(1, int8_t, os::atomic_cmpxchg_byte_func) |
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DEFINE_STUB_CMPXCHG(4, int32_t, os::atomic_cmpxchg_func) |
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DEFINE_STUB_CMPXCHG(8, int64_t, os::atomic_cmpxchg_long_func) |
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#undef DEFINE_STUB_CMPXCHG |
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#else // !AMD64 |
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template<> |
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template<typename D, typename I> |
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inline D Atomic::PlatformAdd<4>::add_and_fetch(D volatile* dest, I add_value, |
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atomic_memory_order order) const { |
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STATIC_ASSERT(4 == sizeof(I)); |
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STATIC_ASSERT(4 == sizeof(D)); |
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__asm { |
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mov edx, dest; |
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mov eax, add_value; |
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mov ecx, eax; |
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lock xadd dword ptr [edx], eax; |
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add eax, ecx; |
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} |
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} |
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template<> |
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template<typename T> |
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inline T Atomic::PlatformXchg<4>::operator()(T volatile* dest, |
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T exchange_value, |
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atomic_memory_order order) const { |
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STATIC_ASSERT(4 == sizeof(T)); |
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// alternative for InterlockedExchange |
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__asm { |
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mov eax, exchange_value; |
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mov ecx, dest; |
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xchg eax, dword ptr [ecx]; |
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} |
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} |
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template<> |
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template<typename T> |
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inline T Atomic::PlatformCmpxchg<1>::operator()(T exchange_value, |
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T volatile* dest, |
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T compare_value, |
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atomic_memory_order order) const { |
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STATIC_ASSERT(1 == sizeof(T)); |
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// alternative for InterlockedCompareExchange |
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__asm { |
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mov edx, dest |
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mov cl, exchange_value |
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mov al, compare_value |
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lock cmpxchg byte ptr [edx], cl |
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} |
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} |
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template<> |
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template<typename T> |
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inline T Atomic::PlatformCmpxchg<4>::operator()(T exchange_value, |
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T volatile* dest, |
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T compare_value, |
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atomic_memory_order order) const { |
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STATIC_ASSERT(4 == sizeof(T)); |
1 | 165 |
// alternative for InterlockedCompareExchange |
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__asm { |
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167 |
mov edx, dest |
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168 |
mov ecx, exchange_value |
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mov eax, compare_value |
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lock cmpxchg dword ptr [edx], ecx |
1 | 171 |
} |
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} |
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template<> |
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template<typename T> |
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inline T Atomic::PlatformCmpxchg<8>::operator()(T exchange_value, |
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T volatile* dest, |
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T compare_value, |
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atomic_memory_order order) const { |
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STATIC_ASSERT(8 == sizeof(T)); |
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int32_t ex_lo = (int32_t)exchange_value; |
182 |
int32_t ex_hi = *( ((int32_t*)&exchange_value) + 1 ); |
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int32_t cmp_lo = (int32_t)compare_value; |
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int32_t cmp_hi = *( ((int32_t*)&compare_value) + 1 ); |
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__asm { |
186 |
push ebx |
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187 |
push edi |
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mov eax, cmp_lo |
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mov edx, cmp_hi |
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mov edi, dest |
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mov ebx, ex_lo |
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mov ecx, ex_hi |
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lock cmpxchg8b qword ptr [edi] |
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pop edi |
195 |
pop ebx |
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196 |
} |
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} |
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198 |
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template<> |
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template<typename T> |
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inline T Atomic::PlatformLoad<8>::operator()(T const volatile* src) const { |
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STATIC_ASSERT(8 == sizeof(T)); |
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volatile T dest; |
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volatile T* pdest = &dest; |
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__asm { |
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mov eax, src |
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fild qword ptr [eax] |
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mov eax, pdest |
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fistp qword ptr [eax] |
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210 |
} |
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return dest; |
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212 |
} |
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213 |
|
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template<> |
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template<typename T> |
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216 |
inline void Atomic::PlatformStore<8>::operator()(T volatile* dest, |
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T store_value) const { |
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STATIC_ASSERT(8 == sizeof(T)); |
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volatile T* src = &store_value; |
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__asm { |
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mov eax, src |
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fild qword ptr [eax] |
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mov eax, dest |
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fistp qword ptr [eax] |
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225 |
} |
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226 |
} |
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227 |
|
1 | 228 |
#endif // AMD64 |
229 |
||
230 |
#pragma warning(default: 4035) // Enables warnings reporting missing return statement |
|
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232 |
#ifndef AMD64 |
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233 |
template<> |
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234 |
struct Atomic::PlatformOrderedStore<1, RELEASE_X_FENCE> |
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235 |
{ |
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236 |
template <typename T> |
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237 |
void operator()(volatile T* p, T v) const { |
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238 |
__asm { |
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239 |
mov edx, p; |
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240 |
mov al, v; |
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241 |
xchg al, byte ptr [edx]; |
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242 |
} |
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243 |
} |
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244 |
}; |
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245 |
|
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246 |
template<> |
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247 |
struct Atomic::PlatformOrderedStore<2, RELEASE_X_FENCE> |
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248 |
{ |
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249 |
template <typename T> |
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250 |
void operator()(volatile T* p, T v) const { |
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251 |
__asm { |
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252 |
mov edx, p; |
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253 |
mov ax, v; |
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254 |
xchg ax, word ptr [edx]; |
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255 |
} |
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256 |
} |
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257 |
}; |
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258 |
|
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259 |
template<> |
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260 |
struct Atomic::PlatformOrderedStore<4, RELEASE_X_FENCE> |
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261 |
{ |
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262 |
template <typename T> |
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263 |
void operator()(volatile T* p, T v) const { |
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264 |
__asm { |
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265 |
mov edx, p; |
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266 |
mov eax, v; |
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267 |
xchg eax, dword ptr [edx]; |
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268 |
} |
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269 |
} |
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270 |
}; |
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271 |
#endif // AMD64 |
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272 |
|
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273 |
#endif // OS_CPU_WINDOWS_X86_ATOMIC_WINDOWS_X86_HPP |