author | dchuyko |
Tue, 19 Jun 2018 19:21:30 +0300 | |
changeset 50644 | 409bfb0c071e |
parent 50641 | 66aa15778c5a |
child 50693 | db0a17475826 |
permissions | -rw-r--r-- |
29183 | 1 |
/* |
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* Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. |
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* Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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||
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#include <sys/types.h> |
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||
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#include "precompiled.hpp" |
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#include "jvm.h" |
29183 | 30 |
#include "asm/assembler.hpp" |
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#include "asm/assembler.inline.hpp" |
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49754 | 32 |
#include "gc/shared/barrierSet.hpp" |
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#include "gc/shared/cardTable.hpp" |
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#include "gc/shared/barrierSetAssembler.hpp" |
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#include "gc/shared/cardTableBarrierSet.hpp" |
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#include "interpreter/interpreter.hpp" |
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#include "compiler/disassembler.hpp" |
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#include "memory/resourceArea.hpp" |
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#include "nativeInst_aarch64.hpp" |
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#include "oops/accessDecorators.hpp" |
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#include "oops/compressedOops.inline.hpp" |
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#include "oops/klass.inline.hpp" |
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#include "oops/oop.hpp" |
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#include "opto/compile.hpp" |
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#include "opto/intrinsicnode.hpp" |
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#include "opto/node.hpp" |
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#include "runtime/biasedLocking.hpp" |
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#include "runtime/icache.hpp" |
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#include "runtime/interfaceSupport.inline.hpp" |
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#include "runtime/jniHandles.inline.hpp" |
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#include "runtime/sharedRuntime.hpp" |
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#include "runtime/thread.hpp" |
29183 | 53 |
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#ifdef PRODUCT |
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#define BLOCK_COMMENT(str) /* nothing */ |
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#define STOP(error) stop(error) |
|
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#else |
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#define BLOCK_COMMENT(str) block_comment(str) |
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#define STOP(error) block_comment(error); stop(error) |
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#endif |
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||
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#define BIND(label) bind(label); BLOCK_COMMENT(#label ":") |
|
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||
64 |
// Patch any kind of instruction; there may be several instructions. |
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// Return the total length (in bytes) of the instructions. |
|
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int MacroAssembler::pd_patch_instruction_size(address branch, address target) { |
|
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int instructions = 1; |
|
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assert((uint64_t)target < (1ul << 48), "48-bit overflow in address constant"); |
|
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long offset = (target - branch) >> 2; |
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unsigned insn = *(unsigned*)branch; |
|
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if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) { |
|
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// Load register (literal) |
|
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Instruction_aarch64::spatch(branch, 23, 5, offset); |
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} else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) { |
|
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// Unconditional branch (immediate) |
|
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Instruction_aarch64::spatch(branch, 25, 0, offset); |
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} else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) { |
|
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// Conditional branch (immediate) |
|
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Instruction_aarch64::spatch(branch, 23, 5, offset); |
|
80 |
} else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) { |
|
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// Compare & branch (immediate) |
|
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Instruction_aarch64::spatch(branch, 23, 5, offset); |
|
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} else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) { |
|
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// Test & branch (immediate) |
|
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Instruction_aarch64::spatch(branch, 18, 5, offset); |
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} else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) { |
|
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// PC-rel. addressing |
|
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offset = target-branch; |
|
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int shift = Instruction_aarch64::extract(insn, 31, 31); |
|
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if (shift) { |
|
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u_int64_t dest = (u_int64_t)target; |
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uint64_t pc_page = (uint64_t)branch >> 12; |
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uint64_t adr_page = (uint64_t)target >> 12; |
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unsigned offset_lo = dest & 0xfff; |
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offset = adr_page - pc_page; |
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||
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// We handle 4 types of PC relative addressing |
29183 | 98 |
// 1 - adrp Rx, target_page |
99 |
// ldr/str Ry, [Rx, #offset_in_page] |
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// 2 - adrp Rx, target_page |
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// add Ry, Rx, #offset_in_page |
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// 3 - adrp Rx, target_page (page aligned reloc, offset == 0) |
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// movk Rx, #imm16<<32 |
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// 4 - adrp Rx, target_page (page aligned reloc, offset == 0) |
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// In the first 3 cases we must check that Rx is the same in the adrp and the |
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// subsequent ldr/str, add or movk instruction. Otherwise we could accidentally end |
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// up treating a type 4 relocation as a type 1, 2 or 3 just because it happened |
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// to be followed by a random unrelated ldr/str, add or movk instruction. |
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// |
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unsigned insn2 = ((unsigned*)branch)[1]; |
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if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 && |
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Instruction_aarch64::extract(insn, 4, 0) == |
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Instruction_aarch64::extract(insn2, 9, 5)) { |
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// Load/store register (unsigned immediate) |
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unsigned size = Instruction_aarch64::extract(insn2, 31, 30); |
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Instruction_aarch64::patch(branch + sizeof (unsigned), |
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21, 10, offset_lo >> size); |
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guarantee(((dest >> size) << size) == dest, "misaligned target"); |
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instructions = 2; |
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} else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 && |
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Instruction_aarch64::extract(insn, 4, 0) == |
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Instruction_aarch64::extract(insn2, 4, 0)) { |
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// add (immediate) |
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Instruction_aarch64::patch(branch + sizeof (unsigned), |
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21, 10, offset_lo); |
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instructions = 2; |
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} else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 && |
128 |
Instruction_aarch64::extract(insn, 4, 0) == |
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Instruction_aarch64::extract(insn2, 4, 0)) { |
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// movk #imm16<<32 |
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Instruction_aarch64::patch(branch + 4, 20, 5, (uint64_t)target >> 32); |
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long dest = ((long)target & 0xffffffffL) | ((long)branch & 0xffff00000000L); |
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long pc_page = (long)branch >> 12; |
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long adr_page = (long)dest >> 12; |
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offset = adr_page - pc_page; |
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instructions = 2; |
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} |
138 |
} |
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int offset_lo = offset & 3; |
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offset >>= 2; |
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Instruction_aarch64::spatch(branch, 23, 5, offset); |
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Instruction_aarch64::patch(branch, 30, 29, offset_lo); |
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} else if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010100) { |
|
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u_int64_t dest = (u_int64_t)target; |
|
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// Move wide constant |
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assert(nativeInstruction_at(branch+4)->is_movk(), "wrong insns in patch"); |
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assert(nativeInstruction_at(branch+8)->is_movk(), "wrong insns in patch"); |
|
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Instruction_aarch64::patch(branch, 20, 5, dest & 0xffff); |
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Instruction_aarch64::patch(branch+4, 20, 5, (dest >>= 16) & 0xffff); |
|
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Instruction_aarch64::patch(branch+8, 20, 5, (dest >>= 16) & 0xffff); |
|
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assert(target_addr_for_insn(branch) == target, "should be"); |
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instructions = 3; |
|
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} else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 && |
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Instruction_aarch64::extract(insn, 4, 0) == 0b11111) { |
|
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// nothing to do |
|
156 |
assert(target == 0, "did not expect to relocate target for polling page load"); |
|
157 |
} else { |
|
158 |
ShouldNotReachHere(); |
|
159 |
} |
|
160 |
return instructions * NativeInstruction::instruction_size; |
|
161 |
} |
|
162 |
||
163 |
int MacroAssembler::patch_oop(address insn_addr, address o) { |
|
164 |
int instructions; |
|
165 |
unsigned insn = *(unsigned*)insn_addr; |
|
166 |
assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch"); |
|
167 |
||
168 |
// OOPs are either narrow (32 bits) or wide (48 bits). We encode |
|
169 |
// narrow OOPs by setting the upper 16 bits in the first |
|
170 |
// instruction. |
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if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) { |
|
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// Move narrow OOP |
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narrowOop n = CompressedOops::encode((oop)o); |
29183 | 174 |
Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16); |
175 |
Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff); |
|
176 |
instructions = 2; |
|
177 |
} else { |
|
178 |
// Move wide OOP |
|
179 |
assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch"); |
|
180 |
uintptr_t dest = (uintptr_t)o; |
|
181 |
Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff); |
|
182 |
Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff); |
|
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Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff); |
|
184 |
instructions = 3; |
|
185 |
} |
|
186 |
return instructions * NativeInstruction::instruction_size; |
|
187 |
} |
|
188 |
||
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int MacroAssembler::patch_narrow_klass(address insn_addr, narrowKlass n) { |
190 |
// Metatdata pointers are either narrow (32 bits) or wide (48 bits). |
|
191 |
// We encode narrow ones by setting the upper 16 bits in the first |
|
192 |
// instruction. |
|
193 |
NativeInstruction *insn = nativeInstruction_at(insn_addr); |
|
194 |
assert(Instruction_aarch64::extract(insn->encoding(), 31, 21) == 0b11010010101 && |
|
195 |
nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch"); |
|
196 |
||
197 |
Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16); |
|
198 |
Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff); |
|
199 |
return 2 * NativeInstruction::instruction_size; |
|
200 |
} |
|
201 |
||
29183 | 202 |
address MacroAssembler::target_addr_for_insn(address insn_addr, unsigned insn) { |
203 |
long offset = 0; |
|
204 |
if ((Instruction_aarch64::extract(insn, 29, 24) & 0b011011) == 0b00011000) { |
|
205 |
// Load register (literal) |
|
206 |
offset = Instruction_aarch64::sextract(insn, 23, 5); |
|
207 |
return address(((uint64_t)insn_addr + (offset << 2))); |
|
208 |
} else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) { |
|
209 |
// Unconditional branch (immediate) |
|
210 |
offset = Instruction_aarch64::sextract(insn, 25, 0); |
|
211 |
} else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) { |
|
212 |
// Conditional branch (immediate) |
|
213 |
offset = Instruction_aarch64::sextract(insn, 23, 5); |
|
214 |
} else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) { |
|
215 |
// Compare & branch (immediate) |
|
216 |
offset = Instruction_aarch64::sextract(insn, 23, 5); |
|
217 |
} else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) { |
|
218 |
// Test & branch (immediate) |
|
219 |
offset = Instruction_aarch64::sextract(insn, 18, 5); |
|
220 |
} else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) { |
|
221 |
// PC-rel. addressing |
|
222 |
offset = Instruction_aarch64::extract(insn, 30, 29); |
|
223 |
offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2; |
|
224 |
int shift = Instruction_aarch64::extract(insn, 31, 31) ? 12 : 0; |
|
225 |
if (shift) { |
|
226 |
offset <<= shift; |
|
227 |
uint64_t target_page = ((uint64_t)insn_addr) + offset; |
|
228 |
target_page &= ((uint64_t)-1) << shift; |
|
229 |
// Return the target address for the following sequences |
|
230 |
// 1 - adrp Rx, target_page |
|
231 |
// ldr/str Ry, [Rx, #offset_in_page] |
|
34206 | 232 |
// 2 - adrp Rx, target_page |
29183 | 233 |
// add Ry, Rx, #offset_in_page |
234 |
// 3 - adrp Rx, target_page (page aligned reloc, offset == 0) |
|
34206 | 235 |
// movk Rx, #imm12<<32 |
236 |
// 4 - adrp Rx, target_page (page aligned reloc, offset == 0) |
|
29183 | 237 |
// |
238 |
// In the first two cases we check that the register is the same and |
|
239 |
// return the target_page + the offset within the page. |
|
240 |
// Otherwise we assume it is a page aligned relocation and return |
|
34206 | 241 |
// the target page only. |
29183 | 242 |
// |
243 |
unsigned insn2 = ((unsigned*)insn_addr)[1]; |
|
244 |
if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 && |
|
245 |
Instruction_aarch64::extract(insn, 4, 0) == |
|
246 |
Instruction_aarch64::extract(insn2, 9, 5)) { |
|
247 |
// Load/store register (unsigned immediate) |
|
248 |
unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10); |
|
249 |
unsigned int size = Instruction_aarch64::extract(insn2, 31, 30); |
|
250 |
return address(target_page + (byte_offset << size)); |
|
251 |
} else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 && |
|
252 |
Instruction_aarch64::extract(insn, 4, 0) == |
|
253 |
Instruction_aarch64::extract(insn2, 4, 0)) { |
|
254 |
// add (immediate) |
|
255 |
unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10); |
|
256 |
return address(target_page + byte_offset); |
|
257 |
} else { |
|
34206 | 258 |
if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 && |
259 |
Instruction_aarch64::extract(insn, 4, 0) == |
|
260 |
Instruction_aarch64::extract(insn2, 4, 0)) { |
|
261 |
target_page = (target_page & 0xffffffff) | |
|
262 |
((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32); |
|
263 |
} |
|
29183 | 264 |
return (address)target_page; |
265 |
} |
|
266 |
} else { |
|
267 |
ShouldNotReachHere(); |
|
268 |
} |
|
269 |
} else if (Instruction_aarch64::extract(insn, 31, 23) == 0b110100101) { |
|
270 |
u_int32_t *insns = (u_int32_t *)insn_addr; |
|
271 |
// Move wide constant: movz, movk, movk. See movptr(). |
|
272 |
assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch"); |
|
273 |
assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch"); |
|
274 |
return address(u_int64_t(Instruction_aarch64::extract(insns[0], 20, 5)) |
|
275 |
+ (u_int64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16) |
|
276 |
+ (u_int64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32)); |
|
277 |
} else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 && |
|
278 |
Instruction_aarch64::extract(insn, 4, 0) == 0b11111) { |
|
279 |
return 0; |
|
280 |
} else { |
|
281 |
ShouldNotReachHere(); |
|
282 |
} |
|
283 |
return address(((uint64_t)insn_addr + (offset << 2))); |
|
284 |
} |
|
285 |
||
286 |
void MacroAssembler::serialize_memory(Register thread, Register tmp) { |
|
287 |
dsb(Assembler::SY); |
|
288 |
} |
|
289 |
||
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290 |
void MacroAssembler::safepoint_poll(Label& slow_path) { |
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291 |
if (SafepointMechanism::uses_thread_local_poll()) { |
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292 |
ldr(rscratch1, Address(rthread, Thread::polling_page_offset())); |
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293 |
tbnz(rscratch1, exact_log2(SafepointMechanism::poll_bit()), slow_path); |
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|
294 |
} else { |
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|
295 |
unsigned long offset; |
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|
296 |
adrp(rscratch1, ExternalAddress(SafepointSynchronize::address_of_state()), offset); |
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297 |
ldrw(rscratch1, Address(rscratch1, offset)); |
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298 |
assert(SafepointSynchronize::_not_synchronized == 0, "rewrite this code"); |
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299 |
cbnz(rscratch1, slow_path); |
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300 |
} |
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301 |
} |
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|
302 |
|
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303 |
// Just like safepoint_poll, but use an acquiring load for thread- |
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|
304 |
// local polling. |
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|
305 |
// |
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|
306 |
// We need an acquire here to ensure that any subsequent load of the |
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|
307 |
// global SafepointSynchronize::_state flag is ordered after this load |
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|
308 |
// of the local Thread::_polling page. We don't want this poll to |
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|
309 |
// return false (i.e. not safepointing) and a later poll of the global |
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|
310 |
// SafepointSynchronize::_state spuriously to return true. |
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|
311 |
// |
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|
312 |
// This is to avoid a race when we're in a native->Java transition |
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|
313 |
// racing the code which wakes up from a safepoint. |
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|
314 |
// |
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|
315 |
void MacroAssembler::safepoint_poll_acquire(Label& slow_path) { |
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|
316 |
if (SafepointMechanism::uses_thread_local_poll()) { |
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|
317 |
lea(rscratch1, Address(rthread, Thread::polling_page_offset())); |
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|
318 |
ldar(rscratch1, rscratch1); |
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|
319 |
tbnz(rscratch1, exact_log2(SafepointMechanism::poll_bit()), slow_path); |
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|
320 |
} else { |
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|
321 |
safepoint_poll(slow_path); |
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|
322 |
} |
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|
323 |
} |
29183 | 324 |
|
40643 | 325 |
void MacroAssembler::reset_last_Java_frame(bool clear_fp) { |
29183 | 326 |
// we must set sp to zero to clear frame |
327 |
str(zr, Address(rthread, JavaThread::last_Java_sp_offset())); |
|
40643 | 328 |
|
29183 | 329 |
// must clear fp, so that compiled frames are not confused; it is |
330 |
// possible that we need it only for debugging |
|
331 |
if (clear_fp) { |
|
332 |
str(zr, Address(rthread, JavaThread::last_Java_fp_offset())); |
|
333 |
} |
|
334 |
||
40643 | 335 |
// Always clear the pc because it could have been set by make_walkable() |
336 |
str(zr, Address(rthread, JavaThread::last_Java_pc_offset())); |
|
29183 | 337 |
} |
338 |
||
339 |
// Calls to C land |
|
340 |
// |
|
341 |
// When entering C land, the rfp, & resp of the last Java frame have to be recorded |
|
342 |
// in the (thread-local) JavaThread object. When leaving C land, the last Java fp |
|
343 |
// has to be reset to 0. This is required to allow proper stack traversal. |
|
344 |
void MacroAssembler::set_last_Java_frame(Register last_java_sp, |
|
345 |
Register last_java_fp, |
|
346 |
Register last_java_pc, |
|
347 |
Register scratch) { |
|
348 |
||
349 |
if (last_java_pc->is_valid()) { |
|
350 |
str(last_java_pc, Address(rthread, |
|
351 |
JavaThread::frame_anchor_offset() |
|
352 |
+ JavaFrameAnchor::last_Java_pc_offset())); |
|
353 |
} |
|
354 |
||
355 |
// determine last_java_sp register |
|
356 |
if (last_java_sp == sp) { |
|
357 |
mov(scratch, sp); |
|
358 |
last_java_sp = scratch; |
|
359 |
} else if (!last_java_sp->is_valid()) { |
|
360 |
last_java_sp = esp; |
|
361 |
} |
|
362 |
||
363 |
str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset())); |
|
364 |
||
365 |
// last_java_fp is optional |
|
366 |
if (last_java_fp->is_valid()) { |
|
367 |
str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset())); |
|
368 |
} |
|
369 |
} |
|
370 |
||
371 |
void MacroAssembler::set_last_Java_frame(Register last_java_sp, |
|
372 |
Register last_java_fp, |
|
373 |
address last_java_pc, |
|
374 |
Register scratch) { |
|
375 |
if (last_java_pc != NULL) { |
|
376 |
adr(scratch, last_java_pc); |
|
377 |
} else { |
|
378 |
// FIXME: This is almost never correct. We should delete all |
|
379 |
// cases of set_last_Java_frame with last_java_pc=NULL and use the |
|
380 |
// correct return address instead. |
|
381 |
adr(scratch, pc()); |
|
382 |
} |
|
383 |
||
384 |
str(scratch, Address(rthread, |
|
385 |
JavaThread::frame_anchor_offset() |
|
386 |
+ JavaFrameAnchor::last_Java_pc_offset())); |
|
387 |
||
388 |
set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch); |
|
389 |
} |
|
390 |
||
391 |
void MacroAssembler::set_last_Java_frame(Register last_java_sp, |
|
392 |
Register last_java_fp, |
|
393 |
Label &L, |
|
394 |
Register scratch) { |
|
395 |
if (L.is_bound()) { |
|
396 |
set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch); |
|
397 |
} else { |
|
398 |
InstructionMark im(this); |
|
399 |
L.add_patch_at(code(), locator()); |
|
400 |
set_last_Java_frame(last_java_sp, last_java_fp, (address)NULL, scratch); |
|
401 |
} |
|
402 |
} |
|
403 |
||
404 |
void MacroAssembler::far_call(Address entry, CodeBuffer *cbuf, Register tmp) { |
|
405 |
assert(ReservedCodeCacheSize < 4*G, "branch out of range"); |
|
406 |
assert(CodeCache::find_blob(entry.target()) != NULL, |
|
407 |
"destination of far call not found in code cache"); |
|
408 |
if (far_branches()) { |
|
409 |
unsigned long offset; |
|
410 |
// We can use ADRP here because we know that the total size of |
|
411 |
// the code cache cannot exceed 2Gb. |
|
412 |
adrp(tmp, entry, offset); |
|
413 |
add(tmp, tmp, offset); |
|
414 |
if (cbuf) cbuf->set_insts_mark(); |
|
415 |
blr(tmp); |
|
416 |
} else { |
|
417 |
if (cbuf) cbuf->set_insts_mark(); |
|
418 |
bl(entry); |
|
419 |
} |
|
420 |
} |
|
421 |
||
422 |
void MacroAssembler::far_jump(Address entry, CodeBuffer *cbuf, Register tmp) { |
|
423 |
assert(ReservedCodeCacheSize < 4*G, "branch out of range"); |
|
424 |
assert(CodeCache::find_blob(entry.target()) != NULL, |
|
425 |
"destination of far call not found in code cache"); |
|
426 |
if (far_branches()) { |
|
427 |
unsigned long offset; |
|
428 |
// We can use ADRP here because we know that the total size of |
|
429 |
// the code cache cannot exceed 2Gb. |
|
430 |
adrp(tmp, entry, offset); |
|
431 |
add(tmp, tmp, offset); |
|
432 |
if (cbuf) cbuf->set_insts_mark(); |
|
433 |
br(tmp); |
|
434 |
} else { |
|
435 |
if (cbuf) cbuf->set_insts_mark(); |
|
436 |
b(entry); |
|
437 |
} |
|
438 |
} |
|
439 |
||
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440 |
void MacroAssembler::reserved_stack_check() { |
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441 |
// testing if reserved zone needs to be enabled |
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442 |
Label no_reserved_zone_enabling; |
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|
443 |
|
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|
444 |
ldr(rscratch1, Address(rthread, JavaThread::reserved_stack_activation_offset())); |
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445 |
cmp(sp, rscratch1); |
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|
446 |
br(Assembler::LO, no_reserved_zone_enabling); |
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|
447 |
|
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|
448 |
enter(); // LR and FP are live. |
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|
449 |
lea(rscratch1, CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone)); |
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|
450 |
mov(c_rarg0, rthread); |
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|
451 |
blr(rscratch1); |
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|
452 |
leave(); |
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|
453 |
|
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|
454 |
// We have already removed our own frame. |
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|
455 |
// throw_delayed_StackOverflowError will think that it's been |
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|
456 |
// called by our caller. |
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|
457 |
lea(rscratch1, RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry())); |
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|
458 |
br(rscratch1); |
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|
459 |
should_not_reach_here(); |
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|
460 |
|
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|
461 |
bind(no_reserved_zone_enabling); |
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|
462 |
} |
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|
463 |
|
29183 | 464 |
int MacroAssembler::biased_locking_enter(Register lock_reg, |
465 |
Register obj_reg, |
|
466 |
Register swap_reg, |
|
467 |
Register tmp_reg, |
|
468 |
bool swap_reg_contains_mark, |
|
469 |
Label& done, |
|
470 |
Label* slow_case, |
|
471 |
BiasedLockingCounters* counters) { |
|
472 |
assert(UseBiasedLocking, "why call this otherwise?"); |
|
473 |
assert_different_registers(lock_reg, obj_reg, swap_reg); |
|
474 |
||
475 |
if (PrintBiasedLockingStatistics && counters == NULL) |
|
476 |
counters = BiasedLocking::counters(); |
|
477 |
||
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|
478 |
assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg, rscratch1, rscratch2, noreg); |
29183 | 479 |
assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); |
480 |
Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); |
|
481 |
Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes()); |
|
482 |
Address saved_mark_addr(lock_reg, 0); |
|
483 |
||
484 |
// Biased locking |
|
485 |
// See whether the lock is currently biased toward our thread and |
|
486 |
// whether the epoch is still valid |
|
487 |
// Note that the runtime guarantees sufficient alignment of JavaThread |
|
488 |
// pointers to allow age to be placed into low bits |
|
489 |
// First check to see whether biasing is even enabled for this object |
|
490 |
Label cas_label; |
|
491 |
int null_check_offset = -1; |
|
492 |
if (!swap_reg_contains_mark) { |
|
493 |
null_check_offset = offset(); |
|
494 |
ldr(swap_reg, mark_addr); |
|
495 |
} |
|
496 |
andr(tmp_reg, swap_reg, markOopDesc::biased_lock_mask_in_place); |
|
497 |
cmp(tmp_reg, markOopDesc::biased_lock_pattern); |
|
498 |
br(Assembler::NE, cas_label); |
|
499 |
// The bias pattern is present in the object's header. Need to check |
|
500 |
// whether the bias owner and the epoch are both still current. |
|
501 |
load_prototype_header(tmp_reg, obj_reg); |
|
502 |
orr(tmp_reg, tmp_reg, rthread); |
|
503 |
eor(tmp_reg, swap_reg, tmp_reg); |
|
504 |
andr(tmp_reg, tmp_reg, ~((int) markOopDesc::age_mask_in_place)); |
|
505 |
if (counters != NULL) { |
|
506 |
Label around; |
|
507 |
cbnz(tmp_reg, around); |
|
32395
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diff
changeset
|
508 |
atomic_incw(Address((address)counters->biased_lock_entry_count_addr()), tmp_reg, rscratch1, rscratch2); |
29183 | 509 |
b(done); |
510 |
bind(around); |
|
511 |
} else { |
|
512 |
cbz(tmp_reg, done); |
|
513 |
} |
|
514 |
||
515 |
Label try_revoke_bias; |
|
516 |
Label try_rebias; |
|
517 |
||
518 |
// At this point we know that the header has the bias pattern and |
|
519 |
// that we are not the bias owner in the current epoch. We need to |
|
520 |
// figure out more details about the state of the header in order to |
|
521 |
// know what operations can be legally performed on the object's |
|
522 |
// header. |
|
523 |
||
524 |
// If the low three bits in the xor result aren't clear, that means |
|
525 |
// the prototype header is no longer biased and we have to revoke |
|
526 |
// the bias on this object. |
|
527 |
andr(rscratch1, tmp_reg, markOopDesc::biased_lock_mask_in_place); |
|
528 |
cbnz(rscratch1, try_revoke_bias); |
|
529 |
||
530 |
// Biasing is still enabled for this data type. See whether the |
|
531 |
// epoch of the current bias is still valid, meaning that the epoch |
|
532 |
// bits of the mark word are equal to the epoch bits of the |
|
533 |
// prototype header. (Note that the prototype header's epoch bits |
|
534 |
// only change at a safepoint.) If not, attempt to rebias the object |
|
535 |
// toward the current thread. Note that we must be absolutely sure |
|
536 |
// that the current epoch is invalid in order to do this because |
|
537 |
// otherwise the manipulations it performs on the mark word are |
|
538 |
// illegal. |
|
539 |
andr(rscratch1, tmp_reg, markOopDesc::epoch_mask_in_place); |
|
540 |
cbnz(rscratch1, try_rebias); |
|
541 |
||
542 |
// The epoch of the current bias is still valid but we know nothing |
|
543 |
// about the owner; it might be set or it might be clear. Try to |
|
544 |
// acquire the bias of the object using an atomic operation. If this |
|
545 |
// fails we will go in to the runtime to revoke the object's bias. |
|
546 |
// Note that we first construct the presumed unbiased header so we |
|
547 |
// don't accidentally blow away another thread's valid bias. |
|
548 |
{ |
|
549 |
Label here; |
|
550 |
mov(rscratch1, markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); |
|
551 |
andr(swap_reg, swap_reg, rscratch1); |
|
552 |
orr(tmp_reg, swap_reg, rthread); |
|
46449
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8167659: Access of mark word should use oopDesc::mark_offset_in_bytes() instead of '0'
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43439
diff
changeset
|
553 |
cmpxchg_obj_header(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case); |
29183 | 554 |
// If the biasing toward our thread failed, this means that |
555 |
// another thread succeeded in biasing it toward itself and we |
|
556 |
// need to revoke that bias. The revocation will occur in the |
|
557 |
// interpreter runtime in the slow case. |
|
558 |
bind(here); |
|
559 |
if (counters != NULL) { |
|
560 |
atomic_incw(Address((address)counters->anonymously_biased_lock_entry_count_addr()), |
|
32395
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8133352: aarch64: generates constrained unpredictable instructions
enevill
parents:
32394
diff
changeset
|
561 |
tmp_reg, rscratch1, rscratch2); |
29183 | 562 |
} |
563 |
} |
|
564 |
b(done); |
|
565 |
||
566 |
bind(try_rebias); |
|
567 |
// At this point we know the epoch has expired, meaning that the |
|
568 |
// current "bias owner", if any, is actually invalid. Under these |
|
569 |
// circumstances _only_, we are allowed to use the current header's |
|
570 |
// value as the comparison value when doing the cas to acquire the |
|
571 |
// bias in the current epoch. In other words, we allow transfer of |
|
572 |
// the bias from one thread to another directly in this situation. |
|
573 |
// |
|
574 |
// FIXME: due to a lack of registers we currently blow away the age |
|
575 |
// bits in this situation. Should attempt to preserve them. |
|
576 |
{ |
|
577 |
Label here; |
|
578 |
load_prototype_header(tmp_reg, obj_reg); |
|
579 |
orr(tmp_reg, rthread, tmp_reg); |
|
46449
7b2416f0f524
8167659: Access of mark word should use oopDesc::mark_offset_in_bytes() instead of '0'
rkennke
parents:
43439
diff
changeset
|
580 |
cmpxchg_obj_header(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case); |
29183 | 581 |
// If the biasing toward our thread failed, then another thread |
582 |
// succeeded in biasing it toward itself and we need to revoke that |
|
583 |
// bias. The revocation will occur in the runtime in the slow case. |
|
584 |
bind(here); |
|
585 |
if (counters != NULL) { |
|
586 |
atomic_incw(Address((address)counters->rebiased_lock_entry_count_addr()), |
|
32395
13b0caf18153
8133352: aarch64: generates constrained unpredictable instructions
enevill
parents:
32394
diff
changeset
|
587 |
tmp_reg, rscratch1, rscratch2); |
29183 | 588 |
} |
589 |
} |
|
590 |
b(done); |
|
591 |
||
592 |
bind(try_revoke_bias); |
|
593 |
// The prototype mark in the klass doesn't have the bias bit set any |
|
594 |
// more, indicating that objects of this data type are not supposed |
|
595 |
// to be biased any more. We are going to try to reset the mark of |
|
596 |
// this object to the prototype value and fall through to the |
|
597 |
// CAS-based locking scheme. Note that if our CAS fails, it means |
|
598 |
// that another thread raced us for the privilege of revoking the |
|
599 |
// bias of this particular object, so it's okay to continue in the |
|
600 |
// normal locking code. |
|
601 |
// |
|
602 |
// FIXME: due to a lack of registers we currently blow away the age |
|
603 |
// bits in this situation. Should attempt to preserve them. |
|
604 |
{ |
|
605 |
Label here, nope; |
|
606 |
load_prototype_header(tmp_reg, obj_reg); |
|
46449
7b2416f0f524
8167659: Access of mark word should use oopDesc::mark_offset_in_bytes() instead of '0'
rkennke
parents:
43439
diff
changeset
|
607 |
cmpxchg_obj_header(swap_reg, tmp_reg, obj_reg, rscratch1, here, &nope); |
29183 | 608 |
bind(here); |
609 |
||
610 |
// Fall through to the normal CAS-based lock, because no matter what |
|
611 |
// the result of the above CAS, some thread must have succeeded in |
|
612 |
// removing the bias bit from the object's header. |
|
613 |
if (counters != NULL) { |
|
614 |
atomic_incw(Address((address)counters->revoked_lock_entry_count_addr()), tmp_reg, |
|
32395
13b0caf18153
8133352: aarch64: generates constrained unpredictable instructions
enevill
parents:
32394
diff
changeset
|
615 |
rscratch1, rscratch2); |
29183 | 616 |
} |
617 |
bind(nope); |
|
618 |
} |
|
619 |
||
620 |
bind(cas_label); |
|
621 |
||
622 |
return null_check_offset; |
|
623 |
} |
|
624 |
||
625 |
void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { |
|
626 |
assert(UseBiasedLocking, "why call this otherwise?"); |
|
627 |
||
628 |
// Check for biased locking unlock case, which is a no-op |
|
629 |
// Note: we do not have to check the thread ID for two reasons. |
|
630 |
// First, the interpreter checks for IllegalMonitorStateException at |
|
631 |
// a higher level. Second, if the bias was revoked while we held the |
|
632 |
// lock, the object could not be rebiased toward another thread, so |
|
633 |
// the bias bit would be clear. |
|
634 |
ldr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); |
|
635 |
andr(temp_reg, temp_reg, markOopDesc::biased_lock_mask_in_place); |
|
636 |
cmp(temp_reg, markOopDesc::biased_lock_pattern); |
|
637 |
br(Assembler::EQ, done); |
|
638 |
} |
|
639 |
||
640 |
static void pass_arg0(MacroAssembler* masm, Register arg) { |
|
641 |
if (c_rarg0 != arg ) { |
|
642 |
masm->mov(c_rarg0, arg); |
|
643 |
} |
|
644 |
} |
|
645 |
||
646 |
static void pass_arg1(MacroAssembler* masm, Register arg) { |
|
647 |
if (c_rarg1 != arg ) { |
|
648 |
masm->mov(c_rarg1, arg); |
|
649 |
} |
|
650 |
} |
|
651 |
||
652 |
static void pass_arg2(MacroAssembler* masm, Register arg) { |
|
653 |
if (c_rarg2 != arg ) { |
|
654 |
masm->mov(c_rarg2, arg); |
|
655 |
} |
|
656 |
} |
|
657 |
||
658 |
static void pass_arg3(MacroAssembler* masm, Register arg) { |
|
659 |
if (c_rarg3 != arg ) { |
|
660 |
masm->mov(c_rarg3, arg); |
|
661 |
} |
|
662 |
} |
|
663 |
||
664 |
void MacroAssembler::call_VM_base(Register oop_result, |
|
665 |
Register java_thread, |
|
666 |
Register last_java_sp, |
|
667 |
address entry_point, |
|
668 |
int number_of_arguments, |
|
669 |
bool check_exceptions) { |
|
670 |
// determine java_thread register |
|
671 |
if (!java_thread->is_valid()) { |
|
672 |
java_thread = rthread; |
|
673 |
} |
|
674 |
||
675 |
// determine last_java_sp register |
|
676 |
if (!last_java_sp->is_valid()) { |
|
677 |
last_java_sp = esp; |
|
678 |
} |
|
679 |
||
680 |
// debugging support |
|
681 |
assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); |
|
682 |
assert(java_thread == rthread, "unexpected register"); |
|
683 |
#ifdef ASSERT |
|
684 |
// TraceBytecodes does not use r12 but saves it over the call, so don't verify |
|
685 |
// if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?"); |
|
686 |
#endif // ASSERT |
|
687 |
||
688 |
assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); |
|
689 |
assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); |
|
690 |
||
691 |
// push java thread (becomes first argument of C function) |
|
692 |
||
693 |
mov(c_rarg0, java_thread); |
|
694 |
||
695 |
// set last Java frame before call |
|
696 |
assert(last_java_sp != rfp, "can't use rfp"); |
|
697 |
||
698 |
Label l; |
|
699 |
set_last_Java_frame(last_java_sp, rfp, l, rscratch1); |
|
700 |
||
701 |
// do the call, remove parameters |
|
702 |
MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l); |
|
703 |
||
704 |
// reset last Java frame |
|
705 |
// Only interpreter should have to clear fp |
|
40643 | 706 |
reset_last_Java_frame(true); |
29183 | 707 |
|
708 |
// C++ interp handles this in the interpreter |
|
709 |
check_and_handle_popframe(java_thread); |
|
710 |
check_and_handle_earlyret(java_thread); |
|
711 |
||
712 |
if (check_exceptions) { |
|
713 |
// check for pending exceptions (java_thread is set upon return) |
|
714 |
ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset()))); |
|
715 |
Label ok; |
|
716 |
cbz(rscratch1, ok); |
|
717 |
lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry())); |
|
718 |
br(rscratch1); |
|
719 |
bind(ok); |
|
720 |
} |
|
721 |
||
722 |
// get oop result if there is one and reset the value in the thread |
|
723 |
if (oop_result->is_valid()) { |
|
724 |
get_vm_result(oop_result, java_thread); |
|
725 |
} |
|
726 |
} |
|
727 |
||
728 |
void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { |
|
729 |
call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions); |
|
730 |
} |
|
731 |
||
732 |
// Maybe emit a call via a trampoline. If the code cache is small |
|
733 |
// trampolines won't be emitted. |
|
734 |
||
32082
2a3323e25de1
8130309: Need to bailout cleanly if creation of stubs fails when codecache is out of space
thartmann
parents:
31958
diff
changeset
|
735 |
address MacroAssembler::trampoline_call(Address entry, CodeBuffer *cbuf) { |
45054 | 736 |
assert(JavaThread::current()->is_Compiler_thread(), "just checking"); |
29183 | 737 |
assert(entry.rspec().type() == relocInfo::runtime_call_type |
738 |
|| entry.rspec().type() == relocInfo::opt_virtual_call_type |
|
739 |
|| entry.rspec().type() == relocInfo::static_call_type |
|
740 |
|| entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type"); |
|
741 |
||
742 |
unsigned int start_offset = offset(); |
|
743 |
if (far_branches() && !Compile::current()->in_scratch_emit_size()) { |
|
32082
2a3323e25de1
8130309: Need to bailout cleanly if creation of stubs fails when codecache is out of space
thartmann
parents:
31958
diff
changeset
|
744 |
address stub = emit_trampoline_stub(start_offset, entry.target()); |
2a3323e25de1
8130309: Need to bailout cleanly if creation of stubs fails when codecache is out of space
thartmann
parents:
31958
diff
changeset
|
745 |
if (stub == NULL) { |
2a3323e25de1
8130309: Need to bailout cleanly if creation of stubs fails when codecache is out of space
thartmann
parents:
31958
diff
changeset
|
746 |
return NULL; // CodeCache is full |
2a3323e25de1
8130309: Need to bailout cleanly if creation of stubs fails when codecache is out of space
thartmann
parents:
31958
diff
changeset
|
747 |
} |
29183 | 748 |
} |
749 |
||
750 |
if (cbuf) cbuf->set_insts_mark(); |
|
751 |
relocate(entry.rspec()); |
|
35159
3ee05e289424
8146286: aarch64: guarantee failures with large code cache sizes on jtreg test java/lang/invoke/LFCaching/LFMultiThreadCachingTest.java
enevill
parents:
35135
diff
changeset
|
752 |
if (!far_branches()) { |
29183 | 753 |
bl(entry.target()); |
754 |
} else { |
|
755 |
bl(pc()); |
|
756 |
} |
|
32086
7590882ae33a
8132875: AArch64: Fix error introduced into AArch64 CodeCache by commit for 8130309
adinn
parents:
32082
diff
changeset
|
757 |
// just need to return a non-null address |
7590882ae33a
8132875: AArch64: Fix error introduced into AArch64 CodeCache by commit for 8130309
adinn
parents:
32082
diff
changeset
|
758 |
return pc(); |
29183 | 759 |
} |
760 |
||
761 |
||
762 |
// Emit a trampoline stub for a call to a target which is too far away. |
|
763 |
// |
|
764 |
// code sequences: |
|
765 |
// |
|
766 |
// call-site: |
|
767 |
// branch-and-link to <destination> or <trampoline stub> |
|
768 |
// |
|
769 |
// Related trampoline stub for this call site in the stub section: |
|
770 |
// load the call target from the constant pool |
|
771 |
// branch (LR still points to the call site above) |
|
772 |
||
32082
2a3323e25de1
8130309: Need to bailout cleanly if creation of stubs fails when codecache is out of space
thartmann
parents:
31958
diff
changeset
|
773 |
address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset, |
29183 | 774 |
address dest) { |
775 |
address stub = start_a_stub(Compile::MAX_stubs_size/2); |
|
776 |
if (stub == NULL) { |
|
32082
2a3323e25de1
8130309: Need to bailout cleanly if creation of stubs fails when codecache is out of space
thartmann
parents:
31958
diff
changeset
|
777 |
return NULL; // CodeBuffer::expand failed |
29183 | 778 |
} |
779 |
||
780 |
// Create a trampoline stub relocation which relates this trampoline stub |
|
781 |
// with the call instruction at insts_call_instruction_offset in the |
|
782 |
// instructions code-section. |
|
783 |
align(wordSize); |
|
784 |
relocate(trampoline_stub_Relocation::spec(code()->insts()->start() |
|
785 |
+ insts_call_instruction_offset)); |
|
786 |
const int stub_start_offset = offset(); |
|
787 |
||
788 |
// Now, create the trampoline stub's code: |
|
789 |
// - load the call |
|
790 |
// - call |
|
791 |
Label target; |
|
792 |
ldr(rscratch1, target); |
|
793 |
br(rscratch1); |
|
794 |
bind(target); |
|
795 |
assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset, |
|
796 |
"should be"); |
|
797 |
emit_int64((int64_t)dest); |
|
798 |
||
799 |
const address stub_start_addr = addr_at(stub_start_offset); |
|
800 |
||
801 |
assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline"); |
|
802 |
||
803 |
end_a_stub(); |
|
48487 | 804 |
return stub_start_addr; |
29183 | 805 |
} |
806 |
||
35086
bbf32241d851
8072008: Emit direct call instead of linkTo* for recursive indy/MH.invoke* calls
vlivanov
parents:
34211
diff
changeset
|
807 |
address MacroAssembler::ic_call(address entry, jint method_index) { |
bbf32241d851
8072008: Emit direct call instead of linkTo* for recursive indy/MH.invoke* calls
vlivanov
parents:
34211
diff
changeset
|
808 |
RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index); |
29183 | 809 |
// address const_ptr = long_constant((jlong)Universe::non_oop_word()); |
810 |
// unsigned long offset; |
|
811 |
// ldr_constant(rscratch2, const_ptr); |
|
812 |
movptr(rscratch2, (uintptr_t)Universe::non_oop_word()); |
|
32082
2a3323e25de1
8130309: Need to bailout cleanly if creation of stubs fails when codecache is out of space
thartmann
parents:
31958
diff
changeset
|
813 |
return trampoline_call(Address(entry, rh)); |
29183 | 814 |
} |
815 |
||
816 |
// Implementation of call_VM versions |
|
817 |
||
818 |
void MacroAssembler::call_VM(Register oop_result, |
|
819 |
address entry_point, |
|
820 |
bool check_exceptions) { |
|
821 |
call_VM_helper(oop_result, entry_point, 0, check_exceptions); |
|
822 |
} |
|
823 |
||
824 |
void MacroAssembler::call_VM(Register oop_result, |
|
825 |
address entry_point, |
|
826 |
Register arg_1, |
|
827 |
bool check_exceptions) { |
|
828 |
pass_arg1(this, arg_1); |
|
829 |
call_VM_helper(oop_result, entry_point, 1, check_exceptions); |
|
830 |
} |
|
831 |
||
832 |
void MacroAssembler::call_VM(Register oop_result, |
|
833 |
address entry_point, |
|
834 |
Register arg_1, |
|
835 |
Register arg_2, |
|
836 |
bool check_exceptions) { |
|
837 |
assert(arg_1 != c_rarg2, "smashed arg"); |
|
838 |
pass_arg2(this, arg_2); |
|
839 |
pass_arg1(this, arg_1); |
|
840 |
call_VM_helper(oop_result, entry_point, 2, check_exceptions); |
|
841 |
} |
|
842 |
||
843 |
void MacroAssembler::call_VM(Register oop_result, |
|
844 |
address entry_point, |
|
845 |
Register arg_1, |
|
846 |
Register arg_2, |
|
847 |
Register arg_3, |
|
848 |
bool check_exceptions) { |
|
849 |
assert(arg_1 != c_rarg3, "smashed arg"); |
|
850 |
assert(arg_2 != c_rarg3, "smashed arg"); |
|
851 |
pass_arg3(this, arg_3); |
|
852 |
||
853 |
assert(arg_1 != c_rarg2, "smashed arg"); |
|
854 |
pass_arg2(this, arg_2); |
|
855 |
||
856 |
pass_arg1(this, arg_1); |
|
857 |
call_VM_helper(oop_result, entry_point, 3, check_exceptions); |
|
858 |
} |
|
859 |
||
860 |
void MacroAssembler::call_VM(Register oop_result, |
|
861 |
Register last_java_sp, |
|
862 |
address entry_point, |
|
863 |
int number_of_arguments, |
|
864 |
bool check_exceptions) { |
|
865 |
call_VM_base(oop_result, rthread, last_java_sp, entry_point, number_of_arguments, check_exceptions); |
|
866 |
} |
|
867 |
||
868 |
void MacroAssembler::call_VM(Register oop_result, |
|
869 |
Register last_java_sp, |
|
870 |
address entry_point, |
|
871 |
Register arg_1, |
|
872 |
bool check_exceptions) { |
|
873 |
pass_arg1(this, arg_1); |
|
874 |
call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); |
|
875 |
} |
|
876 |
||
877 |
void MacroAssembler::call_VM(Register oop_result, |
|
878 |
Register last_java_sp, |
|
879 |
address entry_point, |
|
880 |
Register arg_1, |
|
881 |
Register arg_2, |
|
882 |
bool check_exceptions) { |
|
883 |
||
884 |
assert(arg_1 != c_rarg2, "smashed arg"); |
|
885 |
pass_arg2(this, arg_2); |
|
886 |
pass_arg1(this, arg_1); |
|
887 |
call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); |
|
888 |
} |
|
889 |
||
890 |
void MacroAssembler::call_VM(Register oop_result, |
|
891 |
Register last_java_sp, |
|
892 |
address entry_point, |
|
893 |
Register arg_1, |
|
894 |
Register arg_2, |
|
895 |
Register arg_3, |
|
896 |
bool check_exceptions) { |
|
897 |
assert(arg_1 != c_rarg3, "smashed arg"); |
|
898 |
assert(arg_2 != c_rarg3, "smashed arg"); |
|
899 |
pass_arg3(this, arg_3); |
|
900 |
assert(arg_1 != c_rarg2, "smashed arg"); |
|
901 |
pass_arg2(this, arg_2); |
|
902 |
pass_arg1(this, arg_1); |
|
903 |
call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); |
|
904 |
} |
|
905 |
||
906 |
||
907 |
void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) { |
|
908 |
ldr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); |
|
909 |
str(zr, Address(java_thread, JavaThread::vm_result_offset())); |
|
910 |
verify_oop(oop_result, "broken oop in call_VM_base"); |
|
911 |
} |
|
912 |
||
913 |
void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) { |
|
914 |
ldr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset())); |
|
915 |
str(zr, Address(java_thread, JavaThread::vm_result_2_offset())); |
|
916 |
} |
|
917 |
||
918 |
void MacroAssembler::align(int modulus) { |
|
919 |
while (offset() % modulus != 0) nop(); |
|
920 |
} |
|
921 |
||
922 |
// these are no-ops overridden by InterpreterMacroAssembler |
|
923 |
||
924 |
void MacroAssembler::check_and_handle_earlyret(Register java_thread) { } |
|
925 |
||
926 |
void MacroAssembler::check_and_handle_popframe(Register java_thread) { } |
|
927 |
||
928 |
||
929 |
RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, |
|
930 |
Register tmp, |
|
931 |
int offset) { |
|
932 |
intptr_t value = *delayed_value_addr; |
|
933 |
if (value != 0) |
|
934 |
return RegisterOrConstant(value + offset); |
|
935 |
||
936 |
// load indirectly to solve generation ordering problem |
|
937 |
ldr(tmp, ExternalAddress((address) delayed_value_addr)); |
|
938 |
||
939 |
if (offset != 0) |
|
940 |
add(tmp, tmp, offset); |
|
941 |
||
942 |
return RegisterOrConstant(tmp); |
|
943 |
} |
|
944 |
||
945 |
||
946 |
void MacroAssembler:: notify(int type) { |
|
947 |
if (type == bytecode_start) { |
|
948 |
// set_last_Java_frame(esp, rfp, (address)NULL); |
|
949 |
Assembler:: notify(type); |
|
40643 | 950 |
// reset_last_Java_frame(true); |
29183 | 951 |
} |
952 |
else |
|
953 |
Assembler:: notify(type); |
|
954 |
} |
|
955 |
||
956 |
// Look up the method for a megamorphic invokeinterface call. |
|
957 |
// The target method is determined by <intf_klass, itable_index>. |
|
958 |
// The receiver klass is in recv_klass. |
|
959 |
// On success, the result will be in method_result, and execution falls through. |
|
960 |
// On failure, execution transfers to the given label. |
|
961 |
void MacroAssembler::lookup_interface_method(Register recv_klass, |
|
962 |
Register intf_klass, |
|
963 |
RegisterOrConstant itable_index, |
|
964 |
Register method_result, |
|
965 |
Register scan_temp, |
|
48652
7c03f19d38a7
8195685: AArch64: AArch64 cannot build with JDK-8174962
aph
parents:
48487
diff
changeset
|
966 |
Label& L_no_such_interface, |
7c03f19d38a7
8195685: AArch64: AArch64 cannot build with JDK-8174962
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parents:
48487
diff
changeset
|
967 |
bool return_method) { |
7c03f19d38a7
8195685: AArch64: AArch64 cannot build with JDK-8174962
aph
parents:
48487
diff
changeset
|
968 |
assert_different_registers(recv_klass, intf_klass, scan_temp); |
7c03f19d38a7
8195685: AArch64: AArch64 cannot build with JDK-8174962
aph
parents:
48487
diff
changeset
|
969 |
assert_different_registers(method_result, intf_klass, scan_temp); |
7c03f19d38a7
8195685: AArch64: AArch64 cannot build with JDK-8174962
aph
parents:
48487
diff
changeset
|
970 |
assert(recv_klass != method_result || !return_method, |
7c03f19d38a7
8195685: AArch64: AArch64 cannot build with JDK-8174962
aph
parents:
48487
diff
changeset
|
971 |
"recv_klass can be destroyed when method isn't needed"); |
29183 | 972 |
assert(itable_index.is_constant() || itable_index.as_register() == method_result, |
973 |
"caller must use same register for non-constant itable index as for method"); |
|
974 |
||
975 |
// Compute start of first itableOffsetEntry (which is at the end of the vtable) |
|
35899 | 976 |
int vtable_base = in_bytes(Klass::vtable_start_offset()); |
29183 | 977 |
int itentry_off = itableMethodEntry::method_offset_in_bytes(); |
978 |
int scan_step = itableOffsetEntry::size() * wordSize; |
|
35871
607bf949dfb3
8147461: Use byte offsets for vtable start and vtable length offsets
mgerdin
parents:
35847
diff
changeset
|
979 |
int vte_size = vtableEntry::size_in_bytes(); |
29183 | 980 |
assert(vte_size == wordSize, "else adjust times_vte_scale"); |
981 |
||
35899 | 982 |
ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset())); |
29183 | 983 |
|
984 |
// %%% Could store the aligned, prescaled offset in the klassoop. |
|
985 |
// lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); |
|
986 |
lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3))); |
|
987 |
add(scan_temp, scan_temp, vtable_base); |
|
988 |
||
48652
7c03f19d38a7
8195685: AArch64: AArch64 cannot build with JDK-8174962
aph
parents:
48487
diff
changeset
|
989 |
if (return_method) { |
7c03f19d38a7
8195685: AArch64: AArch64 cannot build with JDK-8174962
aph
parents:
48487
diff
changeset
|
990 |
// Adjust recv_klass by scaled itable_index, so we can free itable_index. |
7c03f19d38a7
8195685: AArch64: AArch64 cannot build with JDK-8174962
aph
parents:
48487
diff
changeset
|
991 |
assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); |
7c03f19d38a7
8195685: AArch64: AArch64 cannot build with JDK-8174962
aph
parents:
48487
diff
changeset
|
992 |
// lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); |
7c03f19d38a7
8195685: AArch64: AArch64 cannot build with JDK-8174962
aph
parents:
48487
diff
changeset
|
993 |
lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3))); |
7c03f19d38a7
8195685: AArch64: AArch64 cannot build with JDK-8174962
aph
parents:
48487
diff
changeset
|
994 |
if (itentry_off) |
7c03f19d38a7
8195685: AArch64: AArch64 cannot build with JDK-8174962
aph
parents:
48487
diff
changeset
|
995 |
add(recv_klass, recv_klass, itentry_off); |
7c03f19d38a7
8195685: AArch64: AArch64 cannot build with JDK-8174962
aph
parents:
48487
diff
changeset
|
996 |
} |
29183 | 997 |
|
998 |
// for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { |
|
999 |
// if (scan->interface() == intf) { |
|
1000 |
// result = (klass + scan->offset() + itable_index); |
|
1001 |
// } |
|
1002 |
// } |
|
1003 |
Label search, found_method; |
|
1004 |
||
1005 |
for (int peel = 1; peel >= 0; peel--) { |
|
1006 |
ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); |
|
1007 |
cmp(intf_klass, method_result); |
|
1008 |
||
1009 |
if (peel) { |
|
1010 |
br(Assembler::EQ, found_method); |
|
1011 |
} else { |
|
1012 |
br(Assembler::NE, search); |
|
1013 |
// (invert the test to fall through to found_method...) |
|
1014 |
} |
|
1015 |
||
1016 |
if (!peel) break; |
|
1017 |
||
1018 |
bind(search); |
|
1019 |
||
1020 |
// Check that the previous entry is non-null. A null entry means that |
|
1021 |
// the receiver class doesn't implement the interface, and wasn't the |
|
1022 |
// same as when the caller was compiled. |
|
1023 |
cbz(method_result, L_no_such_interface); |
|
1024 |
add(scan_temp, scan_temp, scan_step); |
|
1025 |
} |
|
1026 |
||
1027 |
bind(found_method); |
|
1028 |
||
1029 |
// Got a hit. |
|
48652
7c03f19d38a7
8195685: AArch64: AArch64 cannot build with JDK-8174962
aph
parents:
48487
diff
changeset
|
1030 |
if (return_method) { |
7c03f19d38a7
8195685: AArch64: AArch64 cannot build with JDK-8174962
aph
parents:
48487
diff
changeset
|
1031 |
ldrw(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); |
7c03f19d38a7
8195685: AArch64: AArch64 cannot build with JDK-8174962
aph
parents:
48487
diff
changeset
|
1032 |
ldr(method_result, Address(recv_klass, scan_temp, Address::uxtw(0))); |
7c03f19d38a7
8195685: AArch64: AArch64 cannot build with JDK-8174962
aph
parents:
48487
diff
changeset
|
1033 |
} |
29183 | 1034 |
} |
1035 |
||
1036 |
// virtual method calling |
|
1037 |
void MacroAssembler::lookup_virtual_method(Register recv_klass, |
|
1038 |
RegisterOrConstant vtable_index, |
|
1039 |
Register method_result) { |
|
35899 | 1040 |
const int base = in_bytes(Klass::vtable_start_offset()); |
29183 | 1041 |
assert(vtableEntry::size() * wordSize == 8, |
1042 |
"adjust the scaling in the code below"); |
|
1043 |
int vtable_offset_in_bytes = base + vtableEntry::method_offset_in_bytes(); |
|
1044 |
||
1045 |
if (vtable_index.is_register()) { |
|
1046 |
lea(method_result, Address(recv_klass, |
|
1047 |
vtable_index.as_register(), |
|
1048 |
Address::lsl(LogBytesPerWord))); |
|
1049 |
ldr(method_result, Address(method_result, vtable_offset_in_bytes)); |
|
1050 |
} else { |
|
1051 |
vtable_offset_in_bytes += vtable_index.as_constant() * wordSize; |
|
48673
e321560ac819
8195859: AArch64: vtableStubs gtest fails after 8174962
adinn
parents:
48652
diff
changeset
|
1052 |
ldr(method_result, |
48682
34e45260c040
8196221: AArch64: Mistake in committed patch for JDK-8195859
adinn
parents:
48673
diff
changeset
|
1053 |
form_address(rscratch1, recv_klass, vtable_offset_in_bytes, 0)); |
29183 | 1054 |
} |
1055 |
} |
|
1056 |
||
1057 |
void MacroAssembler::check_klass_subtype(Register sub_klass, |
|
1058 |
Register super_klass, |
|
1059 |
Register temp_reg, |
|
1060 |
Label& L_success) { |
|
1061 |
Label L_failure; |
|
1062 |
check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); |
|
1063 |
check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); |
|
1064 |
bind(L_failure); |
|
1065 |
} |
|
1066 |
||
1067 |
||
1068 |
void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, |
|
1069 |
Register super_klass, |
|
1070 |
Register temp_reg, |
|
1071 |
Label* L_success, |
|
1072 |
Label* L_failure, |
|
1073 |
Label* L_slow_path, |
|
1074 |
RegisterOrConstant super_check_offset) { |
|
1075 |
assert_different_registers(sub_klass, super_klass, temp_reg); |
|
1076 |
bool must_load_sco = (super_check_offset.constant_or_zero() == -1); |
|
1077 |
if (super_check_offset.is_register()) { |
|
1078 |
assert_different_registers(sub_klass, super_klass, |
|
1079 |
super_check_offset.as_register()); |
|
1080 |
} else if (must_load_sco) { |
|
1081 |
assert(temp_reg != noreg, "supply either a temp or a register offset"); |
|
1082 |
} |
|
1083 |
||
1084 |
Label L_fallthrough; |
|
1085 |
int label_nulls = 0; |
|
1086 |
if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
|
1087 |
if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
|
1088 |
if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } |
|
1089 |
assert(label_nulls <= 1, "at most one NULL in the batch"); |
|
1090 |
||
1091 |
int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); |
|
1092 |
int sco_offset = in_bytes(Klass::super_check_offset_offset()); |
|
1093 |
Address super_check_offset_addr(super_klass, sco_offset); |
|
1094 |
||
1095 |
// Hacked jmp, which may only be used just before L_fallthrough. |
|
1096 |
#define final_jmp(label) \ |
|
1097 |
if (&(label) == &L_fallthrough) { /*do nothing*/ } \ |
|
1098 |
else b(label) /*omit semi*/ |
|
1099 |
||
1100 |
// If the pointers are equal, we are done (e.g., String[] elements). |
|
1101 |
// This self-check enables sharing of secondary supertype arrays among |
|
1102 |
// non-primary types such as array-of-interface. Otherwise, each such |
|
1103 |
// type would need its own customized SSA. |
|
1104 |
// We move this check to the front of the fast path because many |
|
1105 |
// type checks are in fact trivially successful in this manner, |
|
1106 |
// so we get a nicely predicted branch right at the start of the check. |
|
1107 |
cmp(sub_klass, super_klass); |
|
1108 |
br(Assembler::EQ, *L_success); |
|
1109 |
||
1110 |
// Check the supertype display: |
|
1111 |
if (must_load_sco) { |
|
1112 |
ldrw(temp_reg, super_check_offset_addr); |
|
1113 |
super_check_offset = RegisterOrConstant(temp_reg); |
|
1114 |
} |
|
1115 |
Address super_check_addr(sub_klass, super_check_offset); |
|
1116 |
ldr(rscratch1, super_check_addr); |
|
1117 |
cmp(super_klass, rscratch1); // load displayed supertype |
|
1118 |
||
1119 |
// This check has worked decisively for primary supers. |
|
1120 |
// Secondary supers are sought in the super_cache ('super_cache_addr'). |
|
1121 |
// (Secondary supers are interfaces and very deeply nested subtypes.) |
|
1122 |
// This works in the same check above because of a tricky aliasing |
|
1123 |
// between the super_cache and the primary super display elements. |
|
1124 |
// (The 'super_check_addr' can address either, as the case requires.) |
|
1125 |
// Note that the cache is updated below if it does not help us find |
|
1126 |
// what we need immediately. |
|
1127 |
// So if it was a primary super, we can just fail immediately. |
|
1128 |
// Otherwise, it's the slow path for us (no success at this point). |
|
1129 |
||
1130 |
if (super_check_offset.is_register()) { |
|
1131 |
br(Assembler::EQ, *L_success); |
|
1132 |
cmp(super_check_offset.as_register(), sc_offset); |
|
1133 |
if (L_failure == &L_fallthrough) { |
|
1134 |
br(Assembler::EQ, *L_slow_path); |
|
1135 |
} else { |
|
1136 |
br(Assembler::NE, *L_failure); |
|
1137 |
final_jmp(*L_slow_path); |
|
1138 |
} |
|
1139 |
} else if (super_check_offset.as_constant() == sc_offset) { |
|
1140 |
// Need a slow path; fast failure is impossible. |
|
1141 |
if (L_slow_path == &L_fallthrough) { |
|
1142 |
br(Assembler::EQ, *L_success); |
|
1143 |
} else { |
|
1144 |
br(Assembler::NE, *L_slow_path); |
|
1145 |
final_jmp(*L_success); |
|
1146 |
} |
|
1147 |
} else { |
|
1148 |
// No slow path; it's a fast decision. |
|
1149 |
if (L_failure == &L_fallthrough) { |
|
1150 |
br(Assembler::EQ, *L_success); |
|
1151 |
} else { |
|
1152 |
br(Assembler::NE, *L_failure); |
|
1153 |
final_jmp(*L_success); |
|
1154 |
} |
|
1155 |
} |
|
1156 |
||
1157 |
bind(L_fallthrough); |
|
1158 |
||
1159 |
#undef final_jmp |
|
1160 |
} |
|
1161 |
||
1162 |
// These two are taken from x86, but they look generally useful |
|
1163 |
||
1164 |
// scans count pointer sized words at [addr] for occurence of value, |
|
1165 |
// generic |
|
1166 |
void MacroAssembler::repne_scan(Register addr, Register value, Register count, |
|
1167 |
Register scratch) { |
|
1168 |
Label Lloop, Lexit; |
|
1169 |
cbz(count, Lexit); |
|
1170 |
bind(Lloop); |
|
1171 |
ldr(scratch, post(addr, wordSize)); |
|
1172 |
cmp(value, scratch); |
|
1173 |
br(EQ, Lexit); |
|
1174 |
sub(count, count, 1); |
|
1175 |
cbnz(count, Lloop); |
|
1176 |
bind(Lexit); |
|
1177 |
} |
|
1178 |
||
1179 |
// scans count 4 byte words at [addr] for occurence of value, |
|
1180 |
// generic |
|
1181 |
void MacroAssembler::repne_scanw(Register addr, Register value, Register count, |
|
1182 |
Register scratch) { |
|
1183 |
Label Lloop, Lexit; |
|
1184 |
cbz(count, Lexit); |
|
1185 |
bind(Lloop); |
|
1186 |
ldrw(scratch, post(addr, wordSize)); |
|
1187 |
cmpw(value, scratch); |
|
1188 |
br(EQ, Lexit); |
|
1189 |
sub(count, count, 1); |
|
1190 |
cbnz(count, Lloop); |
|
1191 |
bind(Lexit); |
|
1192 |
} |
|
1193 |
||
1194 |
void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, |
|
1195 |
Register super_klass, |
|
1196 |
Register temp_reg, |
|
1197 |
Register temp2_reg, |
|
1198 |
Label* L_success, |
|
1199 |
Label* L_failure, |
|
1200 |
bool set_cond_codes) { |
|
1201 |
assert_different_registers(sub_klass, super_klass, temp_reg); |
|
1202 |
if (temp2_reg != noreg) |
|
1203 |
assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1); |
|
1204 |
#define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) |
|
1205 |
||
1206 |
Label L_fallthrough; |
|
1207 |
int label_nulls = 0; |
|
1208 |
if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
|
1209 |
if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
|
1210 |
assert(label_nulls <= 1, "at most one NULL in the batch"); |
|
1211 |
||
1212 |
// a couple of useful fields in sub_klass: |
|
1213 |
int ss_offset = in_bytes(Klass::secondary_supers_offset()); |
|
1214 |
int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); |
|
1215 |
Address secondary_supers_addr(sub_klass, ss_offset); |
|
1216 |
Address super_cache_addr( sub_klass, sc_offset); |
|
1217 |
||
1218 |
BLOCK_COMMENT("check_klass_subtype_slow_path"); |
|
1219 |
||
1220 |
// Do a linear scan of the secondary super-klass chain. |
|
1221 |
// This code is rarely used, so simplicity is a virtue here. |
|
1222 |
// The repne_scan instruction uses fixed registers, which we must spill. |
|
1223 |
// Don't worry too much about pre-existing connections with the input regs. |
|
1224 |
||
1225 |
assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super) |
|
1226 |
assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter) |
|
1227 |
||
1228 |
RegSet pushed_registers; |
|
1229 |
if (!IS_A_TEMP(r2)) pushed_registers += r2; |
|
1230 |
if (!IS_A_TEMP(r5)) pushed_registers += r5; |
|
1231 |
||
1232 |
if (super_klass != r0 || UseCompressedOops) { |
|
1233 |
if (!IS_A_TEMP(r0)) pushed_registers += r0; |
|
1234 |
} |
|
1235 |
||
1236 |
push(pushed_registers, sp); |
|
1237 |
||
50270
cc2b36619704
8203699: java/lang/invoke/SpecialInterfaceCall fails with SIGILL on aarch64
adinn
parents:
50110
diff
changeset
|
1238 |
// Get super_klass value into r0 (even if it was in r5 or r2). |
cc2b36619704
8203699: java/lang/invoke/SpecialInterfaceCall fails with SIGILL on aarch64
adinn
parents:
50110
diff
changeset
|
1239 |
if (super_klass != r0) { |
cc2b36619704
8203699: java/lang/invoke/SpecialInterfaceCall fails with SIGILL on aarch64
adinn
parents:
50110
diff
changeset
|
1240 |
mov(r0, super_klass); |
cc2b36619704
8203699: java/lang/invoke/SpecialInterfaceCall fails with SIGILL on aarch64
adinn
parents:
50110
diff
changeset
|
1241 |
} |
cc2b36619704
8203699: java/lang/invoke/SpecialInterfaceCall fails with SIGILL on aarch64
adinn
parents:
50110
diff
changeset
|
1242 |
|
29183 | 1243 |
#ifndef PRODUCT |
1244 |
mov(rscratch2, (address)&SharedRuntime::_partial_subtype_ctr); |
|
1245 |
Address pst_counter_addr(rscratch2); |
|
1246 |
ldr(rscratch1, pst_counter_addr); |
|
1247 |
add(rscratch1, rscratch1, 1); |
|
1248 |
str(rscratch1, pst_counter_addr); |
|
1249 |
#endif //PRODUCT |
|
1250 |
||
1251 |
// We will consult the secondary-super array. |
|
1252 |
ldr(r5, secondary_supers_addr); |
|
1253 |
// Load the array length. |
|
1254 |
ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes())); |
|
1255 |
// Skip to start of data. |
|
1256 |
add(r5, r5, Array<Klass*>::base_offset_in_bytes()); |
|
1257 |
||
1258 |
cmp(sp, zr); // Clear Z flag; SP is never zero |
|
1259 |
// Scan R2 words at [R5] for an occurrence of R0. |
|
1260 |
// Set NZ/Z based on last compare. |
|
1261 |
repne_scan(r5, r0, r2, rscratch1); |
|
1262 |
||
1263 |
// Unspill the temp. registers: |
|
1264 |
pop(pushed_registers, sp); |
|
1265 |
||
1266 |
br(Assembler::NE, *L_failure); |
|
1267 |
||
1268 |
// Success. Cache the super we found and proceed in triumph. |
|
1269 |
str(super_klass, super_cache_addr); |
|
1270 |
||
1271 |
if (L_success != &L_fallthrough) { |
|
1272 |
b(*L_success); |
|
1273 |
} |
|
1274 |
||
1275 |
#undef IS_A_TEMP |
|
1276 |
||
1277 |
bind(L_fallthrough); |
|
1278 |
} |
|
1279 |
||
1280 |
||
1281 |
void MacroAssembler::verify_oop(Register reg, const char* s) { |
|
1282 |
if (!VerifyOops) return; |
|
1283 |
||
1284 |
// Pass register number to verify_oop_subroutine |
|
1285 |
const char* b = NULL; |
|
1286 |
{ |
|
1287 |
ResourceMark rm; |
|
1288 |
stringStream ss; |
|
1289 |
ss.print("verify_oop: %s: %s", reg->name(), s); |
|
1290 |
b = code_string(ss.as_string()); |
|
1291 |
} |
|
1292 |
BLOCK_COMMENT("verify_oop {"); |
|
1293 |
||
1294 |
stp(r0, rscratch1, Address(pre(sp, -2 * wordSize))); |
|
1295 |
stp(rscratch2, lr, Address(pre(sp, -2 * wordSize))); |
|
1296 |
||
1297 |
mov(r0, reg); |
|
1298 |
mov(rscratch1, (address)b); |
|
1299 |
||
1300 |
// call indirectly to solve generation ordering problem |
|
1301 |
lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); |
|
1302 |
ldr(rscratch2, Address(rscratch2)); |
|
1303 |
blr(rscratch2); |
|
1304 |
||
1305 |
ldp(rscratch2, lr, Address(post(sp, 2 * wordSize))); |
|
1306 |
ldp(r0, rscratch1, Address(post(sp, 2 * wordSize))); |
|
1307 |
||
1308 |
BLOCK_COMMENT("} verify_oop"); |
|
1309 |
} |
|
1310 |
||
1311 |
void MacroAssembler::verify_oop_addr(Address addr, const char* s) { |
|
1312 |
if (!VerifyOops) return; |
|
1313 |
||
1314 |
const char* b = NULL; |
|
1315 |
{ |
|
1316 |
ResourceMark rm; |
|
1317 |
stringStream ss; |
|
1318 |
ss.print("verify_oop_addr: %s", s); |
|
1319 |
b = code_string(ss.as_string()); |
|
1320 |
} |
|
1321 |
BLOCK_COMMENT("verify_oop_addr {"); |
|
1322 |
||
1323 |
stp(r0, rscratch1, Address(pre(sp, -2 * wordSize))); |
|
1324 |
stp(rscratch2, lr, Address(pre(sp, -2 * wordSize))); |
|
1325 |
||
1326 |
// addr may contain sp so we will have to adjust it based on the |
|
1327 |
// pushes that we just did. |
|
1328 |
if (addr.uses(sp)) { |
|
1329 |
lea(r0, addr); |
|
1330 |
ldr(r0, Address(r0, 4 * wordSize)); |
|
1331 |
} else { |
|
1332 |
ldr(r0, addr); |
|
1333 |
} |
|
1334 |
mov(rscratch1, (address)b); |
|
1335 |
||
1336 |
// call indirectly to solve generation ordering problem |
|
1337 |
lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); |
|
1338 |
ldr(rscratch2, Address(rscratch2)); |
|
1339 |
blr(rscratch2); |
|
1340 |
||
1341 |
ldp(rscratch2, lr, Address(post(sp, 2 * wordSize))); |
|
1342 |
ldp(r0, rscratch1, Address(post(sp, 2 * wordSize))); |
|
1343 |
||
1344 |
BLOCK_COMMENT("} verify_oop_addr"); |
|
1345 |
} |
|
1346 |
||
1347 |
Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, |
|
1348 |
int extra_slot_offset) { |
|
1349 |
// cf. TemplateTable::prepare_invoke(), if (load_receiver). |
|
1350 |
int stackElementSize = Interpreter::stackElementSize; |
|
1351 |
int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); |
|
1352 |
#ifdef ASSERT |
|
1353 |
int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); |
|
1354 |
assert(offset1 - offset == stackElementSize, "correct arithmetic"); |
|
1355 |
#endif |
|
1356 |
if (arg_slot.is_constant()) { |
|
1357 |
return Address(esp, arg_slot.as_constant() * stackElementSize |
|
1358 |
+ offset); |
|
1359 |
} else { |
|
1360 |
add(rscratch1, esp, arg_slot.as_register(), |
|
1361 |
ext::uxtx, exact_log2(stackElementSize)); |
|
1362 |
return Address(rscratch1, offset); |
|
1363 |
} |
|
1364 |
} |
|
1365 |
||
1366 |
void MacroAssembler::call_VM_leaf_base(address entry_point, |
|
1367 |
int number_of_arguments, |
|
1368 |
Label *retaddr) { |
|
1369 |
call_VM_leaf_base1(entry_point, number_of_arguments, 0, ret_type_integral, retaddr); |
|
1370 |
} |
|
1371 |
||
1372 |
void MacroAssembler::call_VM_leaf_base1(address entry_point, |
|
1373 |
int number_of_gp_arguments, |
|
1374 |
int number_of_fp_arguments, |
|
1375 |
ret_type type, |
|
1376 |
Label *retaddr) { |
|
1377 |
Label E, L; |
|
1378 |
||
1379 |
stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize))); |
|
1380 |
||
1381 |
// We add 1 to number_of_arguments because the thread in arg0 is |
|
1382 |
// not counted |
|
1383 |
mov(rscratch1, entry_point); |
|
1384 |
blrt(rscratch1, number_of_gp_arguments + 1, number_of_fp_arguments, type); |
|
1385 |
if (retaddr) |
|
1386 |
bind(*retaddr); |
|
1387 |
||
1388 |
ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize))); |
|
1389 |
maybe_isb(); |
|
1390 |
} |
|
1391 |
||
1392 |
void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { |
|
1393 |
call_VM_leaf_base(entry_point, number_of_arguments); |
|
1394 |
} |
|
1395 |
||
1396 |
void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { |
|
1397 |
pass_arg0(this, arg_0); |
|
1398 |
call_VM_leaf_base(entry_point, 1); |
|
1399 |
} |
|
1400 |
||
1401 |
void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { |
|
1402 |
pass_arg0(this, arg_0); |
|
1403 |
pass_arg1(this, arg_1); |
|
1404 |
call_VM_leaf_base(entry_point, 2); |
|
1405 |
} |
|
1406 |
||
1407 |
void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, |
|
1408 |
Register arg_1, Register arg_2) { |
|
1409 |
pass_arg0(this, arg_0); |
|
1410 |
pass_arg1(this, arg_1); |
|
1411 |
pass_arg2(this, arg_2); |
|
1412 |
call_VM_leaf_base(entry_point, 3); |
|
1413 |
} |
|
1414 |
||
1415 |
void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { |
|
1416 |
pass_arg0(this, arg_0); |
|
1417 |
MacroAssembler::call_VM_leaf_base(entry_point, 1); |
|
1418 |
} |
|
1419 |
||
1420 |
void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { |
|
1421 |
||
1422 |
assert(arg_0 != c_rarg1, "smashed arg"); |
|
1423 |
pass_arg1(this, arg_1); |
|
1424 |
pass_arg0(this, arg_0); |
|
1425 |
MacroAssembler::call_VM_leaf_base(entry_point, 2); |
|
1426 |
} |
|
1427 |
||
1428 |
void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { |
|
1429 |
assert(arg_0 != c_rarg2, "smashed arg"); |
|
1430 |
assert(arg_1 != c_rarg2, "smashed arg"); |
|
1431 |
pass_arg2(this, arg_2); |
|
1432 |
assert(arg_0 != c_rarg1, "smashed arg"); |
|
1433 |
pass_arg1(this, arg_1); |
|
1434 |
pass_arg0(this, arg_0); |
|
1435 |
MacroAssembler::call_VM_leaf_base(entry_point, 3); |
|
1436 |
} |
|
1437 |
||
1438 |
void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { |
|
1439 |
assert(arg_0 != c_rarg3, "smashed arg"); |
|
1440 |
assert(arg_1 != c_rarg3, "smashed arg"); |
|
1441 |
assert(arg_2 != c_rarg3, "smashed arg"); |
|
1442 |
pass_arg3(this, arg_3); |
|
1443 |
assert(arg_0 != c_rarg2, "smashed arg"); |
|
1444 |
assert(arg_1 != c_rarg2, "smashed arg"); |
|
1445 |
pass_arg2(this, arg_2); |
|
1446 |
assert(arg_0 != c_rarg1, "smashed arg"); |
|
1447 |
pass_arg1(this, arg_1); |
|
1448 |
pass_arg0(this, arg_0); |
|
1449 |
MacroAssembler::call_VM_leaf_base(entry_point, 4); |
|
1450 |
} |
|
1451 |
||
1452 |
void MacroAssembler::null_check(Register reg, int offset) { |
|
1453 |
if (needs_explicit_null_check(offset)) { |
|
1454 |
// provoke OS NULL exception if reg = NULL by |
|
1455 |
// accessing M[reg] w/o changing any registers |
|
1456 |
// NOTE: this is plenty to provoke a segv |
|
1457 |
ldr(zr, Address(reg)); |
|
1458 |
} else { |
|
1459 |
// nothing to do, (later) access of M[reg + offset] |
|
1460 |
// will provoke OS NULL exception if reg = NULL |
|
1461 |
} |
|
1462 |
} |
|
1463 |
||
1464 |
// MacroAssembler protected routines needed to implement |
|
1465 |
// public methods |
|
1466 |
||
1467 |
void MacroAssembler::mov(Register r, Address dest) { |
|
1468 |
code_section()->relocate(pc(), dest.rspec()); |
|
1469 |
u_int64_t imm64 = (u_int64_t)dest.target(); |
|
1470 |
movptr(r, imm64); |
|
1471 |
} |
|
1472 |
||
1473 |
// Move a constant pointer into r. In AArch64 mode the virtual |
|
1474 |
// address space is 48 bits in size, so we only need three |
|
1475 |
// instructions to create a patchable instruction sequence that can |
|
1476 |
// reach anywhere. |
|
1477 |
void MacroAssembler::movptr(Register r, uintptr_t imm64) { |
|
1478 |
#ifndef PRODUCT |
|
1479 |
{ |
|
1480 |
char buffer[64]; |
|
1481 |
snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64); |
|
1482 |
block_comment(buffer); |
|
1483 |
} |
|
1484 |
#endif |
|
1485 |
assert(imm64 < (1ul << 48), "48-bit overflow in address constant"); |
|
1486 |
movz(r, imm64 & 0xffff); |
|
1487 |
imm64 >>= 16; |
|
1488 |
movk(r, imm64 & 0xffff, 16); |
|
1489 |
imm64 >>= 16; |
|
1490 |
movk(r, imm64 & 0xffff, 32); |
|
1491 |
} |
|
1492 |
||
31227
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1493 |
// Macro to mov replicated immediate to vector register. |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1494 |
// Vd will get the following values for different arrangements in T |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1495 |
// imm32 == hex 000000gh T8B: Vd = ghghghghghghghgh |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1496 |
// imm32 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1497 |
// imm32 == hex 0000efgh T4H: Vd = efghefghefghefgh |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1498 |
// imm32 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1499 |
// imm32 == hex abcdefgh T2S: Vd = abcdefghabcdefgh |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1500 |
// imm32 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1501 |
// T1D/T2D: invalid |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1502 |
void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32) { |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1503 |
assert(T != T1D && T != T2D, "invalid arrangement"); |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1504 |
if (T == T8B || T == T16B) { |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1505 |
assert((imm32 & ~0xff) == 0, "extraneous bits in unsigned imm32 (T8B/T16B)"); |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1506 |
movi(Vd, T, imm32 & 0xff, 0); |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1507 |
return; |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1508 |
} |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1509 |
u_int32_t nimm32 = ~imm32; |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1510 |
if (T == T4H || T == T8H) { |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1511 |
assert((imm32 & ~0xffff) == 0, "extraneous bits in unsigned imm32 (T4H/T8H)"); |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1512 |
imm32 &= 0xffff; |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1513 |
nimm32 &= 0xffff; |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1514 |
} |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1515 |
u_int32_t x = imm32; |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1516 |
int movi_cnt = 0; |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1517 |
int movn_cnt = 0; |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1518 |
while (x) { if (x & 0xff) movi_cnt++; x >>= 8; } |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1519 |
x = nimm32; |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1520 |
while (x) { if (x & 0xff) movn_cnt++; x >>= 8; } |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1521 |
if (movn_cnt < movi_cnt) imm32 = nimm32; |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1522 |
unsigned lsl = 0; |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1523 |
while (imm32 && (imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; } |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1524 |
if (movn_cnt < movi_cnt) |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1525 |
mvni(Vd, T, imm32 & 0xff, lsl); |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1526 |
else |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1527 |
movi(Vd, T, imm32 & 0xff, lsl); |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1528 |
imm32 >>= 8; lsl += 8; |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1529 |
while (imm32) { |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1530 |
while ((imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; } |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1531 |
if (movn_cnt < movi_cnt) |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1532 |
bici(Vd, T, imm32 & 0xff, lsl); |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1533 |
else |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1534 |
orri(Vd, T, imm32 & 0xff, lsl); |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1535 |
lsl += 8; imm32 >>= 8; |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1536 |
} |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1537 |
} |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
1538 |
|
29183 | 1539 |
void MacroAssembler::mov_immediate64(Register dst, u_int64_t imm64) |
1540 |
{ |
|
1541 |
#ifndef PRODUCT |
|
1542 |
{ |
|
1543 |
char buffer[64]; |
|
1544 |
snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64); |
|
1545 |
block_comment(buffer); |
|
1546 |
} |
|
1547 |
#endif |
|
1548 |
if (operand_valid_for_logical_immediate(false, imm64)) { |
|
1549 |
orr(dst, zr, imm64); |
|
1550 |
} else { |
|
1551 |
// we can use a combination of MOVZ or MOVN with |
|
1552 |
// MOVK to build up the constant |
|
1553 |
u_int64_t imm_h[4]; |
|
1554 |
int zero_count = 0; |
|
1555 |
int neg_count = 0; |
|
1556 |
int i; |
|
1557 |
for (i = 0; i < 4; i++) { |
|
1558 |
imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL); |
|
1559 |
if (imm_h[i] == 0) { |
|
1560 |
zero_count++; |
|
1561 |
} else if (imm_h[i] == 0xffffL) { |
|
1562 |
neg_count++; |
|
1563 |
} |
|
1564 |
} |
|
1565 |
if (zero_count == 4) { |
|
1566 |
// one MOVZ will do |
|
1567 |
movz(dst, 0); |
|
1568 |
} else if (neg_count == 4) { |
|
1569 |
// one MOVN will do |
|
1570 |
movn(dst, 0); |
|
1571 |
} else if (zero_count == 3) { |
|
1572 |
for (i = 0; i < 4; i++) { |
|
1573 |
if (imm_h[i] != 0L) { |
|
1574 |
movz(dst, (u_int32_t)imm_h[i], (i << 4)); |
|
1575 |
break; |
|
1576 |
} |
|
1577 |
} |
|
1578 |
} else if (neg_count == 3) { |
|
1579 |
// one MOVN will do |
|
1580 |
for (int i = 0; i < 4; i++) { |
|
1581 |
if (imm_h[i] != 0xffffL) { |
|
1582 |
movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); |
|
1583 |
break; |
|
1584 |
} |
|
1585 |
} |
|
1586 |
} else if (zero_count == 2) { |
|
1587 |
// one MOVZ and one MOVK will do |
|
1588 |
for (i = 0; i < 3; i++) { |
|
1589 |
if (imm_h[i] != 0L) { |
|
1590 |
movz(dst, (u_int32_t)imm_h[i], (i << 4)); |
|
1591 |
i++; |
|
1592 |
break; |
|
1593 |
} |
|
1594 |
} |
|
1595 |
for (;i < 4; i++) { |
|
1596 |
if (imm_h[i] != 0L) { |
|
1597 |
movk(dst, (u_int32_t)imm_h[i], (i << 4)); |
|
1598 |
} |
|
1599 |
} |
|
1600 |
} else if (neg_count == 2) { |
|
1601 |
// one MOVN and one MOVK will do |
|
1602 |
for (i = 0; i < 4; i++) { |
|
1603 |
if (imm_h[i] != 0xffffL) { |
|
1604 |
movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); |
|
1605 |
i++; |
|
1606 |
break; |
|
1607 |
} |
|
1608 |
} |
|
1609 |
for (;i < 4; i++) { |
|
1610 |
if (imm_h[i] != 0xffffL) { |
|
1611 |
movk(dst, (u_int32_t)imm_h[i], (i << 4)); |
|
1612 |
} |
|
1613 |
} |
|
1614 |
} else if (zero_count == 1) { |
|
1615 |
// one MOVZ and two MOVKs will do |
|
1616 |
for (i = 0; i < 4; i++) { |
|
1617 |
if (imm_h[i] != 0L) { |
|
1618 |
movz(dst, (u_int32_t)imm_h[i], (i << 4)); |
|
1619 |
i++; |
|
1620 |
break; |
|
1621 |
} |
|
1622 |
} |
|
1623 |
for (;i < 4; i++) { |
|
1624 |
if (imm_h[i] != 0x0L) { |
|
1625 |
movk(dst, (u_int32_t)imm_h[i], (i << 4)); |
|
1626 |
} |
|
1627 |
} |
|
1628 |
} else if (neg_count == 1) { |
|
1629 |
// one MOVN and two MOVKs will do |
|
1630 |
for (i = 0; i < 4; i++) { |
|
1631 |
if (imm_h[i] != 0xffffL) { |
|
1632 |
movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); |
|
1633 |
i++; |
|
1634 |
break; |
|
1635 |
} |
|
1636 |
} |
|
1637 |
for (;i < 4; i++) { |
|
1638 |
if (imm_h[i] != 0xffffL) { |
|
1639 |
movk(dst, (u_int32_t)imm_h[i], (i << 4)); |
|
1640 |
} |
|
1641 |
} |
|
1642 |
} else { |
|
1643 |
// use a MOVZ and 3 MOVKs (makes it easier to debug) |
|
1644 |
movz(dst, (u_int32_t)imm_h[0], 0); |
|
1645 |
for (i = 1; i < 4; i++) { |
|
1646 |
movk(dst, (u_int32_t)imm_h[i], (i << 4)); |
|
1647 |
} |
|
1648 |
} |
|
1649 |
} |
|
1650 |
} |
|
1651 |
||
1652 |
void MacroAssembler::mov_immediate32(Register dst, u_int32_t imm32) |
|
1653 |
{ |
|
1654 |
#ifndef PRODUCT |
|
1655 |
{ |
|
1656 |
char buffer[64]; |
|
1657 |
snprintf(buffer, sizeof(buffer), "0x%"PRIX32, imm32); |
|
1658 |
block_comment(buffer); |
|
1659 |
} |
|
1660 |
#endif |
|
1661 |
if (operand_valid_for_logical_immediate(true, imm32)) { |
|
1662 |
orrw(dst, zr, imm32); |
|
1663 |
} else { |
|
1664 |
// we can use MOVZ, MOVN or two calls to MOVK to build up the |
|
1665 |
// constant |
|
1666 |
u_int32_t imm_h[2]; |
|
1667 |
imm_h[0] = imm32 & 0xffff; |
|
1668 |
imm_h[1] = ((imm32 >> 16) & 0xffff); |
|
1669 |
if (imm_h[0] == 0) { |
|
1670 |
movzw(dst, imm_h[1], 16); |
|
1671 |
} else if (imm_h[0] == 0xffff) { |
|
1672 |
movnw(dst, imm_h[1] ^ 0xffff, 16); |
|
1673 |
} else if (imm_h[1] == 0) { |
|
1674 |
movzw(dst, imm_h[0], 0); |
|
1675 |
} else if (imm_h[1] == 0xffff) { |
|
1676 |
movnw(dst, imm_h[0] ^ 0xffff, 0); |
|
1677 |
} else { |
|
1678 |
// use a MOVZ and MOVK (makes it easier to debug) |
|
1679 |
movzw(dst, imm_h[0], 0); |
|
1680 |
movkw(dst, imm_h[1], 16); |
|
1681 |
} |
|
1682 |
} |
|
1683 |
} |
|
1684 |
||
1685 |
// Form an address from base + offset in Rd. Rd may or may |
|
1686 |
// not actually be used: you must use the Address that is returned. |
|
1687 |
// It is up to you to ensure that the shift provided matches the size |
|
1688 |
// of your data. |
|
1689 |
Address MacroAssembler::form_address(Register Rd, Register base, long byte_offset, int shift) { |
|
1690 |
if (Address::offset_ok_for_immed(byte_offset, shift)) |
|
1691 |
// It fits; no need for any heroics |
|
1692 |
return Address(base, byte_offset); |
|
1693 |
||
1694 |
// Don't do anything clever with negative or misaligned offsets |
|
1695 |
unsigned mask = (1 << shift) - 1; |
|
1696 |
if (byte_offset < 0 || byte_offset & mask) { |
|
1697 |
mov(Rd, byte_offset); |
|
1698 |
add(Rd, base, Rd); |
|
1699 |
return Address(Rd); |
|
1700 |
} |
|
1701 |
||
1702 |
// See if we can do this with two 12-bit offsets |
|
1703 |
{ |
|
1704 |
unsigned long word_offset = byte_offset >> shift; |
|
1705 |
unsigned long masked_offset = word_offset & 0xfff000; |
|
1706 |
if (Address::offset_ok_for_immed(word_offset - masked_offset) |
|
1707 |
&& Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) { |
|
1708 |
add(Rd, base, masked_offset << shift); |
|
1709 |
word_offset -= masked_offset; |
|
1710 |
return Address(Rd, word_offset << shift); |
|
1711 |
} |
|
1712 |
} |
|
1713 |
||
1714 |
// Do it the hard way |
|
1715 |
mov(Rd, byte_offset); |
|
1716 |
add(Rd, base, Rd); |
|
1717 |
return Address(Rd); |
|
1718 |
} |
|
1719 |
||
32395
13b0caf18153
8133352: aarch64: generates constrained unpredictable instructions
enevill
parents:
32394
diff
changeset
|
1720 |
void MacroAssembler::atomic_incw(Register counter_addr, Register tmp, Register tmp2) { |
37269
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
1721 |
if (UseLSE) { |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
1722 |
mov(tmp, 1); |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
1723 |
ldadd(Assembler::word, tmp, zr, counter_addr); |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
1724 |
return; |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
1725 |
} |
29183 | 1726 |
Label retry_load; |
38714
170464570e45
8157841: aarch64: prefetch ignores cache line size
enevill
parents:
38713
diff
changeset
|
1727 |
if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) |
170464570e45
8157841: aarch64: prefetch ignores cache line size
enevill
parents:
38713
diff
changeset
|
1728 |
prfm(Address(counter_addr), PSTL1STRM); |
29183 | 1729 |
bind(retry_load); |
1730 |
// flush and load exclusive from the memory location |
|
1731 |
ldxrw(tmp, counter_addr); |
|
1732 |
addw(tmp, tmp, 1); |
|
1733 |
// if we store+flush with no intervening write tmp wil be zero |
|
32395
13b0caf18153
8133352: aarch64: generates constrained unpredictable instructions
enevill
parents:
32394
diff
changeset
|
1734 |
stxrw(tmp2, tmp, counter_addr); |
13b0caf18153
8133352: aarch64: generates constrained unpredictable instructions
enevill
parents:
32394
diff
changeset
|
1735 |
cbnzw(tmp2, retry_load); |
29183 | 1736 |
} |
1737 |
||
1738 |
||
1739 |
int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb, |
|
1740 |
bool want_remainder, Register scratch) |
|
1741 |
{ |
|
1742 |
// Full implementation of Java idiv and irem. The function |
|
1743 |
// returns the (pc) offset of the div instruction - may be needed |
|
1744 |
// for implicit exceptions. |
|
1745 |
// |
|
1746 |
// constraint : ra/rb =/= scratch |
|
1747 |
// normal case |
|
1748 |
// |
|
1749 |
// input : ra: dividend |
|
1750 |
// rb: divisor |
|
1751 |
// |
|
1752 |
// result: either |
|
1753 |
// quotient (= ra idiv rb) |
|
1754 |
// remainder (= ra irem rb) |
|
1755 |
||
1756 |
assert(ra != scratch && rb != scratch, "reg cannot be scratch"); |
|
1757 |
||
1758 |
int idivl_offset = offset(); |
|
1759 |
if (! want_remainder) { |
|
1760 |
sdivw(result, ra, rb); |
|
1761 |
} else { |
|
1762 |
sdivw(scratch, ra, rb); |
|
30429
c980154ed1a3
8079203: AARCH64: Need to cater for different partner implementations
enevill
parents:
30313
diff
changeset
|
1763 |
Assembler::msubw(result, scratch, rb, ra); |
29183 | 1764 |
} |
1765 |
||
1766 |
return idivl_offset; |
|
1767 |
} |
|
1768 |
||
1769 |
int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb, |
|
1770 |
bool want_remainder, Register scratch) |
|
1771 |
{ |
|
1772 |
// Full implementation of Java ldiv and lrem. The function |
|
1773 |
// returns the (pc) offset of the div instruction - may be needed |
|
1774 |
// for implicit exceptions. |
|
1775 |
// |
|
1776 |
// constraint : ra/rb =/= scratch |
|
1777 |
// normal case |
|
1778 |
// |
|
1779 |
// input : ra: dividend |
|
1780 |
// rb: divisor |
|
1781 |
// |
|
1782 |
// result: either |
|
1783 |
// quotient (= ra idiv rb) |
|
1784 |
// remainder (= ra irem rb) |
|
1785 |
||
1786 |
assert(ra != scratch && rb != scratch, "reg cannot be scratch"); |
|
1787 |
||
1788 |
int idivq_offset = offset(); |
|
1789 |
if (! want_remainder) { |
|
1790 |
sdiv(result, ra, rb); |
|
1791 |
} else { |
|
1792 |
sdiv(scratch, ra, rb); |
|
30429
c980154ed1a3
8079203: AARCH64: Need to cater for different partner implementations
enevill
parents:
30313
diff
changeset
|
1793 |
Assembler::msub(result, scratch, rb, ra); |
29183 | 1794 |
} |
1795 |
||
1796 |
return idivq_offset; |
|
1797 |
} |
|
1798 |
||
33193 | 1799 |
void MacroAssembler::membar(Membar_mask_bits order_constraint) { |
1800 |
address prev = pc() - NativeMembar::instruction_size; |
|
49161
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1801 |
address last = code()->last_insn(); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1802 |
if (last != NULL && nativeInstruction_at(last)->is_Membar() && prev == last) { |
33193 | 1803 |
NativeMembar *bar = NativeMembar_at(prev); |
1804 |
// We are merging two memory barrier instructions. On AArch64 we |
|
1805 |
// can do this simply by ORing them together. |
|
1806 |
bar->set_kind(bar->get_kind() | order_constraint); |
|
1807 |
BLOCK_COMMENT("merged membar"); |
|
1808 |
} else { |
|
49161
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1809 |
code()->set_last_insn(pc()); |
33193 | 1810 |
dmb(Assembler::barrier(order_constraint)); |
1811 |
} |
|
1812 |
} |
|
1813 |
||
49161
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1814 |
bool MacroAssembler::try_merge_ldst(Register rt, const Address &adr, size_t size_in_bytes, bool is_store) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1815 |
if (ldst_can_merge(rt, adr, size_in_bytes, is_store)) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1816 |
merge_ldst(rt, adr, size_in_bytes, is_store); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1817 |
code()->clear_last_insn(); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1818 |
return true; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1819 |
} else { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1820 |
assert(size_in_bytes == 8 || size_in_bytes == 4, "only 8 bytes or 4 bytes load/store is supported."); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1821 |
const unsigned mask = size_in_bytes - 1; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1822 |
if (adr.getMode() == Address::base_plus_offset && |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1823 |
(adr.offset() & mask) == 0) { // only supports base_plus_offset. |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1824 |
code()->set_last_insn(pc()); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1825 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1826 |
return false; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1827 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1828 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1829 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1830 |
void MacroAssembler::ldr(Register Rx, const Address &adr) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1831 |
// We always try to merge two adjacent loads into one ldp. |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1832 |
if (!try_merge_ldst(Rx, adr, 8, false)) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1833 |
Assembler::ldr(Rx, adr); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1834 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1835 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1836 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1837 |
void MacroAssembler::ldrw(Register Rw, const Address &adr) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1838 |
// We always try to merge two adjacent loads into one ldp. |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1839 |
if (!try_merge_ldst(Rw, adr, 4, false)) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1840 |
Assembler::ldrw(Rw, adr); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1841 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1842 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1843 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1844 |
void MacroAssembler::str(Register Rx, const Address &adr) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1845 |
// We always try to merge two adjacent stores into one stp. |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1846 |
if (!try_merge_ldst(Rx, adr, 8, true)) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1847 |
Assembler::str(Rx, adr); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1848 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1849 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1850 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1851 |
void MacroAssembler::strw(Register Rw, const Address &adr) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1852 |
// We always try to merge two adjacent stores into one stp. |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1853 |
if (!try_merge_ldst(Rw, adr, 4, true)) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1854 |
Assembler::strw(Rw, adr); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1855 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
1856 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
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diff
changeset
|
1857 |
|
29183 | 1858 |
// MacroAssembler routines found actually to be needed |
1859 |
||
1860 |
void MacroAssembler::push(Register src) |
|
1861 |
{ |
|
1862 |
str(src, Address(pre(esp, -1 * wordSize))); |
|
1863 |
} |
|
1864 |
||
1865 |
void MacroAssembler::pop(Register dst) |
|
1866 |
{ |
|
1867 |
ldr(dst, Address(post(esp, 1 * wordSize))); |
|
1868 |
} |
|
1869 |
||
1870 |
// Note: load_unsigned_short used to be called load_unsigned_word. |
|
1871 |
int MacroAssembler::load_unsigned_short(Register dst, Address src) { |
|
1872 |
int off = offset(); |
|
1873 |
ldrh(dst, src); |
|
1874 |
return off; |
|
1875 |
} |
|
1876 |
||
1877 |
int MacroAssembler::load_unsigned_byte(Register dst, Address src) { |
|
1878 |
int off = offset(); |
|
1879 |
ldrb(dst, src); |
|
1880 |
return off; |
|
1881 |
} |
|
1882 |
||
1883 |
int MacroAssembler::load_signed_short(Register dst, Address src) { |
|
1884 |
int off = offset(); |
|
1885 |
ldrsh(dst, src); |
|
1886 |
return off; |
|
1887 |
} |
|
1888 |
||
1889 |
int MacroAssembler::load_signed_byte(Register dst, Address src) { |
|
1890 |
int off = offset(); |
|
1891 |
ldrsb(dst, src); |
|
1892 |
return off; |
|
1893 |
} |
|
1894 |
||
1895 |
int MacroAssembler::load_signed_short32(Register dst, Address src) { |
|
1896 |
int off = offset(); |
|
1897 |
ldrshw(dst, src); |
|
1898 |
return off; |
|
1899 |
} |
|
1900 |
||
1901 |
int MacroAssembler::load_signed_byte32(Register dst, Address src) { |
|
1902 |
int off = offset(); |
|
1903 |
ldrsbw(dst, src); |
|
1904 |
return off; |
|
1905 |
} |
|
1906 |
||
1907 |
void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { |
|
1908 |
switch (size_in_bytes) { |
|
1909 |
case 8: ldr(dst, src); break; |
|
1910 |
case 4: ldrw(dst, src); break; |
|
1911 |
case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; |
|
1912 |
case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; |
|
1913 |
default: ShouldNotReachHere(); |
|
1914 |
} |
|
1915 |
} |
|
1916 |
||
1917 |
void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { |
|
1918 |
switch (size_in_bytes) { |
|
1919 |
case 8: str(src, dst); break; |
|
1920 |
case 4: strw(src, dst); break; |
|
1921 |
case 2: strh(src, dst); break; |
|
1922 |
case 1: strb(src, dst); break; |
|
1923 |
default: ShouldNotReachHere(); |
|
1924 |
} |
|
1925 |
} |
|
1926 |
||
1927 |
void MacroAssembler::decrementw(Register reg, int value) |
|
1928 |
{ |
|
1929 |
if (value < 0) { incrementw(reg, -value); return; } |
|
1930 |
if (value == 0) { return; } |
|
1931 |
if (value < (1 << 12)) { subw(reg, reg, value); return; } |
|
1932 |
/* else */ { |
|
1933 |
guarantee(reg != rscratch2, "invalid dst for register decrement"); |
|
1934 |
movw(rscratch2, (unsigned)value); |
|
1935 |
subw(reg, reg, rscratch2); |
|
1936 |
} |
|
1937 |
} |
|
1938 |
||
1939 |
void MacroAssembler::decrement(Register reg, int value) |
|
1940 |
{ |
|
1941 |
if (value < 0) { increment(reg, -value); return; } |
|
1942 |
if (value == 0) { return; } |
|
1943 |
if (value < (1 << 12)) { sub(reg, reg, value); return; } |
|
1944 |
/* else */ { |
|
1945 |
assert(reg != rscratch2, "invalid dst for register decrement"); |
|
1946 |
mov(rscratch2, (unsigned long)value); |
|
1947 |
sub(reg, reg, rscratch2); |
|
1948 |
} |
|
1949 |
} |
|
1950 |
||
1951 |
void MacroAssembler::decrementw(Address dst, int value) |
|
1952 |
{ |
|
1953 |
assert(!dst.uses(rscratch1), "invalid dst for address decrement"); |
|
49959
313dd42409d6
8202186: AArch64: Debug build VM crashes with PrintC1Statistics option
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parents:
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diff
changeset
|
1954 |
if (dst.getMode() == Address::literal) { |
313dd42409d6
8202186: AArch64: Debug build VM crashes with PrintC1Statistics option
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parents:
49816
diff
changeset
|
1955 |
assert(abs(value) < (1 << 12), "invalid value and address mode combination"); |
313dd42409d6
8202186: AArch64: Debug build VM crashes with PrintC1Statistics option
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parents:
49816
diff
changeset
|
1956 |
lea(rscratch2, dst); |
313dd42409d6
8202186: AArch64: Debug build VM crashes with PrintC1Statistics option
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parents:
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diff
changeset
|
1957 |
dst = Address(rscratch2); |
313dd42409d6
8202186: AArch64: Debug build VM crashes with PrintC1Statistics option
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parents:
49816
diff
changeset
|
1958 |
} |
29183 | 1959 |
ldrw(rscratch1, dst); |
1960 |
decrementw(rscratch1, value); |
|
1961 |
strw(rscratch1, dst); |
|
1962 |
} |
|
1963 |
||
1964 |
void MacroAssembler::decrement(Address dst, int value) |
|
1965 |
{ |
|
1966 |
assert(!dst.uses(rscratch1), "invalid address for decrement"); |
|
49959
313dd42409d6
8202186: AArch64: Debug build VM crashes with PrintC1Statistics option
njian
parents:
49816
diff
changeset
|
1967 |
if (dst.getMode() == Address::literal) { |
313dd42409d6
8202186: AArch64: Debug build VM crashes with PrintC1Statistics option
njian
parents:
49816
diff
changeset
|
1968 |
assert(abs(value) < (1 << 12), "invalid value and address mode combination"); |
313dd42409d6
8202186: AArch64: Debug build VM crashes with PrintC1Statistics option
njian
parents:
49816
diff
changeset
|
1969 |
lea(rscratch2, dst); |
313dd42409d6
8202186: AArch64: Debug build VM crashes with PrintC1Statistics option
njian
parents:
49816
diff
changeset
|
1970 |
dst = Address(rscratch2); |
313dd42409d6
8202186: AArch64: Debug build VM crashes with PrintC1Statistics option
njian
parents:
49816
diff
changeset
|
1971 |
} |
29183 | 1972 |
ldr(rscratch1, dst); |
1973 |
decrement(rscratch1, value); |
|
1974 |
str(rscratch1, dst); |
|
1975 |
} |
|
1976 |
||
1977 |
void MacroAssembler::incrementw(Register reg, int value) |
|
1978 |
{ |
|
1979 |
if (value < 0) { decrementw(reg, -value); return; } |
|
1980 |
if (value == 0) { return; } |
|
1981 |
if (value < (1 << 12)) { addw(reg, reg, value); return; } |
|
1982 |
/* else */ { |
|
1983 |
assert(reg != rscratch2, "invalid dst for register increment"); |
|
1984 |
movw(rscratch2, (unsigned)value); |
|
1985 |
addw(reg, reg, rscratch2); |
|
1986 |
} |
|
1987 |
} |
|
1988 |
||
1989 |
void MacroAssembler::increment(Register reg, int value) |
|
1990 |
{ |
|
1991 |
if (value < 0) { decrement(reg, -value); return; } |
|
1992 |
if (value == 0) { return; } |
|
1993 |
if (value < (1 << 12)) { add(reg, reg, value); return; } |
|
1994 |
/* else */ { |
|
1995 |
assert(reg != rscratch2, "invalid dst for register increment"); |
|
1996 |
movw(rscratch2, (unsigned)value); |
|
1997 |
add(reg, reg, rscratch2); |
|
1998 |
} |
|
1999 |
} |
|
2000 |
||
2001 |
void MacroAssembler::incrementw(Address dst, int value) |
|
2002 |
{ |
|
2003 |
assert(!dst.uses(rscratch1), "invalid dst for address increment"); |
|
49959
313dd42409d6
8202186: AArch64: Debug build VM crashes with PrintC1Statistics option
njian
parents:
49816
diff
changeset
|
2004 |
if (dst.getMode() == Address::literal) { |
313dd42409d6
8202186: AArch64: Debug build VM crashes with PrintC1Statistics option
njian
parents:
49816
diff
changeset
|
2005 |
assert(abs(value) < (1 << 12), "invalid value and address mode combination"); |
313dd42409d6
8202186: AArch64: Debug build VM crashes with PrintC1Statistics option
njian
parents:
49816
diff
changeset
|
2006 |
lea(rscratch2, dst); |
313dd42409d6
8202186: AArch64: Debug build VM crashes with PrintC1Statistics option
njian
parents:
49816
diff
changeset
|
2007 |
dst = Address(rscratch2); |
313dd42409d6
8202186: AArch64: Debug build VM crashes with PrintC1Statistics option
njian
parents:
49816
diff
changeset
|
2008 |
} |
29183 | 2009 |
ldrw(rscratch1, dst); |
2010 |
incrementw(rscratch1, value); |
|
2011 |
strw(rscratch1, dst); |
|
2012 |
} |
|
2013 |
||
2014 |
void MacroAssembler::increment(Address dst, int value) |
|
2015 |
{ |
|
2016 |
assert(!dst.uses(rscratch1), "invalid dst for address increment"); |
|
49959
313dd42409d6
8202186: AArch64: Debug build VM crashes with PrintC1Statistics option
njian
parents:
49816
diff
changeset
|
2017 |
if (dst.getMode() == Address::literal) { |
313dd42409d6
8202186: AArch64: Debug build VM crashes with PrintC1Statistics option
njian
parents:
49816
diff
changeset
|
2018 |
assert(abs(value) < (1 << 12), "invalid value and address mode combination"); |
313dd42409d6
8202186: AArch64: Debug build VM crashes with PrintC1Statistics option
njian
parents:
49816
diff
changeset
|
2019 |
lea(rscratch2, dst); |
313dd42409d6
8202186: AArch64: Debug build VM crashes with PrintC1Statistics option
njian
parents:
49816
diff
changeset
|
2020 |
dst = Address(rscratch2); |
313dd42409d6
8202186: AArch64: Debug build VM crashes with PrintC1Statistics option
njian
parents:
49816
diff
changeset
|
2021 |
} |
29183 | 2022 |
ldr(rscratch1, dst); |
2023 |
increment(rscratch1, value); |
|
2024 |
str(rscratch1, dst); |
|
2025 |
} |
|
2026 |
||
2027 |
||
2028 |
void MacroAssembler::pusha() { |
|
2029 |
push(0x7fffffff, sp); |
|
2030 |
} |
|
2031 |
||
2032 |
void MacroAssembler::popa() { |
|
2033 |
pop(0x7fffffff, sp); |
|
2034 |
} |
|
2035 |
||
2036 |
// Push lots of registers in the bit set supplied. Don't push sp. |
|
2037 |
// Return the number of words pushed |
|
2038 |
int MacroAssembler::push(unsigned int bitset, Register stack) { |
|
2039 |
int words_pushed = 0; |
|
2040 |
||
2041 |
// Scan bitset to accumulate register pairs |
|
2042 |
unsigned char regs[32]; |
|
2043 |
int count = 0; |
|
2044 |
for (int reg = 0; reg <= 30; reg++) { |
|
2045 |
if (1 & bitset) |
|
2046 |
regs[count++] = reg; |
|
2047 |
bitset >>= 1; |
|
2048 |
} |
|
2049 |
regs[count++] = zr->encoding_nocheck(); |
|
2050 |
count &= ~1; // Only push an even nuber of regs |
|
2051 |
||
2052 |
if (count) { |
|
2053 |
stp(as_Register(regs[0]), as_Register(regs[1]), |
|
2054 |
Address(pre(stack, -count * wordSize))); |
|
2055 |
words_pushed += 2; |
|
2056 |
} |
|
2057 |
for (int i = 2; i < count; i += 2) { |
|
2058 |
stp(as_Register(regs[i]), as_Register(regs[i+1]), |
|
2059 |
Address(stack, i * wordSize)); |
|
2060 |
words_pushed += 2; |
|
2061 |
} |
|
2062 |
||
2063 |
assert(words_pushed == count, "oops, pushed != count"); |
|
2064 |
||
2065 |
return count; |
|
2066 |
} |
|
2067 |
||
2068 |
int MacroAssembler::pop(unsigned int bitset, Register stack) { |
|
2069 |
int words_pushed = 0; |
|
2070 |
||
2071 |
// Scan bitset to accumulate register pairs |
|
2072 |
unsigned char regs[32]; |
|
2073 |
int count = 0; |
|
2074 |
for (int reg = 0; reg <= 30; reg++) { |
|
2075 |
if (1 & bitset) |
|
2076 |
regs[count++] = reg; |
|
2077 |
bitset >>= 1; |
|
2078 |
} |
|
2079 |
regs[count++] = zr->encoding_nocheck(); |
|
2080 |
count &= ~1; |
|
2081 |
||
2082 |
for (int i = 2; i < count; i += 2) { |
|
2083 |
ldp(as_Register(regs[i]), as_Register(regs[i+1]), |
|
2084 |
Address(stack, i * wordSize)); |
|
2085 |
words_pushed += 2; |
|
2086 |
} |
|
2087 |
if (count) { |
|
2088 |
ldp(as_Register(regs[0]), as_Register(regs[1]), |
|
2089 |
Address(post(stack, count * wordSize))); |
|
2090 |
words_pushed += 2; |
|
2091 |
} |
|
2092 |
||
2093 |
assert(words_pushed == count, "oops, pushed != count"); |
|
2094 |
||
2095 |
return count; |
|
2096 |
} |
|
2097 |
#ifdef ASSERT |
|
2098 |
void MacroAssembler::verify_heapbase(const char* msg) { |
|
2099 |
#if 0 |
|
2100 |
assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed"); |
|
2101 |
assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
2102 |
if (CheckCompressedOops) { |
|
2103 |
Label ok; |
|
2104 |
push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1 |
|
2105 |
cmpptr(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); |
|
2106 |
br(Assembler::EQ, ok); |
|
2107 |
stop(msg); |
|
2108 |
bind(ok); |
|
2109 |
pop(1 << rscratch1->encoding(), sp); |
|
2110 |
} |
|
2111 |
#endif |
|
2112 |
} |
|
2113 |
#endif |
|
2114 |
||
49748 | 2115 |
void MacroAssembler::resolve_jobject(Register value, Register thread, Register tmp) { |
2116 |
Label done, not_weak; |
|
2117 |
cbz(value, done); // Use NULL as-is. |
|
2118 |
||
2119 |
STATIC_ASSERT(JNIHandles::weak_tag_mask == 1u); |
|
2120 |
tbz(r0, 0, not_weak); // Test for jweak tag. |
|
2121 |
||
2122 |
// Resolve jweak. |
|
50599
ecc2af326b5f
8204939: Change Access nomenclature: root to native
kbarrett
parents:
50536
diff
changeset
|
2123 |
access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF, value, |
50517
618526574f8b
8204628: [AArch64] Assertion failure in BarrierSetAssembler::load_at
smonteith
parents:
50446
diff
changeset
|
2124 |
Address(value, -JNIHandles::weak_tag_value), tmp, thread); |
49748 | 2125 |
verify_oop(value); |
2126 |
b(done); |
|
2127 |
||
2128 |
bind(not_weak); |
|
2129 |
// Resolve (untagged) jobject. |
|
50517
618526574f8b
8204628: [AArch64] Assertion failure in BarrierSetAssembler::load_at
smonteith
parents:
50446
diff
changeset
|
2130 |
access_load_at(T_OBJECT, IN_CONCURRENT_ROOT, value, Address(value, 0), tmp, |
618526574f8b
8204628: [AArch64] Assertion failure in BarrierSetAssembler::load_at
smonteith
parents:
50446
diff
changeset
|
2131 |
thread); |
49748 | 2132 |
verify_oop(value); |
2133 |
bind(done); |
|
2134 |
} |
|
2135 |
||
29183 | 2136 |
void MacroAssembler::stop(const char* msg) { |
2137 |
address ip = pc(); |
|
2138 |
pusha(); |
|
2139 |
mov(c_rarg0, (address)msg); |
|
2140 |
mov(c_rarg1, (address)ip); |
|
2141 |
mov(c_rarg2, sp); |
|
2142 |
mov(c_rarg3, CAST_FROM_FN_PTR(address, MacroAssembler::debug64)); |
|
2143 |
// call(c_rarg3); |
|
2144 |
blrt(c_rarg3, 3, 0, 1); |
|
2145 |
hlt(0); |
|
2146 |
} |
|
2147 |
||
46560
388aa8d67c80
8181449: Fix debug.hpp / globalDefinitions.hpp dependency inversion
kbarrett
parents:
46458
diff
changeset
|
2148 |
void MacroAssembler::unimplemented(const char* what) { |
48968
8c64b94dca9d
8197608: MacroAssembler::unimplemented calls global operator new[]
thartmann
parents:
48718
diff
changeset
|
2149 |
const char* buf = NULL; |
8c64b94dca9d
8197608: MacroAssembler::unimplemented calls global operator new[]
thartmann
parents:
48718
diff
changeset
|
2150 |
{ |
8c64b94dca9d
8197608: MacroAssembler::unimplemented calls global operator new[]
thartmann
parents:
48718
diff
changeset
|
2151 |
ResourceMark rm; |
8c64b94dca9d
8197608: MacroAssembler::unimplemented calls global operator new[]
thartmann
parents:
48718
diff
changeset
|
2152 |
stringStream ss; |
8c64b94dca9d
8197608: MacroAssembler::unimplemented calls global operator new[]
thartmann
parents:
48718
diff
changeset
|
2153 |
ss.print("unimplemented: %s", what); |
8c64b94dca9d
8197608: MacroAssembler::unimplemented calls global operator new[]
thartmann
parents:
48718
diff
changeset
|
2154 |
buf = code_string(ss.as_string()); |
8c64b94dca9d
8197608: MacroAssembler::unimplemented calls global operator new[]
thartmann
parents:
48718
diff
changeset
|
2155 |
} |
8c64b94dca9d
8197608: MacroAssembler::unimplemented calls global operator new[]
thartmann
parents:
48718
diff
changeset
|
2156 |
stop(buf); |
46560
388aa8d67c80
8181449: Fix debug.hpp / globalDefinitions.hpp dependency inversion
kbarrett
parents:
46458
diff
changeset
|
2157 |
} |
388aa8d67c80
8181449: Fix debug.hpp / globalDefinitions.hpp dependency inversion
kbarrett
parents:
46458
diff
changeset
|
2158 |
|
29183 | 2159 |
// If a constant does not fit in an immediate field, generate some |
2160 |
// number of MOV instructions and then perform the operation. |
|
2161 |
void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm, |
|
2162 |
add_sub_imm_insn insn1, |
|
2163 |
add_sub_reg_insn insn2) { |
|
2164 |
assert(Rd != zr, "Rd = zr and not setting flags?"); |
|
2165 |
if (operand_valid_for_add_sub_immediate((int)imm)) { |
|
2166 |
(this->*insn1)(Rd, Rn, imm); |
|
2167 |
} else { |
|
2168 |
if (uabs(imm) < (1 << 24)) { |
|
2169 |
(this->*insn1)(Rd, Rn, imm & -(1 << 12)); |
|
2170 |
(this->*insn1)(Rd, Rd, imm & ((1 << 12)-1)); |
|
2171 |
} else { |
|
2172 |
assert_different_registers(Rd, Rn); |
|
2173 |
mov(Rd, (uint64_t)imm); |
|
2174 |
(this->*insn2)(Rd, Rn, Rd, LSL, 0); |
|
2175 |
} |
|
2176 |
} |
|
2177 |
} |
|
2178 |
||
2179 |
// Seperate vsn which sets the flags. Optimisations are more restricted |
|
2180 |
// because we must set the flags correctly. |
|
2181 |
void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm, |
|
2182 |
add_sub_imm_insn insn1, |
|
2183 |
add_sub_reg_insn insn2) { |
|
2184 |
if (operand_valid_for_add_sub_immediate((int)imm)) { |
|
2185 |
(this->*insn1)(Rd, Rn, imm); |
|
2186 |
} else { |
|
2187 |
assert_different_registers(Rd, Rn); |
|
2188 |
assert(Rd != zr, "overflow in immediate operand"); |
|
2189 |
mov(Rd, (uint64_t)imm); |
|
2190 |
(this->*insn2)(Rd, Rn, Rd, LSL, 0); |
|
2191 |
} |
|
2192 |
} |
|
2193 |
||
2194 |
||
2195 |
void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) { |
|
2196 |
if (increment.is_register()) { |
|
2197 |
add(Rd, Rn, increment.as_register()); |
|
2198 |
} else { |
|
2199 |
add(Rd, Rn, increment.as_constant()); |
|
2200 |
} |
|
2201 |
} |
|
2202 |
||
2203 |
void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) { |
|
2204 |
if (increment.is_register()) { |
|
2205 |
addw(Rd, Rn, increment.as_register()); |
|
2206 |
} else { |
|
2207 |
addw(Rd, Rn, increment.as_constant()); |
|
2208 |
} |
|
2209 |
} |
|
2210 |
||
31955 | 2211 |
void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) { |
2212 |
if (decrement.is_register()) { |
|
2213 |
sub(Rd, Rn, decrement.as_register()); |
|
2214 |
} else { |
|
2215 |
sub(Rd, Rn, decrement.as_constant()); |
|
2216 |
} |
|
2217 |
} |
|
2218 |
||
32395
13b0caf18153
8133352: aarch64: generates constrained unpredictable instructions
enevill
parents:
32394
diff
changeset
|
2219 |
void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) { |
13b0caf18153
8133352: aarch64: generates constrained unpredictable instructions
enevill
parents:
32394
diff
changeset
|
2220 |
if (decrement.is_register()) { |
13b0caf18153
8133352: aarch64: generates constrained unpredictable instructions
enevill
parents:
32394
diff
changeset
|
2221 |
subw(Rd, Rn, decrement.as_register()); |
13b0caf18153
8133352: aarch64: generates constrained unpredictable instructions
enevill
parents:
32394
diff
changeset
|
2222 |
} else { |
13b0caf18153
8133352: aarch64: generates constrained unpredictable instructions
enevill
parents:
32394
diff
changeset
|
2223 |
subw(Rd, Rn, decrement.as_constant()); |
13b0caf18153
8133352: aarch64: generates constrained unpredictable instructions
enevill
parents:
32394
diff
changeset
|
2224 |
} |
13b0caf18153
8133352: aarch64: generates constrained unpredictable instructions
enevill
parents:
32394
diff
changeset
|
2225 |
} |
13b0caf18153
8133352: aarch64: generates constrained unpredictable instructions
enevill
parents:
32394
diff
changeset
|
2226 |
|
29183 | 2227 |
void MacroAssembler::reinit_heapbase() |
2228 |
{ |
|
2229 |
if (UseCompressedOops) { |
|
2230 |
if (Universe::is_fully_initialized()) { |
|
2231 |
mov(rheapbase, Universe::narrow_ptrs_base()); |
|
2232 |
} else { |
|
2233 |
lea(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); |
|
2234 |
ldr(rheapbase, Address(rheapbase)); |
|
2235 |
} |
|
2236 |
} |
|
2237 |
} |
|
2238 |
||
2239 |
// this simulates the behaviour of the x86 cmpxchg instruction using a |
|
2240 |
// load linked/store conditional pair. we use the acquire/release |
|
2241 |
// versions of these instructions so that we flush pending writes as |
|
2242 |
// per Java semantics. |
|
2243 |
||
2244 |
// n.b the x86 version assumes the old value to be compared against is |
|
2245 |
// in rax and updates rax with the value located in memory if the |
|
2246 |
// cmpxchg fails. we supply a register for the old value explicitly |
|
2247 |
||
2248 |
// the aarch64 load linked/store conditional instructions do not |
|
2249 |
// accept an offset. so, unlike x86, we must provide a plain register |
|
2250 |
// to identify the memory word to be compared/exchanged rather than a |
|
2251 |
// register+offset Address. |
|
2252 |
||
2253 |
void MacroAssembler::cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp, |
|
2254 |
Label &succeed, Label *fail) { |
|
2255 |
// oldv holds comparison value |
|
2256 |
// newv holds value to write in exchange |
|
2257 |
// addr identifies memory word to compare against/update |
|
36562
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2258 |
if (UseLSE) { |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2259 |
mov(tmp, oldv); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2260 |
casal(Assembler::xword, oldv, newv, addr); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2261 |
cmp(tmp, oldv); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2262 |
br(Assembler::EQ, succeed); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2263 |
membar(AnyAny); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2264 |
} else { |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2265 |
Label retry_load, nope; |
38714
170464570e45
8157841: aarch64: prefetch ignores cache line size
enevill
parents:
38713
diff
changeset
|
2266 |
if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) |
170464570e45
8157841: aarch64: prefetch ignores cache line size
enevill
parents:
38713
diff
changeset
|
2267 |
prfm(Address(addr), PSTL1STRM); |
36562
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2268 |
bind(retry_load); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2269 |
// flush and load exclusive from the memory location |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2270 |
// and fail if it is not what we expect |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2271 |
ldaxr(tmp, addr); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2272 |
cmp(tmp, oldv); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2273 |
br(Assembler::NE, nope); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2274 |
// if we store+flush with no intervening write tmp wil be zero |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2275 |
stlxr(tmp, newv, addr); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2276 |
cbzw(tmp, succeed); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2277 |
// retry so we only ever return after a load fails to compare |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2278 |
// ensures we don't return a stale value after a failed write. |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2279 |
b(retry_load); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2280 |
// if the memory word differs we return it in oldv and signal a fail |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2281 |
bind(nope); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2282 |
membar(AnyAny); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2283 |
mov(oldv, tmp); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2284 |
} |
29183 | 2285 |
if (fail) |
2286 |
b(*fail); |
|
2287 |
} |
|
2288 |
||
46449
7b2416f0f524
8167659: Access of mark word should use oopDesc::mark_offset_in_bytes() instead of '0'
rkennke
parents:
43439
diff
changeset
|
2289 |
void MacroAssembler::cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp, |
7b2416f0f524
8167659: Access of mark word should use oopDesc::mark_offset_in_bytes() instead of '0'
rkennke
parents:
43439
diff
changeset
|
2290 |
Label &succeed, Label *fail) { |
7b2416f0f524
8167659: Access of mark word should use oopDesc::mark_offset_in_bytes() instead of '0'
rkennke
parents:
43439
diff
changeset
|
2291 |
assert(oopDesc::mark_offset_in_bytes() == 0, "assumption"); |
7b2416f0f524
8167659: Access of mark word should use oopDesc::mark_offset_in_bytes() instead of '0'
rkennke
parents:
43439
diff
changeset
|
2292 |
cmpxchgptr(oldv, newv, obj, tmp, succeed, fail); |
7b2416f0f524
8167659: Access of mark word should use oopDesc::mark_offset_in_bytes() instead of '0'
rkennke
parents:
43439
diff
changeset
|
2293 |
} |
7b2416f0f524
8167659: Access of mark word should use oopDesc::mark_offset_in_bytes() instead of '0'
rkennke
parents:
43439
diff
changeset
|
2294 |
|
29183 | 2295 |
void MacroAssembler::cmpxchgw(Register oldv, Register newv, Register addr, Register tmp, |
2296 |
Label &succeed, Label *fail) { |
|
2297 |
// oldv holds comparison value |
|
2298 |
// newv holds value to write in exchange |
|
2299 |
// addr identifies memory word to compare against/update |
|
2300 |
// tmp returns 0/1 for success/failure |
|
36562
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2301 |
if (UseLSE) { |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2302 |
mov(tmp, oldv); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2303 |
casal(Assembler::word, oldv, newv, addr); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2304 |
cmp(tmp, oldv); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2305 |
br(Assembler::EQ, succeed); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2306 |
membar(AnyAny); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2307 |
} else { |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2308 |
Label retry_load, nope; |
38714
170464570e45
8157841: aarch64: prefetch ignores cache line size
enevill
parents:
38713
diff
changeset
|
2309 |
if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) |
170464570e45
8157841: aarch64: prefetch ignores cache line size
enevill
parents:
38713
diff
changeset
|
2310 |
prfm(Address(addr), PSTL1STRM); |
36562
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2311 |
bind(retry_load); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2312 |
// flush and load exclusive from the memory location |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2313 |
// and fail if it is not what we expect |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2314 |
ldaxrw(tmp, addr); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2315 |
cmp(tmp, oldv); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2316 |
br(Assembler::NE, nope); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2317 |
// if we store+flush with no intervening write tmp wil be zero |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2318 |
stlxrw(tmp, newv, addr); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2319 |
cbzw(tmp, succeed); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2320 |
// retry so we only ever return after a load fails to compare |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2321 |
// ensures we don't return a stale value after a failed write. |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2322 |
b(retry_load); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2323 |
// if the memory word differs we return it in oldv and signal a fail |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2324 |
bind(nope); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2325 |
membar(AnyAny); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2326 |
mov(oldv, tmp); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2327 |
} |
29183 | 2328 |
if (fail) |
2329 |
b(*fail); |
|
2330 |
} |
|
2331 |
||
40049
a23a3ed6c7a6
8141633: Implement VarHandles/Unsafe intrinsics on AArch64
aph
parents:
40041
diff
changeset
|
2332 |
// A generic CAS; success or failure is in the EQ flag. A weak CAS |
a23a3ed6c7a6
8141633: Implement VarHandles/Unsafe intrinsics on AArch64
aph
parents:
40041
diff
changeset
|
2333 |
// doesn't retry and may fail spuriously. If the oldval is wanted, |
a23a3ed6c7a6
8141633: Implement VarHandles/Unsafe intrinsics on AArch64
aph
parents:
40041
diff
changeset
|
2334 |
// Pass a register for the result, otherwise pass noreg. |
a23a3ed6c7a6
8141633: Implement VarHandles/Unsafe intrinsics on AArch64
aph
parents:
40041
diff
changeset
|
2335 |
|
a23a3ed6c7a6
8141633: Implement VarHandles/Unsafe intrinsics on AArch64
aph
parents:
40041
diff
changeset
|
2336 |
// Clobbers rscratch1 |
36562
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2337 |
void MacroAssembler::cmpxchg(Register addr, Register expected, |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2338 |
Register new_val, |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2339 |
enum operand_size size, |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2340 |
bool acquire, bool release, |
40049
a23a3ed6c7a6
8141633: Implement VarHandles/Unsafe intrinsics on AArch64
aph
parents:
40041
diff
changeset
|
2341 |
bool weak, |
a23a3ed6c7a6
8141633: Implement VarHandles/Unsafe intrinsics on AArch64
aph
parents:
40041
diff
changeset
|
2342 |
Register result) { |
a23a3ed6c7a6
8141633: Implement VarHandles/Unsafe intrinsics on AArch64
aph
parents:
40041
diff
changeset
|
2343 |
if (result == noreg) result = rscratch1; |
36562
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2344 |
if (UseLSE) { |
40049
a23a3ed6c7a6
8141633: Implement VarHandles/Unsafe intrinsics on AArch64
aph
parents:
40041
diff
changeset
|
2345 |
mov(result, expected); |
a23a3ed6c7a6
8141633: Implement VarHandles/Unsafe intrinsics on AArch64
aph
parents:
40041
diff
changeset
|
2346 |
lse_cas(result, new_val, addr, size, acquire, release, /*not_pair*/ true); |
a23a3ed6c7a6
8141633: Implement VarHandles/Unsafe intrinsics on AArch64
aph
parents:
40041
diff
changeset
|
2347 |
cmp(result, expected); |
36562
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2348 |
} else { |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2349 |
BLOCK_COMMENT("cmpxchg {"); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2350 |
Label retry_load, done; |
38714
170464570e45
8157841: aarch64: prefetch ignores cache line size
enevill
parents:
38713
diff
changeset
|
2351 |
if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) |
170464570e45
8157841: aarch64: prefetch ignores cache line size
enevill
parents:
38713
diff
changeset
|
2352 |
prfm(Address(addr), PSTL1STRM); |
36562
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2353 |
bind(retry_load); |
40049
a23a3ed6c7a6
8141633: Implement VarHandles/Unsafe intrinsics on AArch64
aph
parents:
40041
diff
changeset
|
2354 |
load_exclusive(result, addr, size, acquire); |
36562
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2355 |
if (size == xword) |
40049
a23a3ed6c7a6
8141633: Implement VarHandles/Unsafe intrinsics on AArch64
aph
parents:
40041
diff
changeset
|
2356 |
cmp(result, expected); |
36562
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2357 |
else |
40049
a23a3ed6c7a6
8141633: Implement VarHandles/Unsafe intrinsics on AArch64
aph
parents:
40041
diff
changeset
|
2358 |
cmpw(result, expected); |
36562
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2359 |
br(Assembler::NE, done); |
40049
a23a3ed6c7a6
8141633: Implement VarHandles/Unsafe intrinsics on AArch64
aph
parents:
40041
diff
changeset
|
2360 |
store_exclusive(rscratch1, new_val, addr, size, release); |
a23a3ed6c7a6
8141633: Implement VarHandles/Unsafe intrinsics on AArch64
aph
parents:
40041
diff
changeset
|
2361 |
if (weak) { |
a23a3ed6c7a6
8141633: Implement VarHandles/Unsafe intrinsics on AArch64
aph
parents:
40041
diff
changeset
|
2362 |
cmpw(rscratch1, 0u); // If the store fails, return NE to our caller. |
a23a3ed6c7a6
8141633: Implement VarHandles/Unsafe intrinsics on AArch64
aph
parents:
40041
diff
changeset
|
2363 |
} else { |
a23a3ed6c7a6
8141633: Implement VarHandles/Unsafe intrinsics on AArch64
aph
parents:
40041
diff
changeset
|
2364 |
cbnzw(rscratch1, retry_load); |
a23a3ed6c7a6
8141633: Implement VarHandles/Unsafe intrinsics on AArch64
aph
parents:
40041
diff
changeset
|
2365 |
} |
36562
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2366 |
bind(done); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2367 |
BLOCK_COMMENT("} cmpxchg"); |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2368 |
} |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2369 |
} |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
36338
diff
changeset
|
2370 |
|
29183 | 2371 |
static bool different(Register a, RegisterOrConstant b, Register c) { |
2372 |
if (b.is_constant()) |
|
2373 |
return a != c; |
|
2374 |
else |
|
2375 |
return a != b.as_register() && a != c && b.as_register() != c; |
|
2376 |
} |
|
2377 |
||
37269
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2378 |
#define ATOMIC_OP(NAME, LDXR, OP, IOP, AOP, STXR, sz) \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2379 |
void MacroAssembler::atomic_##NAME(Register prev, RegisterOrConstant incr, Register addr) { \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2380 |
if (UseLSE) { \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2381 |
prev = prev->is_valid() ? prev : zr; \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2382 |
if (incr.is_register()) { \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2383 |
AOP(sz, incr.as_register(), prev, addr); \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2384 |
} else { \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2385 |
mov(rscratch2, incr.as_constant()); \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2386 |
AOP(sz, rscratch2, prev, addr); \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2387 |
} \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2388 |
return; \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2389 |
} \ |
29183 | 2390 |
Register result = rscratch2; \ |
2391 |
if (prev->is_valid()) \ |
|
2392 |
result = different(prev, incr, addr) ? prev : rscratch2; \ |
|
2393 |
\ |
|
2394 |
Label retry_load; \ |
|
38714
170464570e45
8157841: aarch64: prefetch ignores cache line size
enevill
parents:
38713
diff
changeset
|
2395 |
if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) \ |
170464570e45
8157841: aarch64: prefetch ignores cache line size
enevill
parents:
38713
diff
changeset
|
2396 |
prfm(Address(addr), PSTL1STRM); \ |
29183 | 2397 |
bind(retry_load); \ |
2398 |
LDXR(result, addr); \ |
|
2399 |
OP(rscratch1, result, incr); \ |
|
32395
13b0caf18153
8133352: aarch64: generates constrained unpredictable instructions
enevill
parents:
32394
diff
changeset
|
2400 |
STXR(rscratch2, rscratch1, addr); \ |
13b0caf18153
8133352: aarch64: generates constrained unpredictable instructions
enevill
parents:
32394
diff
changeset
|
2401 |
cbnzw(rscratch2, retry_load); \ |
13b0caf18153
8133352: aarch64: generates constrained unpredictable instructions
enevill
parents:
32394
diff
changeset
|
2402 |
if (prev->is_valid() && prev != result) { \ |
13b0caf18153
8133352: aarch64: generates constrained unpredictable instructions
enevill
parents:
32394
diff
changeset
|
2403 |
IOP(prev, rscratch1, incr); \ |
13b0caf18153
8133352: aarch64: generates constrained unpredictable instructions
enevill
parents:
32394
diff
changeset
|
2404 |
} \ |
29183 | 2405 |
} |
2406 |
||
37269
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2407 |
ATOMIC_OP(add, ldxr, add, sub, ldadd, stxr, Assembler::xword) |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2408 |
ATOMIC_OP(addw, ldxrw, addw, subw, ldadd, stxrw, Assembler::word) |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2409 |
ATOMIC_OP(addal, ldaxr, add, sub, ldaddal, stlxr, Assembler::xword) |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2410 |
ATOMIC_OP(addalw, ldaxrw, addw, subw, ldaddal, stlxrw, Assembler::word) |
29183 | 2411 |
|
2412 |
#undef ATOMIC_OP |
|
2413 |
||
37269
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2414 |
#define ATOMIC_XCHG(OP, AOP, LDXR, STXR, sz) \ |
29183 | 2415 |
void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \ |
37269
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2416 |
if (UseLSE) { \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2417 |
prev = prev->is_valid() ? prev : zr; \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2418 |
AOP(sz, newv, prev, addr); \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2419 |
return; \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2420 |
} \ |
29183 | 2421 |
Register result = rscratch2; \ |
2422 |
if (prev->is_valid()) \ |
|
2423 |
result = different(prev, newv, addr) ? prev : rscratch2; \ |
|
2424 |
\ |
|
2425 |
Label retry_load; \ |
|
38714
170464570e45
8157841: aarch64: prefetch ignores cache line size
enevill
parents:
38713
diff
changeset
|
2426 |
if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) \ |
170464570e45
8157841: aarch64: prefetch ignores cache line size
enevill
parents:
38713
diff
changeset
|
2427 |
prfm(Address(addr), PSTL1STRM); \ |
29183 | 2428 |
bind(retry_load); \ |
2429 |
LDXR(result, addr); \ |
|
2430 |
STXR(rscratch1, newv, addr); \ |
|
2431 |
cbnzw(rscratch1, retry_load); \ |
|
2432 |
if (prev->is_valid() && prev != result) \ |
|
2433 |
mov(prev, result); \ |
|
2434 |
} |
|
2435 |
||
37269
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2436 |
ATOMIC_XCHG(xchg, swp, ldxr, stxr, Assembler::xword) |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2437 |
ATOMIC_XCHG(xchgw, swp, ldxrw, stxrw, Assembler::word) |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2438 |
ATOMIC_XCHG(xchgal, swpal, ldaxr, stlxr, Assembler::xword) |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36565
diff
changeset
|
2439 |
ATOMIC_XCHG(xchgalw, swpal, ldaxrw, stlxrw, Assembler::word) |
29183 | 2440 |
|
2441 |
#undef ATOMIC_XCHG |
|
2442 |
||
2443 |
void MacroAssembler::incr_allocated_bytes(Register thread, |
|
2444 |
Register var_size_in_bytes, |
|
2445 |
int con_size_in_bytes, |
|
2446 |
Register t1) { |
|
2447 |
if (!thread->is_valid()) { |
|
2448 |
thread = rthread; |
|
2449 |
} |
|
2450 |
assert(t1->is_valid(), "need temp reg"); |
|
2451 |
||
2452 |
ldr(t1, Address(thread, in_bytes(JavaThread::allocated_bytes_offset()))); |
|
2453 |
if (var_size_in_bytes->is_valid()) { |
|
2454 |
add(t1, t1, var_size_in_bytes); |
|
2455 |
} else { |
|
2456 |
add(t1, t1, con_size_in_bytes); |
|
2457 |
} |
|
2458 |
str(t1, Address(thread, in_bytes(JavaThread::allocated_bytes_offset()))); |
|
2459 |
} |
|
2460 |
||
2461 |
#ifndef PRODUCT |
|
2462 |
extern "C" void findpc(intptr_t x); |
|
2463 |
#endif |
|
2464 |
||
2465 |
void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) |
|
2466 |
{ |
|
2467 |
// In order to get locks to work, we need to fake a in_VM state |
|
2468 |
if (ShowMessageBoxOnError ) { |
|
2469 |
JavaThread* thread = JavaThread::current(); |
|
2470 |
JavaThreadState saved_state = thread->thread_state(); |
|
2471 |
thread->set_thread_state(_thread_in_vm); |
|
2472 |
#ifndef PRODUCT |
|
2473 |
if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { |
|
2474 |
ttyLocker ttyl; |
|
2475 |
BytecodeCounter::print(); |
|
2476 |
} |
|
2477 |
#endif |
|
2478 |
if (os::message_box(msg, "Execution stopped, print registers?")) { |
|
2479 |
ttyLocker ttyl; |
|
2480 |
tty->print_cr(" pc = 0x%016lx", pc); |
|
2481 |
#ifndef PRODUCT |
|
2482 |
tty->cr(); |
|
2483 |
findpc(pc); |
|
2484 |
tty->cr(); |
|
2485 |
#endif |
|
2486 |
tty->print_cr(" r0 = 0x%016lx", regs[0]); |
|
2487 |
tty->print_cr(" r1 = 0x%016lx", regs[1]); |
|
2488 |
tty->print_cr(" r2 = 0x%016lx", regs[2]); |
|
2489 |
tty->print_cr(" r3 = 0x%016lx", regs[3]); |
|
2490 |
tty->print_cr(" r4 = 0x%016lx", regs[4]); |
|
2491 |
tty->print_cr(" r5 = 0x%016lx", regs[5]); |
|
2492 |
tty->print_cr(" r6 = 0x%016lx", regs[6]); |
|
2493 |
tty->print_cr(" r7 = 0x%016lx", regs[7]); |
|
2494 |
tty->print_cr(" r8 = 0x%016lx", regs[8]); |
|
2495 |
tty->print_cr(" r9 = 0x%016lx", regs[9]); |
|
2496 |
tty->print_cr("r10 = 0x%016lx", regs[10]); |
|
2497 |
tty->print_cr("r11 = 0x%016lx", regs[11]); |
|
2498 |
tty->print_cr("r12 = 0x%016lx", regs[12]); |
|
2499 |
tty->print_cr("r13 = 0x%016lx", regs[13]); |
|
2500 |
tty->print_cr("r14 = 0x%016lx", regs[14]); |
|
2501 |
tty->print_cr("r15 = 0x%016lx", regs[15]); |
|
2502 |
tty->print_cr("r16 = 0x%016lx", regs[16]); |
|
2503 |
tty->print_cr("r17 = 0x%016lx", regs[17]); |
|
2504 |
tty->print_cr("r18 = 0x%016lx", regs[18]); |
|
2505 |
tty->print_cr("r19 = 0x%016lx", regs[19]); |
|
2506 |
tty->print_cr("r20 = 0x%016lx", regs[20]); |
|
2507 |
tty->print_cr("r21 = 0x%016lx", regs[21]); |
|
2508 |
tty->print_cr("r22 = 0x%016lx", regs[22]); |
|
2509 |
tty->print_cr("r23 = 0x%016lx", regs[23]); |
|
2510 |
tty->print_cr("r24 = 0x%016lx", regs[24]); |
|
2511 |
tty->print_cr("r25 = 0x%016lx", regs[25]); |
|
2512 |
tty->print_cr("r26 = 0x%016lx", regs[26]); |
|
2513 |
tty->print_cr("r27 = 0x%016lx", regs[27]); |
|
2514 |
tty->print_cr("r28 = 0x%016lx", regs[28]); |
|
2515 |
tty->print_cr("r30 = 0x%016lx", regs[30]); |
|
2516 |
tty->print_cr("r31 = 0x%016lx", regs[31]); |
|
2517 |
BREAKPOINT; |
|
2518 |
} |
|
2519 |
ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); |
|
2520 |
} else { |
|
2521 |
ttyLocker ttyl; |
|
2522 |
::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", |
|
2523 |
msg); |
|
33105
294e48b4f704
8080775: Better argument formatting for assert() and friends
david
parents:
33096
diff
changeset
|
2524 |
assert(false, "DEBUG MESSAGE: %s", msg); |
29183 | 2525 |
} |
2526 |
} |
|
2527 |
||
2528 |
#ifdef BUILTIN_SIM |
|
2529 |
// routine to generate an x86 prolog for a stub function which |
|
2530 |
// bootstraps into the generated ARM code which directly follows the |
|
2531 |
// stub |
|
2532 |
// |
|
2533 |
// the argument encodes the number of general and fp registers |
|
2534 |
// passed by the caller and the callng convention (currently just |
|
2535 |
// the number of general registers and assumes C argument passing) |
|
2536 |
||
2537 |
extern "C" { |
|
2538 |
int aarch64_stub_prolog_size(); |
|
2539 |
void aarch64_stub_prolog(); |
|
2540 |
void aarch64_prolog(); |
|
2541 |
} |
|
2542 |
||
2543 |
void MacroAssembler::c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, |
|
2544 |
address *prolog_ptr) |
|
2545 |
{ |
|
2546 |
int calltype = (((ret_type & 0x3) << 8) | |
|
2547 |
((fp_arg_count & 0xf) << 4) | |
|
2548 |
(gp_arg_count & 0xf)); |
|
2549 |
||
2550 |
// the addresses for the x86 to ARM entry code we need to use |
|
2551 |
address start = pc(); |
|
2552 |
// printf("start = %lx\n", start); |
|
2553 |
int byteCount = aarch64_stub_prolog_size(); |
|
2554 |
// printf("byteCount = %x\n", byteCount); |
|
2555 |
int instructionCount = (byteCount + 3)/ 4; |
|
2556 |
// printf("instructionCount = %x\n", instructionCount); |
|
2557 |
for (int i = 0; i < instructionCount; i++) { |
|
2558 |
nop(); |
|
2559 |
} |
|
2560 |
||
2561 |
memcpy(start, (void*)aarch64_stub_prolog, byteCount); |
|
2562 |
||
2563 |
// write the address of the setup routine and the call format at the |
|
2564 |
// end of into the copied code |
|
2565 |
u_int64_t *patch_end = (u_int64_t *)(start + byteCount); |
|
2566 |
if (prolog_ptr) |
|
2567 |
patch_end[-2] = (u_int64_t)prolog_ptr; |
|
2568 |
patch_end[-1] = calltype; |
|
2569 |
} |
|
2570 |
#endif |
|
2571 |
||
35579
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
2572 |
void MacroAssembler::push_call_clobbered_registers() { |
50641
66aa15778c5a
8204353: AARCH64: optimize FPU load and stores in macroAssembler
dpochepk
parents:
50599
diff
changeset
|
2573 |
int step = 4 * wordSize; |
35579
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
2574 |
push(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp); |
50641
66aa15778c5a
8204353: AARCH64: optimize FPU load and stores in macroAssembler
dpochepk
parents:
50599
diff
changeset
|
2575 |
sub(sp, sp, step); |
66aa15778c5a
8204353: AARCH64: optimize FPU load and stores in macroAssembler
dpochepk
parents:
50599
diff
changeset
|
2576 |
mov(rscratch1, -step); |
35579
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
2577 |
// Push v0-v7, v16-v31. |
50641
66aa15778c5a
8204353: AARCH64: optimize FPU load and stores in macroAssembler
dpochepk
parents:
50599
diff
changeset
|
2578 |
for (int i = 31; i>= 4; i -= 4) { |
66aa15778c5a
8204353: AARCH64: optimize FPU load and stores in macroAssembler
dpochepk
parents:
50599
diff
changeset
|
2579 |
if (i <= v7->encoding() || i >= v16->encoding()) |
66aa15778c5a
8204353: AARCH64: optimize FPU load and stores in macroAssembler
dpochepk
parents:
50599
diff
changeset
|
2580 |
st1(as_FloatRegister(i-3), as_FloatRegister(i-2), as_FloatRegister(i-1), |
66aa15778c5a
8204353: AARCH64: optimize FPU load and stores in macroAssembler
dpochepk
parents:
50599
diff
changeset
|
2581 |
as_FloatRegister(i), T1D, Address(post(sp, rscratch1))); |
35579
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
2582 |
} |
50641
66aa15778c5a
8204353: AARCH64: optimize FPU load and stores in macroAssembler
dpochepk
parents:
50599
diff
changeset
|
2583 |
st1(as_FloatRegister(0), as_FloatRegister(1), as_FloatRegister(2), |
66aa15778c5a
8204353: AARCH64: optimize FPU load and stores in macroAssembler
dpochepk
parents:
50599
diff
changeset
|
2584 |
as_FloatRegister(3), T1D, Address(sp)); |
35579
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
2585 |
} |
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
2586 |
|
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
2587 |
void MacroAssembler::pop_call_clobbered_registers() { |
50641
66aa15778c5a
8204353: AARCH64: optimize FPU load and stores in macroAssembler
dpochepk
parents:
50599
diff
changeset
|
2588 |
for (int i = 0; i < 32; i += 4) { |
66aa15778c5a
8204353: AARCH64: optimize FPU load and stores in macroAssembler
dpochepk
parents:
50599
diff
changeset
|
2589 |
if (i <= v7->encoding() || i >= v16->encoding()) |
66aa15778c5a
8204353: AARCH64: optimize FPU load and stores in macroAssembler
dpochepk
parents:
50599
diff
changeset
|
2590 |
ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2), |
66aa15778c5a
8204353: AARCH64: optimize FPU load and stores in macroAssembler
dpochepk
parents:
50599
diff
changeset
|
2591 |
as_FloatRegister(i+3), T1D, Address(post(sp, 4 * wordSize))); |
35579
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
2592 |
} |
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
2593 |
|
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
2594 |
pop(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp); |
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
2595 |
} |
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
2596 |
|
33061
69a83b5ce390
8136524: aarch64: test/compiler/runtime/7196199/Test7196199.java fails
enevill
parents:
32599
diff
changeset
|
2597 |
void MacroAssembler::push_CPU_state(bool save_vectors) { |
50641
66aa15778c5a
8204353: AARCH64: optimize FPU load and stores in macroAssembler
dpochepk
parents:
50599
diff
changeset
|
2598 |
int step = (save_vectors ? 8 : 4) * wordSize; |
33061
69a83b5ce390
8136524: aarch64: test/compiler/runtime/7196199/Test7196199.java fails
enevill
parents:
32599
diff
changeset
|
2599 |
push(0x3fffffff, sp); // integer registers except lr & sp |
50641
66aa15778c5a
8204353: AARCH64: optimize FPU load and stores in macroAssembler
dpochepk
parents:
50599
diff
changeset
|
2600 |
mov(rscratch1, -step); |
66aa15778c5a
8204353: AARCH64: optimize FPU load and stores in macroAssembler
dpochepk
parents:
50599
diff
changeset
|
2601 |
sub(sp, sp, step); |
66aa15778c5a
8204353: AARCH64: optimize FPU load and stores in macroAssembler
dpochepk
parents:
50599
diff
changeset
|
2602 |
for (int i = 28; i >= 4; i -= 4) { |
66aa15778c5a
8204353: AARCH64: optimize FPU load and stores in macroAssembler
dpochepk
parents:
50599
diff
changeset
|
2603 |
st1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2), |
66aa15778c5a
8204353: AARCH64: optimize FPU load and stores in macroAssembler
dpochepk
parents:
50599
diff
changeset
|
2604 |
as_FloatRegister(i+3), save_vectors ? T2D : T1D, Address(post(sp, rscratch1))); |
33061
69a83b5ce390
8136524: aarch64: test/compiler/runtime/7196199/Test7196199.java fails
enevill
parents:
32599
diff
changeset
|
2605 |
} |
50641
66aa15778c5a
8204353: AARCH64: optimize FPU load and stores in macroAssembler
dpochepk
parents:
50599
diff
changeset
|
2606 |
st1(v0, v1, v2, v3, save_vectors ? T2D : T1D, sp); |
29183 | 2607 |
} |
2608 |
||
33061
69a83b5ce390
8136524: aarch64: test/compiler/runtime/7196199/Test7196199.java fails
enevill
parents:
32599
diff
changeset
|
2609 |
void MacroAssembler::pop_CPU_state(bool restore_vectors) { |
50641
66aa15778c5a
8204353: AARCH64: optimize FPU load and stores in macroAssembler
dpochepk
parents:
50599
diff
changeset
|
2610 |
int step = (restore_vectors ? 8 : 4) * wordSize; |
66aa15778c5a
8204353: AARCH64: optimize FPU load and stores in macroAssembler
dpochepk
parents:
50599
diff
changeset
|
2611 |
for (int i = 0; i <= 28; i += 4) |
66aa15778c5a
8204353: AARCH64: optimize FPU load and stores in macroAssembler
dpochepk
parents:
50599
diff
changeset
|
2612 |
ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2), |
66aa15778c5a
8204353: AARCH64: optimize FPU load and stores in macroAssembler
dpochepk
parents:
50599
diff
changeset
|
2613 |
as_FloatRegister(i+3), restore_vectors ? T2D : T1D, Address(post(sp, step))); |
29183 | 2614 |
pop(0x3fffffff, sp); // integer registers except lr & sp |
2615 |
} |
|
2616 |
||
2617 |
/** |
|
30225
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2618 |
* Helpers for multiply_to_len(). |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2619 |
*/ |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2620 |
void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo, |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2621 |
Register src1, Register src2) { |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2622 |
adds(dest_lo, dest_lo, src1); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2623 |
adc(dest_hi, dest_hi, zr); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2624 |
adds(dest_lo, dest_lo, src2); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2625 |
adc(final_dest_hi, dest_hi, zr); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2626 |
} |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2627 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2628 |
// Generate an address from (r + r1 extend offset). "size" is the |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2629 |
// size of the operand. The result may be in rscratch2. |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2630 |
Address MacroAssembler::offsetted_address(Register r, Register r1, |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2631 |
Address::extend ext, int offset, int size) { |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2632 |
if (offset || (ext.shift() % size != 0)) { |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2633 |
lea(rscratch2, Address(r, r1, ext)); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2634 |
return Address(rscratch2, offset); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2635 |
} else { |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2636 |
return Address(r, r1, ext); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2637 |
} |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2638 |
} |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2639 |
|
31954
eecbca64fad6
8131362: aarch64: C2 does not handle large stack offsets
enevill
parents:
31863
diff
changeset
|
2640 |
Address MacroAssembler::spill_address(int size, int offset, Register tmp) |
eecbca64fad6
8131362: aarch64: C2 does not handle large stack offsets
enevill
parents:
31863
diff
changeset
|
2641 |
{ |
eecbca64fad6
8131362: aarch64: C2 does not handle large stack offsets
enevill
parents:
31863
diff
changeset
|
2642 |
assert(offset >= 0, "spill to negative address?"); |
eecbca64fad6
8131362: aarch64: C2 does not handle large stack offsets
enevill
parents:
31863
diff
changeset
|
2643 |
// Offset reachable ? |
eecbca64fad6
8131362: aarch64: C2 does not handle large stack offsets
enevill
parents:
31863
diff
changeset
|
2644 |
// Not aligned - 9 bits signed offset |
eecbca64fad6
8131362: aarch64: C2 does not handle large stack offsets
enevill
parents:
31863
diff
changeset
|
2645 |
// Aligned - 12 bits unsigned offset shifted |
eecbca64fad6
8131362: aarch64: C2 does not handle large stack offsets
enevill
parents:
31863
diff
changeset
|
2646 |
Register base = sp; |
eecbca64fad6
8131362: aarch64: C2 does not handle large stack offsets
enevill
parents:
31863
diff
changeset
|
2647 |
if ((offset & (size-1)) && offset >= (1<<8)) { |
eecbca64fad6
8131362: aarch64: C2 does not handle large stack offsets
enevill
parents:
31863
diff
changeset
|
2648 |
add(tmp, base, offset & ((1<<12)-1)); |
eecbca64fad6
8131362: aarch64: C2 does not handle large stack offsets
enevill
parents:
31863
diff
changeset
|
2649 |
base = tmp; |
eecbca64fad6
8131362: aarch64: C2 does not handle large stack offsets
enevill
parents:
31863
diff
changeset
|
2650 |
offset &= -1<<12; |
eecbca64fad6
8131362: aarch64: C2 does not handle large stack offsets
enevill
parents:
31863
diff
changeset
|
2651 |
} |
eecbca64fad6
8131362: aarch64: C2 does not handle large stack offsets
enevill
parents:
31863
diff
changeset
|
2652 |
|
eecbca64fad6
8131362: aarch64: C2 does not handle large stack offsets
enevill
parents:
31863
diff
changeset
|
2653 |
if (offset >= (1<<12) * size) { |
eecbca64fad6
8131362: aarch64: C2 does not handle large stack offsets
enevill
parents:
31863
diff
changeset
|
2654 |
add(tmp, base, offset & (((1<<12)-1)<<12)); |
eecbca64fad6
8131362: aarch64: C2 does not handle large stack offsets
enevill
parents:
31863
diff
changeset
|
2655 |
base = tmp; |
eecbca64fad6
8131362: aarch64: C2 does not handle large stack offsets
enevill
parents:
31863
diff
changeset
|
2656 |
offset &= ~(((1<<12)-1)<<12); |
eecbca64fad6
8131362: aarch64: C2 does not handle large stack offsets
enevill
parents:
31863
diff
changeset
|
2657 |
} |
eecbca64fad6
8131362: aarch64: C2 does not handle large stack offsets
enevill
parents:
31863
diff
changeset
|
2658 |
|
eecbca64fad6
8131362: aarch64: C2 does not handle large stack offsets
enevill
parents:
31863
diff
changeset
|
2659 |
return Address(base, offset); |
eecbca64fad6
8131362: aarch64: C2 does not handle large stack offsets
enevill
parents:
31863
diff
changeset
|
2660 |
} |
eecbca64fad6
8131362: aarch64: C2 does not handle large stack offsets
enevill
parents:
31863
diff
changeset
|
2661 |
|
49161
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2662 |
// Checks whether offset is aligned. |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2663 |
// Returns true if it is, else false. |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2664 |
bool MacroAssembler::merge_alignment_check(Register base, |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2665 |
size_t size, |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2666 |
long cur_offset, |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2667 |
long prev_offset) const { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2668 |
if (AvoidUnalignedAccesses) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2669 |
if (base == sp) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2670 |
// Checks whether low offset if aligned to pair of registers. |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2671 |
long pair_mask = size * 2 - 1; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2672 |
long offset = prev_offset > cur_offset ? cur_offset : prev_offset; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2673 |
return (offset & pair_mask) == 0; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2674 |
} else { // If base is not sp, we can't guarantee the access is aligned. |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2675 |
return false; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2676 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2677 |
} else { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2678 |
long mask = size - 1; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2679 |
// Load/store pair instruction only supports element size aligned offset. |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2680 |
return (cur_offset & mask) == 0 && (prev_offset & mask) == 0; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2681 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2682 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2683 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2684 |
// Checks whether current and previous loads/stores can be merged. |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2685 |
// Returns true if it can be merged, else false. |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2686 |
bool MacroAssembler::ldst_can_merge(Register rt, |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2687 |
const Address &adr, |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2688 |
size_t cur_size_in_bytes, |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2689 |
bool is_store) const { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2690 |
address prev = pc() - NativeInstruction::instruction_size; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2691 |
address last = code()->last_insn(); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2692 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2693 |
if (last == NULL || !nativeInstruction_at(last)->is_Imm_LdSt()) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2694 |
return false; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2695 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2696 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2697 |
if (adr.getMode() != Address::base_plus_offset || prev != last) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2698 |
return false; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2699 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2700 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2701 |
NativeLdSt* prev_ldst = NativeLdSt_at(prev); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2702 |
size_t prev_size_in_bytes = prev_ldst->size_in_bytes(); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2703 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2704 |
assert(prev_size_in_bytes == 4 || prev_size_in_bytes == 8, "only supports 64/32bit merging."); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2705 |
assert(cur_size_in_bytes == 4 || cur_size_in_bytes == 8, "only supports 64/32bit merging."); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2706 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2707 |
if (cur_size_in_bytes != prev_size_in_bytes || is_store != prev_ldst->is_store()) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2708 |
return false; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2709 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2710 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2711 |
long max_offset = 63 * prev_size_in_bytes; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2712 |
long min_offset = -64 * prev_size_in_bytes; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2713 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2714 |
assert(prev_ldst->is_not_pre_post_index(), "pre-index or post-index is not supported to be merged."); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2715 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2716 |
// Only same base can be merged. |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2717 |
if (adr.base() != prev_ldst->base()) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2718 |
return false; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2719 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2720 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2721 |
long cur_offset = adr.offset(); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2722 |
long prev_offset = prev_ldst->offset(); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2723 |
size_t diff = abs(cur_offset - prev_offset); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2724 |
if (diff != prev_size_in_bytes) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2725 |
return false; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2726 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2727 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2728 |
// Following cases can not be merged: |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2729 |
// ldr x2, [x2, #8] |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2730 |
// ldr x3, [x2, #16] |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2731 |
// or: |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2732 |
// ldr x2, [x3, #8] |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2733 |
// ldr x2, [x3, #16] |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2734 |
// If t1 and t2 is the same in "ldp t1, t2, [xn, #imm]", we'll get SIGILL. |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2735 |
if (!is_store && (adr.base() == prev_ldst->target() || rt == prev_ldst->target())) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2736 |
return false; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2737 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2738 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2739 |
long low_offset = prev_offset > cur_offset ? cur_offset : prev_offset; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2740 |
// Offset range must be in ldp/stp instruction's range. |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2741 |
if (low_offset > max_offset || low_offset < min_offset) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2742 |
return false; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2743 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2744 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2745 |
if (merge_alignment_check(adr.base(), prev_size_in_bytes, cur_offset, prev_offset)) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2746 |
return true; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2747 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2748 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2749 |
return false; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2750 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2751 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2752 |
// Merge current load/store with previous load/store into ldp/stp. |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2753 |
void MacroAssembler::merge_ldst(Register rt, |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2754 |
const Address &adr, |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2755 |
size_t cur_size_in_bytes, |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2756 |
bool is_store) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2757 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2758 |
assert(ldst_can_merge(rt, adr, cur_size_in_bytes, is_store) == true, "cur and prev must be able to be merged."); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2759 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2760 |
Register rt_low, rt_high; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2761 |
address prev = pc() - NativeInstruction::instruction_size; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2762 |
NativeLdSt* prev_ldst = NativeLdSt_at(prev); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2763 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2764 |
long offset; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2765 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2766 |
if (adr.offset() < prev_ldst->offset()) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2767 |
offset = adr.offset(); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2768 |
rt_low = rt; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2769 |
rt_high = prev_ldst->target(); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2770 |
} else { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2771 |
offset = prev_ldst->offset(); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2772 |
rt_low = prev_ldst->target(); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2773 |
rt_high = rt; |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2774 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2775 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2776 |
Address adr_p = Address(prev_ldst->base(), offset); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2777 |
// Overwrite previous generated binary. |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2778 |
code_section()->set_end(prev); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2779 |
|
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2780 |
const int sz = prev_ldst->size_in_bytes(); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2781 |
assert(sz == 8 || sz == 4, "only supports 64/32bit merging."); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2782 |
if (!is_store) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2783 |
BLOCK_COMMENT("merged ldr pair"); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2784 |
if (sz == 8) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2785 |
ldp(rt_low, rt_high, adr_p); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2786 |
} else { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2787 |
ldpw(rt_low, rt_high, adr_p); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2788 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2789 |
} else { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2790 |
BLOCK_COMMENT("merged str pair"); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2791 |
if (sz == 8) { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2792 |
stp(rt_low, rt_high, adr_p); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2793 |
} else { |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2794 |
stpw(rt_low, rt_high, adr_p); |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2795 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2796 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2797 |
} |
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
2798 |
|
30225
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2799 |
/** |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2800 |
* Multiply 64 bit by 64 bit first loop. |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2801 |
*/ |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2802 |
void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2803 |
Register y, Register y_idx, Register z, |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2804 |
Register carry, Register product, |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2805 |
Register idx, Register kdx) { |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2806 |
// |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2807 |
// jlong carry, x[], y[], z[]; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2808 |
// for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2809 |
// huge_128 product = y[idx] * x[xstart] + carry; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2810 |
// z[kdx] = (jlong)product; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2811 |
// carry = (jlong)(product >>> 64); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2812 |
// } |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2813 |
// z[xstart] = carry; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2814 |
// |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2815 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2816 |
Label L_first_loop, L_first_loop_exit; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2817 |
Label L_one_x, L_one_y, L_multiply; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2818 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2819 |
subsw(xstart, xstart, 1); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2820 |
br(Assembler::MI, L_one_x); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2821 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2822 |
lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt))); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2823 |
ldr(x_xstart, Address(rscratch1)); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2824 |
ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2825 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2826 |
bind(L_first_loop); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2827 |
subsw(idx, idx, 1); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2828 |
br(Assembler::MI, L_first_loop_exit); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2829 |
subsw(idx, idx, 1); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2830 |
br(Assembler::MI, L_one_y); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2831 |
lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt))); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2832 |
ldr(y_idx, Address(rscratch1)); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2833 |
ror(y_idx, y_idx, 32); // convert big-endian to little-endian |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2834 |
bind(L_multiply); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2835 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2836 |
// AArch64 has a multiply-accumulate instruction that we can't use |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2837 |
// here because it has no way to process carries, so we have to use |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2838 |
// separate add and adc instructions. Bah. |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2839 |
umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2840 |
mul(product, x_xstart, y_idx); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2841 |
adds(product, product, carry); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2842 |
adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2843 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2844 |
subw(kdx, kdx, 2); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2845 |
ror(product, product, 32); // back to big-endian |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2846 |
str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong)); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2847 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2848 |
b(L_first_loop); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2849 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2850 |
bind(L_one_y); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2851 |
ldrw(y_idx, Address(y, 0)); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2852 |
b(L_multiply); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2853 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2854 |
bind(L_one_x); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2855 |
ldrw(x_xstart, Address(x, 0)); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2856 |
b(L_first_loop); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2857 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2858 |
bind(L_first_loop_exit); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2859 |
} |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2860 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2861 |
/** |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2862 |
* Multiply 128 bit by 128. Unrolled inner loop. |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2863 |
* |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2864 |
*/ |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2865 |
void MacroAssembler::multiply_128_x_128_loop(Register y, Register z, |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2866 |
Register carry, Register carry2, |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2867 |
Register idx, Register jdx, |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2868 |
Register yz_idx1, Register yz_idx2, |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2869 |
Register tmp, Register tmp3, Register tmp4, |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2870 |
Register tmp6, Register product_hi) { |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2871 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2872 |
// jlong carry, x[], y[], z[]; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2873 |
// int kdx = ystart+1; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2874 |
// for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2875 |
// huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2876 |
// jlong carry2 = (jlong)(tmp3 >>> 64); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2877 |
// huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2878 |
// carry = (jlong)(tmp4 >>> 64); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2879 |
// z[kdx+idx+1] = (jlong)tmp3; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2880 |
// z[kdx+idx] = (jlong)tmp4; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2881 |
// } |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2882 |
// idx += 2; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2883 |
// if (idx > 0) { |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2884 |
// yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2885 |
// z[kdx+idx] = (jlong)yz_idx1; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2886 |
// carry = (jlong)(yz_idx1 >>> 64); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2887 |
// } |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2888 |
// |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2889 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2890 |
Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2891 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2892 |
lsrw(jdx, idx, 2); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2893 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2894 |
bind(L_third_loop); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2895 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2896 |
subsw(jdx, jdx, 1); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2897 |
br(Assembler::MI, L_third_loop_exit); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2898 |
subw(idx, idx, 4); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2899 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2900 |
lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt))); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2901 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2902 |
ldp(yz_idx2, yz_idx1, Address(rscratch1, 0)); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2903 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2904 |
lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt))); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2905 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2906 |
ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2907 |
ror(yz_idx2, yz_idx2, 32); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2908 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2909 |
ldp(rscratch2, rscratch1, Address(tmp6, 0)); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2910 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2911 |
mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3 |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2912 |
umulh(tmp4, product_hi, yz_idx1); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2913 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2914 |
ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2915 |
ror(rscratch2, rscratch2, 32); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2916 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2917 |
mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2918 |
umulh(carry2, product_hi, yz_idx2); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2919 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2920 |
// propagate sum of both multiplications into carry:tmp4:tmp3 |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2921 |
adds(tmp3, tmp3, carry); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2922 |
adc(tmp4, tmp4, zr); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2923 |
adds(tmp3, tmp3, rscratch1); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2924 |
adcs(tmp4, tmp4, tmp); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2925 |
adc(carry, carry2, zr); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2926 |
adds(tmp4, tmp4, rscratch2); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2927 |
adc(carry, carry, zr); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2928 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2929 |
ror(tmp3, tmp3, 32); // convert little-endian to big-endian |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2930 |
ror(tmp4, tmp4, 32); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2931 |
stp(tmp4, tmp3, Address(tmp6, 0)); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2932 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2933 |
b(L_third_loop); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2934 |
bind (L_third_loop_exit); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2935 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2936 |
andw (idx, idx, 0x3); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2937 |
cbz(idx, L_post_third_loop_done); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2938 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2939 |
Label L_check_1; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2940 |
subsw(idx, idx, 2); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2941 |
br(Assembler::MI, L_check_1); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2942 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2943 |
lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt))); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2944 |
ldr(yz_idx1, Address(rscratch1, 0)); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2945 |
ror(yz_idx1, yz_idx1, 32); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2946 |
mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3 |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2947 |
umulh(tmp4, product_hi, yz_idx1); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2948 |
lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt))); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2949 |
ldr(yz_idx2, Address(rscratch1, 0)); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2950 |
ror(yz_idx2, yz_idx2, 32); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2951 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2952 |
add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2953 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2954 |
ror(tmp3, tmp3, 32); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2955 |
str(tmp3, Address(rscratch1, 0)); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2956 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2957 |
bind (L_check_1); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2958 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2959 |
andw (idx, idx, 0x1); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2960 |
subsw(idx, idx, 1); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2961 |
br(Assembler::MI, L_post_third_loop_done); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2962 |
ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt))); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2963 |
mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3 |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2964 |
umulh(carry2, tmp4, product_hi); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2965 |
ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt))); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2966 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2967 |
add2_with_carry(carry2, tmp3, tmp4, carry); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2968 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2969 |
strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt))); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2970 |
extr(carry, carry2, tmp3, 32); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2971 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2972 |
bind(L_post_third_loop_done); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2973 |
} |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2974 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2975 |
/** |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2976 |
* Code for BigInteger::multiplyToLen() instrinsic. |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2977 |
* |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2978 |
* r0: x |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2979 |
* r1: xlen |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2980 |
* r2: y |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2981 |
* r3: ylen |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2982 |
* r4: z |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2983 |
* r5: zlen |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2984 |
* r10: tmp1 |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2985 |
* r11: tmp2 |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2986 |
* r12: tmp3 |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2987 |
* r13: tmp4 |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2988 |
* r14: tmp5 |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2989 |
* r15: tmp6 |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2990 |
* r16: tmp7 |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2991 |
* |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2992 |
*/ |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2993 |
void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2994 |
Register z, Register zlen, |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2995 |
Register tmp1, Register tmp2, Register tmp3, Register tmp4, |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2996 |
Register tmp5, Register tmp6, Register product_hi) { |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2997 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2998 |
assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
2999 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3000 |
const Register idx = tmp1; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3001 |
const Register kdx = tmp2; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3002 |
const Register xstart = tmp3; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3003 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3004 |
const Register y_idx = tmp4; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3005 |
const Register carry = tmp5; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3006 |
const Register product = xlen; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3007 |
const Register x_xstart = zlen; // reuse register |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3008 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3009 |
// First Loop. |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3010 |
// |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3011 |
// final static long LONG_MASK = 0xffffffffL; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3012 |
// int xstart = xlen - 1; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3013 |
// int ystart = ylen - 1; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3014 |
// long carry = 0; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3015 |
// for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3016 |
// long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3017 |
// z[kdx] = (int)product; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3018 |
// carry = product >>> 32; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3019 |
// } |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3020 |
// z[xstart] = (int)carry; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3021 |
// |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3022 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3023 |
movw(idx, ylen); // idx = ylen; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3024 |
movw(kdx, zlen); // kdx = xlen+ylen; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3025 |
mov(carry, zr); // carry = 0; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3026 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3027 |
Label L_done; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3028 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3029 |
movw(xstart, xlen); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3030 |
subsw(xstart, xstart, 1); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3031 |
br(Assembler::MI, L_done); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3032 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3033 |
multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3034 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3035 |
Label L_second_loop; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3036 |
cbzw(kdx, L_second_loop); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3037 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3038 |
Label L_carry; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3039 |
subw(kdx, kdx, 1); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3040 |
cbzw(kdx, L_carry); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3041 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3042 |
strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt))); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3043 |
lsr(carry, carry, 32); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3044 |
subw(kdx, kdx, 1); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3045 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3046 |
bind(L_carry); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3047 |
strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt))); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3048 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3049 |
// Second and third (nested) loops. |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3050 |
// |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3051 |
// for (int i = xstart-1; i >= 0; i--) { // Second loop |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3052 |
// carry = 0; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3053 |
// for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3054 |
// long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) + |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3055 |
// (z[k] & LONG_MASK) + carry; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3056 |
// z[k] = (int)product; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3057 |
// carry = product >>> 32; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3058 |
// } |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3059 |
// z[i] = (int)carry; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3060 |
// } |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3061 |
// |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3062 |
// i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3063 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3064 |
const Register jdx = tmp1; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3065 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3066 |
bind(L_second_loop); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3067 |
mov(carry, zr); // carry = 0; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3068 |
movw(jdx, ylen); // j = ystart+1 |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3069 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3070 |
subsw(xstart, xstart, 1); // i = xstart-1; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3071 |
br(Assembler::MI, L_done); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3072 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3073 |
str(z, Address(pre(sp, -4 * wordSize))); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3074 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3075 |
Label L_last_x; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3076 |
lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3077 |
subsw(xstart, xstart, 1); // i = xstart-1; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3078 |
br(Assembler::MI, L_last_x); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3079 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3080 |
lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt))); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3081 |
ldr(product_hi, Address(rscratch1)); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3082 |
ror(product_hi, product_hi, 32); // convert big-endian to little-endian |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3083 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3084 |
Label L_third_loop_prologue; |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3085 |
bind(L_third_loop_prologue); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3086 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3087 |
str(ylen, Address(sp, wordSize)); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3088 |
stp(x, xstart, Address(sp, 2 * wordSize)); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3089 |
multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product, |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3090 |
tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3091 |
ldp(z, ylen, Address(post(sp, 2 * wordSize))); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3092 |
ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3093 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3094 |
addw(tmp3, xlen, 1); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3095 |
strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt))); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3096 |
subsw(tmp3, tmp3, 1); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3097 |
br(Assembler::MI, L_done); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3098 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3099 |
lsr(carry, carry, 32); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3100 |
strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt))); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3101 |
b(L_second_loop); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3102 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3103 |
// Next infrequent code is moved outside loops. |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3104 |
bind(L_last_x); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3105 |
ldrw(product_hi, Address(x, 0)); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3106 |
b(L_third_loop_prologue); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3107 |
|
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3108 |
bind(L_done); |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3109 |
} |
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3110 |
|
47571
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3111 |
// Code for BigInteger::mulAdd instrinsic |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3112 |
// out = r0 |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3113 |
// in = r1 |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3114 |
// offset = r2 (already out.length-offset) |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3115 |
// len = r3 |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3116 |
// k = r4 |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3117 |
// |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3118 |
// pseudo code from java implementation: |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3119 |
// carry = 0; |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3120 |
// offset = out.length-offset - 1; |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3121 |
// for (int j=len-1; j >= 0; j--) { |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3122 |
// product = (in[j] & LONG_MASK) * kLong + (out[offset] & LONG_MASK) + carry; |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3123 |
// out[offset--] = (int)product; |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3124 |
// carry = product >>> 32; |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3125 |
// } |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3126 |
// return (int)carry; |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3127 |
void MacroAssembler::mul_add(Register out, Register in, Register offset, |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3128 |
Register len, Register k) { |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3129 |
Label LOOP, END; |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3130 |
// pre-loop |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3131 |
cmp(len, zr); // cmp, not cbz/cbnz: to use condition twice => less branches |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3132 |
csel(out, zr, out, Assembler::EQ); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3133 |
br(Assembler::EQ, END); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3134 |
add(in, in, len, LSL, 2); // in[j+1] address |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3135 |
add(offset, out, offset, LSL, 2); // out[offset + 1] address |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3136 |
mov(out, zr); // used to keep carry now |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3137 |
BIND(LOOP); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3138 |
ldrw(rscratch1, Address(pre(in, -4))); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3139 |
madd(rscratch1, rscratch1, k, out); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3140 |
ldrw(rscratch2, Address(pre(offset, -4))); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3141 |
add(rscratch1, rscratch1, rscratch2); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3142 |
strw(rscratch1, Address(offset)); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3143 |
lsr(out, rscratch1, 32); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3144 |
subs(len, len, 1); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3145 |
br(Assembler::NE, LOOP); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3146 |
BIND(END); |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3147 |
} |
c19054f06c14
8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents:
47216
diff
changeset
|
3148 |
|
30225
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
3149 |
/** |
29183 | 3150 |
* Emits code to update CRC-32 with a byte value according to constants in table |
3151 |
* |
|
3152 |
* @param [in,out]crc Register containing the crc. |
|
3153 |
* @param [in]val Register containing the byte to fold into the CRC. |
|
3154 |
* @param [in]table Register containing the table of crc constants. |
|
3155 |
* |
|
3156 |
* uint32_t crc; |
|
3157 |
* val = crc_table[(val ^ crc) & 0xFF]; |
|
3158 |
* crc = val ^ (crc >> 8); |
|
3159 |
* |
|
3160 |
*/ |
|
3161 |
void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) { |
|
3162 |
eor(val, val, crc); |
|
3163 |
andr(val, val, 0xff); |
|
3164 |
ldrw(val, Address(table, val, Address::lsl(2))); |
|
3165 |
eor(crc, val, crc, Assembler::LSR, 8); |
|
3166 |
} |
|
3167 |
||
3168 |
/** |
|
3169 |
* Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3 |
|
3170 |
* |
|
3171 |
* @param [in,out]crc Register containing the crc. |
|
3172 |
* @param [in]v Register containing the 32-bit to fold into the CRC. |
|
3173 |
* @param [in]table0 Register containing table 0 of crc constants. |
|
3174 |
* @param [in]table1 Register containing table 1 of crc constants. |
|
3175 |
* @param [in]table2 Register containing table 2 of crc constants. |
|
3176 |
* @param [in]table3 Register containing table 3 of crc constants. |
|
3177 |
* |
|
3178 |
* uint32_t crc; |
|
3179 |
* v = crc ^ v |
|
3180 |
* crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24] |
|
3181 |
* |
|
3182 |
*/ |
|
3183 |
void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp, |
|
3184 |
Register table0, Register table1, Register table2, Register table3, |
|
3185 |
bool upper) { |
|
3186 |
eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0); |
|
3187 |
uxtb(tmp, v); |
|
3188 |
ldrw(crc, Address(table3, tmp, Address::lsl(2))); |
|
3189 |
ubfx(tmp, v, 8, 8); |
|
3190 |
ldrw(tmp, Address(table2, tmp, Address::lsl(2))); |
|
3191 |
eor(crc, crc, tmp); |
|
3192 |
ubfx(tmp, v, 16, 8); |
|
3193 |
ldrw(tmp, Address(table1, tmp, Address::lsl(2))); |
|
3194 |
eor(crc, crc, tmp); |
|
3195 |
ubfx(tmp, v, 24, 8); |
|
3196 |
ldrw(tmp, Address(table0, tmp, Address::lsl(2))); |
|
3197 |
eor(crc, crc, tmp); |
|
3198 |
} |
|
3199 |
||
47773
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3200 |
void MacroAssembler::kernel_crc32_using_crc32(Register crc, Register buf, |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3201 |
Register len, Register tmp0, Register tmp1, Register tmp2, |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3202 |
Register tmp3) { |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3203 |
Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit; |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3204 |
assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3205 |
|
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3206 |
mvnw(crc, crc); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3207 |
|
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3208 |
subs(len, len, 128); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3209 |
br(Assembler::GE, CRC_by64_pre); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3210 |
BIND(CRC_less64); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3211 |
adds(len, len, 128-32); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3212 |
br(Assembler::GE, CRC_by32_loop); |
47780
895da9d2087b
8190745: AARCH64: fix for JDK-8189176 may break a build
dchuyko
parents:
47773
diff
changeset
|
3213 |
BIND(CRC_less32); |
47773
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3214 |
adds(len, len, 32-4); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3215 |
br(Assembler::GE, CRC_by4_loop); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3216 |
adds(len, len, 4); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3217 |
br(Assembler::GT, CRC_by1_loop); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3218 |
b(L_exit); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3219 |
|
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3220 |
BIND(CRC_by32_loop); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3221 |
ldp(tmp0, tmp1, Address(post(buf, 16))); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3222 |
subs(len, len, 32); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3223 |
crc32x(crc, crc, tmp0); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3224 |
ldr(tmp2, Address(post(buf, 8))); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3225 |
crc32x(crc, crc, tmp1); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3226 |
ldr(tmp3, Address(post(buf, 8))); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3227 |
crc32x(crc, crc, tmp2); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3228 |
crc32x(crc, crc, tmp3); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3229 |
br(Assembler::GE, CRC_by32_loop); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3230 |
cmn(len, 32); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3231 |
br(Assembler::NE, CRC_less32); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3232 |
b(L_exit); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3233 |
|
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3234 |
BIND(CRC_by4_loop); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3235 |
ldrw(tmp0, Address(post(buf, 4))); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3236 |
subs(len, len, 4); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3237 |
crc32w(crc, crc, tmp0); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3238 |
br(Assembler::GE, CRC_by4_loop); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3239 |
adds(len, len, 4); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3240 |
br(Assembler::LE, L_exit); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3241 |
BIND(CRC_by1_loop); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3242 |
ldrb(tmp0, Address(post(buf, 1))); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3243 |
subs(len, len, 1); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3244 |
crc32b(crc, crc, tmp0); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3245 |
br(Assembler::GT, CRC_by1_loop); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3246 |
b(L_exit); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3247 |
|
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3248 |
BIND(CRC_by64_pre); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3249 |
sub(buf, buf, 8); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3250 |
ldp(tmp0, tmp1, Address(buf, 8)); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3251 |
crc32x(crc, crc, tmp0); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3252 |
ldr(tmp2, Address(buf, 24)); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3253 |
crc32x(crc, crc, tmp1); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3254 |
ldr(tmp3, Address(buf, 32)); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3255 |
crc32x(crc, crc, tmp2); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3256 |
ldr(tmp0, Address(buf, 40)); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3257 |
crc32x(crc, crc, tmp3); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3258 |
ldr(tmp1, Address(buf, 48)); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3259 |
crc32x(crc, crc, tmp0); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3260 |
ldr(tmp2, Address(buf, 56)); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3261 |
crc32x(crc, crc, tmp1); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3262 |
ldr(tmp3, Address(pre(buf, 64))); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3263 |
|
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3264 |
b(CRC_by64_loop); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3265 |
|
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3266 |
align(CodeEntryAlignment); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3267 |
BIND(CRC_by64_loop); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3268 |
subs(len, len, 64); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3269 |
crc32x(crc, crc, tmp2); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3270 |
ldr(tmp0, Address(buf, 8)); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3271 |
crc32x(crc, crc, tmp3); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3272 |
ldr(tmp1, Address(buf, 16)); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3273 |
crc32x(crc, crc, tmp0); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3274 |
ldr(tmp2, Address(buf, 24)); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3275 |
crc32x(crc, crc, tmp1); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3276 |
ldr(tmp3, Address(buf, 32)); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3277 |
crc32x(crc, crc, tmp2); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3278 |
ldr(tmp0, Address(buf, 40)); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3279 |
crc32x(crc, crc, tmp3); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3280 |
ldr(tmp1, Address(buf, 48)); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3281 |
crc32x(crc, crc, tmp0); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3282 |
ldr(tmp2, Address(buf, 56)); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3283 |
crc32x(crc, crc, tmp1); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3284 |
ldr(tmp3, Address(pre(buf, 64))); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3285 |
br(Assembler::GE, CRC_by64_loop); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3286 |
|
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3287 |
// post-loop |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3288 |
crc32x(crc, crc, tmp2); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3289 |
crc32x(crc, crc, tmp3); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3290 |
|
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3291 |
sub(len, len, 64); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3292 |
add(buf, buf, 8); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3293 |
cmn(len, 128); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3294 |
br(Assembler::NE, CRC_less64); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3295 |
BIND(L_exit); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3296 |
mvnw(crc, crc); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3297 |
} |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3298 |
|
29183 | 3299 |
/** |
3300 |
* @param crc register containing existing CRC (32-bit) |
|
3301 |
* @param buf register pointing to input byte buffer (byte*) |
|
3302 |
* @param len register containing number of bytes |
|
3303 |
* @param table register that will contain address of CRC table |
|
3304 |
* @param tmp scratch register |
|
3305 |
*/ |
|
3306 |
void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, |
|
3307 |
Register table0, Register table1, Register table2, Register table3, |
|
3308 |
Register tmp, Register tmp2, Register tmp3) { |
|
3309 |
Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit; |
|
3310 |
unsigned long offset; |
|
3311 |
||
3312 |
if (UseCRC32) { |
|
47773
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3313 |
kernel_crc32_using_crc32(crc, buf, len, table0, table1, table2, table3); |
29183 | 3314 |
return; |
3315 |
} |
|
3316 |
||
47773
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3317 |
mvnw(crc, crc); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3318 |
|
29183 | 3319 |
adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset); |
3320 |
if (offset) add(table0, table0, offset); |
|
3321 |
add(table1, table0, 1*256*sizeof(juint)); |
|
3322 |
add(table2, table0, 2*256*sizeof(juint)); |
|
3323 |
add(table3, table0, 3*256*sizeof(juint)); |
|
3324 |
||
3325 |
if (UseNeon) { |
|
3326 |
cmp(len, 64); |
|
3327 |
br(Assembler::LT, L_by16); |
|
3328 |
eor(v16, T16B, v16, v16); |
|
3329 |
||
3330 |
Label L_fold; |
|
3331 |
||
3332 |
add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants |
|
3333 |
||
3334 |
ld1(v0, v1, T2D, post(buf, 32)); |
|
3335 |
ld1r(v4, T2D, post(tmp, 8)); |
|
3336 |
ld1r(v5, T2D, post(tmp, 8)); |
|
3337 |
ld1r(v6, T2D, post(tmp, 8)); |
|
3338 |
ld1r(v7, T2D, post(tmp, 8)); |
|
3339 |
mov(v16, T4S, 0, crc); |
|
3340 |
||
3341 |
eor(v0, T16B, v0, v16); |
|
3342 |
sub(len, len, 64); |
|
3343 |
||
3344 |
BIND(L_fold); |
|
3345 |
pmull(v22, T8H, v0, v5, T8B); |
|
3346 |
pmull(v20, T8H, v0, v7, T8B); |
|
3347 |
pmull(v23, T8H, v0, v4, T8B); |
|
3348 |
pmull(v21, T8H, v0, v6, T8B); |
|
3349 |
||
3350 |
pmull2(v18, T8H, v0, v5, T16B); |
|
3351 |
pmull2(v16, T8H, v0, v7, T16B); |
|
3352 |
pmull2(v19, T8H, v0, v4, T16B); |
|
3353 |
pmull2(v17, T8H, v0, v6, T16B); |
|
3354 |
||
50644
409bfb0c071e
8205341: AARCH64: Clean up duplicate uzp1 & uzp2 instruction definition
dchuyko
parents:
50641
diff
changeset
|
3355 |
uzp1(v24, T8H, v20, v22); |
409bfb0c071e
8205341: AARCH64: Clean up duplicate uzp1 & uzp2 instruction definition
dchuyko
parents:
50641
diff
changeset
|
3356 |
uzp2(v25, T8H, v20, v22); |
29183 | 3357 |
eor(v20, T16B, v24, v25); |
3358 |
||
50644
409bfb0c071e
8205341: AARCH64: Clean up duplicate uzp1 & uzp2 instruction definition
dchuyko
parents:
50641
diff
changeset
|
3359 |
uzp1(v26, T8H, v16, v18); |
409bfb0c071e
8205341: AARCH64: Clean up duplicate uzp1 & uzp2 instruction definition
dchuyko
parents:
50641
diff
changeset
|
3360 |
uzp2(v27, T8H, v16, v18); |
29183 | 3361 |
eor(v16, T16B, v26, v27); |
3362 |
||
3363 |
ushll2(v22, T4S, v20, T8H, 8); |
|
3364 |
ushll(v20, T4S, v20, T4H, 8); |
|
3365 |
||
3366 |
ushll2(v18, T4S, v16, T8H, 8); |
|
3367 |
ushll(v16, T4S, v16, T4H, 8); |
|
3368 |
||
3369 |
eor(v22, T16B, v23, v22); |
|
3370 |
eor(v18, T16B, v19, v18); |
|
3371 |
eor(v20, T16B, v21, v20); |
|
3372 |
eor(v16, T16B, v17, v16); |
|
3373 |
||
50644
409bfb0c071e
8205341: AARCH64: Clean up duplicate uzp1 & uzp2 instruction definition
dchuyko
parents:
50641
diff
changeset
|
3374 |
uzp1(v17, T2D, v16, v20); |
409bfb0c071e
8205341: AARCH64: Clean up duplicate uzp1 & uzp2 instruction definition
dchuyko
parents:
50641
diff
changeset
|
3375 |
uzp2(v21, T2D, v16, v20); |
29183 | 3376 |
eor(v17, T16B, v17, v21); |
3377 |
||
3378 |
ushll2(v20, T2D, v17, T4S, 16); |
|
3379 |
ushll(v16, T2D, v17, T2S, 16); |
|
3380 |
||
3381 |
eor(v20, T16B, v20, v22); |
|
3382 |
eor(v16, T16B, v16, v18); |
|
3383 |
||
50644
409bfb0c071e
8205341: AARCH64: Clean up duplicate uzp1 & uzp2 instruction definition
dchuyko
parents:
50641
diff
changeset
|
3384 |
uzp1(v17, T2D, v20, v16); |
409bfb0c071e
8205341: AARCH64: Clean up duplicate uzp1 & uzp2 instruction definition
dchuyko
parents:
50641
diff
changeset
|
3385 |
uzp2(v21, T2D, v20, v16); |
29183 | 3386 |
eor(v28, T16B, v17, v21); |
3387 |
||
3388 |
pmull(v22, T8H, v1, v5, T8B); |
|
3389 |
pmull(v20, T8H, v1, v7, T8B); |
|
3390 |
pmull(v23, T8H, v1, v4, T8B); |
|
3391 |
pmull(v21, T8H, v1, v6, T8B); |
|
3392 |
||
3393 |
pmull2(v18, T8H, v1, v5, T16B); |
|
3394 |
pmull2(v16, T8H, v1, v7, T16B); |
|
3395 |
pmull2(v19, T8H, v1, v4, T16B); |
|
3396 |
pmull2(v17, T8H, v1, v6, T16B); |
|
3397 |
||
3398 |
ld1(v0, v1, T2D, post(buf, 32)); |
|
3399 |
||
50644
409bfb0c071e
8205341: AARCH64: Clean up duplicate uzp1 & uzp2 instruction definition
dchuyko
parents:
50641
diff
changeset
|
3400 |
uzp1(v24, T8H, v20, v22); |
409bfb0c071e
8205341: AARCH64: Clean up duplicate uzp1 & uzp2 instruction definition
dchuyko
parents:
50641
diff
changeset
|
3401 |
uzp2(v25, T8H, v20, v22); |
29183 | 3402 |
eor(v20, T16B, v24, v25); |
3403 |
||
50644
409bfb0c071e
8205341: AARCH64: Clean up duplicate uzp1 & uzp2 instruction definition
dchuyko
parents:
50641
diff
changeset
|
3404 |
uzp1(v26, T8H, v16, v18); |
409bfb0c071e
8205341: AARCH64: Clean up duplicate uzp1 & uzp2 instruction definition
dchuyko
parents:
50641
diff
changeset
|
3405 |
uzp2(v27, T8H, v16, v18); |
29183 | 3406 |
eor(v16, T16B, v26, v27); |
3407 |
||
3408 |
ushll2(v22, T4S, v20, T8H, 8); |
|
3409 |
ushll(v20, T4S, v20, T4H, 8); |
|
3410 |
||
3411 |
ushll2(v18, T4S, v16, T8H, 8); |
|
3412 |
ushll(v16, T4S, v16, T4H, 8); |
|
3413 |
||
3414 |
eor(v22, T16B, v23, v22); |
|
3415 |
eor(v18, T16B, v19, v18); |
|
3416 |
eor(v20, T16B, v21, v20); |
|
3417 |
eor(v16, T16B, v17, v16); |
|
3418 |
||
50644
409bfb0c071e
8205341: AARCH64: Clean up duplicate uzp1 & uzp2 instruction definition
dchuyko
parents:
50641
diff
changeset
|
3419 |
uzp1(v17, T2D, v16, v20); |
409bfb0c071e
8205341: AARCH64: Clean up duplicate uzp1 & uzp2 instruction definition
dchuyko
parents:
50641
diff
changeset
|
3420 |
uzp2(v21, T2D, v16, v20); |
29183 | 3421 |
eor(v16, T16B, v17, v21); |
3422 |
||
3423 |
ushll2(v20, T2D, v16, T4S, 16); |
|
3424 |
ushll(v16, T2D, v16, T2S, 16); |
|
3425 |
||
3426 |
eor(v20, T16B, v22, v20); |
|
3427 |
eor(v16, T16B, v16, v18); |
|
3428 |
||
50644
409bfb0c071e
8205341: AARCH64: Clean up duplicate uzp1 & uzp2 instruction definition
dchuyko
parents:
50641
diff
changeset
|
3429 |
uzp1(v17, T2D, v20, v16); |
409bfb0c071e
8205341: AARCH64: Clean up duplicate uzp1 & uzp2 instruction definition
dchuyko
parents:
50641
diff
changeset
|
3430 |
uzp2(v21, T2D, v20, v16); |
29183 | 3431 |
eor(v20, T16B, v17, v21); |
3432 |
||
30890
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30777
diff
changeset
|
3433 |
shl(v16, T2D, v28, 1); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30777
diff
changeset
|
3434 |
shl(v17, T2D, v20, 1); |
29183 | 3435 |
|
3436 |
eor(v0, T16B, v0, v16); |
|
3437 |
eor(v1, T16B, v1, v17); |
|
3438 |
||
3439 |
subs(len, len, 32); |
|
3440 |
br(Assembler::GE, L_fold); |
|
3441 |
||
3442 |
mov(crc, 0); |
|
3443 |
mov(tmp, v0, T1D, 0); |
|
3444 |
update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); |
|
3445 |
update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); |
|
3446 |
mov(tmp, v0, T1D, 1); |
|
3447 |
update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); |
|
3448 |
update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); |
|
3449 |
mov(tmp, v1, T1D, 0); |
|
3450 |
update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); |
|
3451 |
update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); |
|
3452 |
mov(tmp, v1, T1D, 1); |
|
3453 |
update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); |
|
3454 |
update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); |
|
3455 |
||
3456 |
add(len, len, 32); |
|
3457 |
} |
|
3458 |
||
3459 |
BIND(L_by16); |
|
3460 |
subs(len, len, 16); |
|
3461 |
br(Assembler::GE, L_by16_loop); |
|
3462 |
adds(len, len, 16-4); |
|
3463 |
br(Assembler::GE, L_by4_loop); |
|
3464 |
adds(len, len, 4); |
|
3465 |
br(Assembler::GT, L_by1_loop); |
|
3466 |
b(L_exit); |
|
3467 |
||
3468 |
BIND(L_by4_loop); |
|
3469 |
ldrw(tmp, Address(post(buf, 4))); |
|
3470 |
update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3); |
|
3471 |
subs(len, len, 4); |
|
3472 |
br(Assembler::GE, L_by4_loop); |
|
3473 |
adds(len, len, 4); |
|
3474 |
br(Assembler::LE, L_exit); |
|
3475 |
BIND(L_by1_loop); |
|
3476 |
subs(len, len, 1); |
|
3477 |
ldrb(tmp, Address(post(buf, 1))); |
|
3478 |
update_byte_crc32(crc, tmp, table0); |
|
3479 |
br(Assembler::GT, L_by1_loop); |
|
3480 |
b(L_exit); |
|
3481 |
||
3482 |
align(CodeEntryAlignment); |
|
3483 |
BIND(L_by16_loop); |
|
3484 |
subs(len, len, 16); |
|
3485 |
ldp(tmp, tmp3, Address(post(buf, 16))); |
|
3486 |
update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); |
|
3487 |
update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); |
|
3488 |
update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false); |
|
3489 |
update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true); |
|
3490 |
br(Assembler::GE, L_by16_loop); |
|
3491 |
adds(len, len, 16-4); |
|
3492 |
br(Assembler::GE, L_by4_loop); |
|
3493 |
adds(len, len, 4); |
|
3494 |
br(Assembler::GT, L_by1_loop); |
|
3495 |
BIND(L_exit); |
|
47773
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47765
diff
changeset
|
3496 |
mvnw(crc, crc); |
29183 | 3497 |
} |
3498 |
||
47915
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3499 |
void MacroAssembler::kernel_crc32c_using_crc32c(Register crc, Register buf, |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3500 |
Register len, Register tmp0, Register tmp1, Register tmp2, |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3501 |
Register tmp3) { |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3502 |
Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit; |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3503 |
assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3504 |
|
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3505 |
subs(len, len, 128); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3506 |
br(Assembler::GE, CRC_by64_pre); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3507 |
BIND(CRC_less64); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3508 |
adds(len, len, 128-32); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3509 |
br(Assembler::GE, CRC_by32_loop); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3510 |
BIND(CRC_less32); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3511 |
adds(len, len, 32-4); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3512 |
br(Assembler::GE, CRC_by4_loop); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3513 |
adds(len, len, 4); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3514 |
br(Assembler::GT, CRC_by1_loop); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3515 |
b(L_exit); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3516 |
|
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3517 |
BIND(CRC_by32_loop); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3518 |
ldp(tmp0, tmp1, Address(post(buf, 16))); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3519 |
subs(len, len, 32); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3520 |
crc32cx(crc, crc, tmp0); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3521 |
ldr(tmp2, Address(post(buf, 8))); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3522 |
crc32cx(crc, crc, tmp1); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3523 |
ldr(tmp3, Address(post(buf, 8))); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3524 |
crc32cx(crc, crc, tmp2); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3525 |
crc32cx(crc, crc, tmp3); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3526 |
br(Assembler::GE, CRC_by32_loop); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3527 |
cmn(len, 32); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3528 |
br(Assembler::NE, CRC_less32); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3529 |
b(L_exit); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3530 |
|
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3531 |
BIND(CRC_by4_loop); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3532 |
ldrw(tmp0, Address(post(buf, 4))); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3533 |
subs(len, len, 4); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3534 |
crc32cw(crc, crc, tmp0); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3535 |
br(Assembler::GE, CRC_by4_loop); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3536 |
adds(len, len, 4); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3537 |
br(Assembler::LE, L_exit); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3538 |
BIND(CRC_by1_loop); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3539 |
ldrb(tmp0, Address(post(buf, 1))); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3540 |
subs(len, len, 1); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3541 |
crc32cb(crc, crc, tmp0); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3542 |
br(Assembler::GT, CRC_by1_loop); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3543 |
b(L_exit); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3544 |
|
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3545 |
BIND(CRC_by64_pre); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3546 |
sub(buf, buf, 8); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3547 |
ldp(tmp0, tmp1, Address(buf, 8)); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3548 |
crc32cx(crc, crc, tmp0); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3549 |
ldr(tmp2, Address(buf, 24)); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3550 |
crc32cx(crc, crc, tmp1); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3551 |
ldr(tmp3, Address(buf, 32)); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3552 |
crc32cx(crc, crc, tmp2); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3553 |
ldr(tmp0, Address(buf, 40)); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3554 |
crc32cx(crc, crc, tmp3); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3555 |
ldr(tmp1, Address(buf, 48)); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3556 |
crc32cx(crc, crc, tmp0); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3557 |
ldr(tmp2, Address(buf, 56)); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3558 |
crc32cx(crc, crc, tmp1); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3559 |
ldr(tmp3, Address(pre(buf, 64))); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3560 |
|
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3561 |
b(CRC_by64_loop); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3562 |
|
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3563 |
align(CodeEntryAlignment); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3564 |
BIND(CRC_by64_loop); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3565 |
subs(len, len, 64); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3566 |
crc32cx(crc, crc, tmp2); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3567 |
ldr(tmp0, Address(buf, 8)); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3568 |
crc32cx(crc, crc, tmp3); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3569 |
ldr(tmp1, Address(buf, 16)); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3570 |
crc32cx(crc, crc, tmp0); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3571 |
ldr(tmp2, Address(buf, 24)); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3572 |
crc32cx(crc, crc, tmp1); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3573 |
ldr(tmp3, Address(buf, 32)); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3574 |
crc32cx(crc, crc, tmp2); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3575 |
ldr(tmp0, Address(buf, 40)); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3576 |
crc32cx(crc, crc, tmp3); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3577 |
ldr(tmp1, Address(buf, 48)); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3578 |
crc32cx(crc, crc, tmp0); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3579 |
ldr(tmp2, Address(buf, 56)); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3580 |
crc32cx(crc, crc, tmp1); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3581 |
ldr(tmp3, Address(pre(buf, 64))); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3582 |
br(Assembler::GE, CRC_by64_loop); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3583 |
|
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3584 |
// post-loop |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3585 |
crc32cx(crc, crc, tmp2); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3586 |
crc32cx(crc, crc, tmp3); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3587 |
|
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3588 |
sub(len, len, 64); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3589 |
add(buf, buf, 8); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3590 |
cmn(len, 128); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3591 |
br(Assembler::NE, CRC_less64); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3592 |
BIND(L_exit); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3593 |
} |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3594 |
|
31591
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
31414
diff
changeset
|
3595 |
/** |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
31414
diff
changeset
|
3596 |
* @param crc register containing existing CRC (32-bit) |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
31414
diff
changeset
|
3597 |
* @param buf register pointing to input byte buffer (byte*) |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
31414
diff
changeset
|
3598 |
* @param len register containing number of bytes |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
31414
diff
changeset
|
3599 |
* @param table register that will contain address of CRC table |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
31414
diff
changeset
|
3600 |
* @param tmp scratch register |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
31414
diff
changeset
|
3601 |
*/ |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
31414
diff
changeset
|
3602 |
void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len, |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
31414
diff
changeset
|
3603 |
Register table0, Register table1, Register table2, Register table3, |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
31414
diff
changeset
|
3604 |
Register tmp, Register tmp2, Register tmp3) { |
47915
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3605 |
kernel_crc32c_using_crc32c(crc, buf, len, table0, table1, table2, table3); |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3606 |
} |
d4af6b80aec3
8189177: AARCH64: Improve _updateBytesCRC32C intrinsic
dchuyko
parents:
47780
diff
changeset
|
3607 |
|
31591
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
31414
diff
changeset
|
3608 |
|
29183 | 3609 |
SkipIfEqual::SkipIfEqual( |
3610 |
MacroAssembler* masm, const bool* flag_addr, bool value) { |
|
3611 |
_masm = masm; |
|
3612 |
unsigned long offset; |
|
3613 |
_masm->adrp(rscratch1, ExternalAddress((address)flag_addr), offset); |
|
3614 |
_masm->ldrb(rscratch1, Address(rscratch1, offset)); |
|
3615 |
_masm->cbzw(rscratch1, _label); |
|
3616 |
} |
|
3617 |
||
3618 |
SkipIfEqual::~SkipIfEqual() { |
|
3619 |
_masm->bind(_label); |
|
3620 |
} |
|
3621 |
||
33175 | 3622 |
void MacroAssembler::addptr(const Address &dst, int32_t src) { |
3623 |
Address adr; |
|
3624 |
switch(dst.getMode()) { |
|
3625 |
case Address::base_plus_offset: |
|
3626 |
// This is the expected mode, although we allow all the other |
|
3627 |
// forms below. |
|
3628 |
adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord); |
|
3629 |
break; |
|
3630 |
default: |
|
3631 |
lea(rscratch2, dst); |
|
3632 |
adr = Address(rscratch2); |
|
3633 |
break; |
|
3634 |
} |
|
3635 |
ldr(rscratch1, adr); |
|
3636 |
add(rscratch1, rscratch1, src); |
|
3637 |
str(rscratch1, adr); |
|
3638 |
} |
|
3639 |
||
29183 | 3640 |
void MacroAssembler::cmpptr(Register src1, Address src2) { |
3641 |
unsigned long offset; |
|
3642 |
adrp(rscratch1, src2, offset); |
|
3643 |
ldr(rscratch1, Address(rscratch1, offset)); |
|
3644 |
cmp(src1, rscratch1); |
|
3645 |
} |
|
3646 |
||
50536
8434981a4137
8203157: Object equals abstraction for BarrierSetAssembler
rkennke
parents:
50517
diff
changeset
|
3647 |
void MacroAssembler::cmpoop(Register obj1, Register obj2) { |
8434981a4137
8203157: Object equals abstraction for BarrierSetAssembler
rkennke
parents:
50517
diff
changeset
|
3648 |
BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); |
8434981a4137
8203157: Object equals abstraction for BarrierSetAssembler
rkennke
parents:
50517
diff
changeset
|
3649 |
bs->obj_equals(this, obj1, obj2); |
8434981a4137
8203157: Object equals abstraction for BarrierSetAssembler
rkennke
parents:
50517
diff
changeset
|
3650 |
} |
8434981a4137
8203157: Object equals abstraction for BarrierSetAssembler
rkennke
parents:
50517
diff
changeset
|
3651 |
|
29183 | 3652 |
void MacroAssembler::load_klass(Register dst, Register src) { |
3653 |
if (UseCompressedClassPointers) { |
|
3654 |
ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
|
3655 |
decode_klass_not_null(dst); |
|
3656 |
} else { |
|
3657 |
ldr(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
|
3658 |
} |
|
3659 |
} |
|
3660 |
||
46961
c9094b1e5f87
8186088: ConstantPoolCache::_resolved_references is not a JNIHandle
coleenp
parents:
46814
diff
changeset
|
3661 |
// ((OopHandle)result).resolve(); |
49816 | 3662 |
void MacroAssembler::resolve_oop_handle(Register result, Register tmp) { |
46961
c9094b1e5f87
8186088: ConstantPoolCache::_resolved_references is not a JNIHandle
coleenp
parents:
46814
diff
changeset
|
3663 |
// OopHandle::resolve is an indirection. |
50517
618526574f8b
8204628: [AArch64] Assertion failure in BarrierSetAssembler::load_at
smonteith
parents:
50446
diff
changeset
|
3664 |
access_load_at(T_OBJECT, IN_CONCURRENT_ROOT, |
618526574f8b
8204628: [AArch64] Assertion failure in BarrierSetAssembler::load_at
smonteith
parents:
50446
diff
changeset
|
3665 |
result, Address(result, 0), tmp, noreg); |
49816 | 3666 |
} |
3667 |
||
3668 |
void MacroAssembler::load_mirror(Register dst, Register method, Register tmp) { |
|
38074
8475fdc6dcc3
8154580: Save mirror in interpreter frame to enable cleanups of CLDClosure
coleenp
parents:
38057
diff
changeset
|
3669 |
const int mirror_offset = in_bytes(Klass::java_mirror_offset()); |
8475fdc6dcc3
8154580: Save mirror in interpreter frame to enable cleanups of CLDClosure
coleenp
parents:
38057
diff
changeset
|
3670 |
ldr(dst, Address(rmethod, Method::const_offset())); |
8475fdc6dcc3
8154580: Save mirror in interpreter frame to enable cleanups of CLDClosure
coleenp
parents:
38057
diff
changeset
|
3671 |
ldr(dst, Address(dst, ConstMethod::constants_offset())); |
8475fdc6dcc3
8154580: Save mirror in interpreter frame to enable cleanups of CLDClosure
coleenp
parents:
38057
diff
changeset
|
3672 |
ldr(dst, Address(dst, ConstantPool::pool_holder_offset_in_bytes())); |
8475fdc6dcc3
8154580: Save mirror in interpreter frame to enable cleanups of CLDClosure
coleenp
parents:
38057
diff
changeset
|
3673 |
ldr(dst, Address(dst, mirror_offset)); |
49816 | 3674 |
resolve_oop_handle(dst, tmp); |
38074
8475fdc6dcc3
8154580: Save mirror in interpreter frame to enable cleanups of CLDClosure
coleenp
parents:
38057
diff
changeset
|
3675 |
} |
8475fdc6dcc3
8154580: Save mirror in interpreter frame to enable cleanups of CLDClosure
coleenp
parents:
38057
diff
changeset
|
3676 |
|
29183 | 3677 |
void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) { |
3678 |
if (UseCompressedClassPointers) { |
|
3679 |
ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes())); |
|
3680 |
if (Universe::narrow_klass_base() == NULL) { |
|
3681 |
cmp(trial_klass, tmp, LSL, Universe::narrow_klass_shift()); |
|
3682 |
return; |
|
3683 |
} else if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0 |
|
3684 |
&& Universe::narrow_klass_shift() == 0) { |
|
3685 |
// Only the bottom 32 bits matter |
|
3686 |
cmpw(trial_klass, tmp); |
|
3687 |
return; |
|
3688 |
} |
|
3689 |
decode_klass_not_null(tmp); |
|
3690 |
} else { |
|
3691 |
ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes())); |
|
3692 |
} |
|
3693 |
cmp(trial_klass, tmp); |
|
3694 |
} |
|
3695 |
||
3696 |
void MacroAssembler::load_prototype_header(Register dst, Register src) { |
|
3697 |
load_klass(dst, src); |
|
3698 |
ldr(dst, Address(dst, Klass::prototype_header_offset())); |
|
3699 |
} |
|
3700 |
||
3701 |
void MacroAssembler::store_klass(Register dst, Register src) { |
|
3702 |
// FIXME: Should this be a store release? concurrent gcs assumes |
|
3703 |
// klass length is valid if klass field is not null. |
|
3704 |
if (UseCompressedClassPointers) { |
|
3705 |
encode_klass_not_null(src); |
|
3706 |
strw(src, Address(dst, oopDesc::klass_offset_in_bytes())); |
|
3707 |
} else { |
|
3708 |
str(src, Address(dst, oopDesc::klass_offset_in_bytes())); |
|
3709 |
} |
|
3710 |
} |
|
3711 |
||
3712 |
void MacroAssembler::store_klass_gap(Register dst, Register src) { |
|
3713 |
if (UseCompressedClassPointers) { |
|
3714 |
// Store to klass gap in destination |
|
3715 |
strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes())); |
|
3716 |
} |
|
3717 |
} |
|
3718 |
||
49592
77fb0be7d19f
8199946: Move load/store and encode/decode out of oopDesc
stefank
parents:
49455
diff
changeset
|
3719 |
// Algorithm must match CompressedOops::encode. |
29183 | 3720 |
void MacroAssembler::encode_heap_oop(Register d, Register s) { |
3721 |
#ifdef ASSERT |
|
3722 |
verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); |
|
3723 |
#endif |
|
3724 |
verify_oop(s, "broken oop in encode_heap_oop"); |
|
3725 |
if (Universe::narrow_oop_base() == NULL) { |
|
3726 |
if (Universe::narrow_oop_shift() != 0) { |
|
3727 |
assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
3728 |
lsr(d, s, LogMinObjAlignmentInBytes); |
|
3729 |
} else { |
|
3730 |
mov(d, s); |
|
3731 |
} |
|
3732 |
} else { |
|
3733 |
subs(d, s, rheapbase); |
|
3734 |
csel(d, d, zr, Assembler::HS); |
|
3735 |
lsr(d, d, LogMinObjAlignmentInBytes); |
|
3736 |
||
3737 |
/* Old algorithm: is this any worse? |
|
3738 |
Label nonnull; |
|
3739 |
cbnz(r, nonnull); |
|
3740 |
sub(r, r, rheapbase); |
|
3741 |
bind(nonnull); |
|
3742 |
lsr(r, r, LogMinObjAlignmentInBytes); |
|
3743 |
*/ |
|
3744 |
} |
|
3745 |
} |
|
3746 |
||
3747 |
void MacroAssembler::encode_heap_oop_not_null(Register r) { |
|
3748 |
#ifdef ASSERT |
|
3749 |
verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); |
|
3750 |
if (CheckCompressedOops) { |
|
3751 |
Label ok; |
|
3752 |
cbnz(r, ok); |
|
3753 |
stop("null oop passed to encode_heap_oop_not_null"); |
|
3754 |
bind(ok); |
|
3755 |
} |
|
3756 |
#endif |
|
3757 |
verify_oop(r, "broken oop in encode_heap_oop_not_null"); |
|
3758 |
if (Universe::narrow_oop_base() != NULL) { |
|
3759 |
sub(r, r, rheapbase); |
|
3760 |
} |
|
3761 |
if (Universe::narrow_oop_shift() != 0) { |
|
3762 |
assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
3763 |
lsr(r, r, LogMinObjAlignmentInBytes); |
|
3764 |
} |
|
3765 |
} |
|
3766 |
||
3767 |
void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { |
|
3768 |
#ifdef ASSERT |
|
3769 |
verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); |
|
3770 |
if (CheckCompressedOops) { |
|
3771 |
Label ok; |
|
3772 |
cbnz(src, ok); |
|
3773 |
stop("null oop passed to encode_heap_oop_not_null2"); |
|
3774 |
bind(ok); |
|
3775 |
} |
|
3776 |
#endif |
|
3777 |
verify_oop(src, "broken oop in encode_heap_oop_not_null2"); |
|
3778 |
||
3779 |
Register data = src; |
|
3780 |
if (Universe::narrow_oop_base() != NULL) { |
|
3781 |
sub(dst, src, rheapbase); |
|
3782 |
data = dst; |
|
3783 |
} |
|
3784 |
if (Universe::narrow_oop_shift() != 0) { |
|
3785 |
assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
3786 |
lsr(dst, data, LogMinObjAlignmentInBytes); |
|
3787 |
data = dst; |
|
3788 |
} |
|
3789 |
if (data == src) |
|
3790 |
mov(dst, src); |
|
3791 |
} |
|
3792 |
||
3793 |
void MacroAssembler::decode_heap_oop(Register d, Register s) { |
|
3794 |
#ifdef ASSERT |
|
3795 |
verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); |
|
3796 |
#endif |
|
3797 |
if (Universe::narrow_oop_base() == NULL) { |
|
3798 |
if (Universe::narrow_oop_shift() != 0 || d != s) { |
|
3799 |
lsl(d, s, Universe::narrow_oop_shift()); |
|
3800 |
} |
|
3801 |
} else { |
|
3802 |
Label done; |
|
3803 |
if (d != s) |
|
3804 |
mov(d, s); |
|
3805 |
cbz(s, done); |
|
3806 |
add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes); |
|
3807 |
bind(done); |
|
3808 |
} |
|
3809 |
verify_oop(d, "broken oop in decode_heap_oop"); |
|
3810 |
} |
|
3811 |
||
3812 |
void MacroAssembler::decode_heap_oop_not_null(Register r) { |
|
3813 |
assert (UseCompressedOops, "should only be used for compressed headers"); |
|
3814 |
assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
3815 |
// Cannot assert, unverified entry point counts instructions (see .ad file) |
|
3816 |
// vtableStubs also counts instructions in pd_code_size_limit. |
|
3817 |
// Also do not verify_oop as this is called by verify_oop. |
|
3818 |
if (Universe::narrow_oop_shift() != 0) { |
|
3819 |
assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
3820 |
if (Universe::narrow_oop_base() != NULL) { |
|
3821 |
add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes); |
|
3822 |
} else { |
|
3823 |
add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes); |
|
3824 |
} |
|
3825 |
} else { |
|
3826 |
assert (Universe::narrow_oop_base() == NULL, "sanity"); |
|
3827 |
} |
|
3828 |
} |
|
3829 |
||
3830 |
void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { |
|
3831 |
assert (UseCompressedOops, "should only be used for compressed headers"); |
|
3832 |
assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
3833 |
// Cannot assert, unverified entry point counts instructions (see .ad file) |
|
3834 |
// vtableStubs also counts instructions in pd_code_size_limit. |
|
3835 |
// Also do not verify_oop as this is called by verify_oop. |
|
3836 |
if (Universe::narrow_oop_shift() != 0) { |
|
3837 |
assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
3838 |
if (Universe::narrow_oop_base() != NULL) { |
|
3839 |
add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes); |
|
3840 |
} else { |
|
3841 |
add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes); |
|
3842 |
} |
|
3843 |
} else { |
|
3844 |
assert (Universe::narrow_oop_base() == NULL, "sanity"); |
|
3845 |
if (dst != src) { |
|
3846 |
mov(dst, src); |
|
3847 |
} |
|
3848 |
} |
|
3849 |
} |
|
3850 |
||
3851 |
void MacroAssembler::encode_klass_not_null(Register dst, Register src) { |
|
3852 |
if (Universe::narrow_klass_base() == NULL) { |
|
3853 |
if (Universe::narrow_klass_shift() != 0) { |
|
3854 |
assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); |
|
3855 |
lsr(dst, src, LogKlassAlignmentInBytes); |
|
3856 |
} else { |
|
3857 |
if (dst != src) mov(dst, src); |
|
3858 |
} |
|
3859 |
return; |
|
3860 |
} |
|
3861 |
||
3862 |
if (use_XOR_for_compressed_class_base) { |
|
3863 |
if (Universe::narrow_klass_shift() != 0) { |
|
3864 |
eor(dst, src, (uint64_t)Universe::narrow_klass_base()); |
|
3865 |
lsr(dst, dst, LogKlassAlignmentInBytes); |
|
3866 |
} else { |
|
3867 |
eor(dst, src, (uint64_t)Universe::narrow_klass_base()); |
|
3868 |
} |
|
3869 |
return; |
|
3870 |
} |
|
3871 |
||
3872 |
if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0 |
|
3873 |
&& Universe::narrow_klass_shift() == 0) { |
|
3874 |
movw(dst, src); |
|
3875 |
return; |
|
3876 |
} |
|
3877 |
||
3878 |
#ifdef ASSERT |
|
3879 |
verify_heapbase("MacroAssembler::encode_klass_not_null2: heap base corrupted?"); |
|
3880 |
#endif |
|
3881 |
||
3882 |
Register rbase = dst; |
|
3883 |
if (dst == src) rbase = rheapbase; |
|
3884 |
mov(rbase, (uint64_t)Universe::narrow_klass_base()); |
|
3885 |
sub(dst, src, rbase); |
|
3886 |
if (Universe::narrow_klass_shift() != 0) { |
|
3887 |
assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); |
|
3888 |
lsr(dst, dst, LogKlassAlignmentInBytes); |
|
3889 |
} |
|
3890 |
if (dst == src) reinit_heapbase(); |
|
3891 |
} |
|
3892 |
||
3893 |
void MacroAssembler::encode_klass_not_null(Register r) { |
|
3894 |
encode_klass_not_null(r, r); |
|
3895 |
} |
|
3896 |
||
3897 |
void MacroAssembler::decode_klass_not_null(Register dst, Register src) { |
|
3898 |
Register rbase = dst; |
|
3899 |
assert (UseCompressedClassPointers, "should only be used for compressed headers"); |
|
3900 |
||
3901 |
if (Universe::narrow_klass_base() == NULL) { |
|
3902 |
if (Universe::narrow_klass_shift() != 0) { |
|
3903 |
assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); |
|
3904 |
lsl(dst, src, LogKlassAlignmentInBytes); |
|
3905 |
} else { |
|
3906 |
if (dst != src) mov(dst, src); |
|
3907 |
} |
|
3908 |
return; |
|
3909 |
} |
|
3910 |
||
3911 |
if (use_XOR_for_compressed_class_base) { |
|
3912 |
if (Universe::narrow_klass_shift() != 0) { |
|
3913 |
lsl(dst, src, LogKlassAlignmentInBytes); |
|
3914 |
eor(dst, dst, (uint64_t)Universe::narrow_klass_base()); |
|
3915 |
} else { |
|
3916 |
eor(dst, src, (uint64_t)Universe::narrow_klass_base()); |
|
3917 |
} |
|
3918 |
return; |
|
3919 |
} |
|
3920 |
||
3921 |
if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0 |
|
3922 |
&& Universe::narrow_klass_shift() == 0) { |
|
3923 |
if (dst != src) |
|
3924 |
movw(dst, src); |
|
3925 |
movk(dst, (uint64_t)Universe::narrow_klass_base() >> 32, 32); |
|
3926 |
return; |
|
3927 |
} |
|
3928 |
||
3929 |
// Cannot assert, unverified entry point counts instructions (see .ad file) |
|
3930 |
// vtableStubs also counts instructions in pd_code_size_limit. |
|
3931 |
// Also do not verify_oop as this is called by verify_oop. |
|
3932 |
if (dst == src) rbase = rheapbase; |
|
3933 |
mov(rbase, (uint64_t)Universe::narrow_klass_base()); |
|
3934 |
if (Universe::narrow_klass_shift() != 0) { |
|
3935 |
assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); |
|
3936 |
add(dst, rbase, src, Assembler::LSL, LogKlassAlignmentInBytes); |
|
3937 |
} else { |
|
3938 |
add(dst, rbase, src); |
|
3939 |
} |
|
3940 |
if (dst == src) reinit_heapbase(); |
|
3941 |
} |
|
3942 |
||
3943 |
void MacroAssembler::decode_klass_not_null(Register r) { |
|
3944 |
decode_klass_not_null(r, r); |
|
3945 |
} |
|
3946 |
||
3947 |
void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { |
|
48419 | 3948 |
#ifdef ASSERT |
3949 |
{ |
|
3950 |
ThreadInVMfromUnknown tiv; |
|
3951 |
assert (UseCompressedOops, "should only be used for compressed oops"); |
|
3952 |
assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
3953 |
assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
3954 |
assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop"); |
|
3955 |
} |
|
3956 |
#endif |
|
29183 | 3957 |
int oop_index = oop_recorder()->find_index(obj); |
3958 |
InstructionMark im(this); |
|
3959 |
RelocationHolder rspec = oop_Relocation::spec(oop_index); |
|
3960 |
code_section()->relocate(inst_mark(), rspec); |
|
3961 |
movz(dst, 0xDEAD, 16); |
|
3962 |
movk(dst, 0xBEEF); |
|
3963 |
} |
|
3964 |
||
3965 |
void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { |
|
3966 |
assert (UseCompressedClassPointers, "should only be used for compressed headers"); |
|
3967 |
assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
3968 |
int index = oop_recorder()->find_index(k); |
|
3969 |
assert(! Universe::heap()->is_in_reserved(k), "should not be an oop"); |
|
3970 |
||
3971 |
InstructionMark im(this); |
|
3972 |
RelocationHolder rspec = metadata_Relocation::spec(index); |
|
3973 |
code_section()->relocate(inst_mark(), rspec); |
|
3974 |
narrowKlass nk = Klass::encode_klass(k); |
|
3975 |
movz(dst, (nk >> 16), 16); |
|
3976 |
movk(dst, nk & 0xffff); |
|
3977 |
} |
|
3978 |
||
50110
3d98842c8677
8202714: Create a MacroAssembler::access_load/store_at wrapper for AArch64
rkennke
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diff
changeset
|
3979 |
void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, |
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diff
changeset
|
3980 |
Register dst, Address src, |
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8202714: Create a MacroAssembler::access_load/store_at wrapper for AArch64
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diff
changeset
|
3981 |
Register tmp1, Register thread_tmp) { |
3d98842c8677
8202714: Create a MacroAssembler::access_load/store_at wrapper for AArch64
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diff
changeset
|
3982 |
BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler(); |
50446
39ca7558bc43
8203353: Fixup inferred decorators in the interpreter
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diff
changeset
|
3983 |
decorators = AccessInternal::decorator_fixup(decorators); |
50110
3d98842c8677
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diff
changeset
|
3984 |
bool as_raw = (decorators & AS_RAW) != 0; |
3d98842c8677
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diff
changeset
|
3985 |
if (as_raw) { |
3d98842c8677
8202714: Create a MacroAssembler::access_load/store_at wrapper for AArch64
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diff
changeset
|
3986 |
bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp); |
29183 | 3987 |
} else { |
50110
3d98842c8677
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diff
changeset
|
3988 |
bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp); |
29183 | 3989 |
} |
3990 |
} |
|
3991 |
||
50110
3d98842c8677
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diff
changeset
|
3992 |
void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, |
3d98842c8677
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diff
changeset
|
3993 |
Address dst, Register src, |
3d98842c8677
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parents:
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diff
changeset
|
3994 |
Register tmp1, Register thread_tmp) { |
3d98842c8677
8202714: Create a MacroAssembler::access_load/store_at wrapper for AArch64
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parents:
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diff
changeset
|
3995 |
BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler(); |
50446
39ca7558bc43
8203353: Fixup inferred decorators in the interpreter
eosterlund
parents:
50270
diff
changeset
|
3996 |
decorators = AccessInternal::decorator_fixup(decorators); |
50110
3d98842c8677
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rkennke
parents:
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diff
changeset
|
3997 |
bool as_raw = (decorators & AS_RAW) != 0; |
3d98842c8677
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parents:
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diff
changeset
|
3998 |
if (as_raw) { |
3d98842c8677
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parents:
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diff
changeset
|
3999 |
bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, thread_tmp); |
29183 | 4000 |
} else { |
50110
3d98842c8677
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diff
changeset
|
4001 |
bs->store_at(this, decorators, type, dst, src, tmp1, thread_tmp); |
29183 | 4002 |
} |
4003 |
} |
|
4004 |
||
50110
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diff
changeset
|
4005 |
void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1, |
3d98842c8677
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parents:
49982
diff
changeset
|
4006 |
Register thread_tmp, DecoratorSet decorators) { |
3d98842c8677
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parents:
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diff
changeset
|
4007 |
access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp); |
3d98842c8677
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diff
changeset
|
4008 |
} |
3d98842c8677
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diff
changeset
|
4009 |
|
3d98842c8677
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rkennke
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diff
changeset
|
4010 |
void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1, |
3d98842c8677
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diff
changeset
|
4011 |
Register thread_tmp, DecoratorSet decorators) { |
3d98842c8677
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diff
changeset
|
4012 |
access_load_at(T_OBJECT, IN_HEAP | OOP_NOT_NULL | decorators, dst, src, tmp1, thread_tmp); |
3d98842c8677
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changeset
|
4013 |
} |
3d98842c8677
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diff
changeset
|
4014 |
|
3d98842c8677
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diff
changeset
|
4015 |
void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1, |
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changeset
|
4016 |
Register thread_tmp, DecoratorSet decorators) { |
3d98842c8677
8202714: Create a MacroAssembler::access_load/store_at wrapper for AArch64
rkennke
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diff
changeset
|
4017 |
access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp); |
29183 | 4018 |
} |
4019 |
||
4020 |
// Used for storing NULLs. |
|
4021 |
void MacroAssembler::store_heap_oop_null(Address dst) { |
|
50110
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changeset
|
4022 |
access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg); |
29183 | 4023 |
} |
4024 |
||
4025 |
Address MacroAssembler::allocate_metadata_address(Metadata* obj) { |
|
4026 |
assert(oop_recorder() != NULL, "this assembler needs a Recorder"); |
|
4027 |
int index = oop_recorder()->allocate_metadata_index(obj); |
|
4028 |
RelocationHolder rspec = metadata_Relocation::spec(index); |
|
4029 |
return Address((address)obj, rspec); |
|
4030 |
} |
|
4031 |
||
4032 |
// Move an oop into a register. immediate is true if we want |
|
4033 |
// immediate instrcutions, i.e. we are not going to patch this |
|
4034 |
// instruction while the code is being executed by another thread. In |
|
4035 |
// that case we can use move immediates rather than the constant pool. |
|
4036 |
void MacroAssembler::movoop(Register dst, jobject obj, bool immediate) { |
|
4037 |
int oop_index; |
|
4038 |
if (obj == NULL) { |
|
4039 |
oop_index = oop_recorder()->allocate_oop_index(obj); |
|
4040 |
} else { |
|
48419 | 4041 |
#ifdef ASSERT |
4042 |
{ |
|
4043 |
ThreadInVMfromUnknown tiv; |
|
4044 |
assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop"); |
|
4045 |
} |
|
4046 |
#endif |
|
29183 | 4047 |
oop_index = oop_recorder()->find_index(obj); |
4048 |
} |
|
4049 |
RelocationHolder rspec = oop_Relocation::spec(oop_index); |
|
4050 |
if (! immediate) { |
|
4051 |
address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address |
|
4052 |
ldr_constant(dst, Address(dummy, rspec)); |
|
4053 |
} else |
|
4054 |
mov(dst, Address((address)obj, rspec)); |
|
4055 |
} |
|
4056 |
||
4057 |
// Move a metadata address into a register. |
|
4058 |
void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { |
|
4059 |
int oop_index; |
|
4060 |
if (obj == NULL) { |
|
4061 |
oop_index = oop_recorder()->allocate_metadata_index(obj); |
|
4062 |
} else { |
|
4063 |
oop_index = oop_recorder()->find_index(obj); |
|
4064 |
} |
|
4065 |
RelocationHolder rspec = metadata_Relocation::spec(oop_index); |
|
4066 |
mov(dst, Address((address)obj, rspec)); |
|
4067 |
} |
|
4068 |
||
4069 |
Address MacroAssembler::constant_oop_address(jobject obj) { |
|
48419 | 4070 |
#ifdef ASSERT |
4071 |
{ |
|
4072 |
ThreadInVMfromUnknown tiv; |
|
4073 |
assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
4074 |
assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "not an oop"); |
|
4075 |
} |
|
4076 |
#endif |
|
29183 | 4077 |
int oop_index = oop_recorder()->find_index(obj); |
4078 |
return Address((address)obj, oop_Relocation::spec(oop_index)); |
|
4079 |
} |
|
4080 |
||
4081 |
// Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. |
|
4082 |
void MacroAssembler::tlab_allocate(Register obj, |
|
4083 |
Register var_size_in_bytes, |
|
4084 |
int con_size_in_bytes, |
|
4085 |
Register t1, |
|
4086 |
Register t2, |
|
4087 |
Label& slow_case) { |
|
4088 |
assert_different_registers(obj, t2); |
|
4089 |
assert_different_registers(obj, var_size_in_bytes); |
|
4090 |
Register end = t2; |
|
4091 |
||
4092 |
// verify_tlab(); |
|
4093 |
||
4094 |
ldr(obj, Address(rthread, JavaThread::tlab_top_offset())); |
|
4095 |
if (var_size_in_bytes == noreg) { |
|
4096 |
lea(end, Address(obj, con_size_in_bytes)); |
|
4097 |
} else { |
|
4098 |
lea(end, Address(obj, var_size_in_bytes)); |
|
4099 |
} |
|
4100 |
ldr(rscratch1, Address(rthread, JavaThread::tlab_end_offset())); |
|
4101 |
cmp(end, rscratch1); |
|
4102 |
br(Assembler::HI, slow_case); |
|
4103 |
||
4104 |
// update the tlab top pointer |
|
4105 |
str(end, Address(rthread, JavaThread::tlab_top_offset())); |
|
4106 |
||
4107 |
// recover var_size_in_bytes if necessary |
|
4108 |
if (var_size_in_bytes == end) { |
|
4109 |
sub(var_size_in_bytes, var_size_in_bytes, obj); |
|
4110 |
} |
|
4111 |
// verify_tlab(); |
|
4112 |
} |
|
4113 |
||
42871
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8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
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parents:
42605
diff
changeset
|
4114 |
// Zero words; len is in bytes |
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42605
diff
changeset
|
4115 |
// Destroys all registers except addr |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
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diff
changeset
|
4116 |
// len must be a nonzero multiple of wordSize |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
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parents:
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diff
changeset
|
4117 |
void MacroAssembler::zero_memory(Register addr, Register len, Register t1) { |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
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parents:
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diff
changeset
|
4118 |
assert_different_registers(addr, len, t1, rscratch1, rscratch2); |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
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parents:
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diff
changeset
|
4119 |
|
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
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diff
changeset
|
4120 |
#ifdef ASSERT |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
42605
diff
changeset
|
4121 |
{ Label L; |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
42605
diff
changeset
|
4122 |
tst(len, BytesPerWord - 1); |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
42605
diff
changeset
|
4123 |
br(Assembler::EQ, L); |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
42605
diff
changeset
|
4124 |
stop("len is not a multiple of BytesPerWord"); |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
42605
diff
changeset
|
4125 |
bind(L); |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
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diff
changeset
|
4126 |
} |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
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diff
changeset
|
4127 |
#endif |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
42605
diff
changeset
|
4128 |
|
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
42605
diff
changeset
|
4129 |
#ifndef PRODUCT |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
42605
diff
changeset
|
4130 |
block_comment("zero memory"); |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
42605
diff
changeset
|
4131 |
#endif |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
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diff
changeset
|
4132 |
|
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
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diff
changeset
|
4133 |
Label loop; |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
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diff
changeset
|
4134 |
Label entry; |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
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diff
changeset
|
4135 |
|
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
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diff
changeset
|
4136 |
// Algorithm: |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
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diff
changeset
|
4137 |
// |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
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diff
changeset
|
4138 |
// scratch1 = cnt & 7; |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
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diff
changeset
|
4139 |
// cnt -= scratch1; |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
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diff
changeset
|
4140 |
// p += scratch1; |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
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diff
changeset
|
4141 |
// switch (scratch1) { |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
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diff
changeset
|
4142 |
// do { |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
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diff
changeset
|
4143 |
// cnt -= 8; |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
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diff
changeset
|
4144 |
// p[-8] = 0; |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
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parents:
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diff
changeset
|
4145 |
// case 7: |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
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diff
changeset
|
4146 |
// p[-7] = 0; |
c89e1f0a084e
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aph
parents:
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diff
changeset
|
4147 |
// case 6: |
c89e1f0a084e
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parents:
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diff
changeset
|
4148 |
// p[-6] = 0; |
c89e1f0a084e
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parents:
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diff
changeset
|
4149 |
// // ... |
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aph
parents:
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diff
changeset
|
4150 |
// case 1: |
c89e1f0a084e
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parents:
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diff
changeset
|
4151 |
// p[-1] = 0; |
c89e1f0a084e
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parents:
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diff
changeset
|
4152 |
// case 0: |
c89e1f0a084e
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parents:
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diff
changeset
|
4153 |
// p += 8; |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
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parents:
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diff
changeset
|
4154 |
// } while (cnt); |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
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parents:
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diff
changeset
|
4155 |
// } |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
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diff
changeset
|
4156 |
|
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
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diff
changeset
|
4157 |
const int unroll = 8; // Number of str(zr) instructions we'll unroll |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
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diff
changeset
|
4158 |
|
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
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diff
changeset
|
4159 |
lsr(len, len, LogBytesPerWord); |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
42605
diff
changeset
|
4160 |
andr(rscratch1, len, unroll - 1); // tmp1 = cnt % unroll |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
42605
diff
changeset
|
4161 |
sub(len, len, rscratch1); // cnt -= unroll |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
42605
diff
changeset
|
4162 |
// t1 always points to the end of the region we're about to zero |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
42605
diff
changeset
|
4163 |
add(t1, addr, rscratch1, Assembler::LSL, LogBytesPerWord); |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
42605
diff
changeset
|
4164 |
adr(rscratch2, entry); |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
42605
diff
changeset
|
4165 |
sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 2); |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
42605
diff
changeset
|
4166 |
br(rscratch2); |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
42605
diff
changeset
|
4167 |
bind(loop); |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
42605
diff
changeset
|
4168 |
sub(len, len, unroll); |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
42605
diff
changeset
|
4169 |
for (int i = -unroll; i < 0; i++) |
49161
8f1bc5a0d16d
8196064: AArch64: Merging ld/st into ldp/stp in macro-assembler
zyao
parents:
49010
diff
changeset
|
4170 |
Assembler::str(zr, Address(t1, i * wordSize)); |
42871
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
42605
diff
changeset
|
4171 |
bind(entry); |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
42605
diff
changeset
|
4172 |
add(t1, t1, unroll * wordSize); |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
42605
diff
changeset
|
4173 |
cbnz(len, loop); |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
42605
diff
changeset
|
4174 |
} |
c89e1f0a084e
8169177: AArch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
aph
parents:
42605
diff
changeset
|
4175 |
|
29183 | 4176 |
// Defines obj, preserves var_size_in_bytes |
4177 |
void MacroAssembler::eden_allocate(Register obj, |
|
4178 |
Register var_size_in_bytes, |
|
4179 |
int con_size_in_bytes, |
|
4180 |
Register t1, |
|
4181 |
Label& slow_case) { |
|
4182 |
assert_different_registers(obj, var_size_in_bytes, t1); |
|
4183 |
if (!Universe::heap()->supports_inline_contig_alloc()) { |
|
4184 |
b(slow_case); |
|
4185 |
} else { |
|
4186 |
Register end = t1; |
|
4187 |
Register heap_end = rscratch2; |
|
4188 |
Label retry; |
|
4189 |
bind(retry); |
|
4190 |
{ |
|
4191 |
unsigned long offset; |
|
4192 |
adrp(rscratch1, ExternalAddress((address) Universe::heap()->end_addr()), offset); |
|
4193 |
ldr(heap_end, Address(rscratch1, offset)); |
|
4194 |
} |
|
4195 |
||
4196 |
ExternalAddress heap_top((address) Universe::heap()->top_addr()); |
|
4197 |
||
4198 |
// Get the current top of the heap |
|
4199 |
{ |
|
4200 |
unsigned long offset; |
|
4201 |
adrp(rscratch1, heap_top, offset); |
|
4202 |
// Use add() here after ARDP, rather than lea(). |
|
4203 |
// lea() does not generate anything if its offset is zero. |
|
4204 |
// However, relocs expect to find either an ADD or a load/store |
|
4205 |
// insn after an ADRP. add() always generates an ADD insn, even |
|
4206 |
// for add(Rn, Rn, 0). |
|
4207 |
add(rscratch1, rscratch1, offset); |
|
4208 |
ldaxr(obj, rscratch1); |
|
4209 |
} |
|
4210 |
||
4211 |
// Adjust it my the size of our new object |
|
4212 |
if (var_size_in_bytes == noreg) { |
|
4213 |
lea(end, Address(obj, con_size_in_bytes)); |
|
4214 |
} else { |
|
4215 |
lea(end, Address(obj, var_size_in_bytes)); |
|
4216 |
} |
|
4217 |
||
4218 |
// if end < obj then we wrapped around high memory |
|
4219 |
cmp(end, obj); |
|
4220 |
br(Assembler::LO, slow_case); |
|
4221 |
||
4222 |
cmp(end, heap_end); |
|
4223 |
br(Assembler::HI, slow_case); |
|
4224 |
||
4225 |
// If heap_top hasn't been changed by some other thread, update it. |
|
31863 | 4226 |
stlxr(rscratch2, end, rscratch1); |
4227 |
cbnzw(rscratch2, retry); |
|
29183 | 4228 |
} |
4229 |
} |
|
4230 |
||
4231 |
void MacroAssembler::verify_tlab() { |
|
4232 |
#ifdef ASSERT |
|
4233 |
if (UseTLAB && VerifyOops) { |
|
4234 |
Label next, ok; |
|
4235 |
||
4236 |
stp(rscratch2, rscratch1, Address(pre(sp, -16))); |
|
4237 |
||
4238 |
ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); |
|
4239 |
ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset()))); |
|
4240 |
cmp(rscratch2, rscratch1); |
|
4241 |
br(Assembler::HS, next); |
|
4242 |
STOP("assert(top >= start)"); |
|
4243 |
should_not_reach_here(); |
|
4244 |
||
4245 |
bind(next); |
|
4246 |
ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset()))); |
|
4247 |
ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); |
|
4248 |
cmp(rscratch2, rscratch1); |
|
4249 |
br(Assembler::HS, ok); |
|
4250 |
STOP("assert(top <= end)"); |
|
4251 |
should_not_reach_here(); |
|
4252 |
||
4253 |
bind(ok); |
|
4254 |
ldp(rscratch2, rscratch1, Address(post(sp, 16))); |
|
4255 |
} |
|
4256 |
#endif |
|
4257 |
} |
|
4258 |
||
4259 |
// Writes to stack successive pages until offset reached to check for |
|
4260 |
// stack overflow + shadow pages. This clobbers tmp. |
|
4261 |
void MacroAssembler::bang_stack_size(Register size, Register tmp) { |
|
4262 |
assert_different_registers(tmp, size, rscratch1); |
|
4263 |
mov(tmp, sp); |
|
4264 |
// Bang stack for total size given plus shadow page size. |
|
4265 |
// Bang one page at a time because large size can bang beyond yellow and |
|
4266 |
// red zones. |
|
4267 |
Label loop; |
|
4268 |
mov(rscratch1, os::vm_page_size()); |
|
4269 |
bind(loop); |
|
4270 |
lea(tmp, Address(tmp, -os::vm_page_size())); |
|
4271 |
subsw(size, size, rscratch1); |
|
4272 |
str(size, Address(tmp)); |
|
4273 |
br(Assembler::GT, loop); |
|
4274 |
||
4275 |
// Bang down shadow pages too. |
|
4276 |
// At this point, (tmp-0) is the last address touched, so don't |
|
4277 |
// touch it again. (It was touched as (tmp-pagesize) but then tmp |
|
4278 |
// was post-decremented.) Skip this address by starting at i=1, and |
|
4279 |
// touch a few more pages below. N.B. It is important to touch all |
|
4280 |
// the way down to and including i=StackShadowPages. |
|
35553
fa41da206b95
8146886: aarch64: fails to build following 8136525 and 8139864
enevill
parents:
35232
diff
changeset
|
4281 |
for (int i = 0; i < (int)(JavaThread::stack_shadow_zone_size() / os::vm_page_size()) - 1; i++) { |
29183 | 4282 |
// this could be any sized move but this is can be a debugging crumb |
4283 |
// so the bigger the better. |
|
4284 |
lea(tmp, Address(tmp, -os::vm_page_size())); |
|
4285 |
str(size, Address(tmp)); |
|
4286 |
} |
|
4287 |
} |
|
4288 |
||
4289 |
||
48127
efc459cf351e
8189596: AArch64: implementation for Thread-local handshakes
aph
parents:
47915
diff
changeset
|
4290 |
// Move the address of the polling page into dest. |
efc459cf351e
8189596: AArch64: implementation for Thread-local handshakes
aph
parents:
47915
diff
changeset
|
4291 |
void MacroAssembler::get_polling_page(Register dest, address page, relocInfo::relocType rtype) { |
efc459cf351e
8189596: AArch64: implementation for Thread-local handshakes
aph
parents:
47915
diff
changeset
|
4292 |
if (SafepointMechanism::uses_thread_local_poll()) { |
efc459cf351e
8189596: AArch64: implementation for Thread-local handshakes
aph
parents:
47915
diff
changeset
|
4293 |
ldr(dest, Address(rthread, Thread::polling_page_offset())); |
efc459cf351e
8189596: AArch64: implementation for Thread-local handshakes
aph
parents:
47915
diff
changeset
|
4294 |
} else { |
efc459cf351e
8189596: AArch64: implementation for Thread-local handshakes
aph
parents:
47915
diff
changeset
|
4295 |
unsigned long off; |
efc459cf351e
8189596: AArch64: implementation for Thread-local handshakes
aph
parents:
47915
diff
changeset
|
4296 |
adrp(dest, Address(page, rtype), off); |
efc459cf351e
8189596: AArch64: implementation for Thread-local handshakes
aph
parents:
47915
diff
changeset
|
4297 |
assert(off == 0, "polling page must be page aligned"); |
efc459cf351e
8189596: AArch64: implementation for Thread-local handshakes
aph
parents:
47915
diff
changeset
|
4298 |
} |
efc459cf351e
8189596: AArch64: implementation for Thread-local handshakes
aph
parents:
47915
diff
changeset
|
4299 |
} |
efc459cf351e
8189596: AArch64: implementation for Thread-local handshakes
aph
parents:
47915
diff
changeset
|
4300 |
|
efc459cf351e
8189596: AArch64: implementation for Thread-local handshakes
aph
parents:
47915
diff
changeset
|
4301 |
// Move the address of the polling page into r, then read the polling |
efc459cf351e
8189596: AArch64: implementation for Thread-local handshakes
aph
parents:
47915
diff
changeset
|
4302 |
// page. |
29183 | 4303 |
address MacroAssembler::read_polling_page(Register r, address page, relocInfo::relocType rtype) { |
48127
efc459cf351e
8189596: AArch64: implementation for Thread-local handshakes
aph
parents:
47915
diff
changeset
|
4304 |
get_polling_page(r, page, rtype); |
efc459cf351e
8189596: AArch64: implementation for Thread-local handshakes
aph
parents:
47915
diff
changeset
|
4305 |
return read_polling_page(r, rtype); |
efc459cf351e
8189596: AArch64: implementation for Thread-local handshakes
aph
parents:
47915
diff
changeset
|
4306 |
} |
efc459cf351e
8189596: AArch64: implementation for Thread-local handshakes
aph
parents:
47915
diff
changeset
|
4307 |
|
efc459cf351e
8189596: AArch64: implementation for Thread-local handshakes
aph
parents:
47915
diff
changeset
|
4308 |
// Read the polling page. The address of the polling page must |
efc459cf351e
8189596: AArch64: implementation for Thread-local handshakes
aph
parents:
47915
diff
changeset
|
4309 |
// already be in r. |
29183 | 4310 |
address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) { |
4311 |
InstructionMark im(this); |
|
4312 |
code_section()->relocate(inst_mark(), rtype); |
|
4313 |
ldrw(zr, Address(r, 0)); |
|
4314 |
return inst_mark(); |
|
4315 |
} |
|
4316 |
||
4317 |
void MacroAssembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) { |
|
4318 |
relocInfo::relocType rtype = dest.rspec().reloc()->type(); |
|
34206 | 4319 |
unsigned long low_page = (unsigned long)CodeCache::low_bound() >> 12; |
4320 |
unsigned long high_page = (unsigned long)(CodeCache::high_bound()-1) >> 12; |
|
4321 |
unsigned long dest_page = (unsigned long)dest.target() >> 12; |
|
4322 |
long offset_low = dest_page - low_page; |
|
4323 |
long offset_high = dest_page - high_page; |
|
4324 |
||
35579
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
4325 |
assert(is_valid_AArch64_address(dest.target()), "bad address"); |
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
4326 |
assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address"); |
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
4327 |
|
34206 | 4328 |
InstructionMark im(this); |
4329 |
code_section()->relocate(inst_mark(), dest.rspec()); |
|
4330 |
// 8143067: Ensure that the adrp can reach the dest from anywhere within |
|
4331 |
// the code cache so that if it is relocated we know it will still reach |
|
4332 |
if (offset_high >= -(1<<20) && offset_low < (1<<20)) { |
|
4333 |
_adrp(reg1, dest.target()); |
|
29183 | 4334 |
} else { |
35840 | 4335 |
unsigned long target = (unsigned long)dest.target(); |
4336 |
unsigned long adrp_target |
|
4337 |
= (target & 0xffffffffUL) | ((unsigned long)pc() & 0xffff00000000UL); |
|
4338 |
||
4339 |
_adrp(reg1, (address)adrp_target); |
|
4340 |
movk(reg1, target >> 32, 32); |
|
29183 | 4341 |
} |
34206 | 4342 |
byte_offset = (unsigned long)dest.target() & 0xfff; |
29183 | 4343 |
} |
4344 |
||
35579
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
4345 |
void MacroAssembler::load_byte_map_base(Register reg) { |
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
4346 |
jbyte *byte_map_base = |
49754 | 4347 |
((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base(); |
35579
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
4348 |
|
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
4349 |
if (is_valid_AArch64_address((address)byte_map_base)) { |
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
4350 |
// Strictly speaking the byte_map_base isn't an address at all, |
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
4351 |
// and it might even be negative. |
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
4352 |
unsigned long offset; |
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
4353 |
adrp(reg, ExternalAddress((address)byte_map_base), offset); |
38093
5bc7b4b8a473
8155100: AArch64: Relax alignment requirement for byte_map_base
aph
parents:
38074
diff
changeset
|
4354 |
// We expect offset to be zero with most collectors. |
5bc7b4b8a473
8155100: AArch64: Relax alignment requirement for byte_map_base
aph
parents:
38074
diff
changeset
|
4355 |
if (offset != 0) { |
5bc7b4b8a473
8155100: AArch64: Relax alignment requirement for byte_map_base
aph
parents:
38074
diff
changeset
|
4356 |
add(reg, reg, offset); |
5bc7b4b8a473
8155100: AArch64: Relax alignment requirement for byte_map_base
aph
parents:
38074
diff
changeset
|
4357 |
} |
35579
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
4358 |
} else { |
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
4359 |
mov(reg, (uint64_t)byte_map_base); |
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
4360 |
} |
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
4361 |
} |
d21d5a0db03f
8146709: AArch64: Incorrect use of ADRP for byte_map_base
aph
parents:
35553
diff
changeset
|
4362 |
|
29183 | 4363 |
void MacroAssembler::build_frame(int framesize) { |
30552
ff209a4a81b5
8079564: Use FP register as proper frame pointer in JIT compiled code on aarch64
enevill
parents:
30429
diff
changeset
|
4364 |
assert(framesize > 0, "framesize must be > 0"); |
ff209a4a81b5
8079564: Use FP register as proper frame pointer in JIT compiled code on aarch64
enevill
parents:
30429
diff
changeset
|
4365 |
if (framesize < ((1 << 9) + 2 * wordSize)) { |
29183 | 4366 |
sub(sp, sp, framesize); |
4367 |
stp(rfp, lr, Address(sp, framesize - 2 * wordSize)); |
|
30552
ff209a4a81b5
8079564: Use FP register as proper frame pointer in JIT compiled code on aarch64
enevill
parents:
30429
diff
changeset
|
4368 |
if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize); |
29183 | 4369 |
} else { |
4370 |
stp(rfp, lr, Address(pre(sp, -2 * wordSize))); |
|
30552
ff209a4a81b5
8079564: Use FP register as proper frame pointer in JIT compiled code on aarch64
enevill
parents:
30429
diff
changeset
|
4371 |
if (PreserveFramePointer) mov(rfp, sp); |
29183 | 4372 |
if (framesize < ((1 << 12) + 2 * wordSize)) |
4373 |
sub(sp, sp, framesize - 2 * wordSize); |
|
4374 |
else { |
|
4375 |
mov(rscratch1, framesize - 2 * wordSize); |
|
4376 |
sub(sp, sp, rscratch1); |
|
4377 |
} |
|
4378 |
} |
|
4379 |
} |
|
4380 |
||
4381 |
void MacroAssembler::remove_frame(int framesize) { |
|
30552
ff209a4a81b5
8079564: Use FP register as proper frame pointer in JIT compiled code on aarch64
enevill
parents:
30429
diff
changeset
|
4382 |
assert(framesize > 0, "framesize must be > 0"); |
ff209a4a81b5
8079564: Use FP register as proper frame pointer in JIT compiled code on aarch64
enevill
parents:
30429
diff
changeset
|
4383 |
if (framesize < ((1 << 9) + 2 * wordSize)) { |
29183 | 4384 |
ldp(rfp, lr, Address(sp, framesize - 2 * wordSize)); |
4385 |
add(sp, sp, framesize); |
|
4386 |
} else { |
|
4387 |
if (framesize < ((1 << 12) + 2 * wordSize)) |
|
4388 |
add(sp, sp, framesize - 2 * wordSize); |
|
4389 |
else { |
|
4390 |
mov(rscratch1, framesize - 2 * wordSize); |
|
4391 |
add(sp, sp, rscratch1); |
|
4392 |
} |
|
4393 |
ldp(rfp, lr, Address(post(sp, 2 * wordSize))); |
|
4394 |
} |
|
4395 |
} |
|
4396 |
||
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
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diff
changeset
|
4397 |
typedef void (MacroAssembler::* chr_insn)(Register Rt, const Address &adr); |
29183 | 4398 |
|
4399 |
// Search for str1 in str2 and return index or -1 |
|
4400 |
void MacroAssembler::string_indexof(Register str2, Register str1, |
|
4401 |
Register cnt2, Register cnt1, |
|
4402 |
Register tmp1, Register tmp2, |
|
4403 |
Register tmp3, Register tmp4, |
|
38713
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38241
diff
changeset
|
4404 |
int icnt1, Register result, int ae) { |
29183 | 4405 |
Label BM, LINEARSEARCH, DONE, NOMATCH, MATCH; |
4406 |
||
4407 |
Register ch1 = rscratch1; |
|
4408 |
Register ch2 = rscratch2; |
|
4409 |
Register cnt1tmp = tmp1; |
|
4410 |
Register cnt2tmp = tmp2; |
|
4411 |
Register cnt1_neg = cnt1; |
|
4412 |
Register cnt2_neg = cnt2; |
|
4413 |
Register result_tmp = tmp4; |
|
4414 |
||
38713
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8157834: aarch64: Hello World crashes with fastdebug build
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diff
changeset
|
4415 |
bool isL = ae == StrIntrinsicNode::LL; |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
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diff
changeset
|
4416 |
|
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
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diff
changeset
|
4417 |
bool str1_isL = ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL; |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
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parents:
38241
diff
changeset
|
4418 |
bool str2_isL = ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::LU; |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
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diff
changeset
|
4419 |
int str1_chr_shift = str1_isL ? 0:1; |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
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diff
changeset
|
4420 |
int str2_chr_shift = str2_isL ? 0:1; |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
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diff
changeset
|
4421 |
int str1_chr_size = str1_isL ? 1:2; |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
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diff
changeset
|
4422 |
int str2_chr_size = str2_isL ? 1:2; |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
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diff
changeset
|
4423 |
chr_insn str1_load_1chr = str1_isL ? (chr_insn)&MacroAssembler::ldrb : |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
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diff
changeset
|
4424 |
(chr_insn)&MacroAssembler::ldrh; |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4425 |
chr_insn str2_load_1chr = str2_isL ? (chr_insn)&MacroAssembler::ldrb : |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
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diff
changeset
|
4426 |
(chr_insn)&MacroAssembler::ldrh; |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
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diff
changeset
|
4427 |
chr_insn load_2chr = isL ? (chr_insn)&MacroAssembler::ldrh : (chr_insn)&MacroAssembler::ldrw; |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
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diff
changeset
|
4428 |
chr_insn load_4chr = isL ? (chr_insn)&MacroAssembler::ldrw : (chr_insn)&MacroAssembler::ldr; |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
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diff
changeset
|
4429 |
|
29183 | 4430 |
// Note, inline_string_indexOf() generates checks: |
4431 |
// if (substr.count > string.count) return -1; |
|
4432 |
// if (substr.count == 0) return 0; |
|
4433 |
||
4434 |
// We have two strings, a source string in str2, cnt2 and a pattern string |
|
4435 |
// in str1, cnt1. Find the 1st occurence of pattern in source or return -1. |
|
4436 |
||
4437 |
// For larger pattern and source we use a simplified Boyer Moore algorithm. |
|
4438 |
// With a small pattern and source we use linear scan. |
|
4439 |
||
4440 |
if (icnt1 == -1) { |
|
4441 |
cmp(cnt1, 256); // Use Linear Scan if cnt1 < 8 || cnt1 >= 256 |
|
4442 |
ccmp(cnt1, 8, 0b0000, LO); // Can't handle skip >= 256 because we use |
|
4443 |
br(LO, LINEARSEARCH); // a byte array. |
|
4444 |
cmp(cnt1, cnt2, LSR, 2); // Source must be 4 * pattern for BM |
|
4445 |
br(HS, LINEARSEARCH); |
|
4446 |
} |
|
4447 |
||
4448 |
// The Boyer Moore alogorithm is based on the description here:- |
|
4449 |
// |
|
4450 |
// http://en.wikipedia.org/wiki/Boyer%E2%80%93Moore_string_search_algorithm |
|
4451 |
// |
|
4452 |
// This describes and algorithm with 2 shift rules. The 'Bad Character' rule |
|
4453 |
// and the 'Good Suffix' rule. |
|
4454 |
// |
|
4455 |
// These rules are essentially heuristics for how far we can shift the |
|
4456 |
// pattern along the search string. |
|
4457 |
// |
|
4458 |
// The implementation here uses the 'Bad Character' rule only because of the |
|
4459 |
// complexity of initialisation for the 'Good Suffix' rule. |
|
4460 |
// |
|
4461 |
// This is also known as the Boyer-Moore-Horspool algorithm:- |
|
4462 |
// |
|
4463 |
// http://en.wikipedia.org/wiki/Boyer-Moore-Horspool_algorithm |
|
4464 |
// |
|
4465 |
// #define ASIZE 128 |
|
4466 |
// |
|
4467 |
// int bm(unsigned char *x, int m, unsigned char *y, int n) { |
|
4468 |
// int i, j; |
|
4469 |
// unsigned c; |
|
4470 |
// unsigned char bc[ASIZE]; |
|
4471 |
// |
|
4472 |
// /* Preprocessing */ |
|
4473 |
// for (i = 0; i < ASIZE; ++i) |
|
4474 |
// bc[i] = 0; |
|
4475 |
// for (i = 0; i < m - 1; ) { |
|
4476 |
// c = x[i]; |
|
4477 |
// ++i; |
|
4478 |
// if (c < ASIZE) bc[c] = i; |
|
4479 |
// } |
|
4480 |
// |
|
4481 |
// /* Searching */ |
|
4482 |
// j = 0; |
|
4483 |
// while (j <= n - m) { |
|
4484 |
// c = y[i+j]; |
|
4485 |
// if (x[m-1] == c) |
|
4486 |
// for (i = m - 2; i >= 0 && x[i] == y[i + j]; --i); |
|
4487 |
// if (i < 0) return j; |
|
4488 |
// if (c < ASIZE) |
|
4489 |
// j = j - bc[y[j+m-1]] + m; |
|
4490 |
// else |
|
4491 |
// j += 1; // Advance by 1 only if char >= ASIZE |
|
4492 |
// } |
|
4493 |
// } |
|
4494 |
||
4495 |
if (icnt1 == -1) { |
|
4496 |
BIND(BM); |
|
4497 |
||
4498 |
Label ZLOOP, BCLOOP, BCSKIP, BMLOOPSTR2, BMLOOPSTR1, BMSKIP; |
|
4499 |
Label BMADV, BMMATCH, BMCHECKEND; |
|
4500 |
||
4501 |
Register cnt1end = tmp2; |
|
4502 |
Register str2end = cnt2; |
|
4503 |
Register skipch = tmp2; |
|
4504 |
||
4505 |
// Restrict ASIZE to 128 to reduce stack space/initialisation. |
|
4506 |
// The presence of chars >= ASIZE in the target string does not affect |
|
4507 |
// performance, but we must be careful not to initialise them in the stack |
|
4508 |
// array. |
|
4509 |
// The presence of chars >= ASIZE in the source string may adversely affect |
|
4510 |
// performance since we can only advance by one when we encounter one. |
|
4511 |
||
4512 |
stp(zr, zr, pre(sp, -128)); |
|
4513 |
for (int i = 1; i < 8; i++) |
|
4514 |
stp(zr, zr, Address(sp, i*16)); |
|
4515 |
||
4516 |
mov(cnt1tmp, 0); |
|
4517 |
sub(cnt1end, cnt1, 1); |
|
4518 |
BIND(BCLOOP); |
|
38713
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8157834: aarch64: Hello World crashes with fastdebug build
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parents:
38241
diff
changeset
|
4519 |
(this->*str1_load_1chr)(ch1, Address(str1, cnt1tmp, Address::lsl(str1_chr_shift))); |
29183 | 4520 |
cmp(ch1, 128); |
4521 |
add(cnt1tmp, cnt1tmp, 1); |
|
4522 |
br(HS, BCSKIP); |
|
4523 |
strb(cnt1tmp, Address(sp, ch1)); |
|
4524 |
BIND(BCSKIP); |
|
4525 |
cmp(cnt1tmp, cnt1end); |
|
4526 |
br(LT, BCLOOP); |
|
4527 |
||
4528 |
mov(result_tmp, str2); |
|
4529 |
||
4530 |
sub(cnt2, cnt2, cnt1); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
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38241
diff
changeset
|
4531 |
add(str2end, str2, cnt2, LSL, str2_chr_shift); |
29183 | 4532 |
BIND(BMLOOPSTR2); |
4533 |
sub(cnt1tmp, cnt1, 1); |
|
38713
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8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4534 |
(this->*str1_load_1chr)(ch1, Address(str1, cnt1tmp, Address::lsl(str1_chr_shift))); |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
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diff
changeset
|
4535 |
(this->*str2_load_1chr)(skipch, Address(str2, cnt1tmp, Address::lsl(str2_chr_shift))); |
29183 | 4536 |
cmp(ch1, skipch); |
4537 |
br(NE, BMSKIP); |
|
4538 |
subs(cnt1tmp, cnt1tmp, 1); |
|
4539 |
br(LT, BMMATCH); |
|
4540 |
BIND(BMLOOPSTR1); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4541 |
(this->*str1_load_1chr)(ch1, Address(str1, cnt1tmp, Address::lsl(str1_chr_shift))); |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
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38241
diff
changeset
|
4542 |
(this->*str2_load_1chr)(ch2, Address(str2, cnt1tmp, Address::lsl(str2_chr_shift))); |
29183 | 4543 |
cmp(ch1, ch2); |
4544 |
br(NE, BMSKIP); |
|
4545 |
subs(cnt1tmp, cnt1tmp, 1); |
|
4546 |
br(GE, BMLOOPSTR1); |
|
4547 |
BIND(BMMATCH); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4548 |
sub(result, str2, result_tmp); |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4549 |
if (!str2_isL) lsr(result, result, 1); |
29183 | 4550 |
add(sp, sp, 128); |
4551 |
b(DONE); |
|
4552 |
BIND(BMADV); |
|
38713
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8157834: aarch64: Hello World crashes with fastdebug build
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parents:
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diff
changeset
|
4553 |
add(str2, str2, str2_chr_size); |
29183 | 4554 |
b(BMCHECKEND); |
4555 |
BIND(BMSKIP); |
|
4556 |
cmp(skipch, 128); |
|
4557 |
br(HS, BMADV); |
|
4558 |
ldrb(ch2, Address(sp, skipch)); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4559 |
add(str2, str2, cnt1, LSL, str2_chr_shift); |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
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diff
changeset
|
4560 |
sub(str2, str2, ch2, LSL, str2_chr_shift); |
29183 | 4561 |
BIND(BMCHECKEND); |
4562 |
cmp(str2, str2end); |
|
4563 |
br(LE, BMLOOPSTR2); |
|
4564 |
add(sp, sp, 128); |
|
4565 |
b(NOMATCH); |
|
4566 |
} |
|
4567 |
||
4568 |
BIND(LINEARSEARCH); |
|
4569 |
{ |
|
4570 |
Label DO1, DO2, DO3; |
|
4571 |
||
4572 |
Register str2tmp = tmp2; |
|
4573 |
Register first = tmp3; |
|
4574 |
||
4575 |
if (icnt1 == -1) |
|
4576 |
{ |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4577 |
Label DOSHORT, FIRST_LOOP, STR2_NEXT, STR1_LOOP, STR1_NEXT; |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4578 |
|
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4579 |
cmp(cnt1, str1_isL == str2_isL ? 4 : 2); |
29183 | 4580 |
br(LT, DOSHORT); |
4581 |
||
4582 |
sub(cnt2, cnt2, cnt1); |
|
4583 |
mov(result_tmp, cnt2); |
|
4584 |
||
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4585 |
lea(str1, Address(str1, cnt1, Address::lsl(str1_chr_shift))); |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4586 |
lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift))); |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4587 |
sub(cnt1_neg, zr, cnt1, LSL, str1_chr_shift); |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4588 |
sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift); |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4589 |
(this->*str1_load_1chr)(first, Address(str1, cnt1_neg)); |
29183 | 4590 |
|
4591 |
BIND(FIRST_LOOP); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4592 |
(this->*str2_load_1chr)(ch2, Address(str2, cnt2_neg)); |
29183 | 4593 |
cmp(first, ch2); |
4594 |
br(EQ, STR1_LOOP); |
|
4595 |
BIND(STR2_NEXT); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4596 |
adds(cnt2_neg, cnt2_neg, str2_chr_size); |
29183 | 4597 |
br(LE, FIRST_LOOP); |
4598 |
b(NOMATCH); |
|
4599 |
||
4600 |
BIND(STR1_LOOP); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4601 |
adds(cnt1tmp, cnt1_neg, str1_chr_size); |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4602 |
add(cnt2tmp, cnt2_neg, str2_chr_size); |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4603 |
br(GE, MATCH); |
29183 | 4604 |
|
4605 |
BIND(STR1_NEXT); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4606 |
(this->*str1_load_1chr)(ch1, Address(str1, cnt1tmp)); |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4607 |
(this->*str2_load_1chr)(ch2, Address(str2, cnt2tmp)); |
29183 | 4608 |
cmp(ch1, ch2); |
4609 |
br(NE, STR2_NEXT); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4610 |
adds(cnt1tmp, cnt1tmp, str1_chr_size); |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4611 |
add(cnt2tmp, cnt2tmp, str2_chr_size); |
29183 | 4612 |
br(LT, STR1_NEXT); |
4613 |
b(MATCH); |
|
4614 |
||
4615 |
BIND(DOSHORT); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4616 |
if (str1_isL == str2_isL) { |
29183 | 4617 |
cmp(cnt1, 2); |
4618 |
br(LT, DO1); |
|
4619 |
br(GT, DO3); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4620 |
} |
29183 | 4621 |
} |
4622 |
||
4623 |
if (icnt1 == 4) { |
|
4624 |
Label CH1_LOOP; |
|
4625 |
||
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4626 |
(this->*load_4chr)(ch1, str1); |
29183 | 4627 |
sub(cnt2, cnt2, 4); |
4628 |
mov(result_tmp, cnt2); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4629 |
lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift))); |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4630 |
sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift); |
29183 | 4631 |
|
4632 |
BIND(CH1_LOOP); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4633 |
(this->*load_4chr)(ch2, Address(str2, cnt2_neg)); |
29183 | 4634 |
cmp(ch1, ch2); |
4635 |
br(EQ, MATCH); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4636 |
adds(cnt2_neg, cnt2_neg, str2_chr_size); |
29183 | 4637 |
br(LE, CH1_LOOP); |
4638 |
b(NOMATCH); |
|
4639 |
} |
|
4640 |
||
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4641 |
if ((icnt1 == -1 && str1_isL == str2_isL) || icnt1 == 2) { |
29183 | 4642 |
Label CH1_LOOP; |
4643 |
||
4644 |
BIND(DO2); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4645 |
(this->*load_2chr)(ch1, str1); |
29183 | 4646 |
sub(cnt2, cnt2, 2); |
4647 |
mov(result_tmp, cnt2); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4648 |
lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift))); |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4649 |
sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift); |
29183 | 4650 |
|
4651 |
BIND(CH1_LOOP); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4652 |
(this->*load_2chr)(ch2, Address(str2, cnt2_neg)); |
29183 | 4653 |
cmp(ch1, ch2); |
4654 |
br(EQ, MATCH); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4655 |
adds(cnt2_neg, cnt2_neg, str2_chr_size); |
29183 | 4656 |
br(LE, CH1_LOOP); |
4657 |
b(NOMATCH); |
|
4658 |
} |
|
4659 |
||
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4660 |
if ((icnt1 == -1 && str1_isL == str2_isL) || icnt1 == 3) { |
29183 | 4661 |
Label FIRST_LOOP, STR2_NEXT, STR1_LOOP; |
4662 |
||
4663 |
BIND(DO3); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4664 |
(this->*load_2chr)(first, str1); |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4665 |
(this->*str1_load_1chr)(ch1, Address(str1, 2*str1_chr_size)); |
29183 | 4666 |
|
4667 |
sub(cnt2, cnt2, 3); |
|
4668 |
mov(result_tmp, cnt2); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4669 |
lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift))); |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4670 |
sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift); |
29183 | 4671 |
|
4672 |
BIND(FIRST_LOOP); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4673 |
(this->*load_2chr)(ch2, Address(str2, cnt2_neg)); |
29183 | 4674 |
cmpw(first, ch2); |
4675 |
br(EQ, STR1_LOOP); |
|
4676 |
BIND(STR2_NEXT); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4677 |
adds(cnt2_neg, cnt2_neg, str2_chr_size); |
29183 | 4678 |
br(LE, FIRST_LOOP); |
4679 |
b(NOMATCH); |
|
4680 |
||
4681 |
BIND(STR1_LOOP); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4682 |
add(cnt2tmp, cnt2_neg, 2*str2_chr_size); |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4683 |
(this->*str2_load_1chr)(ch2, Address(str2, cnt2tmp)); |
29183 | 4684 |
cmp(ch1, ch2); |
4685 |
br(NE, STR2_NEXT); |
|
4686 |
b(MATCH); |
|
4687 |
} |
|
4688 |
||
4689 |
if (icnt1 == -1 || icnt1 == 1) { |
|
4690 |
Label CH1_LOOP, HAS_ZERO; |
|
4691 |
Label DO1_SHORT, DO1_LOOP; |
|
4692 |
||
4693 |
BIND(DO1); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4694 |
(this->*str1_load_1chr)(ch1, str1); |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4695 |
cmp(cnt2, 8); |
29183 | 4696 |
br(LT, DO1_SHORT); |
4697 |
||
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4698 |
if (str2_isL) { |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4699 |
if (!str1_isL) { |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4700 |
tst(ch1, 0xff00); |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4701 |
br(NE, NOMATCH); |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4702 |
} |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4703 |
orr(ch1, ch1, ch1, LSL, 8); |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4704 |
} |
29183 | 4705 |
orr(ch1, ch1, ch1, LSL, 16); |
4706 |
orr(ch1, ch1, ch1, LSL, 32); |
|
4707 |
||
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4708 |
sub(cnt2, cnt2, 8/str2_chr_size); |
29183 | 4709 |
mov(result_tmp, cnt2); |
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4710 |
lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift))); |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4711 |
sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift); |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4712 |
|
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4713 |
mov(tmp3, str2_isL ? 0x0101010101010101 : 0x0001000100010001); |
29183 | 4714 |
BIND(CH1_LOOP); |
4715 |
ldr(ch2, Address(str2, cnt2_neg)); |
|
4716 |
eor(ch2, ch1, ch2); |
|
4717 |
sub(tmp1, ch2, tmp3); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4718 |
orr(tmp2, ch2, str2_isL ? 0x7f7f7f7f7f7f7f7f : 0x7fff7fff7fff7fff); |
29183 | 4719 |
bics(tmp1, tmp1, tmp2); |
4720 |
br(NE, HAS_ZERO); |
|
4721 |
adds(cnt2_neg, cnt2_neg, 8); |
|
4722 |
br(LT, CH1_LOOP); |
|
4723 |
||
4724 |
cmp(cnt2_neg, 8); |
|
4725 |
mov(cnt2_neg, 0); |
|
4726 |
br(LT, CH1_LOOP); |
|
4727 |
b(NOMATCH); |
|
4728 |
||
4729 |
BIND(HAS_ZERO); |
|
4730 |
rev(tmp1, tmp1); |
|
4731 |
clz(tmp1, tmp1); |
|
4732 |
add(cnt2_neg, cnt2_neg, tmp1, LSR, 3); |
|
4733 |
b(MATCH); |
|
4734 |
||
4735 |
BIND(DO1_SHORT); |
|
4736 |
mov(result_tmp, cnt2); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4737 |
lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift))); |
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4738 |
sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift); |
29183 | 4739 |
BIND(DO1_LOOP); |
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4740 |
(this->*str2_load_1chr)(ch2, Address(str2, cnt2_neg)); |
29183 | 4741 |
cmpw(ch1, ch2); |
4742 |
br(EQ, MATCH); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4743 |
adds(cnt2_neg, cnt2_neg, str2_chr_size); |
29183 | 4744 |
br(LT, DO1_LOOP); |
4745 |
} |
|
4746 |
} |
|
4747 |
BIND(NOMATCH); |
|
4748 |
mov(result, -1); |
|
4749 |
b(DONE); |
|
4750 |
BIND(MATCH); |
|
38713
4a16e9ea88a0
8157834: aarch64: Hello World crashes with fastdebug build
enevill
parents:
38241
diff
changeset
|
4751 |
add(result, result_tmp, cnt2_neg, ASR, str2_chr_shift); |
29183 | 4752 |
BIND(DONE); |
4753 |
} |
|
4754 |
||
40041
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4755 |
typedef void (MacroAssembler::* chr_insn)(Register Rt, const Address &adr); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4756 |
typedef void (MacroAssembler::* uxt_insn)(Register Rd, Register Rn); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4757 |
|
41670
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4758 |
void MacroAssembler::string_indexof_char(Register str1, Register cnt1, |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4759 |
Register ch, Register result, |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4760 |
Register tmp1, Register tmp2, Register tmp3) |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4761 |
{ |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4762 |
Label CH1_LOOP, HAS_ZERO, DO1_SHORT, DO1_LOOP, MATCH, NOMATCH, DONE; |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4763 |
Register cnt1_neg = cnt1; |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4764 |
Register ch1 = rscratch1; |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4765 |
Register result_tmp = rscratch2; |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4766 |
|
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4767 |
cmp(cnt1, 4); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4768 |
br(LT, DO1_SHORT); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4769 |
|
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4770 |
orr(ch, ch, ch, LSL, 16); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4771 |
orr(ch, ch, ch, LSL, 32); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4772 |
|
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4773 |
sub(cnt1, cnt1, 4); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4774 |
mov(result_tmp, cnt1); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4775 |
lea(str1, Address(str1, cnt1, Address::uxtw(1))); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4776 |
sub(cnt1_neg, zr, cnt1, LSL, 1); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4777 |
|
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4778 |
mov(tmp3, 0x0001000100010001); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4779 |
|
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4780 |
BIND(CH1_LOOP); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4781 |
ldr(ch1, Address(str1, cnt1_neg)); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4782 |
eor(ch1, ch, ch1); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4783 |
sub(tmp1, ch1, tmp3); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4784 |
orr(tmp2, ch1, 0x7fff7fff7fff7fff); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4785 |
bics(tmp1, tmp1, tmp2); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4786 |
br(NE, HAS_ZERO); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4787 |
adds(cnt1_neg, cnt1_neg, 8); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4788 |
br(LT, CH1_LOOP); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4789 |
|
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4790 |
cmp(cnt1_neg, 8); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4791 |
mov(cnt1_neg, 0); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4792 |
br(LT, CH1_LOOP); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4793 |
b(NOMATCH); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4794 |
|
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4795 |
BIND(HAS_ZERO); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4796 |
rev(tmp1, tmp1); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4797 |
clz(tmp1, tmp1); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4798 |
add(cnt1_neg, cnt1_neg, tmp1, LSR, 3); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4799 |
b(MATCH); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4800 |
|
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4801 |
BIND(DO1_SHORT); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4802 |
mov(result_tmp, cnt1); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4803 |
lea(str1, Address(str1, cnt1, Address::uxtw(1))); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4804 |
sub(cnt1_neg, zr, cnt1, LSL, 1); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4805 |
BIND(DO1_LOOP); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4806 |
ldrh(ch1, Address(str1, cnt1_neg)); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4807 |
cmpw(ch, ch1); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4808 |
br(EQ, MATCH); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4809 |
adds(cnt1_neg, cnt1_neg, 2); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4810 |
br(LT, DO1_LOOP); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4811 |
BIND(NOMATCH); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4812 |
mov(result, -1); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4813 |
b(DONE); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4814 |
BIND(MATCH); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4815 |
add(result, result_tmp, cnt1_neg, ASR, 1); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4816 |
BIND(DONE); |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4817 |
} |
ee918e29fc47
8157708: aarch64: StrIndexOfChar intrinsic is not implemented
enevill
parents:
40643
diff
changeset
|
4818 |
|
29183 | 4819 |
// Compare strings. |
4820 |
void MacroAssembler::string_compare(Register str1, Register str2, |
|
4821 |
Register cnt1, Register cnt2, Register result, |
|
40041
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4822 |
Register tmp1, |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4823 |
FloatRegister vtmp, FloatRegister vtmpZ, int ae) { |
29183 | 4824 |
Label LENGTH_DIFF, DONE, SHORT_LOOP, SHORT_STRING, |
4825 |
NEXT_WORD, DIFFERENCE; |
|
4826 |
||
40041
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4827 |
bool isLL = ae == StrIntrinsicNode::LL; |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4828 |
bool isLU = ae == StrIntrinsicNode::LU; |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4829 |
bool isUL = ae == StrIntrinsicNode::UL; |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4830 |
|
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4831 |
bool str1_isL = isLL || isLU; |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4832 |
bool str2_isL = isLL || isUL; |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4833 |
|
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4834 |
int str1_chr_shift = str1_isL ? 0 : 1; |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4835 |
int str2_chr_shift = str2_isL ? 0 : 1; |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4836 |
int str1_chr_size = str1_isL ? 1 : 2; |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4837 |
int str2_chr_size = str2_isL ? 1 : 2; |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4838 |
|
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4839 |
chr_insn str1_load_chr = str1_isL ? (chr_insn)&MacroAssembler::ldrb : |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4840 |
(chr_insn)&MacroAssembler::ldrh; |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4841 |
chr_insn str2_load_chr = str2_isL ? (chr_insn)&MacroAssembler::ldrb : |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4842 |
(chr_insn)&MacroAssembler::ldrh; |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4843 |
uxt_insn ext_chr = isLL ? (uxt_insn)&MacroAssembler::uxtbw : |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4844 |
(uxt_insn)&MacroAssembler::uxthw; |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4845 |
|
29183 | 4846 |
BLOCK_COMMENT("string_compare {"); |
4847 |
||
40041
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4848 |
// Bizzarely, the counts are passed in bytes, regardless of whether they |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4849 |
// are L or U strings, however the result is always in characters. |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4850 |
if (!str1_isL) asrw(cnt1, cnt1, 1); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4851 |
if (!str2_isL) asrw(cnt2, cnt2, 1); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4852 |
|
29183 | 4853 |
// Compute the minimum of the string lengths and save the difference. |
4854 |
subsw(tmp1, cnt1, cnt2); |
|
4855 |
cselw(cnt2, cnt1, cnt2, Assembler::LE); // min |
|
4856 |
||
4857 |
// A very short string |
|
40041
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4858 |
cmpw(cnt2, isLL ? 8:4); |
29183 | 4859 |
br(Assembler::LT, SHORT_STRING); |
4860 |
||
4861 |
// Check if the strings start at the same location. |
|
4862 |
cmp(str1, str2); |
|
4863 |
br(Assembler::EQ, LENGTH_DIFF); |
|
4864 |
||
4865 |
// Compare longwords |
|
4866 |
{ |
|
40041
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4867 |
subw(cnt2, cnt2, isLL ? 8:4); // The last longword is a special case |
29183 | 4868 |
|
4869 |
// Move both string pointers to the last longword of their |
|
4870 |
// strings, negate the remaining count, and convert it to bytes. |
|
40041
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4871 |
lea(str1, Address(str1, cnt2, Address::uxtw(str1_chr_shift))); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4872 |
lea(str2, Address(str2, cnt2, Address::uxtw(str2_chr_shift))); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4873 |
if (isLU || isUL) { |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4874 |
sub(cnt1, zr, cnt2, LSL, str1_chr_shift); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4875 |
eor(vtmpZ, T16B, vtmpZ, vtmpZ); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4876 |
} |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4877 |
sub(cnt2, zr, cnt2, LSL, str2_chr_shift); |
29183 | 4878 |
|
4879 |
// Loop, loading longwords and comparing them into rscratch2. |
|
4880 |
bind(NEXT_WORD); |
|
40041
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4881 |
if (isLU) { |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4882 |
ldrs(vtmp, Address(str1, cnt1)); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4883 |
zip1(vtmp, T8B, vtmp, vtmpZ); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4884 |
umov(result, vtmp, D, 0); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4885 |
} else { |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4886 |
ldr(result, Address(str1, isUL ? cnt1:cnt2)); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4887 |
} |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4888 |
if (isUL) { |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4889 |
ldrs(vtmp, Address(str2, cnt2)); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4890 |
zip1(vtmp, T8B, vtmp, vtmpZ); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4891 |
umov(rscratch1, vtmp, D, 0); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4892 |
} else { |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4893 |
ldr(rscratch1, Address(str2, cnt2)); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4894 |
} |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4895 |
adds(cnt2, cnt2, isUL ? 4:8); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4896 |
if (isLU || isUL) add(cnt1, cnt1, isLU ? 4:8); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4897 |
eor(rscratch2, result, rscratch1); |
29183 | 4898 |
cbnz(rscratch2, DIFFERENCE); |
4899 |
br(Assembler::LT, NEXT_WORD); |
|
4900 |
||
4901 |
// Last longword. In the case where length == 4 we compare the |
|
4902 |
// same longword twice, but that's still faster than another |
|
4903 |
// conditional branch. |
|
4904 |
||
40041
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4905 |
if (isLU) { |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4906 |
ldrs(vtmp, Address(str1)); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4907 |
zip1(vtmp, T8B, vtmp, vtmpZ); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4908 |
umov(result, vtmp, D, 0); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4909 |
} else { |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4910 |
ldr(result, Address(str1)); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4911 |
} |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4912 |
if (isUL) { |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4913 |
ldrs(vtmp, Address(str2)); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4914 |
zip1(vtmp, T8B, vtmp, vtmpZ); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4915 |
umov(rscratch1, vtmp, D, 0); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4916 |
} else { |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4917 |
ldr(rscratch1, Address(str2)); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4918 |
} |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4919 |
eor(rscratch2, result, rscratch1); |
29183 | 4920 |
cbz(rscratch2, LENGTH_DIFF); |
4921 |
||
4922 |
// Find the first different characters in the longwords and |
|
4923 |
// compute their difference. |
|
4924 |
bind(DIFFERENCE); |
|
4925 |
rev(rscratch2, rscratch2); |
|
4926 |
clz(rscratch2, rscratch2); |
|
40041
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4927 |
andr(rscratch2, rscratch2, isLL ? -8 : -16); |
29183 | 4928 |
lsrv(result, result, rscratch2); |
40041
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4929 |
(this->*ext_chr)(result, result); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4930 |
lsrv(rscratch1, rscratch1, rscratch2); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4931 |
(this->*ext_chr)(rscratch1, rscratch1); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4932 |
subw(result, result, rscratch1); |
29183 | 4933 |
b(DONE); |
4934 |
} |
|
4935 |
||
4936 |
bind(SHORT_STRING); |
|
4937 |
// Is the minimum length zero? |
|
4938 |
cbz(cnt2, LENGTH_DIFF); |
|
4939 |
||
4940 |
bind(SHORT_LOOP); |
|
40041
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4941 |
(this->*str1_load_chr)(result, Address(post(str1, str1_chr_size))); |
c6da347e21a8
8156943: aarch64: string compare does not support CompactStrings
enevill
parents:
40036
diff
changeset
|
4942 |
(this->*str2_load_chr)(cnt1, Address(post(str2, str2_chr_size))); |
29183 | 4943 |
subw(result, result, cnt1); |
4944 |
cbnz(result, DONE); |
|
4945 |
sub(cnt2, cnt2, 1); |
|
4946 |
cbnz(cnt2, SHORT_LOOP); |
|
4947 |
||
4948 |
// Strings are equal up to min length. Return the length difference. |
|
4949 |
bind(LENGTH_DIFF); |
|
4950 |
mov(result, tmp1); |
|
4951 |
||
4952 |
// That's it |
|
4953 |
bind(DONE); |
|
4954 |
||
4955 |
BLOCK_COMMENT("} string_compare"); |
|
4956 |
} |
|
4957 |
||
46814 | 4958 |
// This method checks if provided byte array contains byte with highest bit set. |
4959 |
void MacroAssembler::has_negatives(Register ary1, Register len, Register result) { |
|
4960 |
// Simple and most common case of aligned small array which is not at the |
|
4961 |
// end of memory page is placed here. All other cases are in stub. |
|
4962 |
Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE; |
|
4963 |
const uint64_t UPPER_BIT_MASK=0x8080808080808080; |
|
4964 |
assert_different_registers(ary1, len, result); |
|
4965 |
||
4966 |
cmpw(len, 0); |
|
4967 |
br(LE, SET_RESULT); |
|
4968 |
cmpw(len, 4 * wordSize); |
|
4969 |
br(GE, STUB_LONG); // size > 32 then go to stub |
|
4970 |
||
4971 |
int shift = 64 - exact_log2(os::vm_page_size()); |
|
4972 |
lsl(rscratch1, ary1, shift); |
|
4973 |
mov(rscratch2, (size_t)(4 * wordSize) << shift); |
|
4974 |
adds(rscratch2, rscratch1, rscratch2); // At end of page? |
|
4975 |
br(CS, STUB); // at the end of page then go to stub |
|
4976 |
subs(len, len, wordSize); |
|
4977 |
br(LT, END); |
|
4978 |
||
4979 |
BIND(LOOP); |
|
4980 |
ldr(rscratch1, Address(post(ary1, wordSize))); |
|
4981 |
tst(rscratch1, UPPER_BIT_MASK); |
|
4982 |
br(NE, SET_RESULT); |
|
4983 |
subs(len, len, wordSize); |
|
4984 |
br(GE, LOOP); |
|
4985 |
cmpw(len, -wordSize); |
|
4986 |
br(EQ, SET_RESULT); |
|
4987 |
||
4988 |
BIND(END); |
|
4989 |
ldr(result, Address(ary1)); |
|
4990 |
sub(len, zr, len, LSL, 3); // LSL 3 is to get bits from bytes |
|
4991 |
lslv(result, result, len); |
|
4992 |
tst(result, UPPER_BIT_MASK); |
|
4993 |
b(SET_RESULT); |
|
4994 |
||
4995 |
BIND(STUB); |
|
4996 |
RuntimeAddress has_neg = RuntimeAddress(StubRoutines::aarch64::has_negatives()); |
|
4997 |
assert(has_neg.target() != NULL, "has_negatives stub has not been generated"); |
|
4998 |
trampoline_call(has_neg); |
|
4999 |
b(DONE); |
|
5000 |
||
5001 |
BIND(STUB_LONG); |
|
5002 |
RuntimeAddress has_neg_long = RuntimeAddress( |
|
5003 |
StubRoutines::aarch64::has_negatives_long()); |
|
5004 |
assert(has_neg_long.target() != NULL, "has_negatives stub has not been generated"); |
|
5005 |
trampoline_call(has_neg_long); |
|
5006 |
b(DONE); |
|
5007 |
||
5008 |
BIND(SET_RESULT); |
|
5009 |
cset(result, NE); // set true or false |
|
5010 |
||
5011 |
BIND(DONE); |
|
5012 |
} |
|
5013 |
||
49724
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5014 |
void MacroAssembler::arrays_equals(Register a1, Register a2, Register tmp3, |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5015 |
Register tmp4, Register tmp5, Register result, |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5016 |
Register cnt1, int elem_size) |
35842
1d34635308b0
8149100: AArch64: "bad AD file" for LL enconding AryEq Node matching
hshi
parents:
35840
diff
changeset
|
5017 |
{ |
49724
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5018 |
Label DONE; |
36338
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5019 |
Register tmp1 = rscratch1; |
35842
1d34635308b0
8149100: AArch64: "bad AD file" for LL enconding AryEq Node matching
hshi
parents:
35840
diff
changeset
|
5020 |
Register tmp2 = rscratch2; |
36338
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5021 |
Register cnt2 = tmp2; // cnt2 only used in array length compare |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5022 |
int elem_per_word = wordSize/elem_size; |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5023 |
int log_elem_size = exact_log2(elem_size); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5024 |
int length_offset = arrayOopDesc::length_offset_in_bytes(); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5025 |
int base_offset |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5026 |
= arrayOopDesc::base_offset_in_bytes(elem_size == 2 ? T_CHAR : T_BYTE); |
49724
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5027 |
int stubBytesThreshold = 3 * 64 + (UseSIMDForArrayEquals ? 0 : 16); |
36338
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5028 |
|
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5029 |
assert(elem_size == 1 || elem_size == 2, "must be char or byte"); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5030 |
assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5031 |
|
38002 | 5032 |
#ifndef PRODUCT |
5033 |
{ |
|
5034 |
const char kind = (elem_size == 2) ? 'U' : 'L'; |
|
5035 |
char comment[64]; |
|
49724
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5036 |
snprintf(comment, sizeof comment, "array_equals%c{", kind); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5037 |
BLOCK_COMMENT(comment); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5038 |
} |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5039 |
#endif |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5040 |
if (UseSimpleArrayEquals) { |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5041 |
Label NEXT_WORD, SHORT, SAME, TAIL03, TAIL01, A_MIGHT_BE_NULL, A_IS_NOT_NULL; |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5042 |
// if (a1==a2) |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5043 |
// return true; |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5044 |
// if (a==null || a2==null) |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5045 |
// return false; |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5046 |
// a1 & a2 == 0 means (some-pointer is null) or |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5047 |
// (very-rare-or-even-probably-impossible-pointer-values) |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5048 |
// so, we can save one branch in most cases |
50536
8434981a4137
8203157: Object equals abstraction for BarrierSetAssembler
rkennke
parents:
50517
diff
changeset
|
5049 |
cmpoop(a1, a2); |
8434981a4137
8203157: Object equals abstraction for BarrierSetAssembler
rkennke
parents:
50517
diff
changeset
|
5050 |
br(EQ, SAME); |
49724
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5051 |
eor(rscratch1, a1, a2); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5052 |
tst(a1, a2); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5053 |
mov(result, false); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5054 |
cbz(rscratch1, SAME); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5055 |
br(EQ, A_MIGHT_BE_NULL); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5056 |
// if (a1.length != a2.length) |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5057 |
// return false; |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5058 |
bind(A_IS_NOT_NULL); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5059 |
ldrw(cnt1, Address(a1, length_offset)); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5060 |
ldrw(cnt2, Address(a2, length_offset)); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5061 |
eorw(tmp5, cnt1, cnt2); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5062 |
cbnzw(tmp5, DONE); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5063 |
lea(a1, Address(a1, base_offset)); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5064 |
lea(a2, Address(a2, base_offset)); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5065 |
// Check for short strings, i.e. smaller than wordSize. |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5066 |
subs(cnt1, cnt1, elem_per_word); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5067 |
br(Assembler::LT, SHORT); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5068 |
// Main 8 byte comparison loop. |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5069 |
bind(NEXT_WORD); { |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5070 |
ldr(tmp1, Address(post(a1, wordSize))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5071 |
ldr(tmp2, Address(post(a2, wordSize))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5072 |
subs(cnt1, cnt1, elem_per_word); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5073 |
eor(tmp5, tmp1, tmp2); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5074 |
cbnz(tmp5, DONE); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5075 |
} br(GT, NEXT_WORD); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5076 |
// Last longword. In the case where length == 4 we compare the |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5077 |
// same longword twice, but that's still faster than another |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5078 |
// conditional branch. |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5079 |
// cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5080 |
// length == 4. |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5081 |
if (log_elem_size > 0) |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5082 |
lsl(cnt1, cnt1, log_elem_size); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5083 |
ldr(tmp3, Address(a1, cnt1)); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5084 |
ldr(tmp4, Address(a2, cnt1)); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5085 |
eor(tmp5, tmp3, tmp4); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5086 |
cbnz(tmp5, DONE); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5087 |
b(SAME); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5088 |
bind(A_MIGHT_BE_NULL); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5089 |
// in case both a1 and a2 are not-null, proceed with loads |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5090 |
cbz(a1, DONE); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5091 |
cbz(a2, DONE); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5092 |
b(A_IS_NOT_NULL); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5093 |
bind(SHORT); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5094 |
|
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5095 |
tbz(cnt1, 2 - log_elem_size, TAIL03); // 0-7 bytes left. |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5096 |
{ |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5097 |
ldrw(tmp1, Address(post(a1, 4))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5098 |
ldrw(tmp2, Address(post(a2, 4))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5099 |
eorw(tmp5, tmp1, tmp2); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5100 |
cbnzw(tmp5, DONE); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5101 |
} |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5102 |
bind(TAIL03); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5103 |
tbz(cnt1, 1 - log_elem_size, TAIL01); // 0-3 bytes left. |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5104 |
{ |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5105 |
ldrh(tmp3, Address(post(a1, 2))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5106 |
ldrh(tmp4, Address(post(a2, 2))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5107 |
eorw(tmp5, tmp3, tmp4); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5108 |
cbnzw(tmp5, DONE); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5109 |
} |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5110 |
bind(TAIL01); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5111 |
if (elem_size == 1) { // Only needed when comparing byte arrays. |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5112 |
tbz(cnt1, 0, SAME); // 0-1 bytes left. |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5113 |
{ |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5114 |
ldrb(tmp1, a1); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5115 |
ldrb(tmp2, a2); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5116 |
eorw(tmp5, tmp1, tmp2); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5117 |
cbnzw(tmp5, DONE); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5118 |
} |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5119 |
} |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5120 |
bind(SAME); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5121 |
mov(result, true); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5122 |
} else { |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5123 |
Label NEXT_DWORD, A_IS_NULL, SHORT, TAIL, TAIL2, STUB, EARLY_OUT, |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5124 |
CSET_EQ, LAST_CHECK, LEN_IS_ZERO, SAME; |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5125 |
cbz(a1, A_IS_NULL); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5126 |
ldrw(cnt1, Address(a1, length_offset)); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5127 |
cbz(a2, A_IS_NULL); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5128 |
ldrw(cnt2, Address(a2, length_offset)); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5129 |
mov(result, false); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5130 |
// on most CPUs a2 is still "locked"(surprisingly) in ldrw and it's |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5131 |
// faster to perform another branch before comparing a1 and a2 |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5132 |
cmp(cnt1, elem_per_word); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5133 |
br(LE, SHORT); // short or same |
50536
8434981a4137
8203157: Object equals abstraction for BarrierSetAssembler
rkennke
parents:
50517
diff
changeset
|
5134 |
cmpoop(a1, a2); |
49724
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5135 |
br(EQ, SAME); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5136 |
ldr(tmp3, Address(pre(a1, base_offset))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5137 |
cmp(cnt1, stubBytesThreshold); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5138 |
br(GE, STUB); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5139 |
ldr(tmp4, Address(pre(a2, base_offset))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5140 |
sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5141 |
cmp(cnt2, cnt1); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5142 |
br(NE, DONE); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5143 |
|
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5144 |
// Main 16 byte comparison loop with 2 exits |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5145 |
bind(NEXT_DWORD); { |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5146 |
ldr(tmp1, Address(pre(a1, wordSize))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5147 |
ldr(tmp2, Address(pre(a2, wordSize))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5148 |
subs(cnt1, cnt1, 2 * elem_per_word); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5149 |
br(LE, TAIL); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5150 |
eor(tmp4, tmp3, tmp4); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5151 |
cbnz(tmp4, DONE); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5152 |
ldr(tmp3, Address(pre(a1, wordSize))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5153 |
ldr(tmp4, Address(pre(a2, wordSize))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5154 |
cmp(cnt1, elem_per_word); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5155 |
br(LE, TAIL2); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5156 |
cmp(tmp1, tmp2); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5157 |
} br(EQ, NEXT_DWORD); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5158 |
b(DONE); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5159 |
|
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5160 |
bind(TAIL); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5161 |
eor(tmp4, tmp3, tmp4); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5162 |
eor(tmp2, tmp1, tmp2); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5163 |
lslv(tmp2, tmp2, tmp5); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5164 |
orr(tmp5, tmp4, tmp2); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5165 |
cmp(tmp5, zr); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5166 |
b(CSET_EQ); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5167 |
|
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5168 |
bind(TAIL2); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5169 |
eor(tmp2, tmp1, tmp2); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5170 |
cbnz(tmp2, DONE); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5171 |
b(LAST_CHECK); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5172 |
|
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5173 |
bind(STUB); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5174 |
ldr(tmp4, Address(pre(a2, base_offset))); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5175 |
cmp(cnt2, cnt1); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5176 |
br(NE, DONE); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5177 |
if (elem_size == 2) { // convert to byte counter |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5178 |
lsl(cnt1, cnt1, 1); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5179 |
} |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5180 |
eor(tmp5, tmp3, tmp4); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5181 |
cbnz(tmp5, DONE); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5182 |
RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_array_equals()); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5183 |
assert(stub.target() != NULL, "array_equals_long stub has not been generated"); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5184 |
trampoline_call(stub); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5185 |
b(DONE); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5186 |
|
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5187 |
bind(SAME); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5188 |
mov(result, true); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5189 |
b(DONE); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5190 |
bind(A_IS_NULL); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5191 |
// a1 or a2 is null. if a2 == a2 then return true. else return false |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5192 |
cmp(a1, a2); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5193 |
b(CSET_EQ); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5194 |
bind(EARLY_OUT); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5195 |
// (a1 != null && a2 == null) || (a1 != null && a2 != null && a1 == a2) |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5196 |
// so, if a2 == null => return false(0), else return true, so we can return a2 |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5197 |
mov(result, a2); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5198 |
b(DONE); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5199 |
bind(LEN_IS_ZERO); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5200 |
cmp(cnt2, zr); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5201 |
b(CSET_EQ); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5202 |
bind(SHORT); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5203 |
cbz(cnt1, LEN_IS_ZERO); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5204 |
sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5205 |
ldr(tmp3, Address(a1, base_offset)); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5206 |
ldr(tmp4, Address(a2, base_offset)); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5207 |
bind(LAST_CHECK); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5208 |
eor(tmp4, tmp3, tmp4); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5209 |
lslv(tmp5, tmp4, tmp5); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5210 |
cmp(tmp5, zr); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5211 |
bind(CSET_EQ); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5212 |
cset(result, EQ); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5213 |
} |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5214 |
|
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5215 |
// That's it. |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5216 |
bind(DONE); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5217 |
|
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5218 |
BLOCK_COMMENT("} array_equals"); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5219 |
} |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5220 |
|
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5221 |
// Compare Strings |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5222 |
|
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5223 |
// For Strings we're passed the address of the first characters in a1 |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5224 |
// and a2 and the length in cnt1. |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5225 |
// elem_size is the element size in bytes: either 1 or 2. |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5226 |
// There are two implementations. For arrays >= 8 bytes, all |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5227 |
// comparisons (including the final one, which may overlap) are |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5228 |
// performed 8 bytes at a time. For strings < 8 bytes, we compare a |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5229 |
// halfword, then a short, and then a byte. |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5230 |
|
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5231 |
void MacroAssembler::string_equals(Register a1, Register a2, |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5232 |
Register result, Register cnt1, int elem_size) |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5233 |
{ |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5234 |
Label SAME, DONE, SHORT, NEXT_WORD; |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5235 |
Register tmp1 = rscratch1; |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5236 |
Register tmp2 = rscratch2; |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5237 |
Register cnt2 = tmp2; // cnt2 only used in array length compare |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5238 |
|
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5239 |
assert(elem_size == 1 || elem_size == 2, "must be 2 or 1 byte"); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5240 |
assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5241 |
|
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5242 |
#ifndef PRODUCT |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5243 |
{ |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5244 |
const char kind = (elem_size == 2) ? 'U' : 'L'; |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5245 |
char comment[64]; |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5246 |
snprintf(comment, sizeof comment, "{string_equals%c", kind); |
38002 | 5247 |
BLOCK_COMMENT(comment); |
5248 |
} |
|
5249 |
#endif |
|
36338
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5250 |
|
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5251 |
mov(result, false); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5252 |
|
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5253 |
// Check for short strings, i.e. smaller than wordSize. |
49724
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5254 |
subs(cnt1, cnt1, wordSize); |
36338
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5255 |
br(Assembler::LT, SHORT); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5256 |
// Main 8 byte comparison loop. |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5257 |
bind(NEXT_WORD); { |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5258 |
ldr(tmp1, Address(post(a1, wordSize))); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5259 |
ldr(tmp2, Address(post(a2, wordSize))); |
49724
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5260 |
subs(cnt1, cnt1, wordSize); |
35842
1d34635308b0
8149100: AArch64: "bad AD file" for LL enconding AryEq Node matching
hshi
parents:
35840
diff
changeset
|
5261 |
eor(tmp1, tmp1, tmp2); |
36338
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5262 |
cbnz(tmp1, DONE); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5263 |
} br(GT, NEXT_WORD); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5264 |
// Last longword. In the case where length == 4 we compare the |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5265 |
// same longword twice, but that's still faster than another |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5266 |
// conditional branch. |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5267 |
// cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5268 |
// length == 4. |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5269 |
ldr(tmp1, Address(a1, cnt1)); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5270 |
ldr(tmp2, Address(a2, cnt1)); |
49724
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5271 |
eor(tmp2, tmp1, tmp2); |
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5272 |
cbnz(tmp2, DONE); |
36338
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5273 |
b(SAME); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5274 |
|
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5275 |
bind(SHORT); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5276 |
Label TAIL03, TAIL01; |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5277 |
|
49724
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5278 |
tbz(cnt1, 2, TAIL03); // 0-7 bytes left. |
36338
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5279 |
{ |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5280 |
ldrw(tmp1, Address(post(a1, 4))); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5281 |
ldrw(tmp2, Address(post(a2, 4))); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5282 |
eorw(tmp1, tmp1, tmp2); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5283 |
cbnzw(tmp1, DONE); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5284 |
} |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5285 |
bind(TAIL03); |
49724
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5286 |
tbz(cnt1, 1, TAIL01); // 0-3 bytes left. |
36338
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5287 |
{ |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5288 |
ldrh(tmp1, Address(post(a1, 2))); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5289 |
ldrh(tmp2, Address(post(a2, 2))); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5290 |
eorw(tmp1, tmp1, tmp2); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5291 |
cbnzw(tmp1, DONE); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5292 |
} |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5293 |
bind(TAIL01); |
49724
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5294 |
if (elem_size == 1) { // Only needed when comparing 1-byte elements |
36338
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5295 |
tbz(cnt1, 0, SAME); // 0-1 bytes left. |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5296 |
{ |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5297 |
ldrb(tmp1, a1); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5298 |
ldrb(tmp2, a2); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5299 |
eorw(tmp1, tmp1, tmp2); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5300 |
cbnzw(tmp1, DONE); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5301 |
} |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5302 |
} |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5303 |
// Arrays are equal. |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5304 |
bind(SAME); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5305 |
mov(result, true); |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5306 |
|
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5307 |
// That's it. |
de236db57636
8149733: AArch64: refactor array_equals/string_equals
hshi
parents:
35951
diff
changeset
|
5308 |
bind(DONE); |
49724
bf7f42f2f025
8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents:
49592
diff
changeset
|
5309 |
BLOCK_COMMENT("} string_equals"); |
35842
1d34635308b0
8149100: AArch64: "bad AD file" for LL enconding AryEq Node matching
hshi
parents:
35840
diff
changeset
|
5310 |
} |
1d34635308b0
8149100: AArch64: "bad AD file" for LL enconding AryEq Node matching
hshi
parents:
35840
diff
changeset
|
5311 |
|
38143 | 5312 |
|
45054 | 5313 |
// The size of the blocks erased by the zero_blocks stub. We must |
5314 |
// handle anything smaller than this ourselves in zero_words(). |
|
5315 |
const int MacroAssembler::zero_words_block_size = 8; |
|
5316 |
||
5317 |
// zero_words() is used by C2 ClearArray patterns. It is as small as |
|
5318 |
// possible, handling small word counts locally and delegating |
|
5319 |
// anything larger to the zero_blocks stub. It is expanded many times |
|
5320 |
// in compiled code, so it is important to keep it short. |
|
5321 |
||
5322 |
// ptr: Address of a buffer to be zeroed. |
|
5323 |
// cnt: Count in HeapWords. |
|
5324 |
// |
|
5325 |
// ptr, cnt, rscratch1, and rscratch2 are clobbered. |
|
5326 |
void MacroAssembler::zero_words(Register ptr, Register cnt) |
|
38028 | 5327 |
{ |
45054 | 5328 |
assert(is_power_of_2(zero_words_block_size), "adjust this"); |
5329 |
assert(ptr == r10 && cnt == r11, "mismatch in register usage"); |
|
5330 |
||
5331 |
BLOCK_COMMENT("zero_words {"); |
|
5332 |
cmp(cnt, zero_words_block_size); |
|
5333 |
Label around, done, done16; |
|
5334 |
br(LO, around); |
|
5335 |
{ |
|
5336 |
RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks()); |
|
5337 |
assert(zero_blocks.target() != NULL, "zero_blocks stub has not been generated"); |
|
5338 |
if (StubRoutines::aarch64::complete()) { |
|
5339 |
trampoline_call(zero_blocks); |
|
5340 |
} else { |
|
5341 |
bl(zero_blocks); |
|
5342 |
} |
|
38143 | 5343 |
} |
45054 | 5344 |
bind(around); |
5345 |
for (int i = zero_words_block_size >> 1; i > 1; i >>= 1) { |
|
5346 |
Label l; |
|
5347 |
tbz(cnt, exact_log2(i), l); |
|
5348 |
for (int j = 0; j < i; j += 2) { |
|
5349 |
stp(zr, zr, post(ptr, 16)); |
|
5350 |
} |
|
5351 |
bind(l); |
|
5352 |
} |
|
5353 |
{ |
|
5354 |
Label l; |
|
5355 |
tbz(cnt, 0, l); |
|
5356 |
str(zr, Address(ptr)); |
|
5357 |
bind(l); |
|
5358 |
} |
|
5359 |
BLOCK_COMMENT("} zero_words"); |
|
38028 | 5360 |
} |
5361 |
||
45054 | 5362 |
// base: Address of a buffer to be zeroed, 8 bytes aligned. |
38143 | 5363 |
// cnt: Immediate count in HeapWords. |
45054 | 5364 |
#define SmallArraySize (18 * BytesPerLong) |
38037
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5365 |
void MacroAssembler::zero_words(Register base, u_int64_t cnt) |
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5366 |
{ |
45054 | 5367 |
BLOCK_COMMENT("zero_words {"); |
38037
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5368 |
int i = cnt & 1; // store any odd word to start |
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5369 |
if (i) str(zr, Address(base)); |
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5370 |
|
45054 | 5371 |
if (cnt <= SmallArraySize / BytesPerLong) { |
38037
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5372 |
for (; i < (int)cnt; i += 2) |
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5373 |
stp(zr, zr, Address(base, i * wordSize)); |
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5374 |
} else { |
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5375 |
const int unroll = 4; // Number of stp(zr, zr) instructions we'll unroll |
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5376 |
int remainder = cnt % (2 * unroll); |
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5377 |
for (; i < remainder; i += 2) |
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5378 |
stp(zr, zr, Address(base, i * wordSize)); |
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5379 |
|
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5380 |
Label loop; |
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5381 |
Register cnt_reg = rscratch1; |
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5382 |
Register loop_base = rscratch2; |
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5383 |
cnt = cnt - remainder; |
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5384 |
mov(cnt_reg, cnt); |
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5385 |
// adjust base and prebias by -2 * wordSize so we can pre-increment |
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5386 |
add(loop_base, base, (remainder - 2) * wordSize); |
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5387 |
bind(loop); |
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5388 |
sub(cnt_reg, cnt_reg, 2 * unroll); |
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5389 |
for (i = 1; i < unroll; i++) |
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5390 |
stp(zr, zr, Address(loop_base, 2 * i * wordSize)); |
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5391 |
stp(zr, zr, Address(pre(loop_base, 2 * unroll * wordSize))); |
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5392 |
cbnz(cnt_reg, loop); |
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5393 |
} |
45054 | 5394 |
BLOCK_COMMENT("} zero_words"); |
5395 |
} |
|
5396 |
||
5397 |
// Zero blocks of memory by using DC ZVA. |
|
5398 |
// |
|
5399 |
// Aligns the base address first sufficently for DC ZVA, then uses |
|
5400 |
// DC ZVA repeatedly for every full block. cnt is the size to be |
|
5401 |
// zeroed in HeapWords. Returns the count of words left to be zeroed |
|
5402 |
// in cnt. |
|
5403 |
// |
|
5404 |
// NOTE: This is intended to be used in the zero_blocks() stub. If |
|
5405 |
// you want to use it elsewhere, note that cnt must be >= 2*zva_length. |
|
5406 |
void MacroAssembler::zero_dcache_blocks(Register base, Register cnt) { |
|
5407 |
Register tmp = rscratch1; |
|
5408 |
Register tmp2 = rscratch2; |
|
5409 |
int zva_length = VM_Version::zva_length(); |
|
5410 |
Label initial_table_end, loop_zva; |
|
5411 |
Label fini; |
|
5412 |
||
5413 |
// Base must be 16 byte aligned. If not just return and let caller handle it |
|
5414 |
tst(base, 0x0f); |
|
5415 |
br(Assembler::NE, fini); |
|
5416 |
// Align base with ZVA length. |
|
5417 |
neg(tmp, base); |
|
5418 |
andr(tmp, tmp, zva_length - 1); |
|
5419 |
||
5420 |
// tmp: the number of bytes to be filled to align the base with ZVA length. |
|
5421 |
add(base, base, tmp); |
|
5422 |
sub(cnt, cnt, tmp, Assembler::ASR, 3); |
|
5423 |
adr(tmp2, initial_table_end); |
|
5424 |
sub(tmp2, tmp2, tmp, Assembler::LSR, 2); |
|
5425 |
br(tmp2); |
|
5426 |
||
5427 |
for (int i = -zva_length + 16; i < 0; i += 16) |
|
5428 |
stp(zr, zr, Address(base, i)); |
|
5429 |
bind(initial_table_end); |
|
5430 |
||
5431 |
sub(cnt, cnt, zva_length >> 3); |
|
5432 |
bind(loop_zva); |
|
5433 |
dc(Assembler::ZVA, base); |
|
5434 |
subs(cnt, cnt, zva_length >> 3); |
|
5435 |
add(base, base, zva_length); |
|
5436 |
br(Assembler::GE, loop_zva); |
|
5437 |
add(cnt, cnt, zva_length >> 3); // count not zeroed by DC ZVA |
|
5438 |
bind(fini); |
|
38037
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5439 |
} |
31c22b526d30
8153713: aarch64: improve short array clearing using store pair
fyang
parents:
38028
diff
changeset
|
5440 |
|
38028 | 5441 |
// base: Address of a buffer to be filled, 8 bytes aligned. |
5442 |
// cnt: Count in 8-byte unit. |
|
5443 |
// value: Value to be filled with. |
|
5444 |
// base will point to the end of the buffer after filling. |
|
5445 |
void MacroAssembler::fill_words(Register base, Register cnt, Register value) |
|
5446 |
{ |
|
5447 |
// Algorithm: |
|
5448 |
// |
|
5449 |
// scratch1 = cnt & 7; |
|
5450 |
// cnt -= scratch1; |
|
5451 |
// p += scratch1; |
|
5452 |
// switch (scratch1) { |
|
5453 |
// do { |
|
5454 |
// cnt -= 8; |
|
5455 |
// p[-8] = v; |
|
5456 |
// case 7: |
|
5457 |
// p[-7] = v; |
|
5458 |
// case 6: |
|
5459 |
// p[-6] = v; |
|
5460 |
// // ... |
|
5461 |
// case 1: |
|
5462 |
// p[-1] = v; |
|
5463 |
// case 0: |
|
5464 |
// p += 8; |
|
5465 |
// } while (cnt); |
|
5466 |
// } |
|
5467 |
||
5468 |
assert_different_registers(base, cnt, value, rscratch1, rscratch2); |
|
5469 |
||
38143 | 5470 |
Label fini, skip, entry, loop; |
5471 |
const int unroll = 8; // Number of stp instructions we'll unroll |
|
5472 |
||
5473 |
cbz(cnt, fini); |
|
5474 |
tbz(base, 3, skip); |
|
5475 |
str(value, Address(post(base, 8))); |
|
5476 |
sub(cnt, cnt, 1); |
|
5477 |
bind(skip); |
|
5478 |
||
5479 |
andr(rscratch1, cnt, (unroll-1) * 2); |
|
5480 |
sub(cnt, cnt, rscratch1); |
|
38028 | 5481 |
add(base, base, rscratch1, Assembler::LSL, 3); |
5482 |
adr(rscratch2, entry); |
|
38143 | 5483 |
sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 1); |
38028 | 5484 |
br(rscratch2); |
38143 | 5485 |
|
38028 | 5486 |
bind(loop); |
38225
1e9db94426bd
8155790: aarch64: debug VM fails to start after 8155617
enevill
parents:
38143
diff
changeset
|
5487 |
add(base, base, unroll * 16); |
38028 | 5488 |
for (int i = -unroll; i < 0; i++) |
38143 | 5489 |
stp(value, value, Address(base, i * 16)); |
38028 | 5490 |
bind(entry); |
38143 | 5491 |
subs(cnt, cnt, unroll * 2); |
5492 |
br(Assembler::GE, loop); |
|
5493 |
||
5494 |
tbz(cnt, 0, fini); |
|
38225
1e9db94426bd
8155790: aarch64: debug VM fails to start after 8155617
enevill
parents:
38143
diff
changeset
|
5495 |
str(value, Address(post(base, 8))); |
38143 | 5496 |
bind(fini); |
5497 |
} |
|
5498 |
||
38003
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5499 |
// Intrinsic for sun/nio/cs/ISO_8859_1$Encoder.implEncodeISOArray and |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5500 |
// java/lang/StringUTF16.compress. |
29183 | 5501 |
void MacroAssembler::encode_iso_array(Register src, Register dst, |
5502 |
Register len, Register result, |
|
5503 |
FloatRegister Vtmp1, FloatRegister Vtmp2, |
|
5504 |
FloatRegister Vtmp3, FloatRegister Vtmp4) |
|
5505 |
{ |
|
5506 |
Label DONE, NEXT_32, LOOP_8, NEXT_8, LOOP_1, NEXT_1; |
|
5507 |
Register tmp1 = rscratch1; |
|
5508 |
||
5509 |
mov(result, len); // Save initial len |
|
5510 |
||
5511 |
#ifndef BUILTIN_SIM |
|
5512 |
subs(len, len, 32); |
|
5513 |
br(LT, LOOP_8); |
|
5514 |
||
5515 |
// The following code uses the SIMD 'uqxtn' and 'uqxtn2' instructions |
|
5516 |
// to convert chars to bytes. These set the 'QC' bit in the FPSR if |
|
5517 |
// any char could not fit in a byte, so clear the FPSR so we can test it. |
|
5518 |
clear_fpsr(); |
|
5519 |
||
5520 |
BIND(NEXT_32); |
|
5521 |
ld1(Vtmp1, Vtmp2, Vtmp3, Vtmp4, T8H, src); |
|
5522 |
uqxtn(Vtmp1, T8B, Vtmp1, T8H); // uqxtn - write bottom half |
|
5523 |
uqxtn(Vtmp1, T16B, Vtmp2, T8H); // uqxtn2 - write top half |
|
5524 |
uqxtn(Vtmp2, T8B, Vtmp3, T8H); |
|
5525 |
uqxtn(Vtmp2, T16B, Vtmp4, T8H); // uqxtn2 |
|
5526 |
get_fpsr(tmp1); |
|
5527 |
cbnzw(tmp1, LOOP_8); |
|
5528 |
st1(Vtmp1, Vtmp2, T16B, post(dst, 32)); |
|
5529 |
subs(len, len, 32); |
|
5530 |
add(src, src, 64); |
|
5531 |
br(GE, NEXT_32); |
|
5532 |
||
5533 |
BIND(LOOP_8); |
|
5534 |
adds(len, len, 32-8); |
|
5535 |
br(LT, LOOP_1); |
|
5536 |
clear_fpsr(); // QC may be set from loop above, clear again |
|
5537 |
BIND(NEXT_8); |
|
5538 |
ld1(Vtmp1, T8H, src); |
|
5539 |
uqxtn(Vtmp1, T8B, Vtmp1, T8H); |
|
5540 |
get_fpsr(tmp1); |
|
5541 |
cbnzw(tmp1, LOOP_1); |
|
5542 |
st1(Vtmp1, T8B, post(dst, 8)); |
|
5543 |
subs(len, len, 8); |
|
5544 |
add(src, src, 16); |
|
5545 |
br(GE, NEXT_8); |
|
5546 |
||
5547 |
BIND(LOOP_1); |
|
5548 |
adds(len, len, 8); |
|
5549 |
br(LE, DONE); |
|
5550 |
#else |
|
5551 |
cbz(len, DONE); |
|
5552 |
#endif |
|
5553 |
BIND(NEXT_1); |
|
5554 |
ldrh(tmp1, Address(post(src, 2))); |
|
5555 |
tst(tmp1, 0xff00); |
|
5556 |
br(NE, DONE); |
|
5557 |
strb(tmp1, Address(post(dst, 1))); |
|
5558 |
subs(len, len, 1); |
|
5559 |
br(GT, NEXT_1); |
|
5560 |
||
5561 |
BIND(DONE); |
|
5562 |
sub(result, result, len); // Return index where we stopped |
|
38003
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5563 |
// Return len == 0 if we processed all |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5564 |
// characters |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5565 |
} |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5566 |
|
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5567 |
|
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5568 |
// Inflate byte[] array to char[]. |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5569 |
void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len, |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5570 |
FloatRegister vtmp1, FloatRegister vtmp2, FloatRegister vtmp3, |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5571 |
Register tmp4) { |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5572 |
Label big, done; |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5573 |
|
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5574 |
assert_different_registers(src, dst, len, tmp4, rscratch1); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5575 |
|
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5576 |
fmovd(vtmp1 , zr); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5577 |
lsrw(rscratch1, len, 3); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5578 |
|
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5579 |
cbnzw(rscratch1, big); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5580 |
|
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5581 |
// Short string: less than 8 bytes. |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5582 |
{ |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5583 |
Label loop, around, tiny; |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5584 |
|
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5585 |
subsw(len, len, 4); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5586 |
andw(len, len, 3); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5587 |
br(LO, tiny); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5588 |
|
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5589 |
// Use SIMD to do 4 bytes. |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5590 |
ldrs(vtmp2, post(src, 4)); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5591 |
zip1(vtmp3, T8B, vtmp2, vtmp1); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5592 |
strd(vtmp3, post(dst, 8)); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5593 |
|
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5594 |
cbzw(len, done); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5595 |
|
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5596 |
// Do the remaining bytes by steam. |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5597 |
bind(loop); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5598 |
ldrb(tmp4, post(src, 1)); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5599 |
strh(tmp4, post(dst, 2)); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5600 |
subw(len, len, 1); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5601 |
|
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5602 |
bind(tiny); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5603 |
cbnz(len, loop); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5604 |
|
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5605 |
bind(around); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5606 |
b(done); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5607 |
} |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5608 |
|
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5609 |
// Unpack the bytes 8 at a time. |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5610 |
bind(big); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5611 |
andw(len, len, 7); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5612 |
|
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5613 |
{ |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5614 |
Label loop, around; |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5615 |
|
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5616 |
bind(loop); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5617 |
ldrd(vtmp2, post(src, 8)); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5618 |
sub(rscratch1, rscratch1, 1); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5619 |
zip1(vtmp3, T16B, vtmp2, vtmp1); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5620 |
st1(vtmp3, T8H, post(dst, 16)); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5621 |
cbnz(rscratch1, loop); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5622 |
|
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5623 |
bind(around); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5624 |
} |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5625 |
|
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5626 |
// Do the tail of up to 8 bytes. |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5627 |
sub(src, src, 8); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5628 |
add(src, src, len, ext::uxtw, 0); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5629 |
ldrd(vtmp2, Address(src)); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5630 |
sub(dst, dst, 16); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5631 |
add(dst, dst, len, ext::uxtw, 1); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5632 |
zip1(vtmp3, T16B, vtmp2, vtmp1); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5633 |
st1(vtmp3, T8H, Address(dst)); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5634 |
|
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5635 |
bind(done); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5636 |
} |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5637 |
|
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5638 |
// Compress char[] array to byte[]. |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5639 |
void MacroAssembler::char_array_compress(Register src, Register dst, Register len, |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5640 |
FloatRegister tmp1Reg, FloatRegister tmp2Reg, |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5641 |
FloatRegister tmp3Reg, FloatRegister tmp4Reg, |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5642 |
Register result) { |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5643 |
encode_iso_array(src, dst, len, result, |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5644 |
tmp1Reg, tmp2Reg, tmp3Reg, tmp4Reg); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5645 |
cmp(len, zr); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
38002
diff
changeset
|
5646 |
csel(result, result, zr, EQ); |
29183 | 5647 |
} |
34633
2a6c7c7b30a7
8132510: Replace ThreadLocalStorage with compiler/language-based thread-local variables
dholmes
parents:
34211
diff
changeset
|
5648 |
|
2a6c7c7b30a7
8132510: Replace ThreadLocalStorage with compiler/language-based thread-local variables
dholmes
parents:
34211
diff
changeset
|
5649 |
// get_thread() can be called anywhere inside generated code so we |
2a6c7c7b30a7
8132510: Replace ThreadLocalStorage with compiler/language-based thread-local variables
dholmes
parents:
34211
diff
changeset
|
5650 |
// need to save whatever non-callee save context might get clobbered |
2a6c7c7b30a7
8132510: Replace ThreadLocalStorage with compiler/language-based thread-local variables
dholmes
parents:
34211
diff
changeset
|
5651 |
// by the call to JavaThread::aarch64_get_thread_helper() or, indeed, |
2a6c7c7b30a7
8132510: Replace ThreadLocalStorage with compiler/language-based thread-local variables
dholmes
parents:
34211
diff
changeset
|
5652 |
// the call setup code. |
2a6c7c7b30a7
8132510: Replace ThreadLocalStorage with compiler/language-based thread-local variables
dholmes
parents:
34211
diff
changeset
|
5653 |
// |
2a6c7c7b30a7
8132510: Replace ThreadLocalStorage with compiler/language-based thread-local variables
dholmes
parents:
34211
diff
changeset
|
5654 |
// aarch64_get_thread_helper() clobbers only r0, r1, and flags. |
2a6c7c7b30a7
8132510: Replace ThreadLocalStorage with compiler/language-based thread-local variables
dholmes
parents:
34211
diff
changeset
|
5655 |
// |
2a6c7c7b30a7
8132510: Replace ThreadLocalStorage with compiler/language-based thread-local variables
dholmes
parents:
34211
diff
changeset
|
5656 |
void MacroAssembler::get_thread(Register dst) { |
2a6c7c7b30a7
8132510: Replace ThreadLocalStorage with compiler/language-based thread-local variables
dholmes
parents:
34211
diff
changeset
|
5657 |
RegSet saved_regs = RegSet::range(r0, r1) + lr - dst; |
2a6c7c7b30a7
8132510: Replace ThreadLocalStorage with compiler/language-based thread-local variables
dholmes
parents:
34211
diff
changeset
|
5658 |
push(saved_regs, sp); |
2a6c7c7b30a7
8132510: Replace ThreadLocalStorage with compiler/language-based thread-local variables
dholmes
parents:
34211
diff
changeset
|
5659 |
|
2a6c7c7b30a7
8132510: Replace ThreadLocalStorage with compiler/language-based thread-local variables
dholmes
parents:
34211
diff
changeset
|
5660 |
mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper)); |
2a6c7c7b30a7
8132510: Replace ThreadLocalStorage with compiler/language-based thread-local variables
dholmes
parents:
34211
diff
changeset
|
5661 |
blrt(lr, 1, 0, 1); |
2a6c7c7b30a7
8132510: Replace ThreadLocalStorage with compiler/language-based thread-local variables
dholmes
parents:
34211
diff
changeset
|
5662 |
if (dst != c_rarg0) { |
2a6c7c7b30a7
8132510: Replace ThreadLocalStorage with compiler/language-based thread-local variables
dholmes
parents:
34211
diff
changeset
|
5663 |
mov(dst, c_rarg0); |
2a6c7c7b30a7
8132510: Replace ThreadLocalStorage with compiler/language-based thread-local variables
dholmes
parents:
34211
diff
changeset
|
5664 |
} |
2a6c7c7b30a7
8132510: Replace ThreadLocalStorage with compiler/language-based thread-local variables
dholmes
parents:
34211
diff
changeset
|
5665 |
|
2a6c7c7b30a7
8132510: Replace ThreadLocalStorage with compiler/language-based thread-local variables
dholmes
parents:
34211
diff
changeset
|
5666 |
pop(saved_regs, sp); |
2a6c7c7b30a7
8132510: Replace ThreadLocalStorage with compiler/language-based thread-local variables
dholmes
parents:
34211
diff
changeset
|
5667 |
} |