hotspot/src/share/vm/opto/mulnode.cpp
author thartmann
Tue, 12 Jan 2016 12:55:09 +0100
changeset 35551 36ef3841fb34
parent 35155 db692d3ebbcc
child 36830 ebc8b5e23f63
permissions -rw-r--r--
8146629: Make phase->is_IterGVN() accessible from Node::Identity and Node::Value Summary: Change arguments of Node::Identity() and Node::Value() from PhaseTransform* to PhaseGVN*. Reviewed-by: kvn, roland
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/*
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 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#include "precompiled.hpp"
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#include "memory/allocation.inline.hpp"
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#include "opto/addnode.hpp"
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#include "opto/connode.hpp"
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#include "opto/convertnode.hpp"
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#include "opto/memnode.hpp"
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#include "opto/mulnode.hpp"
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#include "opto/phaseX.hpp"
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#include "opto/subnode.hpp"
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// Portions of code courtesy of Clifford Click
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//=============================================================================
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//------------------------------hash-------------------------------------------
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// Hash function over MulNodes.  Needs to be commutative; i.e., I swap
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// (commute) inputs to MulNodes willy-nilly so the hash function must return
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// the same value in the presence of edge swapping.
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uint MulNode::hash() const {
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  return (uintptr_t)in(1) + (uintptr_t)in(2) + Opcode();
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}
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//------------------------------Identity---------------------------------------
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// Multiplying a one preserves the other argument
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Node* MulNode::Identity(PhaseGVN* phase) {
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  register const Type *one = mul_id();  // The multiplicative identity
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  if( phase->type( in(1) )->higher_equal( one ) ) return in(2);
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  if( phase->type( in(2) )->higher_equal( one ) ) return in(1);
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  return this;
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}
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//------------------------------Ideal------------------------------------------
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// We also canonicalize the Node, moving constants to the right input,
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// and flatten expressions (so that 1+x+2 becomes x+3).
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Node *MulNode::Ideal(PhaseGVN *phase, bool can_reshape) {
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  const Type *t1 = phase->type( in(1) );
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  const Type *t2 = phase->type( in(2) );
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  Node *progress = NULL;        // Progress flag
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  // We are OK if right is a constant, or right is a load and
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  // left is a non-constant.
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  if( !(t2->singleton() ||
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        (in(2)->is_Load() && !(t1->singleton() || in(1)->is_Load())) ) ) {
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    if( t1->singleton() ||       // Left input is a constant?
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        // Otherwise, sort inputs (commutativity) to help value numbering.
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        (in(1)->_idx > in(2)->_idx) ) {
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      swap_edges(1, 2);
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      const Type *t = t1;
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      t1 = t2;
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      t2 = t;
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      progress = this;            // Made progress
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    }
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  }
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  // If the right input is a constant, and the left input is a product of a
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  // constant, flatten the expression tree.
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  uint op = Opcode();
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  if( t2->singleton() &&        // Right input is a constant?
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      op != Op_MulF &&          // Float & double cannot reassociate
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      op != Op_MulD ) {
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    if( t2 == Type::TOP ) return NULL;
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    Node *mul1 = in(1);
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#ifdef ASSERT
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    // Check for dead loop
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    int   op1 = mul1->Opcode();
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    if( phase->eqv( mul1, this ) || phase->eqv( in(2), this ) ||
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        ( op1 == mul_opcode() || op1 == add_opcode() ) &&
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        ( phase->eqv( mul1->in(1), this ) || phase->eqv( mul1->in(2), this ) ||
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          phase->eqv( mul1->in(1), mul1 ) || phase->eqv( mul1->in(2), mul1 ) ) )
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      assert(false, "dead loop in MulNode::Ideal");
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#endif
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    if( mul1->Opcode() == mul_opcode() ) {  // Left input is a multiply?
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      // Mul of a constant?
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      const Type *t12 = phase->type( mul1->in(2) );
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      if( t12->singleton() && t12 != Type::TOP) { // Left input is an add of a constant?
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        // Compute new constant; check for overflow
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        const Type *tcon01 = ((MulNode*)mul1)->mul_ring(t2,t12);
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        if( tcon01->singleton() ) {
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          // The Mul of the flattened expression
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          set_req(1, mul1->in(1));
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          set_req(2, phase->makecon( tcon01 ));
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          t2 = tcon01;
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          progress = this;      // Made progress
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        }
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      }
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    }
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    // If the right input is a constant, and the left input is an add of a
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    // constant, flatten the tree: (X+con1)*con0 ==> X*con0 + con1*con0
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    const Node *add1 = in(1);
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    if( add1->Opcode() == add_opcode() ) {      // Left input is an add?
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      // Add of a constant?
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      const Type *t12 = phase->type( add1->in(2) );
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      if( t12->singleton() && t12 != Type::TOP ) { // Left input is an add of a constant?
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        assert( add1->in(1) != add1, "dead loop in MulNode::Ideal" );
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        // Compute new constant; check for overflow
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        const Type *tcon01 = mul_ring(t2,t12);
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        if( tcon01->singleton() ) {
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        // Convert (X+con1)*con0 into X*con0
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          Node *mul = clone();    // mul = ()*con0
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          mul->set_req(1,add1->in(1));  // mul = X*con0
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          mul = phase->transform(mul);
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          Node *add2 = add1->clone();
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          add2->set_req(1, mul);        // X*con0 + con0*con1
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          add2->set_req(2, phase->makecon(tcon01) );
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          progress = add2;
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        }
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      }
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    } // End of is left input an add
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  } // End of is right input a Mul
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  return progress;
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}
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//------------------------------Value-----------------------------------------
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const Type* MulNode::Value(PhaseGVN* phase) const {
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  const Type *t1 = phase->type( in(1) );
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  const Type *t2 = phase->type( in(2) );
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  // Either input is TOP ==> the result is TOP
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  if( t1 == Type::TOP ) return Type::TOP;
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  if( t2 == Type::TOP ) return Type::TOP;
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  // Either input is ZERO ==> the result is ZERO.
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  // Not valid for floats or doubles since +0.0 * -0.0 --> +0.0
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  int op = Opcode();
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  if( op == Op_MulI || op == Op_AndI || op == Op_MulL || op == Op_AndL ) {
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    const Type *zero = add_id();        // The multiplicative zero
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    if( t1->higher_equal( zero ) ) return zero;
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    if( t2->higher_equal( zero ) ) return zero;
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  }
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  // Either input is BOTTOM ==> the result is the local BOTTOM
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  if( t1 == Type::BOTTOM || t2 == Type::BOTTOM )
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    return bottom_type();
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#if defined(IA32)
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  // Can't trust native compilers to properly fold strict double
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  // multiplication with round-to-zero on this platform.
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  if (op == Op_MulD && phase->C->method()->is_strict()) {
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    return TypeD::DOUBLE;
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  }
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#endif
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  return mul_ring(t1,t2);            // Local flavor of type multiplication
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}
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//=============================================================================
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//------------------------------Ideal------------------------------------------
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// Check for power-of-2 multiply, then try the regular MulNode::Ideal
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Node *MulINode::Ideal(PhaseGVN *phase, bool can_reshape) {
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  // Swap constant to right
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  jint con;
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  if ((con = in(1)->find_int_con(0)) != 0) {
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    swap_edges(1, 2);
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    // Finish rest of method to use info in 'con'
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  } else if ((con = in(2)->find_int_con(0)) == 0) {
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    return MulNode::Ideal(phase, can_reshape);
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  }
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  // Now we have a constant Node on the right and the constant in con
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  if( con == 0 ) return NULL;   // By zero is handled by Value call
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  if( con == 1 ) return NULL;   // By one  is handled by Identity call
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  // Check for negative constant; if so negate the final result
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  bool sign_flip = false;
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  if( con < 0 ) {
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    con = -con;
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    sign_flip = true;
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  }
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  // Get low bit; check for being the only bit
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  Node *res = NULL;
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  jint bit1 = con & -con;       // Extract low bit
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  if( bit1 == con ) {           // Found a power of 2?
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    res = new LShiftINode( in(1), phase->intcon(log2_intptr(bit1)) );
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  } else {
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    // Check for constant with 2 bits set
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    jint bit2 = con-bit1;
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    bit2 = bit2 & -bit2;          // Extract 2nd bit
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    if( bit2 + bit1 == con ) {    // Found all bits in con?
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      Node *n1 = phase->transform( new LShiftINode( in(1), phase->intcon(log2_intptr(bit1)) ) );
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      Node *n2 = phase->transform( new LShiftINode( in(1), phase->intcon(log2_intptr(bit2)) ) );
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      res = new AddINode( n2, n1 );
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    } else if (is_power_of_2(con+1)) {
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      // Sleezy: power-of-2 -1.  Next time be generic.
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      jint temp = (jint) (con + 1);
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      Node *n1 = phase->transform( new LShiftINode( in(1), phase->intcon(log2_intptr(temp)) ) );
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      res = new SubINode( n1, in(1) );
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    } else {
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      return MulNode::Ideal(phase, can_reshape);
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    }
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  }
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  if( sign_flip ) {             // Need to negate result?
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    res = phase->transform(res);// Transform, before making the zero con
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    res = new SubINode(phase->intcon(0),res);
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  }
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  return res;                   // Return final result
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}
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//------------------------------mul_ring---------------------------------------
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// Compute the product type of two integer ranges into this node.
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const Type *MulINode::mul_ring(const Type *t0, const Type *t1) const {
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  const TypeInt *r0 = t0->is_int(); // Handy access
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  const TypeInt *r1 = t1->is_int();
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  // Fetch endpoints of all ranges
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  int32_t lo0 = r0->_lo;
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  double a = (double)lo0;
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  int32_t hi0 = r0->_hi;
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  double b = (double)hi0;
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  int32_t lo1 = r1->_lo;
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  double c = (double)lo1;
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  int32_t hi1 = r1->_hi;
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  double d = (double)hi1;
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  // Compute all endpoints & check for overflow
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  int32_t A = java_multiply(lo0, lo1);
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  if( (double)A != a*c ) return TypeInt::INT; // Overflow?
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  int32_t B = java_multiply(lo0, hi1);
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  if( (double)B != a*d ) return TypeInt::INT; // Overflow?
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  int32_t C = java_multiply(hi0, lo1);
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  if( (double)C != b*c ) return TypeInt::INT; // Overflow?
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  int32_t D = java_multiply(hi0, hi1);
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  if( (double)D != b*d ) return TypeInt::INT; // Overflow?
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  if( A < B ) { lo0 = A; hi0 = B; } // Sort range endpoints
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  else { lo0 = B; hi0 = A; }
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  if( C < D ) {
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    if( C < lo0 ) lo0 = C;
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    if( D > hi0 ) hi0 = D;
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  } else {
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    if( D < lo0 ) lo0 = D;
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    if( C > hi0 ) hi0 = C;
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  }
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  return TypeInt::make(lo0, hi0, MAX2(r0->_widen,r1->_widen));
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}
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//=============================================================================
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//------------------------------Ideal------------------------------------------
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// Check for power-of-2 multiply, then try the regular MulNode::Ideal
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Node *MulLNode::Ideal(PhaseGVN *phase, bool can_reshape) {
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  // Swap constant to right
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  jlong con;
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  if ((con = in(1)->find_long_con(0)) != 0) {
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    swap_edges(1, 2);
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    // Finish rest of method to use info in 'con'
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  } else if ((con = in(2)->find_long_con(0)) == 0) {
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    return MulNode::Ideal(phase, can_reshape);
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  }
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  // Now we have a constant Node on the right and the constant in con
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  if( con == CONST64(0) ) return NULL;  // By zero is handled by Value call
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  if( con == CONST64(1) ) return NULL;  // By one  is handled by Identity call
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  // Check for negative constant; if so negate the final result
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  bool sign_flip = false;
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  if( con < 0 ) {
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    con = -con;
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    sign_flip = true;
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  }
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  // Get low bit; check for being the only bit
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  Node *res = NULL;
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  jlong bit1 = con & -con;      // Extract low bit
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  if( bit1 == con ) {           // Found a power of 2?
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    res = new LShiftLNode( in(1), phase->intcon(log2_long(bit1)) );
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  } else {
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    // Check for constant with 2 bits set
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    jlong bit2 = con-bit1;
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    bit2 = bit2 & -bit2;          // Extract 2nd bit
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    if( bit2 + bit1 == con ) {    // Found all bits in con?
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      Node *n1 = phase->transform( new LShiftLNode( in(1), phase->intcon(log2_long(bit1)) ) );
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      Node *n2 = phase->transform( new LShiftLNode( in(1), phase->intcon(log2_long(bit2)) ) );
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      res = new AddLNode( n2, n1 );
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    } else if (is_power_of_2_long(con+1)) {
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      // Sleezy: power-of-2 -1.  Next time be generic.
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      jlong temp = (jlong) (con + 1);
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      Node *n1 = phase->transform( new LShiftLNode( in(1), phase->intcon(log2_long(temp)) ) );
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      res = new SubLNode( n1, in(1) );
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    } else {
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      return MulNode::Ideal(phase, can_reshape);
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    }
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  }
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  if( sign_flip ) {             // Need to negate result?
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    res = phase->transform(res);// Transform, before making the zero con
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    res = new SubLNode(phase->longcon(0),res);
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  }
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  return res;                   // Return final result
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}
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//------------------------------mul_ring---------------------------------------
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// Compute the product type of two integer ranges into this node.
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const Type *MulLNode::mul_ring(const Type *t0, const Type *t1) const {
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  const TypeLong *r0 = t0->is_long(); // Handy access
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  const TypeLong *r1 = t1->is_long();
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  // Fetch endpoints of all ranges
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  jlong lo0 = r0->_lo;
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  double a = (double)lo0;
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  jlong hi0 = r0->_hi;
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  double b = (double)hi0;
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  jlong lo1 = r1->_lo;
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  double c = (double)lo1;
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  jlong hi1 = r1->_hi;
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  double d = (double)hi1;
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  // Compute all endpoints & check for overflow
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  jlong A = java_multiply(lo0, lo1);
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  if( (double)A != a*c ) return TypeLong::LONG; // Overflow?
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  jlong B = java_multiply(lo0, hi1);
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  if( (double)B != a*d ) return TypeLong::LONG; // Overflow?
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  jlong C = java_multiply(hi0, lo1);
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  if( (double)C != b*c ) return TypeLong::LONG; // Overflow?
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  jlong D = java_multiply(hi0, hi1);
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  if( (double)D != b*d ) return TypeLong::LONG; // Overflow?
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  if( A < B ) { lo0 = A; hi0 = B; } // Sort range endpoints
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  else { lo0 = B; hi0 = A; }
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  if( C < D ) {
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    if( C < lo0 ) lo0 = C;
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    if( D > hi0 ) hi0 = D;
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  } else {
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    if( D < lo0 ) lo0 = D;
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   360
    if( C > hi0 ) hi0 = C;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   361
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   362
  return TypeLong::make(lo0, hi0, MAX2(r0->_widen,r1->_widen));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   363
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   364
489c9b5090e2 Initial load
duke
parents:
diff changeset
   365
//=============================================================================
489c9b5090e2 Initial load
duke
parents:
diff changeset
   366
//------------------------------mul_ring---------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   367
// Compute the product type of two double ranges into this node.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   368
const Type *MulFNode::mul_ring(const Type *t0, const Type *t1) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   369
  if( t0 == Type::FLOAT || t1 == Type::FLOAT ) return Type::FLOAT;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   370
  return TypeF::make( t0->getf() * t1->getf() );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   371
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   372
489c9b5090e2 Initial load
duke
parents:
diff changeset
   373
//=============================================================================
489c9b5090e2 Initial load
duke
parents:
diff changeset
   374
//------------------------------mul_ring---------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   375
// Compute the product type of two double ranges into this node.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   376
const Type *MulDNode::mul_ring(const Type *t0, const Type *t1) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   377
  if( t0 == Type::DOUBLE || t1 == Type::DOUBLE ) return Type::DOUBLE;
1436
6869d58f4f58 6717150: improper constant folding of subnormal strictfp multiplications and divides
rasbold
parents: 670
diff changeset
   378
  // We must be multiplying 2 double constants.
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   379
  return TypeD::make( t0->getd() * t1->getd() );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   380
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   381
489c9b5090e2 Initial load
duke
parents:
diff changeset
   382
//=============================================================================
392
0b3167e2f2de 6603011: RFE: Optimize long division
rasbold
parents: 1
diff changeset
   383
//------------------------------Value------------------------------------------
35551
36ef3841fb34 8146629: Make phase->is_IterGVN() accessible from Node::Identity and Node::Value
thartmann
parents: 35155
diff changeset
   384
const Type* MulHiLNode::Value(PhaseGVN* phase) const {
392
0b3167e2f2de 6603011: RFE: Optimize long division
rasbold
parents: 1
diff changeset
   385
  // Either input is TOP ==> the result is TOP
0b3167e2f2de 6603011: RFE: Optimize long division
rasbold
parents: 1
diff changeset
   386
  const Type *t1 = phase->type( in(1) );
0b3167e2f2de 6603011: RFE: Optimize long division
rasbold
parents: 1
diff changeset
   387
  const Type *t2 = phase->type( in(2) );
0b3167e2f2de 6603011: RFE: Optimize long division
rasbold
parents: 1
diff changeset
   388
  if( t1 == Type::TOP ) return Type::TOP;
0b3167e2f2de 6603011: RFE: Optimize long division
rasbold
parents: 1
diff changeset
   389
  if( t2 == Type::TOP ) return Type::TOP;
0b3167e2f2de 6603011: RFE: Optimize long division
rasbold
parents: 1
diff changeset
   390
0b3167e2f2de 6603011: RFE: Optimize long division
rasbold
parents: 1
diff changeset
   391
  // Either input is BOTTOM ==> the result is the local BOTTOM
0b3167e2f2de 6603011: RFE: Optimize long division
rasbold
parents: 1
diff changeset
   392
  const Type *bot = bottom_type();
0b3167e2f2de 6603011: RFE: Optimize long division
rasbold
parents: 1
diff changeset
   393
  if( (t1 == bot) || (t2 == bot) ||
0b3167e2f2de 6603011: RFE: Optimize long division
rasbold
parents: 1
diff changeset
   394
      (t1 == Type::BOTTOM) || (t2 == Type::BOTTOM) )
0b3167e2f2de 6603011: RFE: Optimize long division
rasbold
parents: 1
diff changeset
   395
    return bot;
0b3167e2f2de 6603011: RFE: Optimize long division
rasbold
parents: 1
diff changeset
   396
0b3167e2f2de 6603011: RFE: Optimize long division
rasbold
parents: 1
diff changeset
   397
  // It is not worth trying to constant fold this stuff!
0b3167e2f2de 6603011: RFE: Optimize long division
rasbold
parents: 1
diff changeset
   398
  return TypeLong::LONG;
0b3167e2f2de 6603011: RFE: Optimize long division
rasbold
parents: 1
diff changeset
   399
}
0b3167e2f2de 6603011: RFE: Optimize long division
rasbold
parents: 1
diff changeset
   400
0b3167e2f2de 6603011: RFE: Optimize long division
rasbold
parents: 1
diff changeset
   401
//=============================================================================
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   402
//------------------------------mul_ring---------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   403
// Supplied function returns the product of the inputs IN THE CURRENT RING.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   404
// For the logical operations the ring's MUL is really a logical AND function.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   405
// This also type-checks the inputs for sanity.  Guaranteed never to
489c9b5090e2 Initial load
duke
parents:
diff changeset
   406
// be passed a TOP or BOTTOM type, these are filtered out by pre-check.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   407
const Type *AndINode::mul_ring( const Type *t0, const Type *t1 ) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   408
  const TypeInt *r0 = t0->is_int(); // Handy access
489c9b5090e2 Initial load
duke
parents:
diff changeset
   409
  const TypeInt *r1 = t1->is_int();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   410
  int widen = MAX2(r0->_widen,r1->_widen);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   411
489c9b5090e2 Initial load
duke
parents:
diff changeset
   412
  // If either input is a constant, might be able to trim cases
489c9b5090e2 Initial load
duke
parents:
diff changeset
   413
  if( !r0->is_con() && !r1->is_con() )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   414
    return TypeInt::INT;        // No constants to be had
489c9b5090e2 Initial load
duke
parents:
diff changeset
   415
489c9b5090e2 Initial load
duke
parents:
diff changeset
   416
  // Both constants?  Return bits
489c9b5090e2 Initial load
duke
parents:
diff changeset
   417
  if( r0->is_con() && r1->is_con() )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   418
    return TypeInt::make( r0->get_con() & r1->get_con() );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   419
489c9b5090e2 Initial load
duke
parents:
diff changeset
   420
  if( r0->is_con() && r0->get_con() > 0 )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   421
    return TypeInt::make(0, r0->get_con(), widen);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   422
489c9b5090e2 Initial load
duke
parents:
diff changeset
   423
  if( r1->is_con() && r1->get_con() > 0 )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   424
    return TypeInt::make(0, r1->get_con(), widen);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   425
489c9b5090e2 Initial load
duke
parents:
diff changeset
   426
  if( r0 == TypeInt::BOOL || r1 == TypeInt::BOOL ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   427
    return TypeInt::BOOL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   428
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   429
489c9b5090e2 Initial load
duke
parents:
diff changeset
   430
  return TypeInt::INT;          // No constants to be had
489c9b5090e2 Initial load
duke
parents:
diff changeset
   431
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   432
489c9b5090e2 Initial load
duke
parents:
diff changeset
   433
//------------------------------Identity---------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   434
// Masking off the high bits of an unsigned load is not required
35551
36ef3841fb34 8146629: Make phase->is_IterGVN() accessible from Node::Identity and Node::Value
thartmann
parents: 35155
diff changeset
   435
Node* AndINode::Identity(PhaseGVN* phase) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   436
489c9b5090e2 Initial load
duke
parents:
diff changeset
   437
  // x & x => x
489c9b5090e2 Initial load
duke
parents:
diff changeset
   438
  if (phase->eqv(in(1), in(2))) return in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   439
3177
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2150
diff changeset
   440
  Node* in1 = in(1);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2150
diff changeset
   441
  uint op = in1->Opcode();
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2150
diff changeset
   442
  const TypeInt* t2 = phase->type(in(2))->isa_int();
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2150
diff changeset
   443
  if (t2 && t2->is_con()) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   444
    int con = t2->get_con();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   445
    // Masking off high bits which are always zero is useless.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   446
    const TypeInt* t1 = phase->type( in(1) )->isa_int();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   447
    if (t1 != NULL && t1->_lo >= 0) {
3177
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2150
diff changeset
   448
      jint t1_support = right_n_bits(1 + log2_intptr(t1->_hi));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   449
      if ((t1_support & con) == t1_support)
3177
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2150
diff changeset
   450
        return in1;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   451
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   452
    // Masking off the high bits of a unsigned-shift-right is not
489c9b5090e2 Initial load
duke
parents:
diff changeset
   453
    // needed either.
3177
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2150
diff changeset
   454
    if (op == Op_URShiftI) {
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2150
diff changeset
   455
      const TypeInt* t12 = phase->type(in1->in(2))->isa_int();
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2150
diff changeset
   456
      if (t12 && t12->is_con()) {  // Shift is by a constant
2023
10d955a8d972 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 2022
diff changeset
   457
        int shift = t12->get_con();
10d955a8d972 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 2022
diff changeset
   458
        shift &= BitsPerJavaInteger - 1;  // semantics of Java shifts
10d955a8d972 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 2022
diff changeset
   459
        int mask = max_juint >> shift;
3177
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2150
diff changeset
   460
        if ((mask & con) == mask)  // If AND is useless, skip it
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2150
diff changeset
   461
          return in1;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   462
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   463
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   464
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   465
  return MulNode::Identity(phase);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   466
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   467
489c9b5090e2 Initial load
duke
parents:
diff changeset
   468
//------------------------------Ideal------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   469
Node *AndINode::Ideal(PhaseGVN *phase, bool can_reshape) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   470
  // Special case constant AND mask
489c9b5090e2 Initial load
duke
parents:
diff changeset
   471
  const TypeInt *t2 = phase->type( in(2) )->isa_int();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   472
  if( !t2 || !t2->is_con() ) return MulNode::Ideal(phase, can_reshape);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   473
  const int mask = t2->get_con();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   474
  Node *load = in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   475
  uint lop = load->Opcode();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   476
489c9b5090e2 Initial load
duke
parents:
diff changeset
   477
  // Masking bits off of a Character?  Hi bits are already zero.
2022
28ce8115a91d 6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents: 1436
diff changeset
   478
  if( lop == Op_LoadUS &&
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   479
      (mask & 0xFFFF0000) )     // Can we make a smaller mask?
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   480
    return new AndINode(load,phase->intcon(mask&0xFFFF));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   481
489c9b5090e2 Initial load
duke
parents:
diff changeset
   482
  // Masking bits off of a Short?  Loading a Character does some masking
14129
291ac612f0c6 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 13974
diff changeset
   483
  if (can_reshape &&
291ac612f0c6 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 13974
diff changeset
   484
      load->outcnt() == 1 && load->unique_out() == this) {
291ac612f0c6 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 13974
diff changeset
   485
    if (lop == Op_LoadS && (mask & 0xFFFF0000) == 0 ) {
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   486
      Node *ldus = new LoadUSNode(load->in(MemNode::Control),
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   487
                                  load->in(MemNode::Memory),
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   488
                                  load->in(MemNode::Address),
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   489
                                  load->adr_type(),
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   490
                                  TypeInt::CHAR, MemNode::unordered);
14129
291ac612f0c6 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 13974
diff changeset
   491
      ldus = phase->transform(ldus);
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   492
      return new AndINode(ldus, phase->intcon(mask & 0xFFFF));
14129
291ac612f0c6 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 13974
diff changeset
   493
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   494
14129
291ac612f0c6 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 13974
diff changeset
   495
    // Masking sign bits off of a Byte?  Do an unsigned byte load plus
291ac612f0c6 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 13974
diff changeset
   496
    // an and.
291ac612f0c6 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 13974
diff changeset
   497
    if (lop == Op_LoadB && (mask & 0xFFFFFF00) == 0) {
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   498
      Node* ldub = new LoadUBNode(load->in(MemNode::Control),
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   499
                                  load->in(MemNode::Memory),
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   500
                                  load->in(MemNode::Address),
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   501
                                  load->adr_type(),
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   502
                                  TypeInt::UBYTE, MemNode::unordered);
14129
291ac612f0c6 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 13974
diff changeset
   503
      ldub = phase->transform(ldub);
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   504
      return new AndINode(ldub, phase->intcon(mask));
14129
291ac612f0c6 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 13974
diff changeset
   505
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   506
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   507
489c9b5090e2 Initial load
duke
parents:
diff changeset
   508
  // Masking off sign bits?  Dont make them!
489c9b5090e2 Initial load
duke
parents:
diff changeset
   509
  if( lop == Op_RShiftI ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   510
    const TypeInt *t12 = phase->type(load->in(2))->isa_int();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   511
    if( t12 && t12->is_con() ) { // Shift is by a constant
489c9b5090e2 Initial load
duke
parents:
diff changeset
   512
      int shift = t12->get_con();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   513
      shift &= BitsPerJavaInteger-1;  // semantics of Java shifts
489c9b5090e2 Initial load
duke
parents:
diff changeset
   514
      const int sign_bits_mask = ~right_n_bits(BitsPerJavaInteger - shift);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   515
      // If the AND'ing of the 2 masks has no bits, then only original shifted
489c9b5090e2 Initial load
duke
parents:
diff changeset
   516
      // bits survive.  NO sign-extension bits survive the maskings.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   517
      if( (sign_bits_mask & mask) == 0 ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   518
        // Use zero-fill shift instead
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   519
        Node *zshift = phase->transform(new URShiftINode(load->in(1),load->in(2)));
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   520
        return new AndINode( zshift, in(2) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   521
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   522
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   523
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   524
489c9b5090e2 Initial load
duke
parents:
diff changeset
   525
  // Check for 'negate/and-1', a pattern emitted when someone asks for
489c9b5090e2 Initial load
duke
parents:
diff changeset
   526
  // 'mod 2'.  Negate leaves the low order bit unchanged (think: complement
489c9b5090e2 Initial load
duke
parents:
diff changeset
   527
  // plus 1) and the mask is of the low order bit.  Skip the negate.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   528
  if( lop == Op_SubI && mask == 1 && load->in(1) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   529
      phase->type(load->in(1)) == TypeInt::ZERO )
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   530
    return new AndINode( load->in(2), in(2) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   531
489c9b5090e2 Initial load
duke
parents:
diff changeset
   532
  return MulNode::Ideal(phase, can_reshape);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   533
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   534
489c9b5090e2 Initial load
duke
parents:
diff changeset
   535
//=============================================================================
489c9b5090e2 Initial load
duke
parents:
diff changeset
   536
//------------------------------mul_ring---------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   537
// Supplied function returns the product of the inputs IN THE CURRENT RING.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   538
// For the logical operations the ring's MUL is really a logical AND function.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   539
// This also type-checks the inputs for sanity.  Guaranteed never to
489c9b5090e2 Initial load
duke
parents:
diff changeset
   540
// be passed a TOP or BOTTOM type, these are filtered out by pre-check.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   541
const Type *AndLNode::mul_ring( const Type *t0, const Type *t1 ) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   542
  const TypeLong *r0 = t0->is_long(); // Handy access
489c9b5090e2 Initial load
duke
parents:
diff changeset
   543
  const TypeLong *r1 = t1->is_long();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   544
  int widen = MAX2(r0->_widen,r1->_widen);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   545
489c9b5090e2 Initial load
duke
parents:
diff changeset
   546
  // If either input is a constant, might be able to trim cases
489c9b5090e2 Initial load
duke
parents:
diff changeset
   547
  if( !r0->is_con() && !r1->is_con() )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   548
    return TypeLong::LONG;      // No constants to be had
489c9b5090e2 Initial load
duke
parents:
diff changeset
   549
489c9b5090e2 Initial load
duke
parents:
diff changeset
   550
  // Both constants?  Return bits
489c9b5090e2 Initial load
duke
parents:
diff changeset
   551
  if( r0->is_con() && r1->is_con() )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   552
    return TypeLong::make( r0->get_con() & r1->get_con() );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   553
489c9b5090e2 Initial load
duke
parents:
diff changeset
   554
  if( r0->is_con() && r0->get_con() > 0 )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   555
    return TypeLong::make(CONST64(0), r0->get_con(), widen);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   556
489c9b5090e2 Initial load
duke
parents:
diff changeset
   557
  if( r1->is_con() && r1->get_con() > 0 )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   558
    return TypeLong::make(CONST64(0), r1->get_con(), widen);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   559
489c9b5090e2 Initial load
duke
parents:
diff changeset
   560
  return TypeLong::LONG;        // No constants to be had
489c9b5090e2 Initial load
duke
parents:
diff changeset
   561
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   562
489c9b5090e2 Initial load
duke
parents:
diff changeset
   563
//------------------------------Identity---------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   564
// Masking off the high bits of an unsigned load is not required
35551
36ef3841fb34 8146629: Make phase->is_IterGVN() accessible from Node::Identity and Node::Value
thartmann
parents: 35155
diff changeset
   565
Node* AndLNode::Identity(PhaseGVN* phase) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   566
489c9b5090e2 Initial load
duke
parents:
diff changeset
   567
  // x & x => x
489c9b5090e2 Initial load
duke
parents:
diff changeset
   568
  if (phase->eqv(in(1), in(2))) return in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   569
489c9b5090e2 Initial load
duke
parents:
diff changeset
   570
  Node *usr = in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   571
  const TypeLong *t2 = phase->type( in(2) )->isa_long();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   572
  if( t2 && t2->is_con() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   573
    jlong con = t2->get_con();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   574
    // Masking off high bits which are always zero is useless.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   575
    const TypeLong* t1 = phase->type( in(1) )->isa_long();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   576
    if (t1 != NULL && t1->_lo >= 0) {
35155
db692d3ebbcc 8145096: Undefined behaviour in HotSpot
aph
parents: 27471
diff changeset
   577
      int bit_count = log2_long(t1->_hi) + 1;
db692d3ebbcc 8145096: Undefined behaviour in HotSpot
aph
parents: 27471
diff changeset
   578
      jlong t1_support = jlong(max_julong >> (BitsPerJavaLong - bit_count));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   579
      if ((t1_support & con) == t1_support)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   580
        return usr;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   581
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   582
    uint lop = usr->Opcode();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   583
    // Masking off the high bits of a unsigned-shift-right is not
489c9b5090e2 Initial load
duke
parents:
diff changeset
   584
    // needed either.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   585
    if( lop == Op_URShiftL ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   586
      const TypeInt *t12 = phase->type( usr->in(2) )->isa_int();
2023
10d955a8d972 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 2022
diff changeset
   587
      if( t12 && t12->is_con() ) {  // Shift is by a constant
10d955a8d972 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 2022
diff changeset
   588
        int shift = t12->get_con();
10d955a8d972 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 2022
diff changeset
   589
        shift &= BitsPerJavaLong - 1;  // semantics of Java shifts
10d955a8d972 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 2022
diff changeset
   590
        jlong mask = max_julong >> shift;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   591
        if( (mask&con) == mask )  // If AND is useless, skip it
489c9b5090e2 Initial load
duke
parents:
diff changeset
   592
          return usr;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   593
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   594
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   595
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   596
  return MulNode::Identity(phase);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   597
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   598
489c9b5090e2 Initial load
duke
parents:
diff changeset
   599
//------------------------------Ideal------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   600
Node *AndLNode::Ideal(PhaseGVN *phase, bool can_reshape) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   601
  // Special case constant AND mask
489c9b5090e2 Initial load
duke
parents:
diff changeset
   602
  const TypeLong *t2 = phase->type( in(2) )->isa_long();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   603
  if( !t2 || !t2->is_con() ) return MulNode::Ideal(phase, can_reshape);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   604
  const jlong mask = t2->get_con();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   605
2150
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2023
diff changeset
   606
  Node* in1 = in(1);
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2023
diff changeset
   607
  uint op = in1->Opcode();
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2023
diff changeset
   608
3177
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2150
diff changeset
   609
  // Are we masking a long that was converted from an int with a mask
3597
572bbef24585 6863155: Server compiler generates incorrect code (x86, long, bitshift, bitmask)
twisti
parents: 3177
diff changeset
   610
  // that fits in 32-bits?  Commute them and use an AndINode.  Don't
572bbef24585 6863155: Server compiler generates incorrect code (x86, long, bitshift, bitmask)
twisti
parents: 3177
diff changeset
   611
  // convert masks which would cause a sign extension of the integer
572bbef24585 6863155: Server compiler generates incorrect code (x86, long, bitshift, bitmask)
twisti
parents: 3177
diff changeset
   612
  // value.  This check includes UI2L masks (0x00000000FFFFFFFF) which
572bbef24585 6863155: Server compiler generates incorrect code (x86, long, bitshift, bitmask)
twisti
parents: 3177
diff changeset
   613
  // would be optimized away later in Identity.
27471
6e56277909f1 8062370: Various minor code improvements
goetz
parents: 24923
diff changeset
   614
  if (op == Op_ConvI2L && (mask & UCONST64(0xFFFFFFFF80000000)) == 0) {
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   615
    Node* andi = new AndINode(in1->in(1), phase->intcon(mask));
3597
572bbef24585 6863155: Server compiler generates incorrect code (x86, long, bitshift, bitmask)
twisti
parents: 3177
diff changeset
   616
    andi = phase->transform(andi);
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   617
    return new ConvI2LNode(andi);
3177
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2150
diff changeset
   618
  }
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2150
diff changeset
   619
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   620
  // Masking off sign bits?  Dont make them!
2150
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2023
diff changeset
   621
  if (op == Op_RShiftL) {
3177
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2150
diff changeset
   622
    const TypeInt* t12 = phase->type(in1->in(2))->isa_int();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   623
    if( t12 && t12->is_con() ) { // Shift is by a constant
489c9b5090e2 Initial load
duke
parents:
diff changeset
   624
      int shift = t12->get_con();
2023
10d955a8d972 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 2022
diff changeset
   625
      shift &= BitsPerJavaLong - 1;  // semantics of Java shifts
10d955a8d972 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 2022
diff changeset
   626
      const jlong sign_bits_mask = ~(((jlong)CONST64(1) << (jlong)(BitsPerJavaLong - shift)) -1);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   627
      // If the AND'ing of the 2 masks has no bits, then only original shifted
489c9b5090e2 Initial load
duke
parents:
diff changeset
   628
      // bits survive.  NO sign-extension bits survive the maskings.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   629
      if( (sign_bits_mask & mask) == 0 ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   630
        // Use zero-fill shift instead
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   631
        Node *zshift = phase->transform(new URShiftLNode(in1->in(1), in1->in(2)));
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   632
        return new AndLNode(zshift, in(2));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   633
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   634
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   635
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   636
489c9b5090e2 Initial load
duke
parents:
diff changeset
   637
  return MulNode::Ideal(phase, can_reshape);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   638
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   639
489c9b5090e2 Initial load
duke
parents:
diff changeset
   640
//=============================================================================
489c9b5090e2 Initial load
duke
parents:
diff changeset
   641
//------------------------------Identity---------------------------------------
35551
36ef3841fb34 8146629: Make phase->is_IterGVN() accessible from Node::Identity and Node::Value
thartmann
parents: 35155
diff changeset
   642
Node* LShiftINode::Identity(PhaseGVN* phase) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   643
  const TypeInt *ti = phase->type( in(2) )->isa_int();  // shift count is an int
489c9b5090e2 Initial load
duke
parents:
diff changeset
   644
  return ( ti && ti->is_con() && ( ti->get_con() & ( BitsPerInt - 1 ) ) == 0 ) ? in(1) : this;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   645
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   646
489c9b5090e2 Initial load
duke
parents:
diff changeset
   647
//------------------------------Ideal------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   648
// If the right input is a constant, and the left input is an add of a
489c9b5090e2 Initial load
duke
parents:
diff changeset
   649
// constant, flatten the tree: (X+con1)<<con0 ==> X<<con0 + con1<<con0
489c9b5090e2 Initial load
duke
parents:
diff changeset
   650
Node *LShiftINode::Ideal(PhaseGVN *phase, bool can_reshape) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   651
  const Type *t  = phase->type( in(2) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   652
  if( t == Type::TOP ) return NULL;       // Right input is dead
489c9b5090e2 Initial load
duke
parents:
diff changeset
   653
  const TypeInt *t2 = t->isa_int();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   654
  if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
489c9b5090e2 Initial load
duke
parents:
diff changeset
   655
  const int con = t2->get_con() & ( BitsPerInt - 1 );  // masked shift count
489c9b5090e2 Initial load
duke
parents:
diff changeset
   656
489c9b5090e2 Initial load
duke
parents:
diff changeset
   657
  if ( con == 0 )  return NULL; // let Identity() handle 0 shift count
489c9b5090e2 Initial load
duke
parents:
diff changeset
   658
489c9b5090e2 Initial load
duke
parents:
diff changeset
   659
  // Left input is an add of a constant?
489c9b5090e2 Initial load
duke
parents:
diff changeset
   660
  Node *add1 = in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   661
  int add1_op = add1->Opcode();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   662
  if( add1_op == Op_AddI ) {    // Left input is an add?
489c9b5090e2 Initial load
duke
parents:
diff changeset
   663
    assert( add1 != add1->in(1), "dead loop in LShiftINode::Ideal" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   664
    const TypeInt *t12 = phase->type(add1->in(2))->isa_int();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   665
    if( t12 && t12->is_con() ){ // Left input is an add of a con?
489c9b5090e2 Initial load
duke
parents:
diff changeset
   666
      // Transform is legal, but check for profit.  Avoid breaking 'i2s'
489c9b5090e2 Initial load
duke
parents:
diff changeset
   667
      // and 'i2b' patterns which typically fold into 'StoreC/StoreB'.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   668
      if( con < 16 ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   669
        // Compute X << con0
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   670
        Node *lsh = phase->transform( new LShiftINode( add1->in(1), in(2) ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   671
        // Compute X<<con0 + (con1<<con0)
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   672
        return new AddINode( lsh, phase->intcon(t12->get_con() << con));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   673
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   674
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   675
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   676
489c9b5090e2 Initial load
duke
parents:
diff changeset
   677
  // Check for "(x>>c0)<<c0" which just masks off low bits
489c9b5090e2 Initial load
duke
parents:
diff changeset
   678
  if( (add1_op == Op_RShiftI || add1_op == Op_URShiftI ) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   679
      add1->in(2) == in(2) )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   680
    // Convert to "(x & -(1<<c0))"
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   681
    return new AndINode(add1->in(1),phase->intcon( -(1<<con)));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   682
489c9b5090e2 Initial load
duke
parents:
diff changeset
   683
  // Check for "((x>>c0) & Y)<<c0" which just masks off more low bits
489c9b5090e2 Initial load
duke
parents:
diff changeset
   684
  if( add1_op == Op_AndI ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   685
    Node *add2 = add1->in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   686
    int add2_op = add2->Opcode();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   687
    if( (add2_op == Op_RShiftI || add2_op == Op_URShiftI ) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   688
        add2->in(2) == in(2) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   689
      // Convert to "(x & (Y<<c0))"
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   690
      Node *y_sh = phase->transform( new LShiftINode( add1->in(2), in(2) ) );
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   691
      return new AndINode( add2->in(1), y_sh );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   692
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   693
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   694
489c9b5090e2 Initial load
duke
parents:
diff changeset
   695
  // Check for ((x & ((1<<(32-c0))-1)) << c0) which ANDs off high bits
489c9b5090e2 Initial load
duke
parents:
diff changeset
   696
  // before shifting them away.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   697
  const jint bits_mask = right_n_bits(BitsPerJavaInteger-con);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   698
  if( add1_op == Op_AndI &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   699
      phase->type(add1->in(2)) == TypeInt::make( bits_mask ) )
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   700
    return new LShiftINode( add1->in(1), in(2) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   701
489c9b5090e2 Initial load
duke
parents:
diff changeset
   702
  return NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   703
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   704
489c9b5090e2 Initial load
duke
parents:
diff changeset
   705
//------------------------------Value------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   706
// A LShiftINode shifts its input2 left by input1 amount.
35551
36ef3841fb34 8146629: Make phase->is_IterGVN() accessible from Node::Identity and Node::Value
thartmann
parents: 35155
diff changeset
   707
const Type* LShiftINode::Value(PhaseGVN* phase) const {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   708
  const Type *t1 = phase->type( in(1) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   709
  const Type *t2 = phase->type( in(2) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   710
  // Either input is TOP ==> the result is TOP
489c9b5090e2 Initial load
duke
parents:
diff changeset
   711
  if( t1 == Type::TOP ) return Type::TOP;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   712
  if( t2 == Type::TOP ) return Type::TOP;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   713
489c9b5090e2 Initial load
duke
parents:
diff changeset
   714
  // Left input is ZERO ==> the result is ZERO.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   715
  if( t1 == TypeInt::ZERO ) return TypeInt::ZERO;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   716
  // Shift by zero does nothing
489c9b5090e2 Initial load
duke
parents:
diff changeset
   717
  if( t2 == TypeInt::ZERO ) return t1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   718
489c9b5090e2 Initial load
duke
parents:
diff changeset
   719
  // Either input is BOTTOM ==> the result is BOTTOM
489c9b5090e2 Initial load
duke
parents:
diff changeset
   720
  if( (t1 == TypeInt::INT) || (t2 == TypeInt::INT) ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
   721
      (t1 == Type::BOTTOM) || (t2 == Type::BOTTOM) )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   722
    return TypeInt::INT;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   723
489c9b5090e2 Initial load
duke
parents:
diff changeset
   724
  const TypeInt *r1 = t1->is_int(); // Handy access
489c9b5090e2 Initial load
duke
parents:
diff changeset
   725
  const TypeInt *r2 = t2->is_int(); // Handy access
489c9b5090e2 Initial load
duke
parents:
diff changeset
   726
489c9b5090e2 Initial load
duke
parents:
diff changeset
   727
  if (!r2->is_con())
489c9b5090e2 Initial load
duke
parents:
diff changeset
   728
    return TypeInt::INT;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   729
489c9b5090e2 Initial load
duke
parents:
diff changeset
   730
  uint shift = r2->get_con();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   731
  shift &= BitsPerJavaInteger-1;  // semantics of Java shifts
489c9b5090e2 Initial load
duke
parents:
diff changeset
   732
  // Shift by a multiple of 32 does nothing:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   733
  if (shift == 0)  return t1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   734
489c9b5090e2 Initial load
duke
parents:
diff changeset
   735
  // If the shift is a constant, shift the bounds of the type,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   736
  // unless this could lead to an overflow.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   737
  if (!r1->is_con()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   738
    jint lo = r1->_lo, hi = r1->_hi;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   739
    if (((lo << shift) >> shift) == lo &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   740
        ((hi << shift) >> shift) == hi) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   741
      // No overflow.  The range shifts up cleanly.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   742
      return TypeInt::make((jint)lo << (jint)shift,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   743
                           (jint)hi << (jint)shift,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   744
                           MAX2(r1->_widen,r2->_widen));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   745
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   746
    return TypeInt::INT;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   747
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   748
489c9b5090e2 Initial load
duke
parents:
diff changeset
   749
  return TypeInt::make( (jint)r1->get_con() << (jint)shift );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   750
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   751
489c9b5090e2 Initial load
duke
parents:
diff changeset
   752
//=============================================================================
489c9b5090e2 Initial load
duke
parents:
diff changeset
   753
//------------------------------Identity---------------------------------------
35551
36ef3841fb34 8146629: Make phase->is_IterGVN() accessible from Node::Identity and Node::Value
thartmann
parents: 35155
diff changeset
   754
Node* LShiftLNode::Identity(PhaseGVN* phase) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   755
  const TypeInt *ti = phase->type( in(2) )->isa_int(); // shift count is an int
489c9b5090e2 Initial load
duke
parents:
diff changeset
   756
  return ( ti && ti->is_con() && ( ti->get_con() & ( BitsPerLong - 1 ) ) == 0 ) ? in(1) : this;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   757
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   758
489c9b5090e2 Initial load
duke
parents:
diff changeset
   759
//------------------------------Ideal------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   760
// If the right input is a constant, and the left input is an add of a
489c9b5090e2 Initial load
duke
parents:
diff changeset
   761
// constant, flatten the tree: (X+con1)<<con0 ==> X<<con0 + con1<<con0
489c9b5090e2 Initial load
duke
parents:
diff changeset
   762
Node *LShiftLNode::Ideal(PhaseGVN *phase, bool can_reshape) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   763
  const Type *t  = phase->type( in(2) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   764
  if( t == Type::TOP ) return NULL;       // Right input is dead
489c9b5090e2 Initial load
duke
parents:
diff changeset
   765
  const TypeInt *t2 = t->isa_int();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   766
  if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
489c9b5090e2 Initial load
duke
parents:
diff changeset
   767
  const int con = t2->get_con() & ( BitsPerLong - 1 );  // masked shift count
489c9b5090e2 Initial load
duke
parents:
diff changeset
   768
489c9b5090e2 Initial load
duke
parents:
diff changeset
   769
  if ( con == 0 ) return NULL;  // let Identity() handle 0 shift count
489c9b5090e2 Initial load
duke
parents:
diff changeset
   770
489c9b5090e2 Initial load
duke
parents:
diff changeset
   771
  // Left input is an add of a constant?
489c9b5090e2 Initial load
duke
parents:
diff changeset
   772
  Node *add1 = in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   773
  int add1_op = add1->Opcode();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   774
  if( add1_op == Op_AddL ) {    // Left input is an add?
489c9b5090e2 Initial load
duke
parents:
diff changeset
   775
    // Avoid dead data cycles from dead loops
489c9b5090e2 Initial load
duke
parents:
diff changeset
   776
    assert( add1 != add1->in(1), "dead loop in LShiftLNode::Ideal" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   777
    const TypeLong *t12 = phase->type(add1->in(2))->isa_long();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   778
    if( t12 && t12->is_con() ){ // Left input is an add of a con?
489c9b5090e2 Initial load
duke
parents:
diff changeset
   779
      // Compute X << con0
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   780
      Node *lsh = phase->transform( new LShiftLNode( add1->in(1), in(2) ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   781
      // Compute X<<con0 + (con1<<con0)
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   782
      return new AddLNode( lsh, phase->longcon(t12->get_con() << con));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   783
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   784
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   785
489c9b5090e2 Initial load
duke
parents:
diff changeset
   786
  // Check for "(x>>c0)<<c0" which just masks off low bits
489c9b5090e2 Initial load
duke
parents:
diff changeset
   787
  if( (add1_op == Op_RShiftL || add1_op == Op_URShiftL ) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   788
      add1->in(2) == in(2) )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   789
    // Convert to "(x & -(1<<c0))"
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   790
    return new AndLNode(add1->in(1),phase->longcon( -(CONST64(1)<<con)));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   791
489c9b5090e2 Initial load
duke
parents:
diff changeset
   792
  // Check for "((x>>c0) & Y)<<c0" which just masks off more low bits
489c9b5090e2 Initial load
duke
parents:
diff changeset
   793
  if( add1_op == Op_AndL ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   794
    Node *add2 = add1->in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   795
    int add2_op = add2->Opcode();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   796
    if( (add2_op == Op_RShiftL || add2_op == Op_URShiftL ) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   797
        add2->in(2) == in(2) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   798
      // Convert to "(x & (Y<<c0))"
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   799
      Node *y_sh = phase->transform( new LShiftLNode( add1->in(2), in(2) ) );
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   800
      return new AndLNode( add2->in(1), y_sh );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   801
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   802
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   803
489c9b5090e2 Initial load
duke
parents:
diff changeset
   804
  // Check for ((x & ((CONST64(1)<<(64-c0))-1)) << c0) which ANDs off high bits
489c9b5090e2 Initial load
duke
parents:
diff changeset
   805
  // before shifting them away.
35155
db692d3ebbcc 8145096: Undefined behaviour in HotSpot
aph
parents: 27471
diff changeset
   806
  const jlong bits_mask = jlong(max_julong >> con);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   807
  if( add1_op == Op_AndL &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   808
      phase->type(add1->in(2)) == TypeLong::make( bits_mask ) )
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   809
    return new LShiftLNode( add1->in(1), in(2) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   810
489c9b5090e2 Initial load
duke
parents:
diff changeset
   811
  return NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   812
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   813
489c9b5090e2 Initial load
duke
parents:
diff changeset
   814
//------------------------------Value------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   815
// A LShiftLNode shifts its input2 left by input1 amount.
35551
36ef3841fb34 8146629: Make phase->is_IterGVN() accessible from Node::Identity and Node::Value
thartmann
parents: 35155
diff changeset
   816
const Type* LShiftLNode::Value(PhaseGVN* phase) const {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   817
  const Type *t1 = phase->type( in(1) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   818
  const Type *t2 = phase->type( in(2) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   819
  // Either input is TOP ==> the result is TOP
489c9b5090e2 Initial load
duke
parents:
diff changeset
   820
  if( t1 == Type::TOP ) return Type::TOP;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   821
  if( t2 == Type::TOP ) return Type::TOP;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   822
489c9b5090e2 Initial load
duke
parents:
diff changeset
   823
  // Left input is ZERO ==> the result is ZERO.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   824
  if( t1 == TypeLong::ZERO ) return TypeLong::ZERO;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   825
  // Shift by zero does nothing
489c9b5090e2 Initial load
duke
parents:
diff changeset
   826
  if( t2 == TypeInt::ZERO ) return t1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   827
489c9b5090e2 Initial load
duke
parents:
diff changeset
   828
  // Either input is BOTTOM ==> the result is BOTTOM
489c9b5090e2 Initial load
duke
parents:
diff changeset
   829
  if( (t1 == TypeLong::LONG) || (t2 == TypeInt::INT) ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
   830
      (t1 == Type::BOTTOM) || (t2 == Type::BOTTOM) )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   831
    return TypeLong::LONG;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   832
489c9b5090e2 Initial load
duke
parents:
diff changeset
   833
  const TypeLong *r1 = t1->is_long(); // Handy access
489c9b5090e2 Initial load
duke
parents:
diff changeset
   834
  const TypeInt  *r2 = t2->is_int();  // Handy access
489c9b5090e2 Initial load
duke
parents:
diff changeset
   835
489c9b5090e2 Initial load
duke
parents:
diff changeset
   836
  if (!r2->is_con())
489c9b5090e2 Initial load
duke
parents:
diff changeset
   837
    return TypeLong::LONG;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   838
489c9b5090e2 Initial load
duke
parents:
diff changeset
   839
  uint shift = r2->get_con();
2023
10d955a8d972 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 2022
diff changeset
   840
  shift &= BitsPerJavaLong - 1;  // semantics of Java shifts
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   841
  // Shift by a multiple of 64 does nothing:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   842
  if (shift == 0)  return t1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   843
489c9b5090e2 Initial load
duke
parents:
diff changeset
   844
  // If the shift is a constant, shift the bounds of the type,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   845
  // unless this could lead to an overflow.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   846
  if (!r1->is_con()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   847
    jlong lo = r1->_lo, hi = r1->_hi;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   848
    if (((lo << shift) >> shift) == lo &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   849
        ((hi << shift) >> shift) == hi) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   850
      // No overflow.  The range shifts up cleanly.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   851
      return TypeLong::make((jlong)lo << (jint)shift,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   852
                            (jlong)hi << (jint)shift,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   853
                            MAX2(r1->_widen,r2->_widen));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   854
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   855
    return TypeLong::LONG;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   856
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   857
489c9b5090e2 Initial load
duke
parents:
diff changeset
   858
  return TypeLong::make( (jlong)r1->get_con() << (jint)shift );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   859
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   860
489c9b5090e2 Initial load
duke
parents:
diff changeset
   861
//=============================================================================
489c9b5090e2 Initial load
duke
parents:
diff changeset
   862
//------------------------------Identity---------------------------------------
35551
36ef3841fb34 8146629: Make phase->is_IterGVN() accessible from Node::Identity and Node::Value
thartmann
parents: 35155
diff changeset
   863
Node* RShiftINode::Identity(PhaseGVN* phase) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   864
  const TypeInt *t2 = phase->type(in(2))->isa_int();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   865
  if( !t2 ) return this;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   866
  if ( t2->is_con() && ( t2->get_con() & ( BitsPerInt - 1 ) ) == 0 )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   867
    return in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   868
489c9b5090e2 Initial load
duke
parents:
diff changeset
   869
  // Check for useless sign-masking
489c9b5090e2 Initial load
duke
parents:
diff changeset
   870
  if( in(1)->Opcode() == Op_LShiftI &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   871
      in(1)->req() == 3 &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   872
      in(1)->in(2) == in(2) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   873
      t2->is_con() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   874
    uint shift = t2->get_con();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   875
    shift &= BitsPerJavaInteger-1; // semantics of Java shifts
489c9b5090e2 Initial load
duke
parents:
diff changeset
   876
    // Compute masks for which this shifting doesn't change
489c9b5090e2 Initial load
duke
parents:
diff changeset
   877
    int lo = (-1 << (BitsPerJavaInteger - shift-1)); // FFFF8000
489c9b5090e2 Initial load
duke
parents:
diff changeset
   878
    int hi = ~lo;               // 00007FFF
489c9b5090e2 Initial load
duke
parents:
diff changeset
   879
    const TypeInt *t11 = phase->type(in(1)->in(1))->isa_int();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   880
    if( !t11 ) return this;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   881
    // Does actual value fit inside of mask?
489c9b5090e2 Initial load
duke
parents:
diff changeset
   882
    if( lo <= t11->_lo && t11->_hi <= hi )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   883
      return in(1)->in(1);      // Then shifting is a nop
489c9b5090e2 Initial load
duke
parents:
diff changeset
   884
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   885
489c9b5090e2 Initial load
duke
parents:
diff changeset
   886
  return this;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   887
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   888
489c9b5090e2 Initial load
duke
parents:
diff changeset
   889
//------------------------------Ideal------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   890
Node *RShiftINode::Ideal(PhaseGVN *phase, bool can_reshape) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   891
  // Inputs may be TOP if they are dead.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   892
  const TypeInt *t1 = phase->type( in(1) )->isa_int();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   893
  if( !t1 ) return NULL;        // Left input is an integer
489c9b5090e2 Initial load
duke
parents:
diff changeset
   894
  const TypeInt *t2 = phase->type( in(2) )->isa_int();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   895
  if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
489c9b5090e2 Initial load
duke
parents:
diff changeset
   896
  const TypeInt *t3;  // type of in(1).in(2)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   897
  int shift = t2->get_con();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   898
  shift &= BitsPerJavaInteger-1;  // semantics of Java shifts
489c9b5090e2 Initial load
duke
parents:
diff changeset
   899
489c9b5090e2 Initial load
duke
parents:
diff changeset
   900
  if ( shift == 0 ) return NULL;  // let Identity() handle 0 shift count
489c9b5090e2 Initial load
duke
parents:
diff changeset
   901
489c9b5090e2 Initial load
duke
parents:
diff changeset
   902
  // Check for (x & 0xFF000000) >> 24, whose mask can be made smaller.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   903
  // Such expressions arise normally from shift chains like (byte)(x >> 24).
489c9b5090e2 Initial load
duke
parents:
diff changeset
   904
  const Node *mask = in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   905
  if( mask->Opcode() == Op_AndI &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   906
      (t3 = phase->type(mask->in(2))->isa_int()) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   907
      t3->is_con() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   908
    Node *x = mask->in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   909
    jint maskbits = t3->get_con();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   910
    // Convert to "(x >> shift) & (mask >> shift)"
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   911
    Node *shr_nomask = phase->transform( new RShiftINode(mask->in(1), in(2)) );
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   912
    return new AndINode(shr_nomask, phase->intcon( maskbits >> shift));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   913
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   914
489c9b5090e2 Initial load
duke
parents:
diff changeset
   915
  // Check for "(short[i] <<16)>>16" which simply sign-extends
489c9b5090e2 Initial load
duke
parents:
diff changeset
   916
  const Node *shl = in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   917
  if( shl->Opcode() != Op_LShiftI ) return NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   918
489c9b5090e2 Initial load
duke
parents:
diff changeset
   919
  if( shift == 16 &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   920
      (t3 = phase->type(shl->in(2))->isa_int()) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   921
      t3->is_con(16) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   922
    Node *ld = shl->in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   923
    if( ld->Opcode() == Op_LoadS ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   924
      // Sign extension is just useless here.  Return a RShiftI of zero instead
489c9b5090e2 Initial load
duke
parents:
diff changeset
   925
      // returning 'ld' directly.  We cannot return an old Node directly as
489c9b5090e2 Initial load
duke
parents:
diff changeset
   926
      // that is the job of 'Identity' calls and Identity calls only work on
489c9b5090e2 Initial load
duke
parents:
diff changeset
   927
      // direct inputs ('ld' is an extra Node removed from 'this').  The
489c9b5090e2 Initial load
duke
parents:
diff changeset
   928
      // combined optimization requires Identity only return direct inputs.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   929
      set_req(1, ld);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   930
      set_req(2, phase->intcon(0));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   931
      return this;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   932
    }
14129
291ac612f0c6 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 13974
diff changeset
   933
    else if( can_reshape &&
291ac612f0c6 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 13974
diff changeset
   934
             ld->Opcode() == Op_LoadUS &&
291ac612f0c6 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 13974
diff changeset
   935
             ld->outcnt() == 1 && ld->unique_out() == shl)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   936
      // Replace zero-extension-load with sign-extension-load
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   937
      return new LoadSNode( ld->in(MemNode::Control),
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   938
                            ld->in(MemNode::Memory),
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   939
                            ld->in(MemNode::Address),
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   940
                            ld->adr_type(), TypeInt::SHORT,
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
   941
                            MemNode::unordered);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   942
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   943
489c9b5090e2 Initial load
duke
parents:
diff changeset
   944
  // Check for "(byte[i] <<24)>>24" which simply sign-extends
489c9b5090e2 Initial load
duke
parents:
diff changeset
   945
  if( shift == 24 &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   946
      (t3 = phase->type(shl->in(2))->isa_int()) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   947
      t3->is_con(24) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   948
    Node *ld = shl->in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   949
    if( ld->Opcode() == Op_LoadB ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   950
      // Sign extension is just useless here
489c9b5090e2 Initial load
duke
parents:
diff changeset
   951
      set_req(1, ld);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   952
      set_req(2, phase->intcon(0));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   953
      return this;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   954
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   955
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   956
489c9b5090e2 Initial load
duke
parents:
diff changeset
   957
  return NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   958
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   959
489c9b5090e2 Initial load
duke
parents:
diff changeset
   960
//------------------------------Value------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   961
// A RShiftINode shifts its input2 right by input1 amount.
35551
36ef3841fb34 8146629: Make phase->is_IterGVN() accessible from Node::Identity and Node::Value
thartmann
parents: 35155
diff changeset
   962
const Type* RShiftINode::Value(PhaseGVN* phase) const {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   963
  const Type *t1 = phase->type( in(1) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   964
  const Type *t2 = phase->type( in(2) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   965
  // Either input is TOP ==> the result is TOP
489c9b5090e2 Initial load
duke
parents:
diff changeset
   966
  if( t1 == Type::TOP ) return Type::TOP;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   967
  if( t2 == Type::TOP ) return Type::TOP;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   968
489c9b5090e2 Initial load
duke
parents:
diff changeset
   969
  // Left input is ZERO ==> the result is ZERO.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   970
  if( t1 == TypeInt::ZERO ) return TypeInt::ZERO;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   971
  // Shift by zero does nothing
489c9b5090e2 Initial load
duke
parents:
diff changeset
   972
  if( t2 == TypeInt::ZERO ) return t1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   973
489c9b5090e2 Initial load
duke
parents:
diff changeset
   974
  // Either input is BOTTOM ==> the result is BOTTOM
489c9b5090e2 Initial load
duke
parents:
diff changeset
   975
  if (t1 == Type::BOTTOM || t2 == Type::BOTTOM)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   976
    return TypeInt::INT;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   977
489c9b5090e2 Initial load
duke
parents:
diff changeset
   978
  if (t2 == TypeInt::INT)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   979
    return TypeInt::INT;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   980
489c9b5090e2 Initial load
duke
parents:
diff changeset
   981
  const TypeInt *r1 = t1->is_int(); // Handy access
489c9b5090e2 Initial load
duke
parents:
diff changeset
   982
  const TypeInt *r2 = t2->is_int(); // Handy access
489c9b5090e2 Initial load
duke
parents:
diff changeset
   983
489c9b5090e2 Initial load
duke
parents:
diff changeset
   984
  // If the shift is a constant, just shift the bounds of the type.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   985
  // For example, if the shift is 31, we just propagate sign bits.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   986
  if (r2->is_con()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   987
    uint shift = r2->get_con();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   988
    shift &= BitsPerJavaInteger-1;  // semantics of Java shifts
489c9b5090e2 Initial load
duke
parents:
diff changeset
   989
    // Shift by a multiple of 32 does nothing:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   990
    if (shift == 0)  return t1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   991
    // Calculate reasonably aggressive bounds for the result.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   992
    // This is necessary if we are to correctly type things
489c9b5090e2 Initial load
duke
parents:
diff changeset
   993
    // like (x<<24>>24) == ((byte)x).
489c9b5090e2 Initial load
duke
parents:
diff changeset
   994
    jint lo = (jint)r1->_lo >> (jint)shift;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   995
    jint hi = (jint)r1->_hi >> (jint)shift;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   996
    assert(lo <= hi, "must have valid bounds");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   997
    const TypeInt* ti = TypeInt::make(lo, hi, MAX2(r1->_widen,r2->_widen));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   998
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   999
    // Make sure we get the sign-capture idiom correct.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1000
    if (shift == BitsPerJavaInteger-1) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1001
      if (r1->_lo >= 0) assert(ti == TypeInt::ZERO,    ">>31 of + is  0");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1002
      if (r1->_hi <  0) assert(ti == TypeInt::MINUS_1, ">>31 of - is -1");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1003
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1004
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1005
    return ti;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1006
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1007
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1008
  if( !r1->is_con() || !r2->is_con() )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1009
    return TypeInt::INT;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1010
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1011
  // Signed shift right
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1012
  return TypeInt::make( r1->get_con() >> (r2->get_con()&31) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1013
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1014
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1015
//=============================================================================
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1016
//------------------------------Identity---------------------------------------
35551
36ef3841fb34 8146629: Make phase->is_IterGVN() accessible from Node::Identity and Node::Value
thartmann
parents: 35155
diff changeset
  1017
Node* RShiftLNode::Identity(PhaseGVN* phase) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1018
  const TypeInt *ti = phase->type( in(2) )->isa_int(); // shift count is an int
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1019
  return ( ti && ti->is_con() && ( ti->get_con() & ( BitsPerLong - 1 ) ) == 0 ) ? in(1) : this;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1020
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1021
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1022
//------------------------------Value------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1023
// A RShiftLNode shifts its input2 right by input1 amount.
35551
36ef3841fb34 8146629: Make phase->is_IterGVN() accessible from Node::Identity and Node::Value
thartmann
parents: 35155
diff changeset
  1024
const Type* RShiftLNode::Value(PhaseGVN* phase) const {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1025
  const Type *t1 = phase->type( in(1) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1026
  const Type *t2 = phase->type( in(2) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1027
  // Either input is TOP ==> the result is TOP
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1028
  if( t1 == Type::TOP ) return Type::TOP;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1029
  if( t2 == Type::TOP ) return Type::TOP;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1030
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1031
  // Left input is ZERO ==> the result is ZERO.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1032
  if( t1 == TypeLong::ZERO ) return TypeLong::ZERO;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1033
  // Shift by zero does nothing
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1034
  if( t2 == TypeInt::ZERO ) return t1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1035
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1036
  // Either input is BOTTOM ==> the result is BOTTOM
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1037
  if (t1 == Type::BOTTOM || t2 == Type::BOTTOM)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1038
    return TypeLong::LONG;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1039
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1040
  if (t2 == TypeInt::INT)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1041
    return TypeLong::LONG;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1042
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1043
  const TypeLong *r1 = t1->is_long(); // Handy access
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1044
  const TypeInt  *r2 = t2->is_int (); // Handy access
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1045
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1046
  // If the shift is a constant, just shift the bounds of the type.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1047
  // For example, if the shift is 63, we just propagate sign bits.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1048
  if (r2->is_con()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1049
    uint shift = r2->get_con();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1050
    shift &= (2*BitsPerJavaInteger)-1;  // semantics of Java shifts
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1051
    // Shift by a multiple of 64 does nothing:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1052
    if (shift == 0)  return t1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1053
    // Calculate reasonably aggressive bounds for the result.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1054
    // This is necessary if we are to correctly type things
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1055
    // like (x<<24>>24) == ((byte)x).
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1056
    jlong lo = (jlong)r1->_lo >> (jlong)shift;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1057
    jlong hi = (jlong)r1->_hi >> (jlong)shift;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1058
    assert(lo <= hi, "must have valid bounds");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1059
    const TypeLong* tl = TypeLong::make(lo, hi, MAX2(r1->_widen,r2->_widen));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1060
    #ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1061
    // Make sure we get the sign-capture idiom correct.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1062
    if (shift == (2*BitsPerJavaInteger)-1) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1063
      if (r1->_lo >= 0) assert(tl == TypeLong::ZERO,    ">>63 of + is 0");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1064
      if (r1->_hi < 0)  assert(tl == TypeLong::MINUS_1, ">>63 of - is -1");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1065
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1066
    #endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1067
    return tl;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1068
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1069
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1070
  return TypeLong::LONG;                // Give up
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1071
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1072
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1073
//=============================================================================
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1074
//------------------------------Identity---------------------------------------
35551
36ef3841fb34 8146629: Make phase->is_IterGVN() accessible from Node::Identity and Node::Value
thartmann
parents: 35155
diff changeset
  1075
Node* URShiftINode::Identity(PhaseGVN* phase) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1076
  const TypeInt *ti = phase->type( in(2) )->isa_int();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1077
  if ( ti && ti->is_con() && ( ti->get_con() & ( BitsPerInt - 1 ) ) == 0 ) return in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1078
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1079
  // Check for "((x << LogBytesPerWord) + (wordSize-1)) >> LogBytesPerWord" which is just "x".
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1080
  // Happens during new-array length computation.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1081
  // Safe if 'x' is in the range [0..(max_int>>LogBytesPerWord)]
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1082
  Node *add = in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1083
  if( add->Opcode() == Op_AddI ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1084
    const TypeInt *t2  = phase->type(add->in(2))->isa_int();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1085
    if( t2 && t2->is_con(wordSize - 1) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1086
        add->in(1)->Opcode() == Op_LShiftI ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1087
      // Check that shift_counts are LogBytesPerWord
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1088
      Node          *lshift_count   = add->in(1)->in(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1089
      const TypeInt *t_lshift_count = phase->type(lshift_count)->isa_int();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1090
      if( t_lshift_count && t_lshift_count->is_con(LogBytesPerWord) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1091
          t_lshift_count == phase->type(in(2)) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1092
        Node          *x   = add->in(1)->in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1093
        const TypeInt *t_x = phase->type(x)->isa_int();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1094
        if( t_x != NULL && 0 <= t_x->_lo && t_x->_hi <= (max_jint>>LogBytesPerWord) ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1095
          return x;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1096
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1097
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1098
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1099
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1100
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1101
  return (phase->type(in(2))->higher_equal(TypeInt::ZERO)) ? in(1) : this;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1102
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1103
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1104
//------------------------------Ideal------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1105
Node *URShiftINode::Ideal(PhaseGVN *phase, bool can_reshape) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1106
  const TypeInt *t2 = phase->type( in(2) )->isa_int();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1107
  if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1108
  const int con = t2->get_con() & 31; // Shift count is always masked
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1109
  if ( con == 0 ) return NULL;  // let Identity() handle a 0 shift count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1110
  // We'll be wanting the right-shift amount as a mask of that many bits
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1111
  const int mask = right_n_bits(BitsPerJavaInteger - con);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1112
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1113
  int in1_op = in(1)->Opcode();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1114
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1115
  // Check for ((x>>>a)>>>b) and replace with (x>>>(a+b)) when a+b < 32
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1116
  if( in1_op == Op_URShiftI ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1117
    const TypeInt *t12 = phase->type( in(1)->in(2) )->isa_int();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1118
    if( t12 && t12->is_con() ) { // Right input is a constant
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1119
      assert( in(1) != in(1)->in(1), "dead loop in URShiftINode::Ideal" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1120
      const int con2 = t12->get_con() & 31; // Shift count is always masked
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1121
      const int con3 = con+con2;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1122
      if( con3 < 32 )           // Only merge shifts if total is < 32
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
  1123
        return new URShiftINode( in(1)->in(1), phase->intcon(con3) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1124
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1125
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1126
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1127
  // Check for ((x << z) + Y) >>> z.  Replace with x + con>>>z
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1128
  // The idiom for rounding to a power of 2 is "(Q+(2^z-1)) >>> z".
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1129
  // If Q is "X << z" the rounding is useless.  Look for patterns like
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1130
  // ((X<<Z) + Y) >>> Z  and replace with (X + Y>>>Z) & Z-mask.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1131
  Node *add = in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1132
  if( in1_op == Op_AddI ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1133
    Node *lshl = add->in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1134
    if( lshl->Opcode() == Op_LShiftI &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1135
        phase->type(lshl->in(2)) == t2 ) {
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
  1136
      Node *y_z = phase->transform( new URShiftINode(add->in(2),in(2)) );
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
  1137
      Node *sum = phase->transform( new AddINode( lshl->in(1), y_z ) );
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
  1138
      return new AndINode( sum, phase->intcon(mask) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1139
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1140
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1141
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1142
  // Check for (x & mask) >>> z.  Replace with (x >>> z) & (mask >>> z)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1143
  // This shortens the mask.  Also, if we are extracting a high byte and
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1144
  // storing it to a buffer, the mask will be removed completely.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1145
  Node *andi = in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1146
  if( in1_op == Op_AndI ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1147
    const TypeInt *t3 = phase->type( andi->in(2) )->isa_int();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1148
    if( t3 && t3->is_con() ) { // Right input is a constant
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1149
      jint mask2 = t3->get_con();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1150
      mask2 >>= con;  // *signed* shift downward (high-order zeroes do not help)
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
  1151
      Node *newshr = phase->transform( new URShiftINode(andi->in(1), in(2)) );
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
  1152
      return new AndINode(newshr, phase->intcon(mask2));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1153
      // The negative values are easier to materialize than positive ones.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1154
      // A typical case from address arithmetic is ((x & ~15) >> 4).
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1155
      // It's better to change that to ((x >> 4) & ~0) versus
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1156
      // ((x >> 4) & 0x0FFFFFFF).  The difference is greatest in LP64.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1157
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1158
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1159
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1160
  // Check for "(X << z ) >>> z" which simply zero-extends
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1161
  Node *shl = in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1162
  if( in1_op == Op_LShiftI &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1163
      phase->type(shl->in(2)) == t2 )
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
  1164
    return new AndINode( shl->in(1), phase->intcon(mask) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1165
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1166
  return NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1167
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1168
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1169
//------------------------------Value------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1170
// A URShiftINode shifts its input2 right by input1 amount.
35551
36ef3841fb34 8146629: Make phase->is_IterGVN() accessible from Node::Identity and Node::Value
thartmann
parents: 35155
diff changeset
  1171
const Type* URShiftINode::Value(PhaseGVN* phase) const {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1172
  // (This is a near clone of RShiftINode::Value.)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1173
  const Type *t1 = phase->type( in(1) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1174
  const Type *t2 = phase->type( in(2) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1175
  // Either input is TOP ==> the result is TOP
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1176
  if( t1 == Type::TOP ) return Type::TOP;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1177
  if( t2 == Type::TOP ) return Type::TOP;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1178
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1179
  // Left input is ZERO ==> the result is ZERO.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1180
  if( t1 == TypeInt::ZERO ) return TypeInt::ZERO;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1181
  // Shift by zero does nothing
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1182
  if( t2 == TypeInt::ZERO ) return t1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1183
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1184
  // Either input is BOTTOM ==> the result is BOTTOM
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1185
  if (t1 == Type::BOTTOM || t2 == Type::BOTTOM)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1186
    return TypeInt::INT;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1187
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1188
  if (t2 == TypeInt::INT)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1189
    return TypeInt::INT;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1190
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1191
  const TypeInt *r1 = t1->is_int();     // Handy access
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1192
  const TypeInt *r2 = t2->is_int();     // Handy access
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1193
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1194
  if (r2->is_con()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1195
    uint shift = r2->get_con();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1196
    shift &= BitsPerJavaInteger-1;  // semantics of Java shifts
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1197
    // Shift by a multiple of 32 does nothing:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1198
    if (shift == 0)  return t1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1199
    // Calculate reasonably aggressive bounds for the result.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1200
    jint lo = (juint)r1->_lo >> (juint)shift;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1201
    jint hi = (juint)r1->_hi >> (juint)shift;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1202
    if (r1->_hi >= 0 && r1->_lo < 0) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1203
      // If the type has both negative and positive values,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1204
      // there are two separate sub-domains to worry about:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1205
      // The positive half and the negative half.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1206
      jint neg_lo = lo;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1207
      jint neg_hi = (juint)-1 >> (juint)shift;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1208
      jint pos_lo = (juint) 0 >> (juint)shift;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1209
      jint pos_hi = hi;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1210
      lo = MIN2(neg_lo, pos_lo);  // == 0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1211
      hi = MAX2(neg_hi, pos_hi);  // == -1 >>> shift;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1212
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1213
    assert(lo <= hi, "must have valid bounds");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1214
    const TypeInt* ti = TypeInt::make(lo, hi, MAX2(r1->_widen,r2->_widen));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1215
    #ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1216
    // Make sure we get the sign-capture idiom correct.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1217
    if (shift == BitsPerJavaInteger-1) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1218
      if (r1->_lo >= 0) assert(ti == TypeInt::ZERO, ">>>31 of + is 0");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1219
      if (r1->_hi < 0)  assert(ti == TypeInt::ONE,  ">>>31 of - is +1");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1220
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1221
    #endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1222
    return ti;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1223
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1224
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1225
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1226
  // Do not support shifted oops in info for GC
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1227
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1228
  // else if( t1->base() == Type::InstPtr ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1229
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1230
  //   const TypeInstPtr *o = t1->is_instptr();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1231
  //   if( t1->singleton() )
24425
53764d2358f9 8041415: remove port.{cpp,hpp} files
zgu
parents: 23528
diff changeset
  1232
  //     return TypeInt::make( ((uint32_t)o->const_oop() + o->_offset) >> shift );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1233
  // }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1234
  // else if( t1->base() == Type::KlassPtr ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1235
  //   const TypeKlassPtr *o = t1->is_klassptr();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1236
  //   if( t1->singleton() )
24425
53764d2358f9 8041415: remove port.{cpp,hpp} files
zgu
parents: 23528
diff changeset
  1237
  //     return TypeInt::make( ((uint32_t)o->const_oop() + o->_offset) >> shift );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1238
  // }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1239
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1240
  return TypeInt::INT;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1241
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1242
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1243
//=============================================================================
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1244
//------------------------------Identity---------------------------------------
35551
36ef3841fb34 8146629: Make phase->is_IterGVN() accessible from Node::Identity and Node::Value
thartmann
parents: 35155
diff changeset
  1245
Node* URShiftLNode::Identity(PhaseGVN* phase) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1246
  const TypeInt *ti = phase->type( in(2) )->isa_int(); // shift count is an int
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1247
  return ( ti && ti->is_con() && ( ti->get_con() & ( BitsPerLong - 1 ) ) == 0 ) ? in(1) : this;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1248
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1249
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1250
//------------------------------Ideal------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1251
Node *URShiftLNode::Ideal(PhaseGVN *phase, bool can_reshape) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1252
  const TypeInt *t2 = phase->type( in(2) )->isa_int();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1253
  if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1254
  const int con = t2->get_con() & ( BitsPerLong - 1 ); // Shift count is always masked
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1255
  if ( con == 0 ) return NULL;  // let Identity() handle a 0 shift count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1256
                              // note: mask computation below does not work for 0 shift count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1257
  // We'll be wanting the right-shift amount as a mask of that many bits
35155
db692d3ebbcc 8145096: Undefined behaviour in HotSpot
aph
parents: 27471
diff changeset
  1258
  const jlong mask = jlong(max_julong >> con);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1259
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1260
  // Check for ((x << z) + Y) >>> z.  Replace with x + con>>>z
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1261
  // The idiom for rounding to a power of 2 is "(Q+(2^z-1)) >>> z".
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1262
  // If Q is "X << z" the rounding is useless.  Look for patterns like
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1263
  // ((X<<Z) + Y) >>> Z  and replace with (X + Y>>>Z) & Z-mask.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1264
  Node *add = in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1265
  if( add->Opcode() == Op_AddL ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1266
    Node *lshl = add->in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1267
    if( lshl->Opcode() == Op_LShiftL &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1268
        phase->type(lshl->in(2)) == t2 ) {
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
  1269
      Node *y_z = phase->transform( new URShiftLNode(add->in(2),in(2)) );
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
  1270
      Node *sum = phase->transform( new AddLNode( lshl->in(1), y_z ) );
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
  1271
      return new AndLNode( sum, phase->longcon(mask) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1272
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1273
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1274
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1275
  // Check for (x & mask) >>> z.  Replace with (x >>> z) & (mask >>> z)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1276
  // This shortens the mask.  Also, if we are extracting a high byte and
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1277
  // storing it to a buffer, the mask will be removed completely.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1278
  Node *andi = in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1279
  if( andi->Opcode() == Op_AndL ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1280
    const TypeLong *t3 = phase->type( andi->in(2) )->isa_long();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1281
    if( t3 && t3->is_con() ) { // Right input is a constant
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1282
      jlong mask2 = t3->get_con();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1283
      mask2 >>= con;  // *signed* shift downward (high-order zeroes do not help)
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
  1284
      Node *newshr = phase->transform( new URShiftLNode(andi->in(1), in(2)) );
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
  1285
      return new AndLNode(newshr, phase->longcon(mask2));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1286
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1287
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1288
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1289
  // Check for "(X << z ) >>> z" which simply zero-extends
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1290
  Node *shl = in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1291
  if( shl->Opcode() == Op_LShiftL &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1292
      phase->type(shl->in(2)) == t2 )
24923
9631f7d691dc 8034812: remove IDX_INIT macro hack in Node class
thartmann
parents: 24425
diff changeset
  1293
    return new AndLNode( shl->in(1), phase->longcon(mask) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1294
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1295
  return NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1296
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1297
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1298
//------------------------------Value------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1299
// A URShiftINode shifts its input2 right by input1 amount.
35551
36ef3841fb34 8146629: Make phase->is_IterGVN() accessible from Node::Identity and Node::Value
thartmann
parents: 35155
diff changeset
  1300
const Type* URShiftLNode::Value(PhaseGVN* phase) const {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1301
  // (This is a near clone of RShiftLNode::Value.)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1302
  const Type *t1 = phase->type( in(1) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1303
  const Type *t2 = phase->type( in(2) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1304
  // Either input is TOP ==> the result is TOP
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1305
  if( t1 == Type::TOP ) return Type::TOP;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1306
  if( t2 == Type::TOP ) return Type::TOP;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1307
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1308
  // Left input is ZERO ==> the result is ZERO.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1309
  if( t1 == TypeLong::ZERO ) return TypeLong::ZERO;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1310
  // Shift by zero does nothing
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1311
  if( t2 == TypeInt::ZERO ) return t1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1312
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1313
  // Either input is BOTTOM ==> the result is BOTTOM
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1314
  if (t1 == Type::BOTTOM || t2 == Type::BOTTOM)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1315
    return TypeLong::LONG;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1316
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1317
  if (t2 == TypeInt::INT)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1318
    return TypeLong::LONG;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1319
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1320
  const TypeLong *r1 = t1->is_long(); // Handy access
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1321
  const TypeInt  *r2 = t2->is_int (); // Handy access
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1322
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1323
  if (r2->is_con()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1324
    uint shift = r2->get_con();
2023
10d955a8d972 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 2022
diff changeset
  1325
    shift &= BitsPerJavaLong - 1;  // semantics of Java shifts
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1326
    // Shift by a multiple of 64 does nothing:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1327
    if (shift == 0)  return t1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1328
    // Calculate reasonably aggressive bounds for the result.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1329
    jlong lo = (julong)r1->_lo >> (juint)shift;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1330
    jlong hi = (julong)r1->_hi >> (juint)shift;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1331
    if (r1->_hi >= 0 && r1->_lo < 0) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1332
      // If the type has both negative and positive values,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1333
      // there are two separate sub-domains to worry about:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1334
      // The positive half and the negative half.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1335
      jlong neg_lo = lo;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1336
      jlong neg_hi = (julong)-1 >> (juint)shift;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1337
      jlong pos_lo = (julong) 0 >> (juint)shift;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1338
      jlong pos_hi = hi;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1339
      //lo = MIN2(neg_lo, pos_lo);  // == 0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1340
      lo = neg_lo < pos_lo ? neg_lo : pos_lo;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1341
      //hi = MAX2(neg_hi, pos_hi);  // == -1 >>> shift;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1342
      hi = neg_hi > pos_hi ? neg_hi : pos_hi;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1343
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1344
    assert(lo <= hi, "must have valid bounds");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1345
    const TypeLong* tl = TypeLong::make(lo, hi, MAX2(r1->_widen,r2->_widen));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1346
    #ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1347
    // Make sure we get the sign-capture idiom correct.
2023
10d955a8d972 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 2022
diff changeset
  1348
    if (shift == BitsPerJavaLong - 1) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1349
      if (r1->_lo >= 0) assert(tl == TypeLong::ZERO, ">>>63 of + is 0");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1350
      if (r1->_hi < 0)  assert(tl == TypeLong::ONE,  ">>>63 of - is +1");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1351
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1352
    #endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1353
    return tl;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1354
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1355
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1356
  return TypeLong::LONG;                // Give up
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1357
}