/*

 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#include "precompiled.hpp"

#include "interp_masm_sparc.hpp"

#include "interpreter/interpreter.hpp"

#include "interpreter/interpreterRuntime.hpp"

#include "oops/arrayOop.hpp"

#include "oops/markOop.hpp"

#include "oops/methodData.hpp"

#include "oops/method.hpp"

#include "oops/methodCounters.hpp"

#include "prims/jvmtiExport.hpp"

#include "prims/jvmtiRedefineClassesTrace.hpp"

#include "prims/jvmtiThreadState.hpp"

#include "runtime/basicLock.hpp"

#include "runtime/biasedLocking.hpp"

#include "runtime/sharedRuntime.hpp"

#include "runtime/thread.inline.hpp"

#ifndef CC_INTERP

#ifndef FAST_DISPATCH

#define FAST_DISPATCH 1

#endif

#undef FAST_DISPATCH

// Implementation of InterpreterMacroAssembler

// This file specializes the assember with interpreter-specific macros

const Address InterpreterMacroAssembler::l_tmp(FP, (frame::interpreter_frame_l_scratch_fp_offset * wordSize) + STACK_BIAS);

const Address InterpreterMacroAssembler::d_tmp(FP, (frame::interpreter_frame_d_scratch_fp_offset * wordSize) + STACK_BIAS);

#else // CC_INTERP

#ifndef STATE

#define STATE(field_name) Lstate, in_bytes(byte_offset_of(BytecodeInterpreter, field_name))

#endif // STATE

#endif // CC_INTERP

void InterpreterMacroAssembler::compute_extra_locals_size_in_bytes(Register args_size, Register locals_size, Register delta) {

  // Note: this algorithm is also used by C1's OSR entry sequence.

  // Any changes should also be applied to CodeEmitter::emit_osr_entry().

  assert_different_registers(args_size, locals_size);

  // max_locals*2 for TAGS.  Assumes that args_size has already been adjusted.

  subcc(locals_size, args_size, delta);// extra space for non-arguments locals in words

  // Use br/mov combination because it works on both V8 and V9 and is

  // faster.

  Label skip_move;

  br(Assembler::negative, true, Assembler::pt, skip_move);

  delayed()->mov(G0, delta);

  bind(skip_move);

  round_to(delta, WordsPerLong);       // make multiple of 2 (SP must be 2-word aligned)

  sll(delta, LogBytesPerWord, delta);  // extra space for locals in bytes

}

#ifndef CC_INTERP

// Dispatch code executed in the prolog of a bytecode which does not do it's

// own dispatch. The dispatch address is computed and placed in IdispatchAddress

void InterpreterMacroAssembler::dispatch_prolog(TosState state, int bcp_incr) {

  assert_not_delayed();

#ifdef FAST_DISPATCH

  // FAST_DISPATCH and ProfileInterpreter are mutually exclusive since

  // they both use I2.

  assert(!ProfileInterpreter, "FAST_DISPATCH and +ProfileInterpreter are mutually exclusive");

  ldub(Lbcp, bcp_incr, Lbyte_code);                     // load next bytecode

  add(Lbyte_code, Interpreter::distance_from_dispatch_table(state), Lbyte_code);

                                                        // add offset to correct dispatch table

  sll(Lbyte_code, LogBytesPerWord, Lbyte_code);         // multiply by wordSize

  ld_ptr(IdispatchTables, Lbyte_code, IdispatchAddress);// get entry addr

#else

  ldub( Lbcp, bcp_incr, Lbyte_code);                    // load next bytecode

  // dispatch table to use

  AddressLiteral tbl(Interpreter::dispatch_table(state));

  sll(Lbyte_code, LogBytesPerWord, Lbyte_code);         // multiply by wordSize

  set(tbl, G3_scratch);                                 // compute addr of table

  ld_ptr(G3_scratch, Lbyte_code, IdispatchAddress);     // get entry addr

#endif

}

// Dispatch code executed in the epilog of a bytecode which does not do it's

// own dispatch. The dispatch address in IdispatchAddress is used for the

// dispatch.

void InterpreterMacroAssembler::dispatch_epilog(TosState state, int bcp_incr) {

  assert_not_delayed();

  verify_FPU(1, state);

  interp_verify_oop(Otos_i, state, __FILE__, __LINE__);

  jmp( IdispatchAddress, 0 );

  if (bcp_incr != 0)  delayed()->inc(Lbcp, bcp_incr);

  else                delayed()->nop();

}

void InterpreterMacroAssembler::dispatch_next(TosState state, int bcp_incr) {

  // %%%% consider branching to a single shared dispatch stub (for each bcp_incr)

  assert_not_delayed();

  ldub( Lbcp, bcp_incr, Lbyte_code);               // load next bytecode

  dispatch_Lbyte_code(state, Interpreter::dispatch_table(state), bcp_incr);

}

void InterpreterMacroAssembler::dispatch_next_noverify_oop(TosState state, int bcp_incr) {

  // %%%% consider branching to a single shared dispatch stub (for each bcp_incr)

  assert_not_delayed();

  ldub( Lbcp, bcp_incr, Lbyte_code);               // load next bytecode

  dispatch_Lbyte_code(state, Interpreter::dispatch_table(state), bcp_incr, false);

}

void InterpreterMacroAssembler::dispatch_via(TosState state, address* table) {

  // load current bytecode

  assert_not_delayed();

  ldub( Lbcp, 0, Lbyte_code);               // load next bytecode

  dispatch_base(state, table);

}

void InterpreterMacroAssembler::call_VM_leaf_base(

  Register java_thread,

  address  entry_point,

  int      number_of_arguments

) {

  if (!java_thread->is_valid())

    java_thread = L7_thread_cache;

  // super call

  MacroAssembler::call_VM_leaf_base(java_thread, entry_point, number_of_arguments);

}

void InterpreterMacroAssembler::call_VM_base(

  Register        oop_result,

  Register        java_thread,

  Register        last_java_sp,

  address         entry_point,

  int             number_of_arguments,

  bool            check_exception

) {

  if (!java_thread->is_valid())

    java_thread = L7_thread_cache;

  // See class ThreadInVMfromInterpreter, which assumes that the interpreter

  // takes responsibility for setting its own thread-state on call-out.

  // However, ThreadInVMfromInterpreter resets the state to "in_Java".

  //save_bcp();                                  // save bcp

  MacroAssembler::call_VM_base(oop_result, java_thread, last_java_sp, entry_point, number_of_arguments, check_exception);

  //restore_bcp();                               // restore bcp

  //restore_locals();                            // restore locals pointer

}

void InterpreterMacroAssembler::check_and_handle_popframe(Register scratch_reg) {

  if (JvmtiExport::can_pop_frame()) {

    Label L;

    // Check the "pending popframe condition" flag in the current thread

    ld(G2_thread, JavaThread::popframe_condition_offset(), scratch_reg);

    // Initiate popframe handling only if it is not already being processed.  If the flag

    // has the popframe_processing bit set, it means that this code is called *during* popframe

    // handling - we don't want to reenter.

    btst(JavaThread::popframe_pending_bit, scratch_reg);

    br(zero, false, pt, L);

    delayed()->nop();

    btst(JavaThread::popframe_processing_bit, scratch_reg);

    br(notZero, false, pt, L);

    delayed()->nop();

    // Call Interpreter::remove_activation_preserving_args_entry() to get the

    // address of the same-named entrypoint in the generated interpreter code.

    call_VM_leaf(noreg, CAST_FROM_FN_PTR(address, Interpreter::remove_activation_preserving_args_entry));

    // Jump to Interpreter::_remove_activation_preserving_args_entry

    jmpl(O0, G0, G0);

    delayed()->nop();

    bind(L);

  }

}

void InterpreterMacroAssembler::load_earlyret_value(TosState state) {

  Register thr_state = G4_scratch;

  ld_ptr(G2_thread, JavaThread::jvmti_thread_state_offset(), thr_state);

  const Address tos_addr(thr_state, JvmtiThreadState::earlyret_tos_offset());

  const Address oop_addr(thr_state, JvmtiThreadState::earlyret_oop_offset());

  const Address val_addr(thr_state, JvmtiThreadState::earlyret_value_offset());

  switch (state) {

  case ltos: ld_long(val_addr, Otos_l);                   break;

  case atos: ld_ptr(oop_addr, Otos_l);

             st_ptr(G0, oop_addr);                        break;

  case btos:                                           // fall through

  case ctos:                                           // fall through

  case stos:                                           // fall through

  case itos: ld(val_addr, Otos_l1);                       break;

  case ftos: ldf(FloatRegisterImpl::S, val_addr, Ftos_f); break;

  case dtos: ldf(FloatRegisterImpl::D, val_addr, Ftos_d); break;

  case vtos: /* nothing to do */                          break;

  default  : ShouldNotReachHere();

  }

  // Clean up tos value in the jvmti thread state

  or3(G0, ilgl, G3_scratch);

  stw(G3_scratch, tos_addr);

  st_long(G0, val_addr);

  interp_verify_oop(Otos_i, state, __FILE__, __LINE__);

}

void InterpreterMacroAssembler::check_and_handle_earlyret(Register scratch_reg) {

  if (JvmtiExport::can_force_early_return()) {

    Label L;

    Register thr_state = G3_scratch;

    ld_ptr(G2_thread, JavaThread::jvmti_thread_state_offset(), thr_state);

    br_null_short(thr_state, pt, L); // if (thread->jvmti_thread_state() == NULL) exit;

    // Initiate earlyret handling only if it is not already being processed.

    // If the flag has the earlyret_processing bit set, it means that this code

    // is called *during* earlyret handling - we don't want to reenter.

    ld(thr_state, JvmtiThreadState::earlyret_state_offset(), G4_scratch);

    cmp_and_br_short(G4_scratch, JvmtiThreadState::earlyret_pending, Assembler::notEqual, pt, L);

    // Call Interpreter::remove_activation_early_entry() to get the address of the

    // same-named entrypoint in the generated interpreter code

    ld(thr_state, JvmtiThreadState::earlyret_tos_offset(), Otos_l1);

    call_VM_leaf(noreg, CAST_FROM_FN_PTR(address, Interpreter::remove_activation_early_entry), Otos_l1);

    // Jump to Interpreter::_remove_activation_early_entry

    jmpl(O0, G0, G0);

    delayed()->nop();

    bind(L);

  }

}

void InterpreterMacroAssembler::super_call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2) {

  mov(arg_1, O0);

  mov(arg_2, O1);

  MacroAssembler::call_VM_leaf_base(thread_cache, entry_point, 2);

}

#endif /* CC_INTERP */

#ifndef CC_INTERP

void InterpreterMacroAssembler::dispatch_base(TosState state, address* table) {

  assert_not_delayed();

  dispatch_Lbyte_code(state, table);

}

void InterpreterMacroAssembler::dispatch_normal(TosState state) {

  dispatch_base(state, Interpreter::normal_table(state));

}

void InterpreterMacroAssembler::dispatch_only(TosState state) {

  dispatch_base(state, Interpreter::dispatch_table(state));

}

// common code to dispatch and dispatch_only

// dispatch value in Lbyte_code and increment Lbcp

void InterpreterMacroAssembler::dispatch_Lbyte_code(TosState state, address* table, int bcp_incr, bool verify) {

  verify_FPU(1, state);

  // %%%%% maybe implement +VerifyActivationFrameSize here

  //verify_thread(); //too slow; we will just verify on method entry & exit

  if (verify) interp_verify_oop(Otos_i, state, __FILE__, __LINE__);

#ifdef FAST_DISPATCH

  if (table == Interpreter::dispatch_table(state)) {

    // use IdispatchTables

    add(Lbyte_code, Interpreter::distance_from_dispatch_table(state), Lbyte_code);

                                                        // add offset to correct dispatch table

    sll(Lbyte_code, LogBytesPerWord, Lbyte_code);       // multiply by wordSize

    ld_ptr(IdispatchTables, Lbyte_code, G3_scratch);    // get entry addr

  } else {

#endif

    // dispatch table to use

    AddressLiteral tbl(table);

    sll(Lbyte_code, LogBytesPerWord, Lbyte_code);       // multiply by wordSize

    set(tbl, G3_scratch);                               // compute addr of table

    ld_ptr(G3_scratch, Lbyte_code, G3_scratch);         // get entry addr

#ifdef FAST_DISPATCH

  }

#endif

  jmp( G3_scratch, 0 );

  if (bcp_incr != 0)  delayed()->inc(Lbcp, bcp_incr);

  else                delayed()->nop();

}

// Helpers for expression stack

// Longs and doubles are Category 2 computational types in the

// JVM specification (section 3.11.1) and take 2 expression stack or

// local slots.

// Aligning them on 32 bit with tagged stacks is hard because the code generated

// for the dup* bytecodes depends on what types are already on the stack.

// If the types are split into the two stack/local slots, that is much easier

// (and we can use 0 for non-reference tags).

// Known good alignment in _LP64 but unknown otherwise

void InterpreterMacroAssembler::load_unaligned_double(Register r1, int offset, FloatRegister d) {

  assert_not_delayed();

#ifdef _LP64

  ldf(FloatRegisterImpl::D, r1, offset, d);

#else

  ldf(FloatRegisterImpl::S, r1, offset, d);

  ldf(FloatRegisterImpl::S, r1, offset + Interpreter::stackElementSize, d->successor());

#endif

}

// Known good alignment in _LP64 but unknown otherwise

void InterpreterMacroAssembler::store_unaligned_double(FloatRegister d, Register r1, int offset) {

  assert_not_delayed();

#ifdef _LP64

  stf(FloatRegisterImpl::D, d, r1, offset);

  // store something more useful here

  debug_only(stx(G0, r1, offset+Interpreter::stackElementSize);)

#else

  stf(FloatRegisterImpl::S, d, r1, offset);

  stf(FloatRegisterImpl::S, d->successor(), r1, offset + Interpreter::stackElementSize);

#endif

}

// Known good alignment in _LP64 but unknown otherwise

void InterpreterMacroAssembler::load_unaligned_long(Register r1, int offset, Register rd) {

  assert_not_delayed();

#ifdef _LP64

  ldx(r1, offset, rd);

#else

  ld(r1, offset, rd);

  ld(r1, offset + Interpreter::stackElementSize, rd->successor());

#endif

}

// Known good alignment in _LP64 but unknown otherwise

void InterpreterMacroAssembler::store_unaligned_long(Register l, Register r1, int offset) {

  assert_not_delayed();

#ifdef _LP64

  stx(l, r1, offset);

  // store something more useful here

  debug_only(stx(G0, r1, offset+Interpreter::stackElementSize);)

#else

  st(l, r1, offset);

  st(l->successor(), r1, offset + Interpreter::stackElementSize);

#endif

}

void InterpreterMacroAssembler::pop_i(Register r) {

  assert_not_delayed();

  ld(Lesp, Interpreter::expr_offset_in_bytes(0), r);

  inc(Lesp, Interpreter::stackElementSize);

  debug_only(verify_esp(Lesp));

}

void InterpreterMacroAssembler::pop_ptr(Register r, Register scratch) {

  assert_not_delayed();

  ld_ptr(Lesp, Interpreter::expr_offset_in_bytes(0), r);

  inc(Lesp, Interpreter::stackElementSize);

  debug_only(verify_esp(Lesp));

}

void InterpreterMacroAssembler::pop_l(Register r) {

  assert_not_delayed();

  load_unaligned_long(Lesp, Interpreter::expr_offset_in_bytes(0), r);

  inc(Lesp, 2*Interpreter::stackElementSize);

  debug_only(verify_esp(Lesp));

}

void InterpreterMacroAssembler::pop_f(FloatRegister f, Register scratch) {

  assert_not_delayed();

  ldf(FloatRegisterImpl::S, Lesp, Interpreter::expr_offset_in_bytes(0), f);

  inc(Lesp, Interpreter::stackElementSize);

  debug_only(verify_esp(Lesp));

}

void InterpreterMacroAssembler::pop_d(FloatRegister f, Register scratch) {

  assert_not_delayed();

  load_unaligned_double(Lesp, Interpreter::expr_offset_in_bytes(0), f);

  inc(Lesp, 2*Interpreter::stackElementSize);

  debug_only(verify_esp(Lesp));

}

void InterpreterMacroAssembler::push_i(Register r) {

  assert_not_delayed();

  debug_only(verify_esp(Lesp));

  st(r, Lesp, 0);

  dec(Lesp, Interpreter::stackElementSize);

}

void InterpreterMacroAssembler::push_ptr(Register r) {

  assert_not_delayed();

  st_ptr(r, Lesp, 0);

  dec(Lesp, Interpreter::stackElementSize);

}

// remember: our convention for longs in SPARC is:

// O0 (Otos_l1) has high-order part in first word,

// O1 (Otos_l2) has low-order part in second word

void InterpreterMacroAssembler::push_l(Register r) {

  assert_not_delayed();

  debug_only(verify_esp(Lesp));

  // Longs are stored in memory-correct order, even if unaligned.

  int offset = -Interpreter::stackElementSize;

  store_unaligned_long(r, Lesp, offset);

  dec(Lesp, 2 * Interpreter::stackElementSize);

}

void InterpreterMacroAssembler::push_f(FloatRegister f) {

  assert_not_delayed();

  debug_only(verify_esp(Lesp));

  stf(FloatRegisterImpl::S, f, Lesp, 0);

  dec(Lesp, Interpreter::stackElementSize);

}

void InterpreterMacroAssembler::push_d(FloatRegister d)   {

  assert_not_delayed();

  debug_only(verify_esp(Lesp));

  // Longs are stored in memory-correct order, even if unaligned.

  int offset = -Interpreter::stackElementSize;

  store_unaligned_double(d, Lesp, offset);

  dec(Lesp, 2 * Interpreter::stackElementSize);

}

void InterpreterMacroAssembler::push(TosState state) {

  interp_verify_oop(Otos_i, state, __FILE__, __LINE__);

  switch (state) {

    case atos: push_ptr();            break;

    case btos: push_i();              break;

    case ctos:

    case stos: push_i();              break;

    case itos: push_i();              break;

    case ltos: push_l();              break;

    case ftos: push_f();              break;

    case dtos: push_d();              break;

    case vtos: /* nothing to do */    break;

    default  : ShouldNotReachHere();

  }

}

void InterpreterMacroAssembler::pop(TosState state) {

  switch (state) {

    case atos: pop_ptr();            break;

    case btos: pop_i();              break;

    case ctos:

    case stos: pop_i();              break;

    case itos: pop_i();              break;

    case ltos: pop_l();              break;

    case ftos: pop_f();              break;

    case dtos: pop_d();              break;

    case vtos: /* nothing to do */   break;

    default  : ShouldNotReachHere();

  }

  interp_verify_oop(Otos_i, state, __FILE__, __LINE__);

}

// Helpers for swap and dup

void InterpreterMacroAssembler::load_ptr(int n, Register val) {

  ld_ptr(Lesp, Interpreter::expr_offset_in_bytes(n), val);

}

void InterpreterMacroAssembler::store_ptr(int n, Register val) {

  st_ptr(val, Lesp, Interpreter::expr_offset_in_bytes(n));

}

void InterpreterMacroAssembler::load_receiver(Register param_count,

                                              Register recv) {

  sll(param_count, Interpreter::logStackElementSize, param_count);

  ld_ptr(Lesp, param_count, recv);  // gets receiver oop

}

void InterpreterMacroAssembler::empty_expression_stack() {

  // Reset Lesp.

  sub( Lmonitors, wordSize, Lesp );

  // Reset SP by subtracting more space from Lesp.

  Label done;

  assert(G4_scratch != Gframe_size, "Only you can prevent register aliasing!");

  // A native does not need to do this, since its callee does not change SP.

  ld(Lmethod, Method::access_flags_offset(), Gframe_size);  // Load access flags.

  btst(JVM_ACC_NATIVE, Gframe_size);

  br(Assembler::notZero, false, Assembler::pt, done);