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/*
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* Copyright (c) 2008, 2016, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#ifndef OS_CPU_LINUX_ARM_VM_ORDERACCESS_LINUX_ARM_INLINE_HPP
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#define OS_CPU_LINUX_ARM_VM_ORDERACCESS_LINUX_ARM_INLINE_HPP
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#include "runtime/orderAccess.hpp"
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#include "runtime/os.hpp"
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#include "vm_version_arm.hpp"
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// Implementation of class OrderAccess.
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// - we define the high level barriers below and use the general
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// implementation in orderAccess.inline.hpp, with customizations
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// on AARCH64 via the specialized_* template functions
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#define VM_HAS_GENERALIZED_ORDER_ACCESS 1
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// Memory Ordering on ARM is weak.
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//
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// Implement all 4 memory ordering barriers by DMB, since it is a
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// lighter version of DSB.
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// dmb_sy implies full system shareability domain. RD/WR access type.
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// dmb_st implies full system shareability domain. WR only access type.
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//
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// NOP on < ARMv6 (MP not supported)
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//
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// Non mcr instructions can be used if we build for armv7 or higher arch
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// __asm__ __volatile__ ("dmb" : : : "memory");
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// __asm__ __volatile__ ("dsb" : : : "memory");
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//
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// inline void _OrderAccess_dsb() {
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// volatile intptr_t dummy = 0;
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// if (os::is_MP()) {
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// __asm__ volatile (
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// "mcr p15, 0, %0, c7, c10, 4"
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// : : "r" (dummy) : "memory");
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// }
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// }
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inline static void dmb_sy() {
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if (!os::is_MP()) {
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return;
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}
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#ifdef AARCH64
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__asm__ __volatile__ ("dmb sy" : : : "memory");
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#else
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if (VM_Version::arm_arch() >= 7) {
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#ifdef __thumb__
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__asm__ volatile (
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"dmb sy": : : "memory");
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#else
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__asm__ volatile (
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".word 0xF57FF050 | 0xf" : : : "memory");
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#endif
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} else {
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intptr_t zero = 0;
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__asm__ volatile (
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"mcr p15, 0, %0, c7, c10, 5"
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: : "r" (zero) : "memory");
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}
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#endif
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}
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inline static void dmb_st() {
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if (!os::is_MP()) {
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return;
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}
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#ifdef AARCH64
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__asm__ __volatile__ ("dmb st" : : : "memory");
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#else
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if (VM_Version::arm_arch() >= 7) {
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#ifdef __thumb__
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__asm__ volatile (
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"dmb st": : : "memory");
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#else
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__asm__ volatile (
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".word 0xF57FF050 | 0xe" : : : "memory");
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#endif
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} else {
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intptr_t zero = 0;
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__asm__ volatile (
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"mcr p15, 0, %0, c7, c10, 5"
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: : "r" (zero) : "memory");
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}
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#endif
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}
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// Load-Load/Store barrier
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inline static void dmb_ld() {
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#ifdef AARCH64
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if (!os::is_MP()) {
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return;
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}
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__asm__ __volatile__ ("dmb ld" : : : "memory");
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#else
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dmb_sy();
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#endif
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}
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inline void OrderAccess::loadload() { dmb_ld(); }
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inline void OrderAccess::loadstore() { dmb_ld(); }
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inline void OrderAccess::acquire() { dmb_ld(); }
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inline void OrderAccess::storestore() { dmb_st(); }
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inline void OrderAccess::storeload() { dmb_sy(); }
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inline void OrderAccess::release() { dmb_sy(); }
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inline void OrderAccess::fence() { dmb_sy(); }
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// specializations for Aarch64
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// TODO-AARCH64: evaluate effectiveness of ldar*/stlr* implementations compared to 32-bit ARM approach
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#ifdef AARCH64
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template<> inline jbyte OrderAccess::specialized_load_acquire<jbyte>(volatile jbyte* p) {
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volatile jbyte result;
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__asm__ volatile(
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"ldarb %w[res], [%[ptr]]"
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: [res] "=&r" (result)
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: [ptr] "r" (p)
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: "memory");
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return result;
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}
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template<> inline jshort OrderAccess::specialized_load_acquire<jshort>(volatile jshort* p) {
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volatile jshort result;
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__asm__ volatile(
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"ldarh %w[res], [%[ptr]]"
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: [res] "=&r" (result)
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: [ptr] "r" (p)
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: "memory");
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return result;
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}
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template<> inline jint OrderAccess::specialized_load_acquire<jint>(volatile jint* p) {
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volatile jint result;
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__asm__ volatile(
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"ldar %w[res], [%[ptr]]"
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: [res] "=&r" (result)
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: [ptr] "r" (p)
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: "memory");
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return result;
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}
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template<> inline jfloat OrderAccess::specialized_load_acquire<jfloat>(volatile jfloat* p) {
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return jfloat_cast(specialized_load_acquire((volatile jint*)p));
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}
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// This is implicit as jlong and intptr_t are both "long int"
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//template<> inline jlong OrderAccess::specialized_load_acquire(volatile jlong* p) {
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// return (volatile jlong)specialized_load_acquire((volatile intptr_t*)p);
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//}
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template<> inline intptr_t OrderAccess::specialized_load_acquire<intptr_t>(volatile intptr_t* p) {
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volatile intptr_t result;
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__asm__ volatile(
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"ldar %[res], [%[ptr]]"
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: [res] "=&r" (result)
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: [ptr] "r" (p)
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: "memory");
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return result;
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}
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template<> inline jdouble OrderAccess::specialized_load_acquire<jdouble>(volatile jdouble* p) {
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return jdouble_cast(specialized_load_acquire((volatile intptr_t*)p));
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}
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template<> inline void OrderAccess::specialized_release_store<jbyte>(volatile jbyte* p, jbyte v) {
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__asm__ volatile(
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"stlrb %w[val], [%[ptr]]"
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:
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: [ptr] "r" (p), [val] "r" (v)
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: "memory");
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}
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template<> inline void OrderAccess::specialized_release_store<jshort>(volatile jshort* p, jshort v) {
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__asm__ volatile(
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"stlrh %w[val], [%[ptr]]"
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:
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: [ptr] "r" (p), [val] "r" (v)
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: "memory");
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}
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template<> inline void OrderAccess::specialized_release_store<jint>(volatile jint* p, jint v) {
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__asm__ volatile(
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"stlr %w[val], [%[ptr]]"
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:
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: [ptr] "r" (p), [val] "r" (v)
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: "memory");
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}
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template<> inline void OrderAccess::specialized_release_store<jlong>(volatile jlong* p, jlong v) {
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__asm__ volatile(
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"stlr %[val], [%[ptr]]"
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:
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: [ptr] "r" (p), [val] "r" (v)
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: "memory");
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}
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#endif // AARCH64
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#endif // OS_CPU_LINUX_ARM_VM_ORDERACCESS_LINUX_ARM_INLINE_HPP
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