/*

 * Copyright (c) 2008, 2016, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#ifndef CPU_ARM_VM_ASSEMBLER_ARM_64_HPP

#define CPU_ARM_VM_ASSEMBLER_ARM_64_HPP

enum AsmShift12 {

  lsl0, lsl12

};

enum AsmPrefetchOp {

    pldl1keep = 0b00000,

    pldl1strm,

    pldl2keep,

    pldl2strm,

    pldl3keep,

    pldl3strm,

    plil1keep = 0b01000,

    plil1strm,

    plil2keep,

    plil2strm,

    plil3keep,

    plil3strm,

    pstl1keep = 0b10000,

    pstl1strm,

    pstl2keep,

    pstl2strm,

    pstl3keep,

    pstl3strm,

};

// Shifted register operand for data processing instructions.

class AsmOperand VALUE_OBJ_CLASS_SPEC {

 private:

  Register _reg;

  AsmShift _shift;

  int _shift_imm;

 public:

  AsmOperand(Register reg) {

    assert(reg != SP, "SP is not allowed in shifted register operand");

    _reg = reg;

    _shift = lsl;

    _shift_imm = 0;

  }

  AsmOperand(Register reg, AsmShift shift, int shift_imm) {

    assert(reg != SP, "SP is not allowed in shifted register operand");

    assert(shift_imm >= 0, "shift amount should be non-negative");

    _reg = reg;

    _shift = shift;

    _shift_imm = shift_imm;

  }

  Register reg() const {

    return _reg;

  }

  AsmShift shift() const {

    return _shift;

  }

  int shift_imm() const {

    return _shift_imm;

  }

};

class Assembler : public AbstractAssembler  {

 public:

  static const int LogInstructionSize = 2;

  static const int InstructionSize    = 1 << LogInstructionSize;

  Assembler(CodeBuffer* code) : AbstractAssembler(code) {}

  static inline AsmCondition inverse(AsmCondition cond) {

    assert ((cond != al) && (cond != nv), "AL and NV conditions cannot be inversed");

    return (AsmCondition)((int)cond ^ 1);

  }

  // Returns value of nzcv flags conforming to the given condition.

  static inline int flags_for_condition(AsmCondition cond) {

    switch(cond) {            // NZCV

      case mi: case lt: return 0b1000;

      case eq: case le: return 0b0100;

      case hs: case hi: return 0b0010;

      case vs:          return 0b0001;

      default:          return 0b0000;

    }

  }

  // Immediate, encoded into logical instructions.

  class LogicalImmediate {

   private:

    bool _encoded;

    bool _is32bit;

    int _immN;

    int _immr;

    int _imms;

    static inline bool has_equal_subpatterns(uintx imm, int size);

    static inline int least_pattern_size(uintx imm);

    static inline int population_count(uintx x);

    static inline uintx set_least_zeroes(uintx x);

#ifdef ASSERT

    uintx decode();

#endif

    void construct(uintx imm, bool is32);

   public:

    LogicalImmediate(uintx imm, bool is32 = false) { construct(imm, is32); }

    // Returns true if given immediate can be used in AArch64 logical instruction.

    bool is_encoded() const { return _encoded; }

    bool is32bit() const { return _is32bit; }

    int immN() const { assert(_encoded, "should be"); return _immN; }

    int immr() const { assert(_encoded, "should be"); return _immr; }

    int imms() const { assert(_encoded, "should be"); return _imms; }

  };

  // Immediate, encoded into arithmetic add/sub instructions.

  class ArithmeticImmediate {

   private:

    bool _encoded;

    int _imm;

    AsmShift12 _shift;

   public:

    ArithmeticImmediate(intx x) {

      if (is_unsigned_imm_in_range(x, 12, 0)) {

        _encoded = true;

        _imm = x;

        _shift = lsl0;

      } else if (is_unsigned_imm_in_range(x, 12, 12)) {

        _encoded = true;

        _imm = x >> 12;

        _shift = lsl12;

      } else {

        _encoded = false;

      }

    }

    ArithmeticImmediate(intx x, AsmShift12 sh) {

      if (is_unsigned_imm_in_range(x, 12, 0)) {

        _encoded = true;

        _imm = x;

        _shift = sh;

      } else {

        _encoded = false;

      }

    }

    // Returns true if this immediate can be used in AArch64 arithmetic (add/sub/cmp/cmn) instructions.

    bool is_encoded() const  { return _encoded; }

    int imm() const          { assert(_encoded, "should be"); return _imm; }

    AsmShift12 shift() const { assert(_encoded, "should be"); return _shift; }

  };

  static inline bool is_imm_in_range(intx value, int bits, int align_bits) {

    intx sign_bits = (value >> (bits + align_bits - 1));

    return ((value & right_n_bits(align_bits)) == 0) && ((sign_bits == 0) || (sign_bits == -1));

  }

  static inline int encode_imm(intx value, int bits, int align_bits, int low_bit_in_encoding) {

    assert (is_imm_in_range(value, bits, align_bits), "immediate value is out of range");

    return ((value >> align_bits) & right_n_bits(bits)) << low_bit_in_encoding;

  }

  static inline bool is_unsigned_imm_in_range(intx value, int bits, int align_bits) {

    return (value >= 0) && ((value & right_n_bits(align_bits)) == 0) && ((value >> (align_bits + bits)) == 0);

  }

  static inline int encode_unsigned_imm(intx value, int bits, int align_bits, int low_bit_in_encoding) {

    assert (is_unsigned_imm_in_range(value, bits, align_bits), "immediate value is out of range");

    return (value >> align_bits) << low_bit_in_encoding;

  }

  static inline bool is_offset_in_range(intx offset, int bits) {

    assert (bits == 14 || bits == 19 || bits == 26, "wrong bits number");

    return is_imm_in_range(offset, bits, 2);

  }

  static inline int encode_offset(intx offset, int bits, int low_bit_in_encoding) {

    return encode_imm(offset, bits, 2, low_bit_in_encoding);

  }

  // Returns true if given value can be used as immediate in arithmetic (add/sub/cmp/cmn) instructions.

  static inline bool is_arith_imm_in_range(intx value) {

    return ArithmeticImmediate(value).is_encoded();

  }

  // Load/store instructions

#define F(mnemonic, opc) \

  void mnemonic(Register rd, address literal_addr) {                                                       \

    intx offset = literal_addr - pc();                                                                     \

    assert (opc != 0b01 || offset == 0 || ((uintx)literal_addr & 7) == 0, "ldr target should be aligned"); \

    assert (is_offset_in_range(offset, 19), "offset is out of range");                                     \

    emit_int32(opc << 30 | 0b011 << 27 | encode_offset(offset, 19, 5) | rd->encoding_with_zr());           \

  }

  F(ldr_w, 0b00)

  F(ldr,   0b01)

  F(ldrsw, 0b10)

#undef F

#define F(mnemonic, opc) \

  void mnemonic(FloatRegister rt, address literal_addr) {                                                  \

    intx offset = literal_addr - pc();                                                                     \

    assert (offset == 0 || ((uintx)literal_addr & right_n_bits(2 + opc)) == 0, "ldr target should be aligned"); \

    assert (is_offset_in_range(offset, 19), "offset is out of range");                                     \

    emit_int32(opc << 30 | 0b011100 << 24 | encode_offset(offset, 19, 5) | rt->encoding());                \

  }

  F(ldr_s, 0b00)

  F(ldr_d, 0b01)

  F(ldr_q, 0b10)

#undef F

#define F(mnemonic, size, o2, L, o1, o0) \

  void mnemonic(Register rt, Register rn) {                                                                \

    emit_int32(size << 30 | 0b001000 << 24 | o2 << 23 | L << 22 | o1 << 21 | 0b11111 << 16 |               \

        o0 << 15 | 0b11111 << 10 | rn->encoding_with_sp() << 5 | rt->encoding_with_zr());                  \

  }

  F(ldxrb,   0b00, 0, 1, 0, 0)

  F(ldaxrb,  0b00, 0, 1, 0, 1)

  F(ldarb,   0b00, 1, 1, 0, 1)

  F(ldxrh,   0b01, 0, 1, 0, 0)

  F(ldaxrh,  0b01, 0, 1, 0, 1)

  F(ldarh,   0b01, 1, 1, 0, 1)

  F(ldxr_w,  0b10, 0, 1, 0, 0)

  F(ldaxr_w, 0b10, 0, 1, 0, 1)

  F(ldar_w,  0b10, 1, 1, 0, 1)

  F(ldxr,    0b11, 0, 1, 0, 0)

  F(ldaxr,   0b11, 0, 1, 0, 1)

  F(ldar,    0b11, 1, 1, 0, 1)

  F(stlrb,   0b00, 1, 0, 0, 1)

  F(stlrh,   0b01, 1, 0, 0, 1)

  F(stlr_w,  0b10, 1, 0, 0, 1)

  F(stlr,    0b11, 1, 0, 0, 1)

#undef F

#define F(mnemonic, size, o2, L, o1, o0) \

  void mnemonic(Register rs, Register rt, Register rn) {                                                     \

    assert (rs != rt, "should be different");                                                                \

    assert (rs != rn, "should be different");                                                                \

    emit_int32(size << 30 | 0b001000 << 24 | o2 << 23 | L << 22 | o1 << 21 | rs->encoding_with_zr() << 16 |  \

        o0 << 15 | 0b11111 << 10 | rn->encoding_with_sp() << 5 | rt->encoding_with_zr());                    \

  }

  F(stxrb,   0b00, 0, 0, 0, 0)

  F(stlxrb,  0b00, 0, 0, 0, 1)

  F(stxrh,   0b01, 0, 0, 0, 0)

  F(stlxrh,  0b01, 0, 0, 0, 1)

  F(stxr_w,  0b10, 0, 0, 0, 0)

  F(stlxr_w, 0b10, 0, 0, 0, 1)

  F(stxr,    0b11, 0, 0, 0, 0)

  F(stlxr,   0b11, 0, 0, 0, 1)

#undef F

#define F(mnemonic, size, o2, L, o1, o0) \

  void mnemonic(Register rt, Register rt2, Register rn) {                                                  \

    assert (rt != rt2, "should be different");                                                             \

    emit_int32(size << 30 | 0b001000 << 24 | o2 << 23 | L << 22 | o1 << 21 | 0b11111 << 16 |               \

        o0 << 15 | rt2->encoding_with_zr() << 10 | rn->encoding_with_sp() << 5 | rt->encoding_with_zr());  \

  }

  F(ldxp_w,  0b10, 0, 1, 1, 0)

  F(ldaxp_w, 0b10, 0, 1, 1, 1)

  F(ldxp,    0b11, 0, 1, 1, 0)

  F(ldaxp,   0b11, 0, 1, 1, 1)

#undef F

#define F(mnemonic, size, o2, L, o1, o0) \

  void mnemonic(Register rs, Register rt, Register rt2, Register rn) {                                       \

    assert (rs != rt, "should be different");                                                                \

    assert (rs != rt2, "should be different");                                                               \

    assert (rs != rn, "should be different");                                                                \

    emit_int32(size << 30 | 0b001000 << 24 | o2 << 23 | L << 22 | o1 << 21 | rs->encoding_with_zr() << 16 |  \

        o0 << 15 | rt2->encoding_with_zr() << 10 | rn->encoding_with_sp() << 5 | rt->encoding_with_zr());    \

  }

  F(stxp_w,  0b10, 0, 0, 1, 0)

  F(stlxp_w, 0b10, 0, 0, 1, 1)

  F(stxp,    0b11, 0, 0, 1, 0)

  F(stlxp,   0b11, 0, 0, 1, 1)

#undef F

#define F(mnemonic, opc, V, L) \

  void mnemonic(Register rt, Register rt2, Register rn, int offset = 0) {                                  \

    assert (!L || rt != rt2, "should be different");                                                       \

    int align_bits = 2 + (opc >> 1);                                                                       \

    assert (is_imm_in_range(offset, 7, align_bits), "offset is out of range");                             \

    emit_int32(opc << 30 | 0b101 << 27 | V << 26 | L << 22 | encode_imm(offset, 7, align_bits, 15) |       \

        rt2->encoding_with_zr() << 10 | rn->encoding_with_sp() << 5 | rt->encoding_with_zr());             \

  }

  F(stnp_w,  0b00, 0, 0)

  F(ldnp_w,  0b00, 0, 1)

  F(stnp,    0b10, 0, 0)

  F(ldnp,    0b10, 0, 1)

#undef F

#define F(mnemonic, opc, V, L) \

  void mnemonic(FloatRegister rt, FloatRegister rt2, Register rn, int offset = 0) {                        \

    assert (!L || (rt != rt2), "should be different");                                                     \

    int align_bits = 2 + opc;                                                                              \

    assert (is_imm_in_range(offset, 7, align_bits), "offset is out of range");                             \

    emit_int32(opc << 30 | 0b101 << 27 | V << 26 | L << 22 | encode_imm(offset, 7, align_bits, 15) |       \

        rt2->encoding() << 10 | rn->encoding_with_sp() << 5 | rt->encoding());                             \

  }

  F(stnp_s,  0b00, 1, 0)

  F(stnp_d,  0b01, 1, 0)

  F(stnp_q,  0b10, 1, 0)

  F(ldnp_s,  0b00, 1, 1)

  F(ldnp_d,  0b01, 1, 1)

  F(ldnp_q,  0b10, 1, 1)

#undef F

#define F(mnemonic, size, V, opc) \

  void mnemonic(Register rt, Address addr) { \

    assert((addr.mode() == basic_offset) || (rt != addr.base()), "should be different");                    \

    if (addr.index() == noreg) {                                                                            \

      if ((addr.mode() == basic_offset) && is_unsigned_imm_in_range(addr.disp(), 12, size)) {               \

        emit_int32(size << 30 | 0b111 << 27 | V << 26 | 0b01 << 24 | opc << 22 |                            \

           encode_unsigned_imm(addr.disp(), 12, size, 10) |                                                 \

           addr.base()->encoding_with_sp() << 5 | rt->encoding_with_zr());                                  \

      } else {                                                                                              \

        assert(is_imm_in_range(addr.disp(), 9, 0), "offset is out of range");                               \

        emit_int32(size << 30 | 0b111 << 27 | V << 26 | opc << 22 | encode_imm(addr.disp(), 9, 0, 12) |     \

           addr.mode() << 10 | addr.base()->encoding_with_sp() << 5 | rt->encoding_with_zr());              \

      }                                                                                                     \

    } else {                                                                                                \

      assert (addr.disp() == 0, "non-zero displacement for [reg + reg] address mode");                      \

      assert ((addr.shift_imm() == 0) || (addr.shift_imm() == size), "invalid shift amount");               \

      emit_int32(size << 30 | 0b111 << 27 | V << 26 | opc << 22 | 1 << 21 |                                 \

         addr.index()->encoding_with_zr() << 16 | addr.extend() << 13 | (addr.shift_imm() != 0) << 12 |     \

         0b10 << 10 | addr.base()->encoding_with_sp() << 5 | rt->encoding_with_zr());                       \

    }                                                                                                       \

  }

  F(strb,    0b00, 0, 0b00)

  F(ldrb,    0b00, 0, 0b01)

  F(ldrsb,   0b00, 0, 0b10)

  F(ldrsb_w, 0b00, 0, 0b11)

  F(strh,    0b01, 0, 0b00)

  F(ldrh,    0b01, 0, 0b01)

  F(ldrsh,   0b01, 0, 0b10)

  F(ldrsh_w, 0b01, 0, 0b11)

  F(str_w,   0b10, 0, 0b00)

  F(ldr_w,   0b10, 0, 0b01)

  F(ldrsw,   0b10, 0, 0b10)

  F(str,     0b11, 0, 0b00)

  F(ldr,     0b11, 0, 0b01)

#undef F

#define F(mnemonic, size, V, opc) \

  void mnemonic(AsmPrefetchOp prfop, Address addr) { \

    assert (addr.mode() == basic_offset, #mnemonic " supports only basic_offset address mode");             \

    if (addr.index() == noreg) {                                                                            \

      if (is_unsigned_imm_in_range(addr.disp(), 12, size)) {                                                \

        emit_int32(size << 30 | 0b111 << 27 | V << 26 | 0b01 << 24 | opc << 22 |                            \

           encode_unsigned_imm(addr.disp(), 12, size, 10) |                                                 \

           addr.base()->encoding_with_sp() << 5 | prfop);                                                   \

      } else {                                                                                              \

        assert(is_imm_in_range(addr.disp(), 9, 0), "offset is out of range");                               \

        emit_int32(size << 30 | 0b111 << 27 | V << 26 | opc << 22 | encode_imm(addr.disp(), 9, 0, 12) |     \

           addr.base()->encoding_with_sp() << 5 | prfop);                                                   \

      }                                                                                                     \

    } else {                                                                                                \

      assert (addr.disp() == 0, "non-zero displacement for [reg + reg] address mode");                      \

      assert ((addr.shift_imm() == 0) || (addr.shift_imm() == size), "invalid shift amount");               \

      emit_int32(size << 30 | 0b111 << 27 | V << 26 | opc << 22 | 1 << 21 |                                 \

         addr.index()->encoding_with_zr() << 16 | addr.extend() << 13 | (addr.shift_imm() != 0) << 12 |     \

         0b10 << 10 | addr.base()->encoding_with_sp() << 5 | prfop);                                        \

    }                                                                                                       \

  }

  F(prfm, 0b11, 0, 0b10)

#undef F

#define F(mnemonic, size, V, opc) \

  void mnemonic(FloatRegister rt, Address addr) { \

    int align_bits = (((opc & 0b10) >> 1) << 2) | size;                                                     \

    if (addr.index() == noreg) {                                                                            \

      if ((addr.mode() == basic_offset) && is_unsigned_imm_in_range(addr.disp(), 12, align_bits)) {         \

        emit_int32(size << 30 | 0b111 << 27 | V << 26 | 0b01 << 24 | opc << 22 |                            \

           encode_unsigned_imm(addr.disp(), 12, align_bits, 10) |                                           \

           addr.base()->encoding_with_sp() << 5 | rt->encoding());                                          \

      } else {                                                                                              \

        assert(is_imm_in_range(addr.disp(), 9, 0), "offset is out of range");                               \

        emit_int32(size << 30 | 0b111 << 27 | V << 26 | opc << 22 | encode_imm(addr.disp(), 9, 0, 12) |     \

           addr.mode() << 10 | addr.base()->encoding_with_sp() << 5 | rt->encoding());                      \

      }                                                                                                     \

    } else {                                                                                                \

      assert (addr.disp() == 0, "non-zero displacement for [reg + reg] address mode");                      \

      assert ((addr.shift_imm() == 0) || (addr.shift_imm() == align_bits), "invalid shift amount");         \

      emit_int32(size << 30 | 0b111 << 27 | V << 26 | opc << 22 | 1 << 21 |                                 \

         addr.index()->encoding_with_zr() << 16 | addr.extend() << 13 | (addr.shift_imm() != 0) << 12 |     \

         0b10 << 10 | addr.base()->encoding_with_sp() << 5 | rt->encoding());                               \

    }                                                                                                       \

  }

  F(str_b, 0b00, 1, 0b00)

  F(ldr_b, 0b00, 1, 0b01)

  F(str_h, 0b01, 1, 0b00)

  F(ldr_h, 0b01, 1, 0b01)

  F(str_s, 0b10, 1, 0b00)

  F(ldr_s, 0b10, 1, 0b01)

  F(str_d, 0b11, 1, 0b00)

  F(ldr_d, 0b11, 1, 0b01)

  F(str_q, 0b00, 1, 0b10)

  F(ldr_q, 0b00, 1, 0b11)

#undef F

#define F(mnemonic, opc, V, L) \

  void mnemonic(Register rt, Register rt2, Address addr) {                                                         \

    assert((addr.mode() == basic_offset) || ((rt != addr.base()) && (rt2 != addr.base())), "should be different"); \

    assert(!L || (rt != rt2), "should be different");                                                              \

    assert(addr.index() == noreg, "[reg + reg] address mode is not available for load/store pair");                \

    int align_bits = 2 + (opc >> 1);                                                                               \

    int mode_encoding = (addr.mode() == basic_offset) ? 0b10 : addr.mode();                                        \

    assert(is_imm_in_range(addr.disp(), 7, align_bits), "offset is out of range");                                 \

    emit_int32(opc << 30 | 0b101 << 27 | V << 26 | mode_encoding << 23 | L << 22 |                                 \

       encode_imm(addr.disp(), 7, align_bits, 15) | rt2->encoding_with_zr() << 10 |                                \

       addr.base()->encoding_with_sp() << 5 | rt->encoding_with_zr());                                             \

  }

  F(stp_w, 0b00, 0, 0)

  F(ldp_w, 0b00, 0, 1)

  F(ldpsw, 0b01, 0, 1)

  F(stp,   0b10, 0, 0)

  F(ldp,   0b10, 0, 1)

#undef F

#define F(mnemonic, opc, V, L) \

  void mnemonic(FloatRegister rt, FloatRegister rt2, Address addr) {                                                         \

    assert(!L || (rt != rt2), "should be different");                                                              \

    assert(addr.index() == noreg, "[reg + reg] address mode is not available for load/store pair");                \

    int align_bits = 2 + opc;                                                                                      \

    int mode_encoding = (addr.mode() == basic_offset) ? 0b10 : addr.mode();                                        \

    assert(is_imm_in_range(addr.disp(), 7, align_bits), "offset is out of range");                                 \

    emit_int32(opc << 30 | 0b101 << 27 | V << 26 | mode_encoding << 23 | L << 22 |                                 \

       encode_imm(addr.disp(), 7, align_bits, 15) | rt2->encoding() << 10 |                                        \

       addr.base()->encoding_with_sp() << 5 | rt->encoding());                                                     \

  }

  F(stp_s, 0b00, 1, 0)

  F(ldp_s, 0b00, 1, 1)

  F(stp_d, 0b01, 1, 0)

  F(ldp_d, 0b01, 1, 1)

  F(stp_q, 0b10, 1, 0)

  F(ldp_q, 0b10, 1, 1)

#undef F

  // Data processing instructions

#define F(mnemonic, sf, opc) \

  void mnemonic(Register rd, Register rn, const LogicalImmediate& imm) {                      \

    assert (imm.is_encoded(), "illegal immediate for logical instruction");                   \

    assert (imm.is32bit() == (sf == 0), "immediate size does not match instruction size");    \

    emit_int32(sf << 31 | opc << 29 | 0b100100 << 23 | imm.immN() << 22 | imm.immr() << 16 |  \

        imm.imms() << 10 | rn->encoding_with_zr() << 5 |                                      \

        ((opc == 0b11) ? rd->encoding_with_zr() : rd->encoding_with_sp()));                   \

  }                                                                                           \

  void mnemonic(Register rd, Register rn, uintx imm) {                                        \

    LogicalImmediate limm(imm, (sf == 0));                                                    \

    mnemonic(rd, rn, limm);                                                                   \

  }                                                                                           \

  void mnemonic(Register rd, Register rn, unsigned int imm) {                                 \

    mnemonic(rd, rn, (uintx)imm);                                                             \

  }

  F(andr_w, 0, 0b00)

  F(orr_w,  0, 0b01)

  F(eor_w,  0, 0b10)

  F(ands_w, 0, 0b11)

  F(andr, 1, 0b00)

  F(orr,  1, 0b01)

  F(eor,  1, 0b10)

  F(ands, 1, 0b11)

#undef F

  void tst(Register rn, unsigned int imm) {

    ands(ZR, rn, imm);

  }

  void tst_w(Register rn, unsigned int imm) {

    ands_w(ZR, rn, imm);

  }

#define F(mnemonic, sf, opc, N) \