src/hotspot/cpu/aarch64/vm_version_aarch64.cpp
author fyang
Fri, 01 Mar 2019 14:38:59 +0800
changeset 53989 247f1a85d736
parent 53943 72ce7dd54939
child 54117 a6221f993616
permissions -rw-r--r--
8219888: aarch64: add CPU detection code for HiSilicon TSV110 Reviewed-by: aph, drwhite, pzhang Contributed-by: dongbo4@huawei.com
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/*
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 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
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 * Copyright (c) 2015, Red Hat Inc. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#include "precompiled.hpp"
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#include "asm/macroAssembler.hpp"
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#include "asm/macroAssembler.inline.hpp"
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#include "memory/resourceArea.hpp"
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#include "runtime/java.hpp"
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#include "runtime/stubCodeGenerator.hpp"
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#include "utilities/macros.hpp"
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#include "vm_version_aarch64.hpp"
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#include OS_HEADER_INLINE(os)
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#ifndef BUILTIN_SIM
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#include <sys/auxv.h>
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#include <asm/hwcap.h>
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#else
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#define getauxval(hwcap) 0
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#endif
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#ifndef HWCAP_AES
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#define HWCAP_AES   (1<<3)
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#endif
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#ifndef HWCAP_PMULL
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#define HWCAP_PMULL (1<<4)
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#endif
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#ifndef HWCAP_SHA1
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#define HWCAP_SHA1  (1<<5)
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#endif
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#ifndef HWCAP_SHA2
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#define HWCAP_SHA2  (1<<6)
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#endif
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#ifndef HWCAP_CRC32
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#define HWCAP_CRC32 (1<<7)
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#endif
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#ifndef HWCAP_ATOMICS
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#define HWCAP_ATOMICS (1<<8)
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#endif
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int VM_Version::_cpu;
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int VM_Version::_model;
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int VM_Version::_model2;
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int VM_Version::_variant;
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int VM_Version::_revision;
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int VM_Version::_stepping;
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VM_Version::PsrInfo VM_Version::_psr_info   = { 0, };
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static BufferBlob* stub_blob;
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static const int stub_size = 550;
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extern "C" {
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  typedef void (*getPsrInfo_stub_t)(void*);
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}
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static getPsrInfo_stub_t getPsrInfo_stub = NULL;
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class VM_Version_StubGenerator: public StubCodeGenerator {
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 public:
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  VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
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  address generate_getPsrInfo() {
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    StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
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#   define __ _masm->
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    address start = __ pc();
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#ifdef BUILTIN_SIM
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    __ c_stub_prolog(1, 0, MacroAssembler::ret_type_void);
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#endif
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    // void getPsrInfo(VM_Version::PsrInfo* psr_info);
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    address entry = __ pc();
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    __ enter();
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    __ get_dczid_el0(rscratch1);
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    __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::dczid_el0_offset())));
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    __ get_ctr_el0(rscratch1);
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    __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::ctr_el0_offset())));
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    __ leave();
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    __ ret(lr);
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#   undef __
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    return start;
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  }
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};
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void VM_Version::get_processor_features() {
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  _supports_cx8 = true;
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  _supports_atomic_getset4 = true;
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  _supports_atomic_getadd4 = true;
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  _supports_atomic_getset8 = true;
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  _supports_atomic_getadd8 = true;
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  getPsrInfo_stub(&_psr_info);
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  int dcache_line = VM_Version::dcache_line_size();
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  if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
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    FLAG_SET_DEFAULT(AllocatePrefetchDistance, 3*dcache_line);
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  if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
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    FLAG_SET_DEFAULT(AllocatePrefetchStepSize, dcache_line);
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  if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes))
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    FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 3*dcache_line);
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  if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes))
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    FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 3*dcache_line);
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  if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance))
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    FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, 3*dcache_line);
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  if (PrefetchCopyIntervalInBytes != -1 &&
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       ((PrefetchCopyIntervalInBytes & 7) || (PrefetchCopyIntervalInBytes >= 32768))) {
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    warning("PrefetchCopyIntervalInBytes must be -1, or a multiple of 8 and < 32768");
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    PrefetchCopyIntervalInBytes &= ~7;
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    if (PrefetchCopyIntervalInBytes >= 32768)
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      PrefetchCopyIntervalInBytes = 32760;
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  }
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  if (AllocatePrefetchDistance !=-1 && (AllocatePrefetchDistance & 7)) {
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    warning("AllocatePrefetchDistance must be multiple of 8");
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    AllocatePrefetchDistance &= ~7;
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   154
  }
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   156
  if (AllocatePrefetchStepSize & 7) {
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   157
    warning("AllocatePrefetchStepSize must be multiple of 8");
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   158
    AllocatePrefetchStepSize &= ~7;
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   159
  }
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   160
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   161
  if (SoftwarePrefetchHintDistance != -1 &&
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   162
       (SoftwarePrefetchHintDistance & 7)) {
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   163
    warning("SoftwarePrefetchHintDistance must be -1, or a multiple of 8");
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   164
    SoftwarePrefetchHintDistance &= ~7;
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   165
  }
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   166
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  unsigned long auxv = getauxval(AT_HWCAP);
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   169
  char buf[512];
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   170
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   171
  _features = auxv;
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   173
  int cpu_lines = 0;
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   174
  if (FILE *f = fopen("/proc/cpuinfo", "r")) {
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   175
    char buf[128], *p;
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   176
    while (fgets(buf, sizeof (buf), f) != NULL) {
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   177
      if (p = strchr(buf, ':')) {
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   178
        long v = strtol(p+1, NULL, 0);
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   179
        if (strncmp(buf, "CPU implementer", sizeof "CPU implementer" - 1) == 0) {
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   180
          _cpu = v;
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   181
          cpu_lines++;
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   182
        } else if (strncmp(buf, "CPU variant", sizeof "CPU variant" - 1) == 0) {
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   183
          _variant = v;
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   184
        } else if (strncmp(buf, "CPU part", sizeof "CPU part" - 1) == 0) {
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   185
          if (_model != v)  _model2 = _model;
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   186
          _model = v;
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   187
        } else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) {
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   188
          _revision = v;
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   189
        }
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   190
      }
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   191
    }
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   192
    fclose(f);
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   193
  }
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   194
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   195
  // Enable vendor specific features
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   196
cf4562e8a3f9 8198293: AARCH64 - Add CPU detection code for Cavium Thunder X2
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   197
  // ThunderX
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   198
  if (_cpu == CPU_CAVIUM && (_model == 0xA1)) {
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   199
    if (_variant == 0) _features |= CPU_DMB_ATOMICS;
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   200
    if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
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   201
      FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
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   202
    }
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   203
    if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
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   204
      FLAG_SET_DEFAULT(UseSIMDForMemoryOps, (_variant > 0));
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   205
    }
49724
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   206
    if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
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   207
      FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
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   208
    }
40023
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   209
  }
49724
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   210
49173
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   211
  // ThunderX2
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   212
  if ((_cpu == CPU_CAVIUM && (_model == 0xAF)) ||
cf4562e8a3f9 8198293: AARCH64 - Add CPU detection code for Cavium Thunder X2
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   213
      (_cpu == CPU_BROADCOM && (_model == 0x516))) {
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diff changeset
   214
    if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
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   215
      FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
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   216
    }
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   217
    if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
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   218
      FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
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   219
    }
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   220
  }
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parents: 48196
diff changeset
   221
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   222
  // HiSilicon TSV110
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diff changeset
   223
  if (_cpu == CPU_HISILICON && _model == 0xd01) {
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diff changeset
   224
    if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
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   225
      FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
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parents: 53943
diff changeset
   226
    }
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diff changeset
   227
    if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
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   228
      FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
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diff changeset
   229
    }
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diff changeset
   230
  }
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parents: 53943
diff changeset
   231
49724
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   232
  // Cortex A53
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diff changeset
   233
  if (_cpu == CPU_ARM && (_model == 0xd03 || _model2 == 0xd03)) {
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diff changeset
   234
    _features |= CPU_A53MAC;
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dpochepk
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diff changeset
   235
    if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
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parents: 49173
diff changeset
   236
      FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
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diff changeset
   237
    }
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diff changeset
   238
  }
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
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diff changeset
   239
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
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diff changeset
   240
  // Cortex A73
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
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diff changeset
   241
  if (_cpu == CPU_ARM && (_model == 0xd09 || _model2 == 0xd09)) {
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
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parents: 49173
diff changeset
   242
    if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance)) {
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
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diff changeset
   243
      FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, -1);
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diff changeset
   244
    }
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diff changeset
   245
    // A73 is faster with short-and-easy-for-speculative-execution-loop
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49173
diff changeset
   246
    if (FLAG_IS_DEFAULT(UseSimpleArrayEquals)) {
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
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diff changeset
   247
      FLAG_SET_DEFAULT(UseSimpleArrayEquals, true);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
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diff changeset
   248
    }
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
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diff changeset
   249
  }
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
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diff changeset
   250
38714
170464570e45 8157841: aarch64: prefetch ignores cache line size
enevill
parents: 38143
diff changeset
   251
  if (_cpu == CPU_ARM && (_model == 0xd07 || _model2 == 0xd07)) _features |= CPU_STXR_PREFETCH;
30429
c980154ed1a3 8079203: AARCH64: Need to cater for different partner implementations
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diff changeset
   252
  // If an olde style /proc/cpuinfo (cpu_lines == 1) then if _model is an A57 (0xd07)
c980154ed1a3 8079203: AARCH64: Need to cater for different partner implementations
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diff changeset
   253
  // we assume the worst and assume we could be on a big little system and have
c980154ed1a3 8079203: AARCH64: Need to cater for different partner implementations
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diff changeset
   254
  // undisclosed A53 cores which we could be swapped to at any stage
35148
5cfafc99d791 8143072: [JVMCI] Port JVMCI to AArch64
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parents: 35110
diff changeset
   255
  if (_cpu == CPU_ARM && cpu_lines == 1 && _model == 0xd07) _features |= CPU_A53MAC;
30429
c980154ed1a3 8079203: AARCH64: Need to cater for different partner implementations
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diff changeset
   256
c980154ed1a3 8079203: AARCH64: Need to cater for different partner implementations
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diff changeset
   257
  sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
c980154ed1a3 8079203: AARCH64: Need to cater for different partner implementations
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diff changeset
   258
  if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2);
c980154ed1a3 8079203: AARCH64: Need to cater for different partner implementations
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diff changeset
   259
  if (auxv & HWCAP_ASIMD) strcat(buf, ", simd");
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   260
  if (auxv & HWCAP_CRC32) strcat(buf, ", crc");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   261
  if (auxv & HWCAP_AES)   strcat(buf, ", aes");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   262
  if (auxv & HWCAP_SHA1)  strcat(buf, ", sha1");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   263
  if (auxv & HWCAP_SHA2)  strcat(buf, ", sha256");
36562
4d1e93624d6a 8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents: 35841
diff changeset
   264
  if (auxv & HWCAP_ATOMICS) strcat(buf, ", lse");
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   265
35148
5cfafc99d791 8143072: [JVMCI] Port JVMCI to AArch64
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diff changeset
   266
  _features_string = os::strdup(buf);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   267
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   268
  if (FLAG_IS_DEFAULT(UseCRC32)) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   269
    UseCRC32 = (auxv & HWCAP_CRC32) != 0;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   270
  }
53943
72ce7dd54939 8219698: aarch64: SIGILL triggered when specifying unsupported hardware features
fyang
parents: 52425
diff changeset
   271
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   272
  if (UseCRC32 && (auxv & HWCAP_CRC32) == 0) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   273
    warning("UseCRC32 specified, but not supported on this CPU");
53943
72ce7dd54939 8219698: aarch64: SIGILL triggered when specifying unsupported hardware features
fyang
parents: 52425
diff changeset
   274
    FLAG_SET_DEFAULT(UseCRC32, false);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   275
  }
32581
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31961
diff changeset
   276
33176
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32581
diff changeset
   277
  if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
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diff changeset
   278
    FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
32581
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31961
diff changeset
   279
  }
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31961
diff changeset
   280
35110
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 33176
diff changeset
   281
  if (UseVectorizedMismatchIntrinsic) {
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
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parents: 33176
diff changeset
   282
    warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 33176
diff changeset
   283
    FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 33176
diff changeset
   284
  }
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 33176
diff changeset
   285
36562
4d1e93624d6a 8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents: 35841
diff changeset
   286
  if (auxv & HWCAP_ATOMICS) {
4d1e93624d6a 8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents: 35841
diff changeset
   287
    if (FLAG_IS_DEFAULT(UseLSE))
4d1e93624d6a 8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents: 35841
diff changeset
   288
      FLAG_SET_DEFAULT(UseLSE, true);
4d1e93624d6a 8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents: 35841
diff changeset
   289
  } else {
4d1e93624d6a 8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents: 35841
diff changeset
   290
    if (UseLSE) {
4d1e93624d6a 8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents: 35841
diff changeset
   291
      warning("UseLSE specified, but not supported on this CPU");
53943
72ce7dd54939 8219698: aarch64: SIGILL triggered when specifying unsupported hardware features
fyang
parents: 52425
diff changeset
   292
      FLAG_SET_DEFAULT(UseLSE, false);
36562
4d1e93624d6a 8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents: 35841
diff changeset
   293
    }
4d1e93624d6a 8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents: 35841
diff changeset
   294
  }
4d1e93624d6a 8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents: 35841
diff changeset
   295
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   296
  if (auxv & HWCAP_AES) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   297
    UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   298
    UseAESIntrinsics =
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   299
        UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   300
    if (UseAESIntrinsics && !UseAES) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   301
      warning("UseAESIntrinsics enabled, but UseAES not, enabling");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   302
      UseAES = true;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   303
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   304
  } else {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   305
    if (UseAES) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   306
      warning("UseAES specified, but not supported on this CPU");
53943
72ce7dd54939 8219698: aarch64: SIGILL triggered when specifying unsupported hardware features
fyang
parents: 52425
diff changeset
   307
      FLAG_SET_DEFAULT(UseAES, false);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   308
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   309
    if (UseAESIntrinsics) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   310
      warning("UseAESIntrinsics specified, but not supported on this CPU");
53943
72ce7dd54939 8219698: aarch64: SIGILL triggered when specifying unsupported hardware features
fyang
parents: 52425
diff changeset
   311
      FLAG_SET_DEFAULT(UseAESIntrinsics, false);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   312
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   313
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   314
35154
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35148
diff changeset
   315
  if (UseAESCTRIntrinsics) {
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35148
diff changeset
   316
    warning("AES/CTR intrinsics are not available on this CPU");
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35148
diff changeset
   317
    FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35148
diff changeset
   318
  }
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35148
diff changeset
   319
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   320
  if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   321
    UseCRC32Intrinsics = true;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   322
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   323
31591
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 31588
diff changeset
   324
  if (auxv & HWCAP_CRC32) {
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 31588
diff changeset
   325
    if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 31588
diff changeset
   326
      FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 31588
diff changeset
   327
    }
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 31588
diff changeset
   328
  } else if (UseCRC32CIntrinsics) {
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 31588
diff changeset
   329
    warning("CRC32C is not available on the CPU");
31515
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
   330
    FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
   331
  }
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
   332
42653
62a5d76872d4 8162338: AArch64: Intrinsify fused mac operations
roland
parents: 41323
diff changeset
   333
  if (FLAG_IS_DEFAULT(UseFMA)) {
62a5d76872d4 8162338: AArch64: Intrinsify fused mac operations
roland
parents: 41323
diff changeset
   334
    FLAG_SET_DEFAULT(UseFMA, true);
41323
ddd5600d4762 8154122: Intrinsify fused mac operations
vdeshpande
parents: 40093
diff changeset
   335
  }
ddd5600d4762 8154122: Intrinsify fused mac operations
vdeshpande
parents: 40093
diff changeset
   336
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   337
  if (auxv & (HWCAP_SHA1 | HWCAP_SHA2)) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   338
    if (FLAG_IS_DEFAULT(UseSHA)) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   339
      FLAG_SET_DEFAULT(UseSHA, true);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   340
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   341
  } else if (UseSHA) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   342
    warning("SHA instructions are not available on this CPU");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   343
    FLAG_SET_DEFAULT(UseSHA, false);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   344
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   345
31588
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   346
  if (UseSHA && (auxv & HWCAP_SHA1)) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   347
    if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   348
      FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   349
    }
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   350
  } else if (UseSHA1Intrinsics) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   351
    warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   352
    FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
31588
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   353
  }
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   354
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   355
  if (UseSHA && (auxv & HWCAP_SHA2)) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   356
    if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   357
      FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   358
    }
31588
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   359
  } else if (UseSHA256Intrinsics) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   360
    warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
31960
4e66771a3e0a 8132010: aarch64: regression test fails compiler/intrinsics/sha/cli/TestUseSHA256IntrinsicsOptionOnSupportedCPU.java
enevill
parents: 31955
diff changeset
   361
    FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
31588
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   362
  }
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   363
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   364
  if (UseSHA512Intrinsics) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   365
    warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   366
    FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   367
  }
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   368
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   369
  if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   370
    FLAG_SET_DEFAULT(UseSHA, false);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   371
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   372
31961
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   373
  if (auxv & HWCAP_PMULL) {
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   374
    if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   375
      FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   376
    }
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   377
  } else if (UseGHASHIntrinsics) {
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   378
    warning("GHASH intrinsics are not available on this CPU");
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   379
    FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   380
  }
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   381
38143
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 36562
diff changeset
   382
  if (is_zva_enabled()) {
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 36562
diff changeset
   383
    if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 36562
diff changeset
   384
      FLAG_SET_DEFAULT(UseBlockZeroing, true);
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 36562
diff changeset
   385
    }
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 36562
diff changeset
   386
    if (FLAG_IS_DEFAULT(BlockZeroingLowLimit)) {
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 36562
diff changeset
   387
      FLAG_SET_DEFAULT(BlockZeroingLowLimit, 4 * VM_Version::zva_length());
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 36562
diff changeset
   388
    }
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 36562
diff changeset
   389
  } else if (UseBlockZeroing) {
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 36562
diff changeset
   390
    warning("DC ZVA is not available on this CPU");
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 36562
diff changeset
   391
    FLAG_SET_DEFAULT(UseBlockZeroing, false);
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 36562
diff changeset
   392
  }
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 36562
diff changeset
   393
30209
8ea30dc99369 8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents: 29183
diff changeset
   394
  // This machine allows unaligned memory accesses
8ea30dc99369 8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents: 29183
diff changeset
   395
  if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
8ea30dc99369 8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents: 29183
diff changeset
   396
    FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
8ea30dc99369 8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents: 29183
diff changeset
   397
  }
8ea30dc99369 8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents: 29183
diff changeset
   398
51619
dca697c71e5d 8207247: AARCH64: Enable Minimal and Client VM builds
avoitylov
parents: 49724
diff changeset
   399
  if (FLAG_IS_DEFAULT(UseBarriersForVolatile)) {
dca697c71e5d 8207247: AARCH64: Enable Minimal and Client VM builds
avoitylov
parents: 49724
diff changeset
   400
    UseBarriersForVolatile = (_features & CPU_DMB_ATOMICS) != 0;
dca697c71e5d 8207247: AARCH64: Enable Minimal and Client VM builds
avoitylov
parents: 49724
diff changeset
   401
  }
dca697c71e5d 8207247: AARCH64: Enable Minimal and Client VM builds
avoitylov
parents: 49724
diff changeset
   402
dca697c71e5d 8207247: AARCH64: Enable Minimal and Client VM builds
avoitylov
parents: 49724
diff changeset
   403
  if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
dca697c71e5d 8207247: AARCH64: Enable Minimal and Client VM builds
avoitylov
parents: 49724
diff changeset
   404
    UsePopCountInstruction = true;
dca697c71e5d 8207247: AARCH64: Enable Minimal and Client VM builds
avoitylov
parents: 49724
diff changeset
   405
  }
dca697c71e5d 8207247: AARCH64: Enable Minimal and Client VM builds
avoitylov
parents: 49724
diff changeset
   406
dca697c71e5d 8207247: AARCH64: Enable Minimal and Client VM builds
avoitylov
parents: 49724
diff changeset
   407
#ifdef COMPILER2
30225
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 30209
diff changeset
   408
  if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 30209
diff changeset
   409
    UseMultiplyToLenIntrinsic = true;
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 30209
diff changeset
   410
  }
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 30209
diff changeset
   411
47571
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
   412
  if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
   413
    UseSquareToLenIntrinsic = true;
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
   414
  }
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
   415
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
   416
  if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
   417
    UseMulAddIntrinsic = true;
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
   418
  }
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
   419
31955
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
   420
  if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
   421
    UseMontgomeryMultiplyIntrinsic = true;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
   422
  }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
   423
  if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
   424
    UseMontgomerySquareIntrinsic = true;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
   425
  }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
   426
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   427
  if (FLAG_IS_DEFAULT(OptoScheduling)) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   428
    OptoScheduling = true;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   429
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   430
#endif
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   431
}
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   432
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   433
void VM_Version::initialize() {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   434
  ResourceMark rm;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   435
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   436
  stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   437
  if (stub_blob == NULL) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   438
    vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   439
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   440
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   441
  CodeBuffer c(stub_blob);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   442
  VM_Version_StubGenerator g(&c);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   443
  getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   444
                                   g.generate_getPsrInfo());
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   445
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   446
  get_processor_features();
48182
5fb0f3f24f6b 8191129: AARCH64: Invalid value passed to critical JNI function
dchuyko
parents: 47571
diff changeset
   447
5fb0f3f24f6b 8191129: AARCH64: Invalid value passed to critical JNI function
dchuyko
parents: 47571
diff changeset
   448
  UNSUPPORTED_OPTION(CriticalJNINatives);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   449
}