author | kvn |
Tue, 04 Sep 2018 12:44:02 -0700 | |
changeset 51633 | 21154cb84d2a |
parent 47216 | 71c04702a3d5 |
child 52351 | 0ecb4e520110 |
permissions | -rw-r--r-- |
42664 | 1 |
/* |
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* Copyright (c) 2008, 2014, Oracle and/or its affiliates. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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#ifndef CPU_ARM_VM_MACROASSEMBLER_ARM_INLINE_HPP |
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#define CPU_ARM_VM_MACROASSEMBLER_ARM_INLINE_HPP |
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#include "asm/assembler.inline.hpp" |
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#include "asm/codeBuffer.hpp" |
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#include "code/codeCache.hpp" |
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#include "runtime/handles.inline.hpp" |
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51633
21154cb84d2a
8209594: guarantee(this->is8bit(imm8)) failed: Short forward jump exceeds 8-bit offset
kvn
parents:
47216
diff
changeset
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inline void MacroAssembler::pd_patch_instruction(address branch, address target, const char* file, int line) { |
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int instr = *(int*)branch; |
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int new_offset = (int)(target - branch NOT_AARCH64(- 8)); |
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assert((new_offset & 3) == 0, "bad alignment"); |
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#ifdef AARCH64 |
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if ((instr & (0x1f << 26)) == (0b00101 << 26)) { |
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// Unconditional B or BL |
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assert (is_offset_in_range(new_offset, 26), "offset is too large"); |
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*(int*)branch = (instr & ~right_n_bits(26)) | encode_offset(new_offset, 26, 0); |
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} else if ((instr & (0xff << 24)) == (0b01010100 << 24) && (instr & (1 << 4)) == 0) { |
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// Conditional B |
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assert (is_offset_in_range(new_offset, 19), "offset is too large"); |
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*(int*)branch = (instr & ~(right_n_bits(19) << 5)) | encode_offset(new_offset, 19, 5); |
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} else if ((instr & (0b111111 << 25)) == (0b011010 << 25)) { |
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// Compare & branch CBZ/CBNZ |
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assert (is_offset_in_range(new_offset, 19), "offset is too large"); |
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*(int*)branch = (instr & ~(right_n_bits(19) << 5)) | encode_offset(new_offset, 19, 5); |
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} else if ((instr & (0b111111 << 25)) == (0b011011 << 25)) { |
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// Test & branch TBZ/TBNZ |
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assert (is_offset_in_range(new_offset, 14), "offset is too large"); |
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*(int*)branch = (instr & ~(right_n_bits(14) << 5)) | encode_offset(new_offset, 14, 5); |
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} else if ((instr & (0b111011 << 24)) == (0b011000 << 24)) { |
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// LDR (literal) |
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unsigned opc = ((unsigned)instr >> 30); |
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assert (opc != 0b01 || ((uintx)target & 7) == 0, "ldr target should be aligned"); |
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assert (is_offset_in_range(new_offset, 19), "offset is too large"); |
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*(int*)branch = (instr & ~(right_n_bits(19) << 5)) | encode_offset(new_offset, 19, 5); |
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} else if (((instr & (1 << 31)) == 0) && ((instr & (0b11111 << 24)) == (0b10000 << 24))) { |
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// ADR |
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assert (is_imm_in_range(new_offset, 21, 0), "offset is too large"); |
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instr = (instr & ~(right_n_bits(2) << 29)) | (new_offset & 3) << 29; |
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*(int*)branch = (instr & ~(right_n_bits(19) << 5)) | encode_imm(new_offset >> 2, 19, 0, 5); |
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} else if((unsigned int)instr == address_placeholder_instruction) { |
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// address |
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assert (*(unsigned int *)(branch + InstructionSize) == address_placeholder_instruction, "address placeholder occupies two instructions"); |
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*(intx*)branch = (intx)target; |
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} else { |
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::tty->print_cr("=============== instruction: 0x%x ================\n", instr); |
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Unimplemented(); // TODO-AARCH64 |
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} |
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#else |
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if ((instr & 0x0e000000) == 0x0a000000) { |
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// B or BL instruction |
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assert(new_offset < 0x2000000 && new_offset > -0x2000000, "encoding constraint"); |
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*(int*)branch = (instr & 0xff000000) | ((unsigned int)new_offset << 6 >> 8); |
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} else if((unsigned int)instr == address_placeholder_instruction) { |
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// address |
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*(int*)branch = (int)target; |
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} else if ((instr & 0x0fff0000) == 0x028f0000 || ((instr & 0x0fff0000) == 0x024f0000)) { |
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// ADR |
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int encoding = 0x8 << 20; // ADD |
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if (new_offset < 0) { |
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encoding = 0x4 << 20; // SUB |
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new_offset = -new_offset; |
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} |
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AsmOperand o(new_offset); |
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*(int*)branch = (instr & 0xff0ff000) | encoding | o.encoding(); |
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} else { |
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// LDR Rd, [PC, offset] instruction |
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assert((instr & 0x0f7f0000) == 0x051f0000, "Must be ldr_literal"); |
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assert(new_offset < 4096 && new_offset > -4096, "encoding constraint"); |
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if (new_offset >= 0) { |
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*(int*)branch = (instr & 0xff0ff000) | 9 << 20 | new_offset; |
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} else { |
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*(int*)branch = (instr & 0xff0ff000) | 1 << 20 | -new_offset; |
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} |
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} |
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#endif // AARCH64 |
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} |
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#endif // CPU_ARM_VM_MACROASSEMBLER_ARM_INLINE_HPP |