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/*
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* Copyright (c) 2008, 2015, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#ifndef CPU_ARM_VM_REGISTER_ARM_HPP
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#define CPU_ARM_VM_REGISTER_ARM_HPP
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#include "asm/register.hpp"
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#include "vm_version_arm.hpp"
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class VMRegImpl;
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typedef VMRegImpl* VMReg;
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// These are declared ucontext.h
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#undef R0
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#undef R1
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#undef R2
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#undef R3
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#undef R4
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#undef R5
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#undef R6
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#undef R7
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#undef R8
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#undef R9
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#undef R10
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#undef R11
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#undef R12
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#undef R13
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#undef R14
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#undef R15
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#define R(r) ((Register)(r))
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/////////////////////////////////
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// Support for different ARM ABIs
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// Note: default ABI is for linux
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// R9_IS_SCRATCHED
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//
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// The ARM ABI does not guarantee that R9 is callee saved.
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// Set R9_IS_SCRATCHED to 1 to ensure it is properly saved/restored by
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// the caller.
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#ifndef R9_IS_SCRATCHED
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// Default: R9 is callee saved
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#define R9_IS_SCRATCHED 0
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#endif
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// FP_REG_NUM
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//
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// The ARM ABI does not state which register is used for the frame pointer.
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// Note: for the ABIs we are currently aware of, FP is currently
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// either R7 or R11. Code may have to be extended if a third register
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// register must be supported (see altFP_7_11).
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#ifndef FP_REG_NUM
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// Default: FP is R11
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#define FP_REG_NUM 11
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#endif
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// ALIGN_WIDE_ARGUMENTS
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//
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// The ARM ABI requires 64-bits arguments to be aligned on 4 words
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// or on even registers. Set ALIGN_WIDE_ARGUMENTS to 1 for that behavior.
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//
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// Unfortunately, some platforms do not endorse that part of the ABI.
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//
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// We are aware of one which expects 64-bit arguments to only be 4
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// bytes aligned and can for instance use R3 + a stack slot for such
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// an argument.
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//
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// This is the behavor implemented if (ALIGN_WIDE_ARGUMENTS == 0)
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#ifndef ALIGN_WIDE_ARGUMENTS
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// Default: align on 8 bytes and avoid using <r3+stack>
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#define ALIGN_WIDE_ARGUMENTS 1
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#endif
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#define R0 ((Register)0)
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#define R1 ((Register)1)
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#define R2 ((Register)2)
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#define R3 ((Register)3)
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#define R4 ((Register)4)
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#define R5 ((Register)5)
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#define R6 ((Register)6)
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#define R7 ((Register)7)
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#define R8 ((Register)8)
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#define R9 ((Register)9)
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#define R10 ((Register)10)
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#define R11 ((Register)11)
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#define R12 ((Register)12)
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#define R13 ((Register)13)
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#define R14 ((Register)14)
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#define R15 ((Register)15)
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#define FP ((Register)FP_REG_NUM)
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// Safe use of registers which may be FP on some platforms.
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//
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// altFP_7_11: R7 if not equal to FP, else R11 (the default FP)
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//
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// Note: add additional altFP_#_11 for each register potentially used
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// as FP on supported ABIs (and replace R# by altFP_#_11). altFP_#_11
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// must be #define to R11 if and only if # is FP_REG_NUM.
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#if (FP_REG_NUM == 7)
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#define altFP_7_11 ((Register)11)
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#else
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#define altFP_7_11 ((Register)7)
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#endif
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#define SP R13
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#define LR R14
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#define PC R15
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class RegisterImpl;
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typedef RegisterImpl* Register;
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inline Register as_Register(int encoding) {
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return (Register)(intptr_t)encoding;
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}
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class RegisterImpl : public AbstractRegisterImpl {
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public:
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enum {
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number_of_registers = 16
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};
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Register successor() const { return as_Register(encoding() + 1); }
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inline friend Register as_Register(int encoding);
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VMReg as_VMReg();
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// accessors
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int encoding() const { assert(is_valid(), "invalid register"); return value(); }
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const char* name() const;
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// testers
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bool is_valid() const { return 0 <= value() && value() < number_of_registers; }
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};
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CONSTANT_REGISTER_DECLARATION(Register, noreg, (-1));
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// Use FloatRegister as shortcut
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class FloatRegisterImpl;
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typedef FloatRegisterImpl* FloatRegister;
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inline FloatRegister as_FloatRegister(int encoding) {
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return (FloatRegister)(intptr_t)encoding;
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}
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class FloatRegisterImpl : public AbstractRegisterImpl {
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public:
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enum {
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number_of_registers = NOT_COMPILER2(32) COMPILER2_PRESENT(64)
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};
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inline friend FloatRegister as_FloatRegister(int encoding);
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VMReg as_VMReg();
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int encoding() const { assert(is_valid(), "invalid register"); return value(); }
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bool is_valid() const { return 0 <= (intx)this && (intx)this < number_of_registers; }
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FloatRegister successor() const { return as_FloatRegister(encoding() + 1); }
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const char* name() const;
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int hi_bits() const {
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return (encoding() >> 1) & 0xf;
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}
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int lo_bit() const {
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return encoding() & 1;
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}
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int hi_bit() const {
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return encoding() >> 5;
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}
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};
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CONSTANT_REGISTER_DECLARATION(FloatRegister, fnoreg, (-1));
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/*
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* S1-S6 are named with "_reg" suffix to avoid conflict with
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* constants defined in sharedRuntimeTrig.cpp
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*/
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S0, ( 0));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S1_reg, ( 1));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S2_reg, ( 2));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S3_reg, ( 3));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S4_reg, ( 4));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S5_reg, ( 5));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S6_reg, ( 6));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S7, ( 7));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S8, ( 8));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S9, ( 9));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S10, (10));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S11, (11));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S12, (12));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S13, (13));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S14, (14));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S15, (15));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S16, (16));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S17, (17));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S18, (18));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S19, (19));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S20, (20));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S21, (21));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S22, (22));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S23, (23));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S24, (24));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S25, (25));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S26, (26));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S27, (27));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S28, (28));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S29, (29));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S30, (30));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, S31, (31));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, Stemp, (30));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D0, ( 0));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D1, ( 2));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D2, ( 4));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D3, ( 6));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D4, ( 8));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D5, ( 10));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D6, ( 12));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D7, ( 14));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D8, ( 16));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D9, ( 18));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D10, ( 20));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D11, ( 22));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D12, ( 24));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D13, ( 26));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D14, ( 28));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D15, (30));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D16, (32));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D17, (34));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D18, (36));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D19, (38));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D20, (40));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D21, (42));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D22, (44));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D23, (46));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D24, (48));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D25, (50));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D26, (52));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D27, (54));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D28, (56));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D29, (58));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D30, (60));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, D31, (62));
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class ConcreteRegisterImpl : public AbstractRegisterImpl {
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public:
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enum {
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log_vmregs_per_word = LogBytesPerWord - LogBytesPerInt, // VMRegs are of 4-byte size
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#ifdef COMPILER2
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log_bytes_per_fpr = 2, // quad vectors
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#else
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log_bytes_per_fpr = 2, // double vectors
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#endif
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log_words_per_fpr = log_bytes_per_fpr - LogBytesPerWord,
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words_per_fpr = 1 << log_words_per_fpr,
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log_vmregs_per_fpr = log_bytes_per_fpr - LogBytesPerInt,
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log_vmregs_per_gpr = log_vmregs_per_word,
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vmregs_per_gpr = 1 << log_vmregs_per_gpr,
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vmregs_per_fpr = 1 << log_vmregs_per_fpr,
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num_gpr = RegisterImpl::number_of_registers << log_vmregs_per_gpr,
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max_gpr0 = num_gpr,
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num_fpr = FloatRegisterImpl::number_of_registers << log_vmregs_per_fpr,
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max_fpr0 = max_gpr0 + num_fpr,
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number_of_registers = num_gpr + num_fpr + 1+1 // APSR and FPSCR so that c2's REG_COUNT <= ConcreteRegisterImpl::number_of_registers
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};
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static const int max_gpr;
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static const int max_fpr;
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};
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class VFPSystemRegisterImpl;
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typedef VFPSystemRegisterImpl* VFPSystemRegister;
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class VFPSystemRegisterImpl : public AbstractRegisterImpl {
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public:
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int encoding() const { return value(); }
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};
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#define FPSID ((VFPSystemRegister)0)
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#define FPSCR ((VFPSystemRegister)1)
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#define MVFR0 ((VFPSystemRegister)0x6)
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#define MVFR1 ((VFPSystemRegister)0x7)
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/*
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* Register definitions shared across interpreter and compiler
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*/
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#define Rexception_obj R4
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#define Rexception_pc R5
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/*
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* Interpreter register definitions common to C++ and template interpreters.
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*/
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#define Rlocals R8
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#define Rmethod R9
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#define Rthread R10
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#define Rtemp R12
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// Interpreter calling conventions
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#define Rparams SP
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#define Rsender_sp R4
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// JSR292
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// Note: R5_mh is needed only during the call setup, including adapters
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// This does not seem to conflict with Rexception_pc
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// In case of issues, R3 might be OK but adapters calling the runtime would have to save it
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#define R5_mh R5 // MethodHandle register, used during the call setup
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#define Rmh_SP_save FP // for C1
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/*
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* C++ Interpreter Register Defines
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*/
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#define Rsave0 R4
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#define Rsave1 R5
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#define Rsave2 R6
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#define Rstate altFP_7_11 // R7 or R11
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#define Ricklass R8
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/*
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* TemplateTable Interpreter Register Usage
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*/
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// Temporary registers
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#define R0_tmp R0
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#define R1_tmp R1
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#define R2_tmp R2
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#define R3_tmp R3
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#define R4_tmp R4
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#define R5_tmp R5
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#define R12_tmp R12
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#define LR_tmp LR
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#define S0_tmp S0
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#define S1_tmp S1_reg
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#define D0_tmp D0
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#define D1_tmp D1
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// Temporary registers saved across VM calls (according to C calling conventions)
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#define Rtmp_save0 R4
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#define Rtmp_save1 R5
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// Cached TOS value
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#define R0_tos R0
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#define R0_tos_lo R0
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#define R1_tos_hi R1
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#define S0_tos S0
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#define D0_tos D0
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// Dispatch table
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52351
|
387 |
#define RdispatchTable R6
|
42664
|
388 |
|
|
389 |
// Bytecode pointer
|
52351
|
390 |
#define Rbcp altFP_7_11
|
42664
|
391 |
|
|
392 |
// Pre-loaded next bytecode for the dispatch
|
|
393 |
#define R3_bytecode R3
|
|
394 |
|
|
395 |
// Conventions between bytecode templates and stubs
|
|
396 |
#define R2_ClassCastException_obj R2
|
|
397 |
#define R4_ArrayIndexOutOfBounds_index R4
|
|
398 |
|
|
399 |
// Interpreter expression stack top
|
52351
|
400 |
#define Rstack_top SP
|
42664
|
401 |
|
|
402 |
/*
|
|
403 |
* Linux 32-bit ARM C ABI Register calling conventions
|
|
404 |
*
|
|
405 |
* REG use callee/caller saved
|
|
406 |
*
|
|
407 |
* R0 First argument reg caller
|
|
408 |
* result register
|
|
409 |
* R1 Second argument reg caller
|
|
410 |
* result register
|
|
411 |
* R2 Third argument reg caller
|
|
412 |
* R3 Fourth argument reg caller
|
|
413 |
*
|
|
414 |
* R4 - R8 Local variable registers callee
|
|
415 |
* R9
|
|
416 |
* R10, R11 Local variable registers callee
|
|
417 |
*
|
|
418 |
* R12 (IP) Scratch register used in inter-procedural calling
|
|
419 |
* R13 (SP) Stack Pointer callee
|
|
420 |
* R14 (LR) Link register
|
|
421 |
* R15 (PC) Program Counter
|
|
422 |
*/
|
|
423 |
#define c_rarg0 R0
|
|
424 |
#define c_rarg1 R1
|
|
425 |
#define c_rarg2 R2
|
|
426 |
#define c_rarg3 R3
|
|
427 |
|
|
428 |
|
|
429 |
#define GPR_PARAMS 4
|
|
430 |
|
|
431 |
|
|
432 |
// Java ABI
|
|
433 |
// XXX Is this correct?
|
|
434 |
#define j_rarg0 c_rarg0
|
|
435 |
#define j_rarg1 c_rarg1
|
|
436 |
#define j_rarg2 c_rarg2
|
|
437 |
#define j_rarg3 c_rarg3
|
|
438 |
|
|
439 |
|
|
440 |
#endif // CPU_ARM_VM_REGISTER_ARM_HPP
|