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/*
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* Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2014, Red Hat Inc. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#ifndef CPU_AARCH64_VM_REGISTER_AARCH64_HPP
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#define CPU_AARCH64_VM_REGISTER_AARCH64_HPP
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#include "asm/register.hpp"
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class VMRegImpl;
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typedef VMRegImpl* VMReg;
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// Use Register as shortcut
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class RegisterImpl;
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typedef RegisterImpl* Register;
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inline Register as_Register(int encoding) {
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return (Register)(intptr_t) encoding;
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}
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class RegisterImpl: public AbstractRegisterImpl {
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public:
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enum {
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number_of_registers = 32,
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number_of_byte_registers = 32
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};
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// derived registers, offsets, and addresses
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Register successor() const { return as_Register(encoding() + 1); }
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// construction
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inline friend Register as_Register(int encoding);
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VMReg as_VMReg();
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// accessors
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int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; }
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bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
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bool has_byte_register() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_byte_registers; }
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const char* name() const;
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int encoding_nocheck() const { return (intptr_t)this; }
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unsigned long bit(bool yes = true) const { return yes << encoding(); }
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};
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// The integer registers of the aarch64 architecture
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CONSTANT_REGISTER_DECLARATION(Register, noreg, (-1));
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CONSTANT_REGISTER_DECLARATION(Register, r0, (0));
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CONSTANT_REGISTER_DECLARATION(Register, r1, (1));
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CONSTANT_REGISTER_DECLARATION(Register, r2, (2));
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CONSTANT_REGISTER_DECLARATION(Register, r3, (3));
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CONSTANT_REGISTER_DECLARATION(Register, r4, (4));
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CONSTANT_REGISTER_DECLARATION(Register, r5, (5));
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CONSTANT_REGISTER_DECLARATION(Register, r6, (6));
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CONSTANT_REGISTER_DECLARATION(Register, r7, (7));
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CONSTANT_REGISTER_DECLARATION(Register, r8, (8));
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CONSTANT_REGISTER_DECLARATION(Register, r9, (9));
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CONSTANT_REGISTER_DECLARATION(Register, r10, (10));
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CONSTANT_REGISTER_DECLARATION(Register, r11, (11));
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CONSTANT_REGISTER_DECLARATION(Register, r12, (12));
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CONSTANT_REGISTER_DECLARATION(Register, r13, (13));
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CONSTANT_REGISTER_DECLARATION(Register, r14, (14));
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CONSTANT_REGISTER_DECLARATION(Register, r15, (15));
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CONSTANT_REGISTER_DECLARATION(Register, r16, (16));
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CONSTANT_REGISTER_DECLARATION(Register, r17, (17));
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CONSTANT_REGISTER_DECLARATION(Register, r18, (18));
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CONSTANT_REGISTER_DECLARATION(Register, r19, (19));
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CONSTANT_REGISTER_DECLARATION(Register, r20, (20));
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CONSTANT_REGISTER_DECLARATION(Register, r21, (21));
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CONSTANT_REGISTER_DECLARATION(Register, r22, (22));
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CONSTANT_REGISTER_DECLARATION(Register, r23, (23));
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CONSTANT_REGISTER_DECLARATION(Register, r24, (24));
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CONSTANT_REGISTER_DECLARATION(Register, r25, (25));
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CONSTANT_REGISTER_DECLARATION(Register, r26, (26));
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CONSTANT_REGISTER_DECLARATION(Register, r27, (27));
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CONSTANT_REGISTER_DECLARATION(Register, r28, (28));
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CONSTANT_REGISTER_DECLARATION(Register, r29, (29));
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CONSTANT_REGISTER_DECLARATION(Register, r30, (30));
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CONSTANT_REGISTER_DECLARATION(Register, r31_sp, (31));
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CONSTANT_REGISTER_DECLARATION(Register, zr, (32));
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CONSTANT_REGISTER_DECLARATION(Register, sp, (33));
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// Use FloatRegister as shortcut
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class FloatRegisterImpl;
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typedef FloatRegisterImpl* FloatRegister;
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inline FloatRegister as_FloatRegister(int encoding) {
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return (FloatRegister)(intptr_t) encoding;
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}
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// The implementation of floating point registers for the architecture
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class FloatRegisterImpl: public AbstractRegisterImpl {
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public:
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enum {
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number_of_registers = 32
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};
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// construction
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inline friend FloatRegister as_FloatRegister(int encoding);
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VMReg as_VMReg();
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// derived registers, offsets, and addresses
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FloatRegister successor() const { return as_FloatRegister(encoding() + 1); }
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// accessors
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int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; }
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int encoding_nocheck() const { return (intptr_t)this; }
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bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
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const char* name() const;
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};
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// The float registers of the AARCH64 architecture
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CONSTANT_REGISTER_DECLARATION(FloatRegister, fnoreg , (-1));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v0 , ( 0));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v1 , ( 1));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v2 , ( 2));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v3 , ( 3));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v4 , ( 4));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v5 , ( 5));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v6 , ( 6));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v7 , ( 7));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v8 , ( 8));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v9 , ( 9));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v10 , (10));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v11 , (11));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v12 , (12));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v13 , (13));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v14 , (14));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v15 , (15));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v16 , (16));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v17 , (17));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v18 , (18));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v19 , (19));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v20 , (20));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v21 , (21));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v22 , (22));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v23 , (23));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v24 , (24));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v25 , (25));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v26 , (26));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v27 , (27));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v28 , (28));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v29 , (29));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v30 , (30));
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CONSTANT_REGISTER_DECLARATION(FloatRegister, v31 , (31));
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// Need to know the total number of registers of all sorts for SharedInfo.
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// Define a class that exports it.
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class ConcreteRegisterImpl : public AbstractRegisterImpl {
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public:
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enum {
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// A big enough number for C2: all the registers plus flags
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// This number must be large enough to cover REG_COUNT (defined by c2) registers.
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// There is no requirement that any ordering here matches any ordering c2 gives
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// it's optoregs.
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number_of_registers = (2 * RegisterImpl::number_of_registers +
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2 * FloatRegisterImpl::number_of_registers +
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1) // flags
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};
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// added to make it compile
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static const int max_gpr;
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static const int max_fpr;
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};
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// A set of registers
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class RegSet {
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uint32_t _bitset;
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RegSet(uint32_t bitset) : _bitset(bitset) { }
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public:
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RegSet() : _bitset(0) { }
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RegSet(Register r1) : _bitset(r1->bit()) { }
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RegSet operator+(const RegSet aSet) const {
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RegSet result(_bitset | aSet._bitset);
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return result;
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}
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RegSet operator-(const RegSet aSet) const {
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RegSet result(_bitset & ~aSet._bitset);
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return result;
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}
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RegSet &operator+=(const RegSet aSet) {
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*this = *this + aSet;
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return *this;
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}
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static RegSet of(Register r1) {
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return RegSet(r1);
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}
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static RegSet of(Register r1, Register r2) {
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return of(r1) + r2;
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}
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static RegSet of(Register r1, Register r2, Register r3) {
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return of(r1, r2) + r3;
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}
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static RegSet of(Register r1, Register r2, Register r3, Register r4) {
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return of(r1, r2, r3) + r4;
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}
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static RegSet range(Register start, Register end) {
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uint32_t bits = ~0;
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bits <<= start->encoding();
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bits <<= 31 - end->encoding();
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bits >>= 31 - end->encoding();
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return RegSet(bits);
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}
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uint32_t bits() const { return _bitset; }
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};
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#endif // CPU_AARCH64_VM_REGISTER_AARCH64_HPP
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