author | eosterlund |
Tue, 26 Sep 2017 21:37:01 +0200 | |
changeset 47578 | 09c41c4913d9 |
parent 47552 | 8a3599d60996 |
child 47593 | 2d56326b98f0 |
permissions | -rw-r--r-- |
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/* |
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* Copyright (c) 2008, 2017, Oracle and/or its affiliates. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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#ifndef OS_CPU_LINUX_ARM_VM_ATOMIC_LINUX_ARM_HPP |
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#define OS_CPU_LINUX_ARM_VM_ATOMIC_LINUX_ARM_HPP |
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#include "runtime/os.hpp" |
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#include "vm_version_arm.hpp" |
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// Implementation of class atomic |
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/* |
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* Atomic long operations on 32-bit ARM |
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* ARM v7 supports LDREXD/STREXD synchronization instructions so no problem. |
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* ARM < v7 does not have explicit 64 atomic load/store capability. |
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* However, gcc emits LDRD/STRD instructions on v5te and LDM/STM on v5t |
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* when loading/storing 64 bits. |
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* For non-MP machines (which is all we support for ARM < v7) |
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* under current Linux distros these instructions appear atomic. |
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* See section A3.5.3 of ARM Architecture Reference Manual for ARM v7. |
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* Also, for cmpxchg64, if ARM < v7 we check for cmpxchg64 support in the |
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* Linux kernel using _kuser_helper_version. See entry-armv.S in the Linux |
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* kernel source or kernel_user_helpers.txt in Linux Doc. |
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*/ |
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inline void Atomic::store (jbyte store_value, jbyte* dest) { *dest = store_value; } |
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inline void Atomic::store (jshort store_value, jshort* dest) { *dest = store_value; } |
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inline void Atomic::store (jint store_value, jint* dest) { *dest = store_value; } |
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inline void Atomic::store_ptr(intptr_t store_value, intptr_t* dest) { *dest = store_value; } |
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inline void Atomic::store_ptr(void* store_value, void* dest) { *(void**)dest = store_value; } |
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inline void Atomic::store (jbyte store_value, volatile jbyte* dest) { *dest = store_value; } |
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inline void Atomic::store (jshort store_value, volatile jshort* dest) { *dest = store_value; } |
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inline void Atomic::store (jint store_value, volatile jint* dest) { *dest = store_value; } |
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inline void Atomic::store_ptr(intptr_t store_value, volatile intptr_t* dest) { *dest = store_value; } |
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inline void Atomic::store_ptr(void* store_value, volatile void* dest) { *(void* volatile *)dest = store_value; } |
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inline jlong Atomic::load (const volatile jlong* src) { |
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assert(((intx)src & (sizeof(jlong)-1)) == 0, "Atomic load jlong mis-aligned"); |
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#ifdef AARCH64 |
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return *src; |
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#else |
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return (*os::atomic_load_long_func)(src); |
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#endif |
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} |
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inline void Atomic::store (jlong value, volatile jlong* dest) { |
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assert(((intx)dest & (sizeof(jlong)-1)) == 0, "Atomic store jlong mis-aligned"); |
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#ifdef AARCH64 |
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*dest = value; |
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#else |
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(*os::atomic_store_long_func)(value, dest); |
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#endif |
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} |
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inline void Atomic::store (jlong value, jlong* dest) { |
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store(value, (volatile jlong*)dest); |
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} |
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// As per atomic.hpp all read-modify-write operations have to provide two-way |
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// barriers semantics. For AARCH64 we are using load-acquire-with-reservation and |
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// store-release-with-reservation. While load-acquire combined with store-release |
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// do not generally form two-way barriers, their use with reservations does - the |
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// ARMv8 architecture manual Section F "Barrier Litmus Tests" indicates they |
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// provide sequentially consistent semantics. All we need to add is an explicit |
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// barrier in the failure path of the cmpxchg operations (as these don't execute |
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// the store) - arguably this may be overly cautious as there is a very low |
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// likelihood that the hardware would pull loads/stores into the region guarded |
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// by the reservation. |
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// |
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// For ARMv7 we add explicit barriers in the stubs. |
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template<size_t byte_size> |
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struct Atomic::PlatformAdd |
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: Atomic::AddAndFetch<Atomic::PlatformAdd<byte_size> > |
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{ |
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template<typename I, typename D> |
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D add_and_fetch(I add_value, D volatile* dest) const; |
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}; |
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template<> |
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template<typename I, typename D> |
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inline D Atomic::PlatformAdd<4>::add_and_fetch(I add_value, D volatile* dest) const { |
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STATIC_ASSERT(4 == sizeof(I)); |
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STATIC_ASSERT(4 == sizeof(D)); |
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#ifdef AARCH64 |
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D val; |
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int tmp; |
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__asm__ volatile( |
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"1:\n\t" |
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" ldaxr %w[val], [%[dest]]\n\t" |
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" add %w[val], %w[val], %w[add_val]\n\t" |
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" stlxr %w[tmp], %w[val], [%[dest]]\n\t" |
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" cbnz %w[tmp], 1b\n\t" |
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: [val] "=&r" (val), [tmp] "=&r" (tmp) |
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: [add_val] "r" (add_value), [dest] "r" (dest) |
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: "memory"); |
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return val; |
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#else |
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return add_using_helper<jint>(os::atomic_add_func, add_value, dest); |
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#endif |
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} |
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#ifdef AARCH64 |
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template<> |
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template<typename I, typename D> |
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inline D Atomic::PlatformAdd<8>::add_and_fetch(I add_value, D volatile* dest) const { |
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STATIC_ASSERT(8 == sizeof(I)); |
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STATIC_ASSERT(8 == sizeof(D)); |
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D val; |
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int tmp; |
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__asm__ volatile( |
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"1:\n\t" |
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" ldaxr %[val], [%[dest]]\n\t" |
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" add %[val], %[val], %[add_val]\n\t" |
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" stlxr %w[tmp], %[val], [%[dest]]\n\t" |
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" cbnz %w[tmp], 1b\n\t" |
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: [val] "=&r" (val), [tmp] "=&r" (tmp) |
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: [add_val] "r" (add_value), [dest] "r" (dest) |
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: "memory"); |
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return val; |
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} |
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#endif |
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template<> |
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template<typename T> |
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inline T Atomic::PlatformXchg<4>::operator()(T exchange_value, |
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T volatile* dest) const { |
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STATIC_ASSERT(4 == sizeof(T)); |
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#ifdef AARCH64 |
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T old_val; |
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int tmp; |
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__asm__ volatile( |
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"1:\n\t" |
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" ldaxr %w[old_val], [%[dest]]\n\t" |
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" stlxr %w[tmp], %w[new_val], [%[dest]]\n\t" |
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" cbnz %w[tmp], 1b\n\t" |
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: [old_val] "=&r" (old_val), [tmp] "=&r" (tmp) |
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: [new_val] "r" (exchange_value), [dest] "r" (dest) |
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: "memory"); |
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return old_val; |
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#else |
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return xchg_using_helper<jint>(os::atomic_xchg_func, exchange_value, dest); |
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#endif |
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} |
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#ifdef AARCH64 |
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template<> |
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template<typename T> |
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inline T Atomic::PlatformXchg<8>::operator()(T exchange_value, |
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T volatile* dest) const { |
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STATIC_ASSERT(8 == sizeof(T)); |
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T old_val; |
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int tmp; |
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__asm__ volatile( |
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"1:\n\t" |
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" ldaxr %[old_val], [%[dest]]\n\t" |
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" stlxr %w[tmp], %[new_val], [%[dest]]\n\t" |
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" cbnz %w[tmp], 1b\n\t" |
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: [old_val] "=&r" (old_val), [tmp] "=&r" (tmp) |
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: [new_val] "r" (exchange_value), [dest] "r" (dest) |
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: "memory"); |
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return old_val; |
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} |
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#endif // AARCH64 |
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// The memory_order parameter is ignored - we always provide the strongest/most-conservative ordering |
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// No direct support for cmpxchg of bytes; emulate using int. |
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template<> |
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struct Atomic::PlatformCmpxchg<1> : Atomic::CmpxchgByteUsingInt {}; |
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|
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#ifndef AARCH64 |
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inline jint reorder_cmpxchg_func(jint exchange_value, |
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jint volatile* dest, |
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jint compare_value) { |
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// Warning: Arguments are swapped to avoid moving them for kernel call |
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return (*os::atomic_cmpxchg_func)(compare_value, exchange_value, dest); |
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} |
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|
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inline jlong reorder_cmpxchg_long_func(jlong exchange_value, |
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jlong volatile* dest, |
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jlong compare_value) { |
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assert(VM_Version::supports_cx8(), "Atomic compare and exchange jlong not supported on this architecture!"); |
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// Warning: Arguments are swapped to avoid moving them for kernel call |
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return (*os::atomic_cmpxchg_long_func)(compare_value, exchange_value, dest); |
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} |
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#endif // !AARCH64 |
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template<> |
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template<typename T> |
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inline T Atomic::PlatformCmpxchg<4>::operator()(T exchange_value, |
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T volatile* dest, |
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T compare_value, |
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cmpxchg_memory_order order) const { |
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STATIC_ASSERT(4 == sizeof(T)); |
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#ifdef AARCH64 |
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T rv; |
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int tmp; |
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__asm__ volatile( |
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"1:\n\t" |
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" ldaxr %w[rv], [%[dest]]\n\t" |
|
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" cmp %w[rv], %w[cv]\n\t" |
|
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" b.ne 2f\n\t" |
|
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" stlxr %w[tmp], %w[ev], [%[dest]]\n\t" |
|
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" cbnz %w[tmp], 1b\n\t" |
|
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" b 3f\n\t" |
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"2:\n\t" |
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" dmb sy\n\t" |
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"3:\n\t" |
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: [rv] "=&r" (rv), [tmp] "=&r" (tmp) |
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: [ev] "r" (exchange_value), [dest] "r" (dest), [cv] "r" (compare_value) |
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: "memory"); |
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return rv; |
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#else |
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return cmpxchg_using_helper<jint>(reorder_cmpxchg_func, exchange_value, dest, compare_value); |
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#endif |
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} |
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template<> |
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template<typename T> |
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inline T Atomic::PlatformCmpxchg<8>::operator()(T exchange_value, |
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T volatile* dest, |
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T compare_value, |
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cmpxchg_memory_order order) const { |
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STATIC_ASSERT(8 == sizeof(T)); |
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#ifdef AARCH64 |
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T rv; |
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int tmp; |
253 |
__asm__ volatile( |
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"1:\n\t" |
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" ldaxr %[rv], [%[dest]]\n\t" |
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" cmp %[rv], %[cv]\n\t" |
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" b.ne 2f\n\t" |
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" stlxr %w[tmp], %[ev], [%[dest]]\n\t" |
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" cbnz %w[tmp], 1b\n\t" |
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" b 3f\n\t" |
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"2:\n\t" |
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" dmb sy\n\t" |
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"3:\n\t" |
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: [rv] "=&r" (rv), [tmp] "=&r" (tmp) |
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: [ev] "r" (exchange_value), [dest] "r" (dest), [cv] "r" (compare_value) |
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: "memory"); |
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return rv; |
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#else |
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return cmpxchg_using_helper<jlong>(reorder_cmpxchg_long_func, exchange_value, dest, compare_value); |
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#endif |
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} |
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#endif // OS_CPU_LINUX_ARM_VM_ATOMIC_LINUX_ARM_HPP |