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/*
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* Copyright (c) 2013, 2018, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*/
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package org.graalvm.compiler.lir.amd64.vector;
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import static jdk.vm.ci.code.ValueUtil.asRegister;
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import static jdk.vm.ci.code.ValueUtil.isRegister;
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import static jdk.vm.ci.code.ValueUtil.isStackSlot;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMRIOp.VEXTRACTF128;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMRIOp.VEXTRACTI128;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMRIOp.VPEXTRB;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMRIOp.VPEXTRD;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMRIOp.VPEXTRQ;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMRIOp.VPEXTRW;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMoveOp.VMOVD;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMoveOp.VMOVQ;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRVMIOp.VINSERTF128;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRVMIOp.VINSERTI128;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRVMIOp.VSHUFPD;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRVMIOp.VSHUFPS;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRVMOp.VPSHUFB;
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import static org.graalvm.compiler.asm.amd64.AVXKind.AVXSize.XMM;
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import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.REG;
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import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.STACK;
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import org.graalvm.compiler.asm.amd64.AMD64Address;
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import org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMRIOp;
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import org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRMIOp;
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import org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRVMIOp;
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import org.graalvm.compiler.asm.amd64.AMD64MacroAssembler;
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import org.graalvm.compiler.asm.amd64.AVXKind;
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import org.graalvm.compiler.debug.GraalError;
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import org.graalvm.compiler.lir.LIRInstructionClass;
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import org.graalvm.compiler.lir.amd64.AMD64LIRInstruction;
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import org.graalvm.compiler.lir.asm.CompilationResultBuilder;
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import jdk.vm.ci.amd64.AMD64;
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import jdk.vm.ci.amd64.AMD64.CPUFeature;
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import jdk.vm.ci.amd64.AMD64Kind;
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import jdk.vm.ci.meta.AllocatableValue;
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public class AMD64VectorShuffle {
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public static final class IntToVectorOp extends AMD64LIRInstruction {
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public static final LIRInstructionClass<IntToVectorOp> TYPE = LIRInstructionClass.create(IntToVectorOp.class);
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@Def({REG}) protected AllocatableValue result;
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@Use({REG, STACK}) protected AllocatableValue value;
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public IntToVectorOp(AllocatableValue result, AllocatableValue value) {
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super(TYPE);
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assert ((AMD64Kind) result.getPlatformKind()).getScalar().isInteger() : result.getPlatformKind();
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this.result = result;
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this.value = value;
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}
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@Override
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public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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if (isRegister(value)) {
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VMOVD.emit(masm, XMM, asRegister(result), asRegister(value));
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} else {
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assert isStackSlot(value);
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VMOVD.emit(masm, XMM, asRegister(result), (AMD64Address) crb.asAddress(value));
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}
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}
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}
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public static final class LongToVectorOp extends AMD64LIRInstruction {
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public static final LIRInstructionClass<LongToVectorOp> TYPE = LIRInstructionClass.create(LongToVectorOp.class);
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@Def({REG}) protected AllocatableValue result;
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@Use({REG, STACK}) protected AllocatableValue value;
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public LongToVectorOp(AllocatableValue result, AllocatableValue value) {
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super(TYPE);
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assert result.getPlatformKind() == AMD64Kind.V128_QWORD || result.getPlatformKind() == AMD64Kind.V256_QWORD;
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this.result = result;
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this.value = value;
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}
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@Override
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public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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if (isRegister(value)) {
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VMOVQ.emit(masm, XMM, asRegister(result), asRegister(value));
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} else {
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assert isStackSlot(value);
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VMOVQ.emit(masm, XMM, asRegister(result), (AMD64Address) crb.asAddress(value));
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}
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}
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}
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public static final class ShuffleBytesOp extends AMD64LIRInstruction {
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public static final LIRInstructionClass<ShuffleBytesOp> TYPE = LIRInstructionClass.create(ShuffleBytesOp.class);
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@Def({REG}) protected AllocatableValue result;
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@Use({REG}) protected AllocatableValue source;
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@Use({REG, STACK}) protected AllocatableValue selector;
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public ShuffleBytesOp(AllocatableValue result, AllocatableValue source, AllocatableValue selector) {
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super(TYPE);
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this.result = result;
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this.source = source;
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this.selector = selector;
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}
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@Override
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public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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AMD64Kind kind = (AMD64Kind) result.getPlatformKind();
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if (isRegister(selector)) {
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VPSHUFB.emit(masm, AVXKind.getRegisterSize(kind), asRegister(result), asRegister(source), asRegister(selector));
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} else {
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assert isStackSlot(selector);
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VPSHUFB.emit(masm, AVXKind.getRegisterSize(kind), asRegister(result), asRegister(source), (AMD64Address) crb.asAddress(selector));
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}
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}
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}
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public static final class ConstShuffleBytesOp extends AMD64LIRInstruction {
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public static final LIRInstructionClass<ConstShuffleBytesOp> TYPE = LIRInstructionClass.create(ConstShuffleBytesOp.class);
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@Def({REG}) protected AllocatableValue result;
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@Use({REG}) protected AllocatableValue source;
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private final byte[] selector;
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public ConstShuffleBytesOp(AllocatableValue result, AllocatableValue source, byte... selector) {
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super(TYPE);
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assert AVXKind.getRegisterSize(((AMD64Kind) result.getPlatformKind())).getBytes() == selector.length;
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this.result = result;
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this.source = source;
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this.selector = selector;
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}
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@Override
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public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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AMD64Kind kind = (AMD64Kind) result.getPlatformKind();
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AMD64Address address = (AMD64Address) crb.recordDataReferenceInCode(selector, selector.length);
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VPSHUFB.emit(masm, AVXKind.getRegisterSize(kind), asRegister(result), asRegister(source), address);
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}
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}
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public static class ShuffleWordOp extends AMD64LIRInstruction {
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public static final LIRInstructionClass<ShuffleWordOp> TYPE = LIRInstructionClass.create(ShuffleWordOp.class);
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private final VexRMIOp op;
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@Def({REG}) protected AllocatableValue result;
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@Use({REG, STACK}) protected AllocatableValue source;
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private final int selector;
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public ShuffleWordOp(VexRMIOp op, AllocatableValue result, AllocatableValue source, int selector) {
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super(TYPE);
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this.op = op;
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this.result = result;
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this.source = source;
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this.selector = selector;
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}
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@Override
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public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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AMD64Kind kind = (AMD64Kind) source.getPlatformKind();
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if (isRegister(source)) {
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op.emit(masm, AVXKind.getRegisterSize(kind), asRegister(result), asRegister(source), selector);
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} else {
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op.emit(masm, AVXKind.getRegisterSize(kind), asRegister(result), (AMD64Address) crb.asAddress(source), selector);
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}
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}
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}
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public static class ShuffleFloatOp extends AMD64LIRInstruction {
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public static final LIRInstructionClass<ShuffleFloatOp> TYPE = LIRInstructionClass.create(ShuffleFloatOp.class);
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@Def({REG}) protected AllocatableValue result;
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@Use({REG}) protected AllocatableValue source1;
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@Use({REG, STACK}) protected AllocatableValue source2;
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private final int selector;
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public ShuffleFloatOp(AllocatableValue result, AllocatableValue source1, AllocatableValue source2, int selector) {
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super(TYPE);
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this.result = result;
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this.source1 = source1;
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this.source2 = source2;
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this.selector = selector;
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}
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@Override
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public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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AMD64Kind kind = (AMD64Kind) result.getPlatformKind();
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VexRVMIOp op;
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switch (kind.getScalar()) {
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case SINGLE:
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op = VSHUFPS;
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break;
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case DOUBLE:
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op = VSHUFPD;
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break;
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default:
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throw GraalError.shouldNotReachHere();
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}
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if (isRegister(source2)) {
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op.emit(masm, AVXKind.getRegisterSize(kind), asRegister(result), asRegister(source1), asRegister(source2), selector);
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} else {
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assert isStackSlot(source2);
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op.emit(masm, AVXKind.getRegisterSize(kind), asRegister(result), asRegister(source1), (AMD64Address) crb.asAddress(source2), selector);
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}
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}
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}
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public static final class Extract128Op extends AMD64LIRInstruction {
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public static final LIRInstructionClass<Extract128Op> TYPE = LIRInstructionClass.create(Extract128Op.class);
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@Def({REG, STACK}) protected AllocatableValue result;
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@Use({REG}) protected AllocatableValue source;
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private final int selector;
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public Extract128Op(AllocatableValue result, AllocatableValue source, int selector) {
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super(TYPE);
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this.result = result;
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this.source = source;
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this.selector = selector;
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}
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@Override
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public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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AMD64Kind kind = (AMD64Kind) source.getPlatformKind();
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VexMRIOp op;
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switch (kind.getScalar()) {
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case SINGLE:
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case DOUBLE:
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op = VEXTRACTF128;
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break;
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default:
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AMD64 arch = (AMD64) crb.target.arch;
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// if supported we want VEXTRACTI128
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// on AVX1, we have to use VEXTRACTF128
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op = arch.getFeatures().contains(CPUFeature.AVX2) ? VEXTRACTI128 : VEXTRACTF128;
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break;
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}
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if (isRegister(result)) {
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op.emit(masm, AVXKind.getRegisterSize(kind), asRegister(result), asRegister(source), selector);
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} else {
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assert isStackSlot(result);
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op.emit(masm, AVXKind.getRegisterSize(kind), (AMD64Address) crb.asAddress(result), asRegister(source), selector);
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}
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}
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}
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public static final class Insert128Op extends AMD64LIRInstruction {
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public static final LIRInstructionClass<Insert128Op> TYPE = LIRInstructionClass.create(Insert128Op.class);
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@Def({REG}) protected AllocatableValue result;
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@Use({REG}) protected AllocatableValue source1;
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@Use({REG, STACK}) protected AllocatableValue source2;
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private final int selector;
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public Insert128Op(AllocatableValue result, AllocatableValue source1, AllocatableValue source2, int selector) {
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super(TYPE);
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this.result = result;
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this.source1 = source1;
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this.source2 = source2;
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this.selector = selector;
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}
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@Override
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public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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AMD64Kind kind = (AMD64Kind) result.getPlatformKind();
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VexRVMIOp op;
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switch (kind.getScalar()) {
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case SINGLE:
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case DOUBLE:
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op = VINSERTF128;
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break;
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default:
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AMD64 arch = (AMD64) crb.target.arch;
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// if supported we want VINSERTI128 - on AVX1, we have to use VINSERTF128.
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// using instructions with an incorrect data type is possible but typically
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// results in an additional overhead whenever the value is being accessed.
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op = arch.getFeatures().contains(CPUFeature.AVX2) ? VINSERTI128 : VINSERTF128;
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break;
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}
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if (isRegister(source2)) {
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op.emit(masm, AVXKind.getRegisterSize(kind), asRegister(result), asRegister(source1), asRegister(source2), selector);
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} else {
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assert isStackSlot(source2);
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op.emit(masm, AVXKind.getRegisterSize(kind), asRegister(result), asRegister(source1), (AMD64Address) crb.asAddress(source2), selector);
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}
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}
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}
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public static final class ExtractByteOp extends AMD64LIRInstruction {
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public static final LIRInstructionClass<ExtractByteOp> TYPE = LIRInstructionClass.create(ExtractByteOp.class);
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@Def({REG}) protected AllocatableValue result;
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@Use({REG}) protected AllocatableValue vector;
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private final int selector;
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public ExtractByteOp(AllocatableValue result, AllocatableValue vector, int selector) {
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super(TYPE);
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assert result.getPlatformKind() == AMD64Kind.DWORD;
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assert ((AMD64Kind) vector.getPlatformKind()).getScalar() == AMD64Kind.BYTE;
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this.result = result;
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this.vector = vector;
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this.selector = selector;
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}
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@Override
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public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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VPEXTRB.emit(masm, XMM, asRegister(result), asRegister(vector), selector);
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}
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}
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public static final class ExtractShortOp extends AMD64LIRInstruction {
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public static final LIRInstructionClass<ExtractShortOp> TYPE = LIRInstructionClass.create(ExtractShortOp.class);
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@Def({REG}) protected AllocatableValue result;
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@Use({REG}) protected AllocatableValue vector;
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private final int selector;
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public ExtractShortOp(AllocatableValue result, AllocatableValue vector, int selector) {
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super(TYPE);
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assert result.getPlatformKind() == AMD64Kind.DWORD;
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assert ((AMD64Kind) vector.getPlatformKind()).getScalar() == AMD64Kind.WORD;
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this.result = result;
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this.vector = vector;
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this.selector = selector;
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}
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344 |
@Override
|
51436
|
345 |
public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
|
|
346 |
VPEXTRW.emit(masm, XMM, asRegister(result), asRegister(vector), selector);
|
50609
|
347 |
}
|
|
348 |
}
|
|
349 |
|
51436
|
350 |
public static final class ExtractIntOp extends AMD64LIRInstruction {
|
50609
|
351 |
public static final LIRInstructionClass<ExtractIntOp> TYPE = LIRInstructionClass.create(ExtractIntOp.class);
|
|
352 |
@Def({REG, STACK}) protected AllocatableValue result;
|
|
353 |
@Use({REG}) protected AllocatableValue vector;
|
|
354 |
private final int selector;
|
|
355 |
|
|
356 |
public ExtractIntOp(AllocatableValue result, AllocatableValue vector, int selector) {
|
|
357 |
super(TYPE);
|
|
358 |
assert result.getPlatformKind() == AMD64Kind.DWORD;
|
|
359 |
assert ((AMD64Kind) vector.getPlatformKind()).getScalar() == AMD64Kind.DWORD;
|
|
360 |
this.result = result;
|
|
361 |
this.vector = vector;
|
|
362 |
this.selector = selector;
|
|
363 |
}
|
|
364 |
|
|
365 |
@Override
|
51436
|
366 |
public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
|
50609
|
367 |
if (isRegister(result)) {
|
|
368 |
if (selector == 0) {
|
51436
|
369 |
VMOVD.emitReverse(masm, XMM, asRegister(result), asRegister(vector));
|
50609
|
370 |
} else {
|
51436
|
371 |
VPEXTRD.emit(masm, XMM, asRegister(result), asRegister(vector), selector);
|
50609
|
372 |
}
|
|
373 |
} else {
|
|
374 |
assert isStackSlot(result);
|
|
375 |
if (selector == 0) {
|
51436
|
376 |
VMOVD.emit(masm, XMM, (AMD64Address) crb.asAddress(result), asRegister(vector));
|
50609
|
377 |
} else {
|
51436
|
378 |
VPEXTRD.emit(masm, XMM, (AMD64Address) crb.asAddress(result), asRegister(vector), selector);
|
50609
|
379 |
}
|
|
380 |
}
|
|
381 |
}
|
|
382 |
}
|
|
383 |
|
51436
|
384 |
public static final class ExtractLongOp extends AMD64LIRInstruction {
|
50609
|
385 |
public static final LIRInstructionClass<ExtractLongOp> TYPE = LIRInstructionClass.create(ExtractLongOp.class);
|
|
386 |
@Def({REG, STACK}) protected AllocatableValue result;
|
|
387 |
@Use({REG}) protected AllocatableValue vector;
|
|
388 |
private final int selector;
|
|
389 |
|
|
390 |
public ExtractLongOp(AllocatableValue result, AllocatableValue vector, int selector) {
|
|
391 |
super(TYPE);
|
|
392 |
assert result.getPlatformKind() == AMD64Kind.QWORD;
|
|
393 |
assert ((AMD64Kind) vector.getPlatformKind()).getScalar() == AMD64Kind.QWORD;
|
|
394 |
this.result = result;
|
|
395 |
this.vector = vector;
|
|
396 |
this.selector = selector;
|
|
397 |
}
|
|
398 |
|
|
399 |
@Override
|
51436
|
400 |
public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
|
50609
|
401 |
if (isRegister(result)) {
|
|
402 |
if (selector == 0) {
|
51436
|
403 |
VMOVQ.emitReverse(masm, XMM, asRegister(result), asRegister(vector));
|
50609
|
404 |
} else {
|
51436
|
405 |
VPEXTRQ.emit(masm, XMM, asRegister(result), asRegister(vector), selector);
|
50609
|
406 |
}
|
|
407 |
} else {
|
|
408 |
assert isStackSlot(result);
|
|
409 |
if (selector == 0) {
|
51436
|
410 |
VMOVQ.emit(masm, XMM, (AMD64Address) crb.asAddress(result), asRegister(vector));
|
50609
|
411 |
} else {
|
51436
|
412 |
VPEXTRQ.emit(masm, XMM, (AMD64Address) crb.asAddress(result), asRegister(vector), selector);
|
50609
|
413 |
}
|
|
414 |
}
|
|
415 |
}
|
|
416 |
}
|
|
417 |
}
|