src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.lir.amd64/src/org/graalvm/compiler/lir/amd64/vector/AMD64VectorShuffle.java
author iveresov
Fri, 17 Aug 2018 13:20:53 -0700
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permissions -rw-r--r--
8206992: Update Graal Reviewed-by: kvn
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/*
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 * Copyright (c) 2013, 2018, Oracle and/or its affiliates. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 */
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package org.graalvm.compiler.lir.amd64.vector;
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import static jdk.vm.ci.code.ValueUtil.asRegister;
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import static jdk.vm.ci.code.ValueUtil.isRegister;
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import static jdk.vm.ci.code.ValueUtil.isStackSlot;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMRIOp.VEXTRACTF128;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMRIOp.VEXTRACTI128;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMRIOp.VPEXTRB;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMRIOp.VPEXTRD;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMRIOp.VPEXTRQ;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMRIOp.VPEXTRW;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMoveOp.VMOVD;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMoveOp.VMOVQ;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRVMIOp.VINSERTF128;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRVMIOp.VINSERTI128;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRVMIOp.VSHUFPD;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRVMIOp.VSHUFPS;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRVMOp.VPSHUFB;
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import static org.graalvm.compiler.asm.amd64.AVXKind.AVXSize.XMM;
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import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.REG;
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import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.STACK;
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import org.graalvm.compiler.asm.amd64.AMD64Address;
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import org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMRIOp;
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import org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRMIOp;
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import org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRVMIOp;
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import org.graalvm.compiler.asm.amd64.AMD64MacroAssembler;
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import org.graalvm.compiler.asm.amd64.AVXKind;
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import org.graalvm.compiler.debug.GraalError;
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import org.graalvm.compiler.lir.LIRInstructionClass;
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import org.graalvm.compiler.lir.amd64.AMD64LIRInstruction;
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import org.graalvm.compiler.lir.asm.CompilationResultBuilder;
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import jdk.vm.ci.amd64.AMD64;
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import jdk.vm.ci.amd64.AMD64.CPUFeature;
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import jdk.vm.ci.amd64.AMD64Kind;
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import jdk.vm.ci.meta.AllocatableValue;
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public class AMD64VectorShuffle {
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    public static final class IntToVectorOp extends AMD64LIRInstruction {
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        public static final LIRInstructionClass<IntToVectorOp> TYPE = LIRInstructionClass.create(IntToVectorOp.class);
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        @Def({REG}) protected AllocatableValue result;
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        @Use({REG, STACK}) protected AllocatableValue value;
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        public IntToVectorOp(AllocatableValue result, AllocatableValue value) {
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            super(TYPE);
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            assert ((AMD64Kind) result.getPlatformKind()).getScalar().isInteger() : result.getPlatformKind();
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            this.result = result;
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            this.value = value;
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        }
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        @Override
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        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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            if (isRegister(value)) {
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                VMOVD.emit(masm, XMM, asRegister(result), asRegister(value));
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            } else {
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                assert isStackSlot(value);
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                VMOVD.emit(masm, XMM, asRegister(result), (AMD64Address) crb.asAddress(value));
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            }
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        }
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    }
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    public static final class LongToVectorOp extends AMD64LIRInstruction {
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        public static final LIRInstructionClass<LongToVectorOp> TYPE = LIRInstructionClass.create(LongToVectorOp.class);
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        @Def({REG}) protected AllocatableValue result;
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        @Use({REG, STACK}) protected AllocatableValue value;
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        public LongToVectorOp(AllocatableValue result, AllocatableValue value) {
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            super(TYPE);
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            assert result.getPlatformKind() == AMD64Kind.V128_QWORD || result.getPlatformKind() == AMD64Kind.V256_QWORD;
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            this.result = result;
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            this.value = value;
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        }
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        @Override
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        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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            if (isRegister(value)) {
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                VMOVQ.emit(masm, XMM, asRegister(result), asRegister(value));
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            } else {
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                assert isStackSlot(value);
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                VMOVQ.emit(masm, XMM, asRegister(result), (AMD64Address) crb.asAddress(value));
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            }
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        }
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    }
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    public static final class ShuffleBytesOp extends AMD64LIRInstruction {
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        public static final LIRInstructionClass<ShuffleBytesOp> TYPE = LIRInstructionClass.create(ShuffleBytesOp.class);
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        @Def({REG}) protected AllocatableValue result;
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        @Use({REG}) protected AllocatableValue source;
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        @Use({REG, STACK}) protected AllocatableValue selector;
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        public ShuffleBytesOp(AllocatableValue result, AllocatableValue source, AllocatableValue selector) {
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            super(TYPE);
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            this.result = result;
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            this.source = source;
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            this.selector = selector;
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        }
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        @Override
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        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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            AMD64Kind kind = (AMD64Kind) result.getPlatformKind();
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            if (isRegister(selector)) {
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                VPSHUFB.emit(masm, AVXKind.getRegisterSize(kind), asRegister(result), asRegister(source), asRegister(selector));
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            } else {
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                assert isStackSlot(selector);
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                VPSHUFB.emit(masm, AVXKind.getRegisterSize(kind), asRegister(result), asRegister(source), (AMD64Address) crb.asAddress(selector));
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            }
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        }
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    }
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    public static final class ConstShuffleBytesOp extends AMD64LIRInstruction {
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        public static final LIRInstructionClass<ConstShuffleBytesOp> TYPE = LIRInstructionClass.create(ConstShuffleBytesOp.class);
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        @Def({REG}) protected AllocatableValue result;
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        @Use({REG}) protected AllocatableValue source;
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        private final byte[] selector;
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        public ConstShuffleBytesOp(AllocatableValue result, AllocatableValue source, byte... selector) {
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            super(TYPE);
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            assert AVXKind.getRegisterSize(((AMD64Kind) result.getPlatformKind())).getBytes() == selector.length;
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            this.result = result;
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            this.source = source;
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            this.selector = selector;
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        }
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        @Override
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        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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            AMD64Kind kind = (AMD64Kind) result.getPlatformKind();
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            AMD64Address address = (AMD64Address) crb.recordDataReferenceInCode(selector, selector.length);
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            VPSHUFB.emit(masm, AVXKind.getRegisterSize(kind), asRegister(result), asRegister(source), address);
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        }
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    }
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    public static class ShuffleWordOp extends AMD64LIRInstruction {
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        public static final LIRInstructionClass<ShuffleWordOp> TYPE = LIRInstructionClass.create(ShuffleWordOp.class);
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        private final VexRMIOp op;
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        @Def({REG}) protected AllocatableValue result;
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        @Use({REG, STACK}) protected AllocatableValue source;
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parents:
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   164
        private final int selector;
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dlong
parents:
diff changeset
   165
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dlong
parents:
diff changeset
   166
        public ShuffleWordOp(VexRMIOp op, AllocatableValue result, AllocatableValue source, int selector) {
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dlong
parents:
diff changeset
   167
            super(TYPE);
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dlong
parents:
diff changeset
   168
            this.op = op;
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dlong
parents:
diff changeset
   169
            this.result = result;
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dlong
parents:
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   170
            this.source = source;
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dlong
parents:
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   171
            this.selector = selector;
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dlong
parents:
diff changeset
   172
        }
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dlong
parents:
diff changeset
   173
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dlong
parents:
diff changeset
   174
        @Override
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        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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parents:
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   176
            AMD64Kind kind = (AMD64Kind) source.getPlatformKind();
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parents:
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   177
            if (isRegister(source)) {
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                op.emit(masm, AVXKind.getRegisterSize(kind), asRegister(result), asRegister(source), selector);
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            } else {
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                op.emit(masm, AVXKind.getRegisterSize(kind), asRegister(result), (AMD64Address) crb.asAddress(source), selector);
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parents:
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   181
            }
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dlong
parents:
diff changeset
   182
        }
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dlong
parents:
diff changeset
   183
    }
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dlong
parents:
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   184
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   185
    public static class ShuffleFloatOp extends AMD64LIRInstruction {
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parents:
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   186
        public static final LIRInstructionClass<ShuffleFloatOp> TYPE = LIRInstructionClass.create(ShuffleFloatOp.class);
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dlong
parents:
diff changeset
   187
        @Def({REG}) protected AllocatableValue result;
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dlong
parents:
diff changeset
   188
        @Use({REG}) protected AllocatableValue source1;
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dlong
parents:
diff changeset
   189
        @Use({REG, STACK}) protected AllocatableValue source2;
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dlong
parents:
diff changeset
   190
        private final int selector;
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dlong
parents:
diff changeset
   191
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dlong
parents:
diff changeset
   192
        public ShuffleFloatOp(AllocatableValue result, AllocatableValue source1, AllocatableValue source2, int selector) {
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dlong
parents:
diff changeset
   193
            super(TYPE);
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dlong
parents:
diff changeset
   194
            this.result = result;
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dlong
parents:
diff changeset
   195
            this.source1 = source1;
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dlong
parents:
diff changeset
   196
            this.source2 = source2;
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dlong
parents:
diff changeset
   197
            this.selector = selector;
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dlong
parents:
diff changeset
   198
        }
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dlong
parents:
diff changeset
   199
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dlong
parents:
diff changeset
   200
        @Override
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   201
        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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parents:
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   202
            AMD64Kind kind = (AMD64Kind) result.getPlatformKind();
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dlong
parents:
diff changeset
   203
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dlong
parents:
diff changeset
   204
            VexRVMIOp op;
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dlong
parents:
diff changeset
   205
            switch (kind.getScalar()) {
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dlong
parents:
diff changeset
   206
                case SINGLE:
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dlong
parents:
diff changeset
   207
                    op = VSHUFPS;
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dlong
parents:
diff changeset
   208
                    break;
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dlong
parents:
diff changeset
   209
                case DOUBLE:
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dlong
parents:
diff changeset
   210
                    op = VSHUFPD;
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dlong
parents:
diff changeset
   211
                    break;
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dlong
parents:
diff changeset
   212
                default:
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dlong
parents:
diff changeset
   213
                    throw GraalError.shouldNotReachHere();
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dlong
parents:
diff changeset
   214
            }
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dlong
parents:
diff changeset
   215
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dlong
parents:
diff changeset
   216
            if (isRegister(source2)) {
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diff changeset
   217
                op.emit(masm, AVXKind.getRegisterSize(kind), asRegister(result), asRegister(source1), asRegister(source2), selector);
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dlong
parents:
diff changeset
   218
            } else {
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dlong
parents:
diff changeset
   219
                assert isStackSlot(source2);
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diff changeset
   220
                op.emit(masm, AVXKind.getRegisterSize(kind), asRegister(result), asRegister(source1), (AMD64Address) crb.asAddress(source2), selector);
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dlong
parents:
diff changeset
   221
            }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   222
        }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   223
    }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   224
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diff changeset
   225
    public static final class Extract128Op extends AMD64LIRInstruction {
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dlong
parents:
diff changeset
   226
        public static final LIRInstructionClass<Extract128Op> TYPE = LIRInstructionClass.create(Extract128Op.class);
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dlong
parents:
diff changeset
   227
        @Def({REG, STACK}) protected AllocatableValue result;
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dlong
parents:
diff changeset
   228
        @Use({REG}) protected AllocatableValue source;
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dlong
parents:
diff changeset
   229
        private final int selector;
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dlong
parents:
diff changeset
   230
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   231
        public Extract128Op(AllocatableValue result, AllocatableValue source, int selector) {
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   232
            super(TYPE);
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dlong
parents:
diff changeset
   233
            this.result = result;
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dlong
parents:
diff changeset
   234
            this.source = source;
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dlong
parents:
diff changeset
   235
            this.selector = selector;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   236
        }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   237
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   238
        @Override
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parents: 50858
diff changeset
   239
        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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dlong
parents:
diff changeset
   240
            AMD64Kind kind = (AMD64Kind) source.getPlatformKind();
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   241
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   242
            VexMRIOp op;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   243
            switch (kind.getScalar()) {
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dlong
parents:
diff changeset
   244
                case SINGLE:
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dlong
parents:
diff changeset
   245
                case DOUBLE:
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   246
                    op = VEXTRACTF128;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   247
                    break;
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dlong
parents:
diff changeset
   248
                default:
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dlong
parents:
diff changeset
   249
                    AMD64 arch = (AMD64) crb.target.arch;
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dlong
parents:
diff changeset
   250
                    // if supported we want VEXTRACTI128
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   251
                    // on AVX1, we have to use VEXTRACTF128
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dlong
parents:
diff changeset
   252
                    op = arch.getFeatures().contains(CPUFeature.AVX2) ? VEXTRACTI128 : VEXTRACTF128;
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dlong
parents:
diff changeset
   253
                    break;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   254
            }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   255
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   256
            if (isRegister(result)) {
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parents: 50858
diff changeset
   257
                op.emit(masm, AVXKind.getRegisterSize(kind), asRegister(result), asRegister(source), selector);
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dlong
parents:
diff changeset
   258
            } else {
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   259
                assert isStackSlot(result);
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parents: 50858
diff changeset
   260
                op.emit(masm, AVXKind.getRegisterSize(kind), (AMD64Address) crb.asAddress(result), asRegister(source), selector);
50609
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dlong
parents:
diff changeset
   261
            }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   262
        }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   263
    }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   264
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parents: 50858
diff changeset
   265
    public static final class Insert128Op extends AMD64LIRInstruction {
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dlong
parents:
diff changeset
   266
        public static final LIRInstructionClass<Insert128Op> TYPE = LIRInstructionClass.create(Insert128Op.class);
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dlong
parents:
diff changeset
   267
        @Def({REG}) protected AllocatableValue result;
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dlong
parents:
diff changeset
   268
        @Use({REG}) protected AllocatableValue source1;
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dlong
parents:
diff changeset
   269
        @Use({REG, STACK}) protected AllocatableValue source2;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   270
        private final int selector;
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dlong
parents:
diff changeset
   271
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   272
        public Insert128Op(AllocatableValue result, AllocatableValue source1, AllocatableValue source2, int selector) {
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   273
            super(TYPE);
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   274
            this.result = result;
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dlong
parents:
diff changeset
   275
            this.source1 = source1;
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dlong
parents:
diff changeset
   276
            this.source2 = source2;
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dlong
parents:
diff changeset
   277
            this.selector = selector;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   278
        }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   279
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   280
        @Override
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parents: 50858
diff changeset
   281
        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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dlong
parents:
diff changeset
   282
            AMD64Kind kind = (AMD64Kind) result.getPlatformKind();
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dlong
parents:
diff changeset
   283
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   284
            VexRVMIOp op;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   285
            switch (kind.getScalar()) {
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dlong
parents:
diff changeset
   286
                case SINGLE:
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   287
                case DOUBLE:
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   288
                    op = VINSERTF128;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   289
                    break;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   290
                default:
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   291
                    AMD64 arch = (AMD64) crb.target.arch;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   292
                    // if supported we want VINSERTI128 - on AVX1, we have to use VINSERTF128.
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dlong
parents:
diff changeset
   293
                    // using instructions with an incorrect data type is possible but typically
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   294
                    // results in an additional overhead whenever the value is being accessed.
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dlong
parents:
diff changeset
   295
                    op = arch.getFeatures().contains(CPUFeature.AVX2) ? VINSERTI128 : VINSERTF128;
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dlong
parents:
diff changeset
   296
                    break;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   297
            }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   298
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   299
            if (isRegister(source2)) {
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parents: 50858
diff changeset
   300
                op.emit(masm, AVXKind.getRegisterSize(kind), asRegister(result), asRegister(source1), asRegister(source2), selector);
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dlong
parents:
diff changeset
   301
            } else {
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dlong
parents:
diff changeset
   302
                assert isStackSlot(source2);
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parents: 50858
diff changeset
   303
                op.emit(masm, AVXKind.getRegisterSize(kind), asRegister(result), asRegister(source1), (AMD64Address) crb.asAddress(source2), selector);
50609
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dlong
parents:
diff changeset
   304
            }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   305
        }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   306
    }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   307
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iveresov
parents: 50858
diff changeset
   308
    public static final class ExtractByteOp extends AMD64LIRInstruction {
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dlong
parents:
diff changeset
   309
        public static final LIRInstructionClass<ExtractByteOp> TYPE = LIRInstructionClass.create(ExtractByteOp.class);
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   310
        @Def({REG}) protected AllocatableValue result;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   311
        @Use({REG}) protected AllocatableValue vector;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   312
        private final int selector;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   313
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   314
        public ExtractByteOp(AllocatableValue result, AllocatableValue vector, int selector) {
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   315
            super(TYPE);
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   316
            assert result.getPlatformKind() == AMD64Kind.DWORD;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   317
            assert ((AMD64Kind) vector.getPlatformKind()).getScalar() == AMD64Kind.BYTE;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   318
            this.result = result;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   319
            this.vector = vector;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   320
            this.selector = selector;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   321
        }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   322
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   323
        @Override
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parents: 50858
diff changeset
   324
        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
091c0d22e735 8206992: Update Graal
iveresov
parents: 50858
diff changeset
   325
            VPEXTRB.emit(masm, XMM, asRegister(result), asRegister(vector), selector);
50609
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dlong
parents:
diff changeset
   326
        }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   327
    }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   328
51436
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iveresov
parents: 50858
diff changeset
   329
    public static final class ExtractShortOp extends AMD64LIRInstruction {
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dlong
parents:
diff changeset
   330
        public static final LIRInstructionClass<ExtractShortOp> TYPE = LIRInstructionClass.create(ExtractShortOp.class);
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   331
        @Def({REG}) protected AllocatableValue result;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   332
        @Use({REG}) protected AllocatableValue vector;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   333
        private final int selector;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   334
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   335
        public ExtractShortOp(AllocatableValue result, AllocatableValue vector, int selector) {
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   336
            super(TYPE);
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   337
            assert result.getPlatformKind() == AMD64Kind.DWORD;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   338
            assert ((AMD64Kind) vector.getPlatformKind()).getScalar() == AMD64Kind.WORD;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   339
            this.result = result;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   340
            this.vector = vector;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   341
            this.selector = selector;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   342
        }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   343
bf414874c28f 8204231: Update Graal
dlong
parents:
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   344
        @Override
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   345
        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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   346
            VPEXTRW.emit(masm, XMM, asRegister(result), asRegister(vector), selector);
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dlong
parents:
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   347
        }
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dlong
parents:
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   348
    }
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dlong
parents:
diff changeset
   349
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   350
    public static final class ExtractIntOp extends AMD64LIRInstruction {
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   351
        public static final LIRInstructionClass<ExtractIntOp> TYPE = LIRInstructionClass.create(ExtractIntOp.class);
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dlong
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   352
        @Def({REG, STACK}) protected AllocatableValue result;
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dlong
parents:
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   353
        @Use({REG}) protected AllocatableValue vector;
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dlong
parents:
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   354
        private final int selector;
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dlong
parents:
diff changeset
   355
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dlong
parents:
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   356
        public ExtractIntOp(AllocatableValue result, AllocatableValue vector, int selector) {
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dlong
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   357
            super(TYPE);
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dlong
parents:
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   358
            assert result.getPlatformKind() == AMD64Kind.DWORD;
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dlong
parents:
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   359
            assert ((AMD64Kind) vector.getPlatformKind()).getScalar() == AMD64Kind.DWORD;
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dlong
parents:
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   360
            this.result = result;
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dlong
parents:
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   361
            this.vector = vector;
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dlong
parents:
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   362
            this.selector = selector;
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dlong
parents:
diff changeset
   363
        }
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dlong
parents:
diff changeset
   364
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dlong
parents:
diff changeset
   365
        @Override
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diff changeset
   366
        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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dlong
parents:
diff changeset
   367
            if (isRegister(result)) {
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dlong
parents:
diff changeset
   368
                if (selector == 0) {
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diff changeset
   369
                    VMOVD.emitReverse(masm, XMM, asRegister(result), asRegister(vector));
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dlong
parents:
diff changeset
   370
                } else {
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diff changeset
   371
                    VPEXTRD.emit(masm, XMM, asRegister(result), asRegister(vector), selector);
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dlong
parents:
diff changeset
   372
                }
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dlong
parents:
diff changeset
   373
            } else {
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dlong
parents:
diff changeset
   374
                assert isStackSlot(result);
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dlong
parents:
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   375
                if (selector == 0) {
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   376
                    VMOVD.emit(masm, XMM, (AMD64Address) crb.asAddress(result), asRegister(vector));
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dlong
parents:
diff changeset
   377
                } else {
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parents: 50858
diff changeset
   378
                    VPEXTRD.emit(masm, XMM, (AMD64Address) crb.asAddress(result), asRegister(vector), selector);
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dlong
parents:
diff changeset
   379
                }
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dlong
parents:
diff changeset
   380
            }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   381
        }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   382
    }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   383
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parents: 50858
diff changeset
   384
    public static final class ExtractLongOp extends AMD64LIRInstruction {
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dlong
parents:
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   385
        public static final LIRInstructionClass<ExtractLongOp> TYPE = LIRInstructionClass.create(ExtractLongOp.class);
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   386
        @Def({REG, STACK}) protected AllocatableValue result;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   387
        @Use({REG}) protected AllocatableValue vector;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   388
        private final int selector;
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dlong
parents:
diff changeset
   389
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dlong
parents:
diff changeset
   390
        public ExtractLongOp(AllocatableValue result, AllocatableValue vector, int selector) {
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   391
            super(TYPE);
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dlong
parents:
diff changeset
   392
            assert result.getPlatformKind() == AMD64Kind.QWORD;
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dlong
parents:
diff changeset
   393
            assert ((AMD64Kind) vector.getPlatformKind()).getScalar() == AMD64Kind.QWORD;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   394
            this.result = result;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   395
            this.vector = vector;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   396
            this.selector = selector;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   397
        }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   398
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   399
        @Override
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parents: 50858
diff changeset
   400
        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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dlong
parents:
diff changeset
   401
            if (isRegister(result)) {
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   402
                if (selector == 0) {
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iveresov
parents: 50858
diff changeset
   403
                    VMOVQ.emitReverse(masm, XMM, asRegister(result), asRegister(vector));
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dlong
parents:
diff changeset
   404
                } else {
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091c0d22e735 8206992: Update Graal
iveresov
parents: 50858
diff changeset
   405
                    VPEXTRQ.emit(masm, XMM, asRegister(result), asRegister(vector), selector);
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bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   406
                }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   407
            } else {
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   408
                assert isStackSlot(result);
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   409
                if (selector == 0) {
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iveresov
parents: 50858
diff changeset
   410
                    VMOVQ.emit(masm, XMM, (AMD64Address) crb.asAddress(result), asRegister(vector));
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dlong
parents:
diff changeset
   411
                } else {
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iveresov
parents: 50858
diff changeset
   412
                    VPEXTRQ.emit(masm, XMM, (AMD64Address) crb.asAddress(result), asRegister(vector), selector);
50609
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dlong
parents:
diff changeset
   413
                }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   414
            }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   415
        }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   416
    }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   417
}