src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.lir.amd64/src/org/graalvm/compiler/lir/amd64/vector/AMD64VectorMove.java
author iveresov
Fri, 17 Aug 2018 13:20:53 -0700
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child 58299 6df94ce3ab2f
permissions -rw-r--r--
8206992: Update Graal Reviewed-by: kvn
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/*
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 * Copyright (c) 2013, 2018, Oracle and/or its affiliates. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 */
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package org.graalvm.compiler.lir.amd64.vector;
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import static jdk.vm.ci.code.ValueUtil.asRegister;
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import static jdk.vm.ci.code.ValueUtil.isRegister;
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import static jdk.vm.ci.code.ValueUtil.isStackSlot;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMoveOp.VMOVD;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMoveOp.VMOVDQU;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMoveOp.VMOVQ;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMoveOp.VMOVSD;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMoveOp.VMOVSS;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMoveOp.VMOVUPD;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMoveOp.VMOVUPS;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRVMOp.VXORPD;
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import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.COMPOSITE;
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import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.HINT;
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import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.REG;
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import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.STACK;
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import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.UNINITIALIZED;
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import org.graalvm.compiler.asm.amd64.AMD64Address;
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import org.graalvm.compiler.asm.amd64.AMD64Assembler.VexMoveOp;
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import org.graalvm.compiler.asm.amd64.AMD64MacroAssembler;
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import org.graalvm.compiler.asm.amd64.AVXKind;
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import org.graalvm.compiler.asm.amd64.AVXKind.AVXSize;
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import org.graalvm.compiler.debug.GraalError;
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import org.graalvm.compiler.lir.LIRFrameState;
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import org.graalvm.compiler.lir.LIRInstructionClass;
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import org.graalvm.compiler.lir.Opcode;
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import org.graalvm.compiler.lir.StandardOp.LoadConstantOp;
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import org.graalvm.compiler.lir.StandardOp.ValueMoveOp;
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import org.graalvm.compiler.lir.amd64.AMD64AddressValue;
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import org.graalvm.compiler.lir.amd64.AMD64LIRInstruction;
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import org.graalvm.compiler.lir.amd64.AMD64Move;
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import org.graalvm.compiler.lir.amd64.AMD64RestoreRegistersOp;
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import org.graalvm.compiler.lir.amd64.AMD64SaveRegistersOp;
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import org.graalvm.compiler.lir.asm.CompilationResultBuilder;
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import jdk.vm.ci.amd64.AMD64Kind;
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import jdk.vm.ci.code.Register;
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import jdk.vm.ci.code.RegisterValue;
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import jdk.vm.ci.code.StackSlot;
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import jdk.vm.ci.meta.AllocatableValue;
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import jdk.vm.ci.meta.Constant;
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import jdk.vm.ci.meta.JavaConstant;
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import jdk.vm.ci.meta.Value;
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public class AMD64VectorMove {
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    @Opcode("VMOVE")
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    public static final class MoveToRegOp extends AMD64LIRInstruction implements ValueMoveOp {
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        public static final LIRInstructionClass<MoveToRegOp> TYPE = LIRInstructionClass.create(MoveToRegOp.class);
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        @Def({REG, HINT}) protected AllocatableValue result;
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        @Use({REG, STACK}) protected AllocatableValue input;
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        public MoveToRegOp(AllocatableValue result, AllocatableValue input) {
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            super(TYPE);
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            this.result = result;
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            this.input = input;
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        }
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        @Override
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        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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            move(crb, masm, result, input);
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        }
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        @Override
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        public AllocatableValue getInput() {
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            return input;
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        }
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        @Override
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        public AllocatableValue getResult() {
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            return result;
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        }
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    }
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    @Opcode("VMOVE")
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    public static final class MoveFromRegOp extends AMD64LIRInstruction implements ValueMoveOp {
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        public static final LIRInstructionClass<MoveFromRegOp> TYPE = LIRInstructionClass.create(MoveFromRegOp.class);
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        @Def({REG, STACK}) protected AllocatableValue result;
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        @Use({REG, HINT}) protected AllocatableValue input;
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        public MoveFromRegOp(AllocatableValue result, AllocatableValue input) {
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            super(TYPE);
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            this.result = result;
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            this.input = input;
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        }
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        @Override
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        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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            move(crb, masm, result, input);
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        }
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        @Override
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        public AllocatableValue getInput() {
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            return input;
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        }
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        @Override
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        public AllocatableValue getResult() {
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            return result;
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        }
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    }
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    @Opcode("VMOVE")
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    public static class MoveFromConstOp extends AMD64LIRInstruction implements LoadConstantOp {
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        public static final LIRInstructionClass<MoveFromConstOp> TYPE = LIRInstructionClass.create(MoveFromConstOp.class);
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        @Def({REG, STACK}) protected AllocatableValue result;
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        private final JavaConstant input;
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        public MoveFromConstOp(AllocatableValue result, JavaConstant input) {
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            super(TYPE);
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            this.result = result;
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            this.input = input;
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        }
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        @Override
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        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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            if (isRegister(result)) {
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                const2reg(crb, masm, (RegisterValue) result, input);
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            } else {
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                assert isStackSlot(result);
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                AMD64Move.const2stack(crb, masm, result, input);
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            }
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        }
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        @Override
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        public Constant getConstant() {
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            return input;
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        }
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        @Override
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        public AllocatableValue getResult() {
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            return result;
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        }
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    }
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    @Opcode("VSTACKMOVE")
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    public static final class StackMoveOp extends AMD64LIRInstruction implements ValueMoveOp {
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        public static final LIRInstructionClass<StackMoveOp> TYPE = LIRInstructionClass.create(StackMoveOp.class);
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        @Def({STACK}) protected AllocatableValue result;
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        @Use({STACK, HINT}) protected AllocatableValue input;
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        @Alive({STACK, UNINITIALIZED}) private AllocatableValue backupSlot;
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        private Register scratch;
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        public StackMoveOp(AllocatableValue result, AllocatableValue input, Register scratch, AllocatableValue backupSlot) {
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            super(TYPE);
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            this.result = result;
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            this.input = input;
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            this.backupSlot = backupSlot;
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            this.scratch = scratch;
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        }
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        @Override
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        public AllocatableValue getInput() {
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            return input;
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        }
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        @Override
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        public AllocatableValue getResult() {
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            return result;
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        }
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        @Override
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        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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            // backup scratch register
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            move(crb, masm, backupSlot, scratch.asValue(backupSlot.getValueKind()));
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            // move stack slot
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            move(crb, masm, scratch.asValue(getInput().getValueKind()), getInput());
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            move(crb, masm, getResult(), scratch.asValue(getResult().getValueKind()));
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            // restore scratch register
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            move(crb, masm, scratch.asValue(backupSlot.getValueKind()), backupSlot);
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        }
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    }
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    public abstract static class VectorMemOp extends AMD64LIRInstruction {
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        protected final AVXSize size;
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        protected final VexMoveOp op;
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        @Use({COMPOSITE}) protected AMD64AddressValue address;
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        @State protected LIRFrameState state;
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        protected VectorMemOp(LIRInstructionClass<? extends VectorMemOp> c, AVXSize size, VexMoveOp op, AMD64AddressValue address, LIRFrameState state) {
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            super(c);
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            this.size = size;
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            this.op = op;
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            this.address = address;
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            this.state = state;
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        }
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        protected abstract void emitMemAccess(AMD64MacroAssembler masm);
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        @Override
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        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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            if (state != null) {
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                crb.recordImplicitException(masm.position(), state);
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            }
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            emitMemAccess(masm);
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        }
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    }
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    public static final class VectorLoadOp extends VectorMemOp {
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        public static final LIRInstructionClass<VectorLoadOp> TYPE = LIRInstructionClass.create(VectorLoadOp.class);
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        @Def({REG}) protected AllocatableValue result;
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        public VectorLoadOp(AVXSize size, VexMoveOp op, AllocatableValue result, AMD64AddressValue address, LIRFrameState state) {
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            super(TYPE, size, op, address, state);
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            this.result = result;
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        }
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        @Override
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        public void emitMemAccess(AMD64MacroAssembler masm) {
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            op.emit(masm, size, asRegister(result), address.toAddress());
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        }
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    }
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    public static class VectorStoreOp extends VectorMemOp {
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        public static final LIRInstructionClass<VectorStoreOp> TYPE = LIRInstructionClass.create(VectorStoreOp.class);
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        @Use({REG}) protected AllocatableValue input;
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        public VectorStoreOp(AVXSize size, VexMoveOp op, AMD64AddressValue address, AllocatableValue input, LIRFrameState state) {
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            super(TYPE, size, op, address, state);
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            this.input = input;
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        }
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        @Override
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        public void emitMemAccess(AMD64MacroAssembler masm) {
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            op.emit(masm, size, address.toAddress(), asRegister(input));
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        }
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    }
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    @Opcode("SAVE_REGISTER")
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    public static class SaveRegistersOp extends AMD64SaveRegistersOp {
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        public static final LIRInstructionClass<SaveRegistersOp> TYPE = LIRInstructionClass.create(SaveRegistersOp.class);
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        public SaveRegistersOp(Register[] savedRegisters, AllocatableValue[] slots, boolean supportsRemove) {
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            super(TYPE, savedRegisters, slots, supportsRemove);
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        }
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        @Override
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        protected void saveRegister(CompilationResultBuilder crb, AMD64MacroAssembler masm, StackSlot result, Register register) {
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            AMD64Kind kind = (AMD64Kind) result.getPlatformKind();
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            if (kind.isXMM()) {
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                VexMoveOp op;
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                if (kind.getVectorLength() > 1) {
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                    op = getVectorMoveOp(kind.getScalar());
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                } else {
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                    op = getScalarMoveOp(kind);
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                }
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                AMD64Address addr = (AMD64Address) crb.asAddress(result);
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                op.emit(masm, AVXKind.getRegisterSize(kind), addr, register);
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            } else {
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                super.saveRegister(crb, masm, result, register);
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            }
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        }
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    }
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    @Opcode("RESTORE_REGISTER")
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    public static final class RestoreRegistersOp extends AMD64RestoreRegistersOp {
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        public static final LIRInstructionClass<RestoreRegistersOp> TYPE = LIRInstructionClass.create(RestoreRegistersOp.class);
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        public RestoreRegistersOp(AllocatableValue[] source, AMD64SaveRegistersOp save) {
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            super(TYPE, source, save);
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        }
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        @Override
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        protected void restoreRegister(CompilationResultBuilder crb, AMD64MacroAssembler masm, Register register, StackSlot input) {
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            AMD64Kind kind = (AMD64Kind) input.getPlatformKind();
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            if (kind.isXMM()) {
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                VexMoveOp op;
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                if (kind.getVectorLength() > 1) {
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                    op = getVectorMoveOp(kind.getScalar());
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                } else {
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                    op = getScalarMoveOp(kind);
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                }
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                AMD64Address addr = (AMD64Address) crb.asAddress(input);
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                op.emit(masm, AVXKind.getRegisterSize(kind), register, addr);
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            } else {
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                super.restoreRegister(crb, masm, register, input);
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            }
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        }
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    }
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    private static VexMoveOp getScalarMoveOp(AMD64Kind kind) {
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        switch (kind) {
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            case SINGLE:
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                return VMOVSS;
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            case DOUBLE:
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                return VMOVSD;
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            default:
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                throw GraalError.shouldNotReachHere();
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        }
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    }
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    private static VexMoveOp getVectorMoveOp(AMD64Kind kind) {
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        switch (kind) {
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            case SINGLE:
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                return VMOVUPS;
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            case DOUBLE:
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                return VMOVUPD;
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            default:
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                return VMOVDQU;
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        }
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    }
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    private static VexMoveOp getVectorMemMoveOp(AMD64Kind kind) {
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        switch (AVXKind.getDataSize(kind)) {
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            case DWORD:
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                return VMOVD;
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            case QWORD:
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                return VMOVQ;
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            default:
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                return getVectorMoveOp(kind.getScalar());
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        }
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    }
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    private static void move(CompilationResultBuilder crb, AMD64MacroAssembler masm, AllocatableValue result, Value input) {
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        VexMoveOp op;
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        AVXSize size;
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        AMD64Kind kind = (AMD64Kind) result.getPlatformKind();
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        if (kind.getVectorLength() > 1) {
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            size = AVXKind.getRegisterSize(kind);
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   358
            if (isRegister(input) && isRegister(result)) {
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                op = getVectorMoveOp(kind.getScalar());
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   360
            } else {
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                op = getVectorMemMoveOp(kind);
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            }
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        } else {
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diff changeset
   364
            size = AVXSize.XMM;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   365
            if (isRegister(input) && isRegister(result)) {
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   366
                op = getVectorMoveOp(kind);
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   367
            } else {
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   368
                op = getScalarMoveOp(kind);
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   369
            }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   370
        }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   371
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   372
        if (isRegister(input)) {
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   373
            if (isRegister(result)) {
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   374
                if (!asRegister(input).equals(asRegister(result))) {
51436
091c0d22e735 8206992: Update Graal
iveresov
parents: 50858
diff changeset
   375
                    op.emit(masm, size, asRegister(result), asRegister(input));
50609
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   376
                }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   377
            } else {
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   378
                assert isStackSlot(result);
51436
091c0d22e735 8206992: Update Graal
iveresov
parents: 50858
diff changeset
   379
                op.emit(masm, size, (AMD64Address) crb.asAddress(result), asRegister(input));
50609
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   380
            }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   381
        } else {
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   382
            assert isStackSlot(input) && isRegister(result);
51436
091c0d22e735 8206992: Update Graal
iveresov
parents: 50858
diff changeset
   383
            op.emit(masm, size, asRegister(result), (AMD64Address) crb.asAddress(input));
50609
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   384
        }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   385
    }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   386
51436
091c0d22e735 8206992: Update Graal
iveresov
parents: 50858
diff changeset
   387
    private static void const2reg(CompilationResultBuilder crb, AMD64MacroAssembler masm, RegisterValue result, JavaConstant input) {
50609
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   388
        if (input.isDefaultForKind()) {
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   389
            AMD64Kind kind = (AMD64Kind) result.getPlatformKind();
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   390
            Register register = result.getRegister();
51436
091c0d22e735 8206992: Update Graal
iveresov
parents: 50858
diff changeset
   391
            VXORPD.emit(masm, AVXKind.getRegisterSize(kind), register, register, register);
50609
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   392
            return;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   393
        }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   394
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   395
        AMD64Address address;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   396
        switch (input.getJavaKind()) {
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   397
            case Float:
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   398
                address = (AMD64Address) crb.asFloatConstRef(input);
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   399
                break;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   400
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   401
            case Double:
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   402
                address = (AMD64Address) crb.asDoubleConstRef(input);
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   403
                break;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   404
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   405
            default:
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   406
                throw GraalError.shouldNotReachHere();
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   407
        }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   408
        VexMoveOp op = getScalarMoveOp((AMD64Kind) result.getPlatformKind());
51436
091c0d22e735 8206992: Update Graal
iveresov
parents: 50858
diff changeset
   409
        op.emit(masm, AVXSize.XMM, asRegister(result), address);
50609
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   410
    }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   411
51436
091c0d22e735 8206992: Update Graal
iveresov
parents: 50858
diff changeset
   412
    public static final class AVXMoveToIntOp extends AMD64LIRInstruction {
50609
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   413
        public static final LIRInstructionClass<AVXMoveToIntOp> TYPE = LIRInstructionClass.create(AVXMoveToIntOp.class);
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   414
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   415
        @Opcode private final VexMoveOp opcode;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   416
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   417
        @Def({REG, STACK}) protected AllocatableValue result;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   418
        @Use({REG}) protected AllocatableValue input;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   419
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   420
        public AVXMoveToIntOp(VexMoveOp opcode, AllocatableValue result, AllocatableValue input) {
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   421
            super(TYPE);
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   422
            this.opcode = opcode;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   423
            this.result = result;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   424
            this.input = input;
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   425
        }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   426
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   427
        @Override
51436
091c0d22e735 8206992: Update Graal
iveresov
parents: 50858
diff changeset
   428
        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
50609
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   429
            if (isRegister(result)) {
51436
091c0d22e735 8206992: Update Graal
iveresov
parents: 50858
diff changeset
   430
                opcode.emitReverse(masm, AVXSize.XMM, asRegister(result), asRegister(input));
50609
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   431
            } else {
51436
091c0d22e735 8206992: Update Graal
iveresov
parents: 50858
diff changeset
   432
                opcode.emit(masm, AVXSize.XMM, (AMD64Address) crb.asAddress(result), asRegister(input));
50609
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   433
            }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   434
        }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   435
    }
bf414874c28f 8204231: Update Graal
dlong
parents:
diff changeset
   436
}