/*

 * Copyright (c) 2019, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 */

package org.graalvm.compiler.lir.amd64;

import static jdk.vm.ci.code.ValueUtil.asRegister;

import static jdk.vm.ci.code.ValueUtil.isRegister;

import static jdk.vm.ci.code.ValueUtil.isStackSlot;

import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.HINT;

import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.REG;

import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.STACK;

import org.graalvm.compiler.asm.amd64.AMD64Address;

import org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRVMOp;

import org.graalvm.compiler.asm.amd64.AMD64MacroAssembler;

import org.graalvm.compiler.asm.amd64.AVXKind.AVXSize;

import org.graalvm.compiler.lir.LIRInstructionClass;

import org.graalvm.compiler.lir.Opcode;

import org.graalvm.compiler.lir.asm.CompilationResultBuilder;

import jdk.vm.ci.meta.AllocatableValue;

/**

 * AMD64 LIR instructions that have three inputs and one output.

 */

public class AMD64Ternary {

    /**

     * Instruction that has two {@link AllocatableValue} operands.

     */

        public static final LIRInstructionClass<ThreeOp> TYPE = LIRInstructionClass.create(ThreeOp.class);

        @Opcode private final VexRVMOp opcode;

        @Def({REG, HINT}) protected AllocatableValue result;

        @Use({REG}) protected AllocatableValue x;

        /**

         * This argument must be Alive to ensure that result and y are not assigned to the same

         * register, which would break the code generation by destroying y too early.

         */

        @Alive({REG}) protected AllocatableValue y;

        @Alive({REG, STACK}) protected AllocatableValue z;

        public ThreeOp(VexRVMOp opcode, AVXSize size, AllocatableValue result, AllocatableValue x, AllocatableValue y, AllocatableValue z) {

            this.opcode = opcode;

            this.result = result;

            this.x = x;

            this.y = y;

            this.z = z;

        }

        @Override

        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {

            AMD64Move.move(crb, masm, result, x);

            if (isRegister(z)) {

                opcode.emit(masm, size, asRegister(result), asRegister(y), asRegister(z));

            } else {

                assert isStackSlot(z);

                opcode.emit(masm, size, asRegister(result), asRegister(y), (AMD64Address) crb.asAddress(z));

            }

        }

    }

}