--- a/src/hotspot/cpu/ppc/assembler_ppc.hpp	Tue Sep 18 11:09:18 2018 +0800
+++ b/src/hotspot/cpu/ppc/assembler_ppc.hpp	Mon Sep 17 23:35:00 2018 -0400
@@ -529,6 +529,7 @@
     XVNEGDP_OPCODE = (60u << OPCODE_SHIFT |  505u << 2),
     XVSQRTSP_OPCODE= (60u << OPCODE_SHIFT |  139u << 2),
     XVSQRTDP_OPCODE= (60u << OPCODE_SHIFT |  203u << 2),
+    XSCVDPSPN_OPCODE=(60u << OPCODE_SHIFT |  267u << 2),
     XVADDDP_OPCODE = (60u << OPCODE_SHIFT |   96u << 3),
     XVSUBDP_OPCODE = (60u << OPCODE_SHIFT |  104u << 3),
     XVMULSP_OPCODE = (60u << OPCODE_SHIFT |   80u << 3),
@@ -2202,6 +2203,7 @@
   inline void xvnegdp(  VectorSRegister d, VectorSRegister b);
   inline void xvsqrtsp( VectorSRegister d, VectorSRegister b);
   inline void xvsqrtdp( VectorSRegister d, VectorSRegister b);
+  inline void xscvdpspn(VectorSRegister d, VectorSRegister b);
   inline void xvadddp(  VectorSRegister d, VectorSRegister a, VectorSRegister b);
   inline void xvsubdp(  VectorSRegister d, VectorSRegister a, VectorSRegister b);
   inline void xvmulsp(  VectorSRegister d, VectorSRegister a, VectorSRegister b);

--- a/src/hotspot/cpu/ppc/assembler_ppc.inline.hpp	Tue Sep 18 11:09:18 2018 +0800
+++ b/src/hotspot/cpu/ppc/assembler_ppc.inline.hpp	Mon Sep 17 23:35:00 2018 -0400
@@ -777,6 +777,7 @@
 inline void Assembler::xvnegdp( VectorSRegister d, VectorSRegister b)                    { emit_int32( XVNEGDP_OPCODE | vsrt(d) | vsrb(b)); }
 inline void Assembler::xvsqrtsp(VectorSRegister d, VectorSRegister b)                    { emit_int32( XVSQRTSP_OPCODE| vsrt(d) | vsrb(b)); }
 inline void Assembler::xvsqrtdp(VectorSRegister d, VectorSRegister b)                    { emit_int32( XVSQRTDP_OPCODE| vsrt(d) | vsrb(b)); }
+inline void Assembler::xscvdpspn(VectorSRegister d, VectorSRegister b)                   { emit_int32( XSCVDPSPN_OPCODE | vsrt(d) | vsrb(b)); }
 inline void Assembler::xvadddp( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XVADDDP_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
 inline void Assembler::xvsubdp( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XVSUBDP_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
 inline void Assembler::xvmulsp( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XVMULSP_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }

--- a/src/hotspot/cpu/ppc/ppc.ad	Tue Sep 18 11:09:18 2018 +0800
+++ b/src/hotspot/cpu/ppc/ppc.ad	Mon Sep 17 23:35:00 2018 -0400
@@ -13682,6 +13682,7 @@
 instruct mtvsrwz(vecX temp1, iRegIsrc src) %{
   effect(DEF temp1, USE src);
 
+  format %{ "MTVSRWZ $temp1, $src \t// Move to 16-byte register" %}
   size(4);
   ins_encode %{
     __ mtvsrwz($temp1$$VectorSRegister, $src$$Register);
@@ -13692,6 +13693,7 @@
 instruct xxspltw(vecX dst, vecX src, immI8 imm1) %{
   effect(DEF dst, USE src, USE imm1);
 
+  format %{ "XXSPLTW $dst, $src, $imm1 \t// Splat word" %}
   size(4);
   ins_encode %{
     __ xxspltw($dst$$VectorSRegister, $src$$VectorSRegister, $imm1$$constant);
@@ -13699,6 +13701,17 @@
   ins_pipe(pipe_class_default);
 %}
 
+instruct xscvdpspn_regF(vecX dst, regF src) %{
+  effect(DEF dst, USE src);
+
+  format %{ "XSCVDPSPN $dst, $src \t// Convert scalar single precision to vector single precision" %}
+  size(4);
+  ins_encode %{
+    __ xscvdpspn($dst$$VectorSRegister, $src$$FloatRegister->to_vsr());
+  %}
+  ins_pipe(pipe_class_default);
+%}
+
 //---------- Replicate Vector Instructions ------------------------------------
 
 // Insrdi does replicate if src == dst.
@@ -14360,24 +14373,16 @@
   ins_pipe(pipe_class_default);
 %}
 
-
 instruct repl4F_reg_Ex(vecX dst, regF src) %{
   match(Set dst (ReplicateF src));
   predicate(n->as_Vector()->length() == 4);
-  ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
-  expand %{
-    stackSlotL tmpS;
-    iRegIdst tmpI;
-    iRegLdst tmpL;
+  ins_cost(DEFAULT_COST);
+  expand %{
     vecX tmpV;
     immI8  zero %{ (int)  0 %}
 
-    moveF2I_reg_stack(tmpS, src);   // Move float to stack.
-    moveF2I_stack_reg(tmpI, tmpS);  // Move stack to int reg.
-    moveReg(tmpL, tmpI);             // Move int to long reg.
-    repl32(tmpL);                    // Replicate bitpattern.
-    mtvsrd(tmpV, tmpL);
-    xxpermdi(dst, tmpV, tmpV, zero);
+    xscvdpspn_regF(tmpV, src);
+    xxspltw(dst, tmpV, zero);
   %}
 %}
 
@@ -14404,17 +14409,13 @@
 instruct repl2D_reg_Ex(vecX dst, regD src) %{
   match(Set dst (ReplicateD src));
   predicate(n->as_Vector()->length() == 2);
-  expand %{
-    stackSlotL tmpS;
-    iRegLdst tmpL;
-    iRegLdst tmp;
-    vecX tmpV;
-    immI8  zero %{ (int)  0 %}
-    moveD2L_reg_stack(tmpS, src);
-    moveD2L_stack_reg(tmpL, tmpS);
-    mtvsrd(tmpV, tmpL);
-    xxpermdi(dst, tmpV, tmpV, zero);
-  %}
+
+  format %{ "XXPERMDI      $dst, $src, $src, 0 \t// Splat doubleword" %}
+  size(4);
+  ins_encode %{
+    __ xxpermdi($dst$$VectorSRegister, $src$$FloatRegister->to_vsr(), $src$$FloatRegister->to_vsr(), 0);
+  %}
+  ins_pipe(pipe_class_default);
 %}
 
 instruct repl2D_immI0(vecX dst, immI_0 zero) %{
@@ -14445,7 +14446,7 @@
   predicate(false);
   effect(DEF dst, USE src);
 
-  format %{ "MTVSRD      $dst, $src \t// Move to 16-byte register"%}
+  format %{ "MTVSRD      $dst, $src \t// Move to 16-byte register" %}
   size(4);
   ins_encode %{
     __ mtvsrd($dst$$VectorSRegister, $src$$Register);
@@ -14456,7 +14457,7 @@
 instruct xxspltd(vecX dst, vecX src, immI8 zero) %{
   effect(DEF dst, USE src, USE zero);
 
-  format %{ "XXSPLATD      $dst, $src, $zero \t// Permute 16-byte register"%}
+  format %{ "XXSPLATD      $dst, $src, $zero \t// Splat doubleword" %}
   size(4);
   ins_encode %{
     __ xxpermdi($dst$$VectorSRegister, $src$$VectorSRegister, $src$$VectorSRegister, $zero$$constant);
@@ -14467,7 +14468,7 @@
 instruct xxpermdi(vecX dst, vecX src1, vecX src2, immI8 zero) %{
   effect(DEF dst, USE src1, USE src2, USE zero);
 
-  format %{ "XXPERMDI      $dst, $src1, $src2, $zero \t// Permute 16-byte register"%}
+  format %{ "XXPERMDI      $dst, $src1, $src2, $zero \t// Splat doubleword" %}
   size(4);
   ins_encode %{
     __ xxpermdi($dst$$VectorSRegister, $src1$$VectorSRegister, $src2$$VectorSRegister, $zero$$constant);

--- a/src/hotspot/cpu/ppc/register_ppc.cpp	Tue Sep 18 11:09:18 2018 +0800
+++ b/src/hotspot/cpu/ppc/register_ppc.cpp	Mon Sep 17 23:35:00 2018 -0400
@@ -85,6 +85,12 @@
   return is_valid() ? names[encoding()] : "vsnoreg";
 }
 
+// Method to convert a FloatRegister to a Vector-Scalar Register (VectorSRegister)
+VectorSRegister FloatRegisterImpl::to_vsr() const {
+  if (this == fnoreg) { return vsnoreg; }
+  return as_VectorSRegister(encoding());
+}
+
 // Method to convert a VectorRegister to a Vector-Scalar Register (VectorSRegister)
 VectorSRegister VectorRegisterImpl::to_vsr() const {
   if (this == vnoreg) { return vsnoreg; }

--- a/src/hotspot/cpu/ppc/register_ppc.hpp	Tue Sep 18 11:09:18 2018 +0800
+++ b/src/hotspot/cpu/ppc/register_ppc.hpp	Mon Sep 17 23:35:00 2018 -0400
@@ -241,6 +241,10 @@
 
 #endif // DONT_USE_REGISTER_DEFINES
 
+// Forward declaration
+// Use VectorSRegister as a shortcut.
+class VectorSRegisterImpl;
+typedef VectorSRegisterImpl* VectorSRegister;
 
 // Use FloatRegister as shortcut
 class FloatRegisterImpl;
@@ -270,6 +274,9 @@
   bool is_valid() const { return (0 <= value() && value() < number_of_registers); }
 
   const char* name() const;
+
+  // convert to VSR
+  VectorSRegister to_vsr() const;
 };
 
 // The float registers of the PPC architecture
@@ -398,11 +405,6 @@
   return (VectorRegister)(intptr_t)encoding;
 }
 
-// Forward declaration
-// Use VectorSRegister as a shortcut.
-class VectorSRegisterImpl;
-typedef VectorSRegisterImpl* VectorSRegister;
-
 // The implementation of vector registers for the Power architecture
 class VectorRegisterImpl: public AbstractRegisterImpl {
  public: