--- a/src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetAssembler_x86.cpp	Wed Aug 14 12:57:34 2019 -0400
+++ b/src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetAssembler_x86.cpp	Wed Aug 14 20:32:43 2019 +0200
@@ -807,8 +807,15 @@
   __ mov(tmp1, res);
   __ shrptr(tmp1, ShenandoahHeapRegion::region_size_bytes_shift_jint());
   __ movptr(tmp2, (intptr_t) ShenandoahHeap::in_cset_fast_test_addr());
+#ifdef _LP64
   __ movbool(tmp2, Address(tmp2, tmp1, Address::times_1));
   __ testbool(tmp2);
+#else
+  // On x86_32, C1 register allocator can give us the register without 8-bit support.
+  // Do the full-register access and test to avoid compilation failures.
+  __ movptr(tmp2, Address(tmp2, tmp1, Address::times_1));
+  __ testptr(tmp2, 0xFF);
+#endif
   __ jcc(Assembler::zero, *stub->continuation());
 
   // Test if object is resolved.
@@ -816,7 +823,13 @@
   // Test if both lowest bits are set. We trick it by negating the bits
   // then test for both bits clear.
   __ notptr(tmp1);
+#ifdef _LP64
   __ testb(tmp1, markOopDesc::marked_value);
+#else
+  // On x86_32, C1 register allocator can give us the register without 8-bit support.
+  // Do the full-register access and test to avoid compilation failures.
+  __ testptr(tmp1, markOopDesc::marked_value);
+#endif
   __ jccb(Assembler::notZero, slow_path);
   // Clear both lower bits. It's still inverted, so set them, and then invert back.
   __ orptr(tmp1, markOopDesc::marked_value);
@@ -898,8 +911,8 @@
   // arg0 : object to be resolved
 
   __ save_live_registers_no_oop_map(true);
-  __ load_parameter(0, c_rarg0);
-  __ call_VM_leaf(CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier), c_rarg0);
+  __ load_parameter(0, LP64_ONLY(c_rarg0) NOT_LP64(rax));
+  __ call_VM_leaf(CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier), LP64_ONLY(c_rarg0) NOT_LP64(rax));
   __ restore_live_registers_except_rax(true);
 
   __ epilogue();