--- a/hotspot/src/cpu/sparc/vm/vm_version_sparc.cpp	Tue Dec 06 16:42:42 2016 +0300
+++ b/hotspot/src/cpu/sparc/vm/vm_version_sparc.cpp	Wed Dec 07 09:29:28 2016 -0800
@@ -89,8 +89,18 @@
     if (is_niagara_plus()) {
       if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
           FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
-        // Use BIS instruction for TLAB allocation prefetch.
-        FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
+        if (!has_sparc5_instr()) {
+          // Use BIS instruction for TLAB allocation prefetch
+          // on Niagara plus processors other than those based on CoreS4
+          FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
+        } else {
+          // On CoreS4 processors use prefetch instruction
+          // to avoid partial RAW issue, also use prefetch style 3
+          FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
+          if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
+            FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
+          }
+        }
       }
       if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
         if (AllocatePrefetchInstr == 0) {

--- a/hotspot/src/share/vm/opto/macro.cpp	Tue Dec 06 16:42:42 2016 +0300
+++ b/hotspot/src/share/vm/opto/macro.cpp	Wed Dec 07 09:29:28 2016 -0800
@@ -1952,7 +1952,7 @@
       i_o = pf_phi_abio;
    } else if( UseTLAB && AllocatePrefetchStyle == 3 ) {
       // Insert a prefetch instruction for each allocation.
-      // This code is used for SPARC with BIS.
+      // This code is used to generate 1 prefetch instruction per cache line.
 
       // Generate several prefetch instructions.
       uint lines = (length != NULL) ? AllocatePrefetchLines : AllocateInstancePrefetchLines;
@@ -1965,11 +1965,8 @@
       transform_later(cache_adr);
       cache_adr = new CastP2XNode(needgc_false, cache_adr);
       transform_later(cache_adr);
-      // For BIS instructions to be emitted, the address must be aligned at cache line size.
-      // (The VM sets AllocatePrefetchStepSize to the cache line size, unless a value is
-      // specified at the command line.) If the address is not aligned at cache line size
-      // boundary, a standard store instruction is triggered (instead of the BIS). For the
-      // latter, 8-byte alignment is necessary.
+      // Address is aligned to execute prefetch to the beginning of cache line size
+      // (it is important when BIS instruction is used on SPARC as prefetch).
       Node* mask = _igvn.MakeConX(~(intptr_t)(step_size-1));
       cache_adr = new AndXNode(cache_adr, mask);
       transform_later(cache_adr);