--- a/hotspot/src/cpu/sparc/vm/sparc.ad	Fri May 29 17:04:21 2015 +0300
+++ b/hotspot/src/cpu/sparc/vm/sparc.ad	Fri May 29 17:04:22 2015 +0300
@@ -3372,6 +3372,25 @@
   interface(CONST_INTER);
 %}
 
+// Integer Immediate: 0-bit
+operand immI0() %{
+  predicate(n->get_int() == 0);
+  match(ConI);
+  op_cost(0);
+
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
+// Integer Immediate: 5-bit
+operand immI5() %{
+  predicate(Assembler::is_simm5(n->get_int()));
+  match(ConI);
+  op_cost(0);
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
 // Integer Immediate: 8-bit
 operand immI8() %{
   predicate(Assembler::is_simm8(n->get_int()));
@@ -3381,6 +3400,25 @@
   interface(CONST_INTER);
 %}
 
+// Integer Immediate: the value 10
+operand immI10() %{
+  predicate(n->get_int() == 10);
+  match(ConI);
+  op_cost(0);
+
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
+// Integer Immediate: 11-bit
+operand immI11() %{
+  predicate(Assembler::is_simm11(n->get_int()));
+  match(ConI);
+  op_cost(0);
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
 // Integer Immediate: 13-bit
 operand immI13() %{
   predicate(Assembler::is_simm13(n->get_int()));
@@ -3410,84 +3448,6 @@
   interface(CONST_INTER);
 %}
 
-// Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
-operand immU12() %{
-  predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
-  match(ConI);
-  op_cost(0);
-
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-// Integer Immediate: 6-bit
-operand immU6() %{
-  predicate(n->get_int() >= 0 && n->get_int() <= 63);
-  match(ConI);
-  op_cost(0);
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-// Integer Immediate: 11-bit
-operand immI11() %{
-  predicate(Assembler::is_simm11(n->get_int()));
-  match(ConI);
-  op_cost(0);
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-// Integer Immediate: 5-bit
-operand immI5() %{
-  predicate(Assembler::is_simm5(n->get_int()));
-  match(ConI);
-  op_cost(0);
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-// Int Immediate non-negative
-operand immU31()
-%{
-  predicate(n->get_int() >= 0);
-  match(ConI);
-
-  op_cost(0);
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-// Integer Immediate: 0-bit
-operand immI0() %{
-  predicate(n->get_int() == 0);
-  match(ConI);
-  op_cost(0);
-
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-// Integer Immediate: the value 10
-operand immI10() %{
-  predicate(n->get_int() == 10);
-  match(ConI);
-  op_cost(0);
-
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-// Integer Immediate: the values 0-31
-operand immU5() %{
-  predicate(n->get_int() >= 0 && n->get_int() <= 31);
-  match(ConI);
-  op_cost(0);
-
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
 // Integer Immediate: the values 1-31
 operand immI_1_31() %{
   predicate(n->get_int() >= 1 && n->get_int() <= 31);
@@ -3529,7 +3489,6 @@
   format %{ %}
   interface(CONST_INTER);
 %}
-
 // Integer Immediate: the value 255
 operand immI_255() %{
   predicate( n->get_int() == 255 );
@@ -3550,6 +3509,46 @@
   interface(CONST_INTER);
 %}
 
+// Integer Immediate: the values 0-31
+operand immU5() %{
+  predicate(n->get_int() >= 0 && n->get_int() <= 31);
+  match(ConI);
+  op_cost(0);
+
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
+// Integer Immediate: 6-bit
+operand immU6() %{
+  predicate(n->get_int() >= 0 && n->get_int() <= 63);
+  match(ConI);
+  op_cost(0);
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
+// Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
+operand immU12() %{
+  predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
+  match(ConI);
+  op_cost(0);
+
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
+// Integer Immediate non-negative
+operand immU31()
+%{
+  predicate(n->get_int() >= 0);
+  match(ConI);
+
+  op_cost(0);
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
 // Long Immediate: the value FF
 operand immL_FF() %{
   predicate( n->get_long() == 0xFFL );
@@ -5653,17 +5652,17 @@
   ins_pipe(iload_mem);
 %}
 
-// Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
-instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
+// Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
+instruct loadUB2L_immI(iRegL dst, memory mem, immI mask) %{
   match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
 
   size(2*4);
-  format %{ "LDUB   $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
-            "AND    $dst,$mask,$dst" %}
+  format %{ "LDUB   $mem,$dst\t# ubyte & 32-bit mask -> long\n\t"
+            "AND    $dst,right_n_bits($mask, 8),$dst" %}
   ins_encode %{
     __ ldub($mem$$Address, $dst$$Register);
-    __ and3($dst$$Register, $mask$$constant, $dst$$Register);
+    __ and3($dst$$Register, $mask$$constant & right_n_bits(8), $dst$$Register);
   %}
   ins_pipe(iload_mem);
 %}
@@ -5776,20 +5775,20 @@
   ins_pipe(iload_mem);
 %}
 
-// Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
-instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
+// Load Unsigned Short/Char (16bit UNsigned) with a 32-bit mask into a Long Register
+instruct loadUS2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
   effect(TEMP dst, TEMP tmp);
   ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
 
-  format %{ "LDUH   $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
-            "SET    $mask,$tmp\n\t"
+  format %{ "LDUH   $mem,$dst\t! ushort/char & 32-bit mask -> long\n\t"
+            "SET    right_n_bits($mask, 16),$tmp\n\t"
             "AND    $dst,$tmp,$dst" %}
   ins_encode %{
     Register Rdst = $dst$$Register;
     Register Rtmp = $tmp$$Register;
     __ lduh($mem$$Address, Rdst);
-    __ set($mask$$constant, Rtmp);
+    __ set($mask$$constant & right_n_bits(16), Rtmp);
     __ and3(Rdst, Rtmp, Rdst);
   %}
   ins_pipe(iload_mem);

--- a/hotspot/src/cpu/x86/vm/x86_32.ad	Fri May 29 17:04:21 2015 +0300
+++ b/hotspot/src/cpu/x86/vm/x86_32.ad	Fri May 29 17:04:22 2015 +0300
@@ -5431,18 +5431,18 @@
 %}
 
 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
-instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
+instruct loadUB2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
   match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
   effect(KILL cr);
 
-  format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
+  format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 32-bit mask -> long\n\t"
             "XOR    $dst.hi,$dst.hi\n\t"
-            "AND    $dst.lo,$mask" %}
+            "AND    $dst.lo,right_n_bits($mask, 8)" %}
   ins_encode %{
     Register Rdst = $dst$$Register;
     __ movzbl(Rdst, $mem$$Address);
     __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
-    __ andl(Rdst, $mask$$constant);
+    __ andl(Rdst, $mask$$constant & right_n_bits(8));
   %}
   ins_pipe(ialu_reg_mem);
 %}
@@ -5550,19 +5550,19 @@
   ins_pipe(ialu_reg_mem);
 %}
 
-// Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
-instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
+// Load Unsigned Short/Char (16 bit UNsigned) with a 32-bit mask into Long Register
+instruct loadUS2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
   effect(KILL cr);
 
-  format %{ "MOVZX  $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
+  format %{ "MOVZX  $dst.lo, $mem\t# ushort/char & 32-bit mask -> long\n\t"
             "XOR    $dst.hi,$dst.hi\n\t"
-            "AND    $dst.lo,$mask" %}
+            "AND    $dst.lo,right_n_bits($mask, 16)" %}
   ins_encode %{
     Register Rdst = $dst$$Register;
     __ movzwl(Rdst, $mem$$Address);
     __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
-    __ andl(Rdst, $mask$$constant);
+    __ andl(Rdst, $mask$$constant & right_n_bits(16));
   %}
   ins_pipe(ialu_reg_mem);
 %}

--- a/hotspot/src/cpu/x86/vm/x86_64.ad	Fri May 29 17:04:21 2015 +0300
+++ b/hotspot/src/cpu/x86/vm/x86_64.ad	Fri May 29 17:04:22 2015 +0300
@@ -4753,17 +4753,17 @@
   ins_pipe(ialu_reg_mem);
 %}
 
-// Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register
-instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{
+// Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
+instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
   match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
   effect(KILL cr);
 
-  format %{ "movzbq  $dst, $mem\t# ubyte & 8-bit mask -> long\n\t"
-            "andl    $dst, $mask" %}
+  format %{ "movzbq  $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
+            "andl    $dst, right_n_bits($mask, 8)" %}
   ins_encode %{
     Register Rdst = $dst$$Register;
     __ movzbq(Rdst, $mem$$Address);
-    __ andl(Rdst, $mask$$constant);
+    __ andl(Rdst, $mask$$constant & right_n_bits(8));
   %}
   ins_pipe(ialu_reg_mem);
 %}
@@ -4863,17 +4863,17 @@
   ins_pipe(ialu_reg_mem);
 %}
 
-// Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register
-instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{
+// Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
+instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
   effect(KILL cr);
 
-  format %{ "movzwq  $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t"
-            "andl    $dst, $mask" %}
+  format %{ "movzwq  $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
+            "andl    $dst, right_n_bits($mask, 16)" %}
   ins_encode %{
     Register Rdst = $dst$$Register;
     __ movzwq(Rdst, $mem$$Address);
-    __ andl(Rdst, $mask$$constant);
+    __ andl(Rdst, $mask$$constant & right_n_bits(16));
   %}
   ins_pipe(ialu_reg_mem);
 %}